Data recovery within the memory subsystem

Abstract

Receiving a command from a host system to transfer data in a portion of a memory component to a recovery portion of a different memory component, wherein the portion of the memory component is associated with a portion of the memory component that has failed, and in response to receiving the command, recovering the data in the portion of the memory component and transferring the data to the recovery portion of the different memory component without moving or processing the data by the host system.

Description

Technical Field

[0001] The present disclosure relates generally to memory subsystems and, more particularly, to data recovery within a memory subsystem. Background Art

[0002] The memory subsystem may be a storage system such as a solid-state drive (SSD) and may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. Generally speaking, a host system may utilize the memory subsystem to store data in the memory components and retrieve data from the memory components. Summary of the Invention

[0003] One aspect of the present disclosure relates to a system comprising: a memory component; and a processing device operably coupled to the memory component to: receive a command from a host system to transfer data in a portion of the memory component to a restored portion of a different memory component, wherein the portion of the memory component is associated with a portion of the memory component that has failed; and in response to receiving the command, recover the data in the portion of the memory component and transfer the data to the restored portion of the different memory component without moving or processing the data by the host system.

[0004] Another aspect of the present disclosure relates to a method, comprising: receiving, by a memory subsystem, a command from a host system to transfer data in a portion of a memory component of the memory subsystem to a recovery portion of a different memory component of the memory subsystem, wherein the portion of the memory component is associated with a portion of the memory component that has failed; and recovering, by the memory subsystem, the data in the portion of the memory component and transferring the data to the recovery portion of the different memory component in response to receiving the command from the host system without moving or processing the data by the host system.

[0005] Yet another aspect of the present disclosure relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receive an address range from a host system that is outside an existing address range associated with a memory component; receive a command from the host system to transfer data in a Redundant Array of Independent Disks (RAID) stripe of the memory component to a recovery portion of the memory component, wherein the RAID stripe is associated with a portion of the memory component that has failed; and in response to receiving the command, recover the data in the RAID stripe of the memory component using the received address range and transfer the data to the recovery portion of the memory component, such that the data is recovered and transferred without requiring the data to be moved or processed by the host system. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 An example memory subsystem according to some embodiments of the present disclosure is described.

[0009] Figure 3 is a flow chart of an example method for performing data recovery within a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to data recovery within a memory subsystem. The memory subsystem is also referred to hereinafter as a "memory device." An example of a memory subsystem is a storage system such as a solid-state drive (SSD). In some embodiments, the memory subsystem is a hybrid memory / storage subsystem. Generally, a host system may utilize a memory subsystem comprising one or more memory components. The host system may provide data stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0012] During the operation of a memory subsystem (e.g., a storage system), a number of defects and / or errors may occur. Such defects and / or errors may cause the loss of data stored in the memory subsystem, which may result in a failure of the memory subsystem. The memory subsystem may protect against data loss using various data protection and / or recovery schemes, such as, for example, a Redundant Array of Independent Disks (RAID) data protection and recovery scheme, which may distribute and / or replicate data stored in the memory subsystem across multiple memory devices. For example, a RAID data protection and recovery scheme may distribute and / or replicate data stored in the memory subsystem across stripes across the memory devices and subsequently use the data in the stripes to recover the lost data.

[0013] Conventional data recovery schemes, such as conventional RAID schemes, are managed and executed at the host system level. For example, in conventional RAID data recovery, the recovered data must be processed and then moved by the host system (e.g., data from a failed device to a healthy device). However, processing and moving data by the host system increases the amount of time required to recover the data, which can adversely affect the performance of the host system and / or the memory subsystem. Furthermore, a second (e.g., additional) failure may occur during this extended data recovery process, which could be catastrophic to the memory subsystem.

[0014] Aspects of the present disclosure address the above-mentioned and other shortcomings by performing data recovery within the memory subsystem. For example, aspects of the present disclosure do not process or move recovered data through a host system. Rather, recovered data can be processed and moved directly between devices in the memory subsystem, which can reduce the amount of time required to recover data (e.g., improve the efficiency of data processing and movement) compared to conventional solutions (e.g., conventional RAID data recovery solutions in which recovered data is moved and processed by a host system).

[0015] Furthermore, aspects of the present disclosure can process and move recovered data in parallel throughout the memory subsystem, which can further reduce (e.g., speed up) data recovery time. Furthermore, aspects of the present disclosure can utilize any data (e.g., "good" data) in the memory subsystem that is not lost to further reduce data recovery time.

[0016] Thus, aspects of the present disclosure can improve the performance of the host system and / or memory subsystem over conventional approaches. Furthermore, aspects of the present disclosure can utilize existing components and / or elements of the memory subsystem, such as (for example) existing processing and / or memory capabilities of the memory subsystem and / or existing RAID functionality. Furthermore, aspects of the present disclosure can reduce the cost and / or power consumption of the overall system by utilizing the processing power of the memory subsystem, so that the host does not have to use processing power for data recovery. Furthermore, aspects of the present disclosure can be used for both complete and partial data loss (e.g., both complete and partial failures) that occur in the memory subsystem.

[0017] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure is described. Memory subsystem 110 may include media, such as memory components 112-1 through 112-N. Memory components 112-1 through 112-N may be volatile memory components, non-volatile memory components, or a combination of such components. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, memory subsystem 110 is a hybrid memory / storage subsystem. Generally speaking, computing environment 100 may include a host system 120 that utilizes memory subsystem 110. For example, host system 120 may write data to and read data from memory subsystem 110.

[0018] Host system 120 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, or any other computing device that includes memory and processing devices. Host system 120 may include or be coupled to memory subsystem 110, such that host system 120 can read data from or write data to memory subsystem 110. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface may be used to transfer data between host system 120 and memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access the memory components 112-1 to 112-N. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0019] Memory components 112-1 to 112-N may include any combination of different types of nonvolatile memory components and / or volatile memory components. An example of a nonvolatile memory component includes NAND-type flash memory. Each of memory components 112-1 to 112-N may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC), such as triple-level cells (TLC) or quad-level cells (QLC). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of memory cells. Each of the memory cells may store one or more data bits (e.g., a block of data) used by host system 120. Although nonvolatile memory components (e.g., NAND-type flash memory) are described, memory components 112-1 to 112-N may be based on any other type of memory, such as volatile memory. In some embodiments, memory components 112-1 through 112-N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point non-volatile memory cell arrays. Cross-point non-volatile memory arrays can perform bit storage based on changes in bulk resistance in conjunction with a stackable crossbar-type data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing them. Furthermore, the memory cells of memory components 112-1 through 112-N can be grouped into memory pages or data blocks, which can refer to a unit of memory component used to store data.

[0020] A memory system controller 115 (hereinafter referred to as the "controller") can communicate with memory components 112-1 through 112-N to perform operations, such as reading, writing, or erasing data at memory components 112-1 through 112-N, and other such operations. Controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. Controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. Controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, local memory 119 of controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines for controlling the operation of memory subsystem 110, including handling communications between memory subsystem 110 and host system 120. In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, and the like. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include a controller 115 and may rely on external control (e.g., provided by an external host or a processor or controller separate from the memory subsystem).

[0021] In general, the controller 115 may receive commands or operations from the host system 120 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112-1 to 112-N. The controller 115 may be responsible for other operations associated with the memory components 112-1 to 112-N, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses. The controller 115 may further include host interface circuitry that communicates with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory components 112-1 to 112-N and convert responses associated with the memory components 112-1 to 112-N into information for the host system 120.

[0022] The memory subsystem 110 includes registers 113 and switches 114 that can be used by the memory subsystem 110 to perform data recovery within the memory subsystem 110. In some embodiments, the controller 115 includes at least a portion of the registers 113 and / or the switches 114. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. For example, the processor 117 may execute instructions stored in the local memory 119 to perform data recovery operations within the memory subsystem 110 with optional hardware assistance.

[0023] Register 113 and switch 114 can be used by memory subsystem 110 to perform data recovery without moving or processing the recovered data through host system 120. For example, register 113 and switch 114 can be used by memory subsystem 110 to process and move recovered data directly between devices in the memory subsystem. Register 113 can be, for example, a base address register, and switch 114 can be, for example, a PCIe switch. More details regarding the operation of register 113 and switch 114 will be described below.

[0024] For example, the memory subsystem 110 (e.g., the controller 115) may receive a command (e.g., a read command) from the host system 120 to transfer data from a portion of a memory component 112-1, ..., 112-N to a recovery portion of a different memory component 112-1, ..., 112-N. The portion of the memory component 112-1, ..., 112-N may be, for example, a RAID stripe of memory components and may be associated with a portion of a failed memory component 112-1, ..., 112-N (e.g., covering a logical block address of a portion of the failed memory component 112-1, ..., 112-N). The recovery portion may be one of multiple recovery portions of different memory components, as will be further described herein.

[0025] As used herein, RAID is an umbrella term for computer information (e.g., data) storage schemes that distribute and / or replicate (e.g., mirror) information across multiple pages of multiple memory devices and / or components, for example, to help protect the data stored therein. The multiple memory devices and / or components in a RAID array appear to the user and the computer's operating system as a single memory device (e.g., disk). RAID may include blocking (e.g., striping) information so that different portions of the information are stored on different pages of different memory devices and / or components. The storage of portions of the striped data across more than one device or component is collectively referred to as a stripe. In contrast, RAID may also include mirroring, which may include storing copies of data on more than one page of more than one device or component. As an example of the former, write data may be blocked across N-1 of N memory devices and / or components, with error information stored in the Nth memory device or component. A RAID stripe may include user data and parity data (e.g., a combination of user data and parity data). The parity data of a RAID stripe may include error protection data that can be used to protect user data stored in the memory from defects and / or errors that may occur during operation of the memory. For example, a RAID stripe may protect user data stored in the memory from defects and / or errors that may occur during operation of the memory, and may therefore provide protection against memory failures.

[0026] As used herein, a portion of a failed memory component may refer to and / or include a portion of a memory component whose data has been lost. For example, a portion of a failed memory component may include one or more data arrays, pages, and / or blocks that have been lost. In some examples, a portion of a failed memory component 112-1, ..., 112-N may include less than the entire memory component (e.g., less than all data stored in the memory component has been lost). This example may be referred to as a partial failure of the memory component. In some examples, a portion of a failed memory component 112-1, ..., 112-N may include the entire memory component (e.g., all data stored in the memory component has been lost). This example may be referred to as a complete failure of the memory component.

[0027] In some instances (e.g., in a partial failure instance), the memory subsystem 110 may send a notification to the host system 120 that a partial failure of the memory components 112-1, ..., 112-N has occurred. For example, the memory subsystem 110 may notify the host system 120 of the logical block addresses (LBAs) associated with the lost data. These LBAs may include multiple ranges of LBAs. In some instances (e.g., in a complete failure instance), the host system 120 may detect that the partial failure of the memory components 112-1, ..., 112-N has occurred because, for example, the entire component has gone offline.

[0028] Upon receiving notification of a partial failure of a memory component 112-1, ..., 112-N or upon detecting a partial failure of a memory component 112-1, ..., 112-N, the host system 120 may determine (e.g., identify) the location of the RAID stripe associated with the memory component and the location of the recovery portion of the different memory component. The host system 120 may then send a command to the memory subsystem 110 to transfer the data in the RAID stripe to the recovery portion, wherein the command includes identifying the RAID stripe and the recovery portion of the different memory component (e.g., identifying the location of the RAID stripe and the recovery portion of the different memory component). After sending the command, the host system 120 may operate in a reduced operating mode, such as, for example, a degraded read mode, until the lost data is recovered. For example, the lost data may be unmapped, with reads resulting in zeros, until data recovery is complete.

[0029] Furthermore, upon receiving notification of a partial failure of a memory component 112-1, 112-N or upon detecting a partial failure of a memory component 112-1, 112-N, the host system 120 may define an address range (e.g., an LBA range) outside of an existing address range associated with the memory component. The existing address range may, for example, be an address range used by the host system 120 to access the memory component (e.g., to access data stored by the memory component) during normal operation. That is, the defined address range may be outside of the normal LBA range used by the host system 120 to access the memory component during normal operation to prevent the host system 120 from accessing the data until it is fully recovered.

[0030] The host system 120 may then send the defined address range to the memory subsystem 110. Upon receiving the defined address range from the host system 120, the memory subsystem 110 may store the address range in registers 113 for performing data recovery within the memory subsystem 110, as will be further described herein.

[0031] In response to receiving a command from the host system 120 to transfer data in a portion (e.g., a RAID stripe) of the memory components 112-1, ..., 112-N to a recovery portion of a different memory component 112-1, ..., 112-N, the memory subsystem 110 may recover the data and transfer the data to the recovery portion without requiring the data to be moved or processed by the host system 120. For example, the memory subsystem 110 may recover the data and transfer the data directly from the RAID stripe of the memory components to the recovery portion of the different memory component.

[0032] The memory subsystem 110 can recover data in portions of the memory components 112-1, . . . , 112-N and transfer the data to a recovered portion of a different memory component without requiring the data to be moved or processed by the host system 120 by, for example, recovering and transferring the data using a defined address range (e.g., an address range outside of an existing address range associated with the memory component) received from the host system 120 and stored in registers 113. For example, addresses within the defined address range (e.g., LBAs) can provide an indication to the memory subsystem 110 that the data is to be accessed as part of a data recovery portion (e.g., rather than as part of a normal host access operation). Thus, accessing the data using an address within the defined address range can provide an indication to the memory subsystem 110 that the data is to be recovered and transferred within the memory subsystem 110 (e.g., directly to a recovered portion of a different memory component) rather than to the host system 120. For example, memory subsystem 110 may know to recover data in a RAID stripe and transfer that data to a recovery portion of a different memory component (rather than to host system 120) because the RAID stripe is accessed using addresses in registers 113 (e.g., addresses outside the range for normal host access).

[0033] Furthermore, the memory subsystem 110 can recover data in portions of the memory components 112-1, ..., 112-N and transfer the data to the recovery portions of different memory components 112-1, ..., 112-N without requiring the data to be moved or processed by the host system 120 by, for example, recovering and transferring the data using (e.g., through) the switch 114. For example, the switch 114 can receive data from the RAID stripe and direct the data to the recovery portion using addresses within a defined range in the register 113.

[0034] Recovery of data in the RAID stripes of memory components 112-1, ..., 112-N and transfer of the recovered portion to a different memory component may include performing an XOR operation on the data in the RAID stripes to recover the data of the lost memory component. The parameters of the XOR operation (e.g., stripe length, RAID ratio, etc.) may be defined by the host system 120.

[0035] In instances where the portion of the failed memory component 112-1, ..., 112-N includes less than the entire memory component, data stored in the remaining portion of the surviving memory component (e.g., "good" data that was not lost) may be moved to a different portion of a different memory component as part of a recovery process without requiring the data to be moved or processed by the host system 120. That is, the remaining "good" data may be utilized as part of the recovery process.

[0036] For example, the host 120 may determine (e.g., identify) a portion of a memory component to which the "good" data will be moved. This portion of the memory component may be, for example, a recovery portion of a different memory component 112-1, ..., 112-N to which the RAID stripe data is transferred, or may be a different portion of a different memory component (e.g., a different recovery portion). The host system 120 may then send a command to the memory subsystem 110 to transfer the "good" data to the portion of the memory component, wherein the command includes identifying the portion (e.g., identifying the location of the portion).

[0037] In response to receiving a command from the host system 120 to transfer good data for a memory component, the memory subsystem 110 may transfer the good data to the portion of the different memory component identified in the command, without requiring the data to be moved or processed by the host system 120. For example, the memory subsystem 110 may transfer the good data directly to the identified portion of the different memory component in a manner similar to that previously described for data in a RAID stripe of memory components (e.g., using switches 114 and a defined address range stored in registers 113). Furthermore, the memory subsystem 110 may transfer the good data to the identified portion of the different memory component while restoring the RAID stripe data and (e.g., in parallel) transferring the RAID stripe data to the restored portion.

[0038] In instances where different memory components 112-1, ..., 112-N include multiple recovery portions, multiple data recovery operations may be performed in parallel such that the data recovered in each respective operation may be moved in parallel to its respective recovery portion. For example, if an additional portion of a memory component 112-1, ..., 112-N has failed, the memory subsystem 110 may receive additional commands from the host system 120 to transfer data in additional RAID stripes of the memory components 112-1, ..., 112-N associated with the additional failed portion to additional recovery portions of different memory components in a manner similar to the commands received to transfer data in RAID stripes to recovery portions (as previously described herein). The memory subsystem 110 can, in response to receiving additional commands and while recovering data in the previously described RAID stripes and transferring the data to the previously described recovery portions (e.g., in parallel), recover data in additional RAID stripes and transfer the data to the additional recovery portions without requiring the data to be moved or processed by the host system 120 in a manner similar to the data recovery and transfer previously described herein (e.g., using switches 114 and registers 113).

[0039] After recovering the data in the RAID stripes of the memory components 112-1, ..., 112-N and transferring the data to the recovered portion of the different memory components, the memory subsystem 110 may change (e.g., move and / or update) the addresses (e.g., LBAs) associated with the transferred data to an address within an existing address range associated with the different memory components (e.g., an address range used by the host system 120 to access the different memory components during normal operation). For example, the address may be changed to the original address of the lost data. Furthermore, after recovering the data in the RAID stripes of the memory components 112-1, ..., 112-N and transferring the data to the recovered portion of the different memory components, the memory subsystem 110 may send a notification to the host system 120 indicating that the data recovery is complete.

[0040] Figure 2 An example memory subsystem 210 according to some embodiments of the present disclosure is illustrated. The memory subsystem 210 may be, for example, a memory subsystem 210 as previously described. Figure 1 Memory subsystem 110 is described.

[0041] like Figure 2 , the memory subsystem 210 may include memory components 212-1 to 212-5 and a switch 214 operatively coupled to the memory components 212-1 to 212-5. The memory components 212-1 to 212-5 and the switch 214 may be, for example, the memory components 212-1 to 212-5 and the switch 214, respectively. Figure 1 1, ..., 112-N and switch 114 are described. As an example, switch 214 may be a PCIe switch included on a PCIe expansion board coupled to a PCIe driver plane board where memory components 212-1 to 212-5 are located. Figure 2 The embodiment described in the accompanying drawings includes five memory components, but the embodiments of the present disclosure are not limited to a specific number of memory components.

[0042] like Figure 2 As previously mentioned Figure 1 As depicted, each respective memory component 212-1, ..., 212-5 may include an array of memory cells. For example, memory component 212-1 may include arrays 221-1 through 221-8, memory component 212-2 may include arrays 222-1 through 222-8, memory component 212-3 may include arrays 223-1 through 223-8, and so on. Although Figure 2 In the embodiment described in

[15] , each corresponding memory component includes eight arrays, but the embodiments of the present disclosure are not limited to a specific number of arrays per memory component. In addition, as an example, each corresponding array can store 4 terabytes (TB) of data. However, the embodiments of the present disclosure are not limited to this.

[0043] exist Figure 2 In the example illustrated in , RAID stripes are stored across portions of arrays 221-3, 223-3, 224-3, and 225-3 of memory components 212-1, 212-3, 212-4, 212-5, respectively. For example, a RAID stripe may be stored across multiple pages of each respective array 221-3, 223-3, 224-3, and 225-3.

[0044] exist Figure 2 In the example illustrated in FIG, portions of arrays 221-5, 223-6, 224-1, and 225-1 of memory elements 212-1, 212-3, 212-4, and 212-5, respectively (e.g., as previously described with respect to FIG). Figure 1 The host system 120 depicted in FIG. 2 may designate a portion of the array as a recovery portion. For example, the recovery portion of each respective array 221-5, 223-6, 224-1, and 225-1 may include one or more pages and / or blocks of memory cells within the respective array. The portion of the array designated as a recovery portion may change during operation of the memory subsystem 210, or may remain the same (e.g., fixed) throughout operation of the memory subsystem 210. Furthermore, the greater the number of portions designated as recovery portions, the greater the number of recovery operations that may be performed in parallel. Although Figure 2 In the embodiment described in FIG, parts of four different arrays are marked as recovery parts, but the embodiments of the present disclosure are not limited thereto.

[0045] exist Figure 2 In the example illustrated in FIG, a portion of array 222-3 of memory component 212 (e.g., for example, one or more pages and / or blocks of memory cells of array 22-3) has failed. Accordingly, data in the RAID stripes stored across arrays 221-3, 222-3, 224-3, and 225-3 associated with the failed portion of array 222-3 (e.g., LBAs covering the failed portion of array 222-3) may be recovered and transferred to one of the recovered portions of arrays 221-5, 223-6, 224-1, and 225-1, as previously described with respect to FIG. Figure 1 For example, data may be recovered using (e.g., through) switch 214 and transferred to the recovery portion, as previously described with respect to Figure 1 describe.

[0046] Figure 3 is a flow chart of an example method 330 for performing data recovery within a memory subsystem according to some embodiments of the present disclosure. The method 330 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 330 is performed by Figure 1 The controller 115 of the memory subsystem 110 uses the registers 113 and switches 114 of the memory subsystem 110 to perform. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, in various embodiments, one or more processes may be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0047] At block 332, the memory subsystem receives a command from the host system to transfer data in a portion of a memory component of the memory subsystem to a recovery portion of a different memory component of the memory subsystem, wherein the portion of the memory component is associated with a portion of the failed memory component. The portion of the memory component may be, for example, a RAID stripe, as previously described with respect to Figure 1 Description. The host system may be, for example, Figure 1 The host system 120 described above and the commands received from the host system may be similar to those previously described with respect to Figure 1 Furthermore, the memory component may be, for example, the one previously described Figure 1 The memory components 112-1, ..., 112-N described, and the recovery portion and failure portion of the memory components can be similar to those previously described with respect to Figure 1 The recovery part and the failure part of the description.

[0048] At block 334, the memory subsystem recovers data in the portion of the memory component and transfers the data to the recovered portion of a different memory component in response to receiving the command from the host system without moving or processing the data by the host system. The data may be recovered and transferred to the recovered portion without requiring a process similar to that previously described with respect to Figure 1 For example, data may be recovered and transferred to the recovery portion without the need for the host system to move or process the data by using registers 113 and switches 114, as previously described. Figure 1 describe.

[0049] Figure 4 An example machine illustrating a computer system 440 in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 440 may correspond to a host system (e.g., Figure 1 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or can be used to perform operations of the controller (for example, execute an operating system to perform operations corresponding to Figure 1The controller 115 (including Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user in a cloud-based computing infrastructure or environment.

[0050] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0051] The example computer system 440 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 406 (e.g., flash memory, static random access memory (SRAM)), etc.), and a data storage system 418, which communicate with each other via a bus 430.

[0052] Processing device 402 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing another instruction set, or multiple processors implementing a combination of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 440 may further include a network interface device 408 for communicating over a network 420.

[0053] The data storage system 418 may include a machine-readable storage medium 424 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 426 or software embodying any one or more of the methodologies or functionality described herein. The instructions 426 may also reside, completely or at least partially, within the main memory 404 and / or the processing device 402 during execution thereof by the computer system 440, with the main memory 404 and the processing device 402 also constituting machine-readable storage media. The machine-readable storage medium 424, the data storage system 418, and / or the main memory 404 may correspond to Figure 1 Memory subsystem 110.

[0054] In one embodiment, the instructions 426 include instructions for implementing the instructions corresponding to the Figure 1 113 and switch 114, registers 413 and switches 414. Although the machine-readable storage medium 424 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium capable of storing or encoding a set of instructions to be executed by a machine and causing the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" should accordingly be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0055] As used herein, "a," "an," or "a number" may refer to one or more of something, and "a plurality" may refer to one or more of such things. For example, a memory device may refer to one or more memory devices, and a plurality of memory devices may refer to two or more memory devices. Additionally, the designator "N" used herein, particularly with respect to reference numerals in the figures, indicates that a number of the particular feature indicated may be included with several embodiments of the present disclosure.

[0056] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar digits. For example, 114 may refer to Figure 1 Element "14" in, and similar elements may be found in Figure 2 It is called 214 in China.

[0057] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to those skilled in other arts. An algorithm is herein, and generally, considered to be a self-consistent sequence of operations leading to a desired result. An operation is one requiring physical manipulation of physical quantities. Typically, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0058] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. This disclosure may refer to the actions and processes of computer systems or similar electronic computing devices that manipulate or transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0059] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0060] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various such systems will appear as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that various programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0061] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0062] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. Obviously, various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are to be regarded accordingly as illustrative rather than restrictive.

Claims

1. A system for data recovery, comprising: Memory components (112-1, ..., 112-N, 212-1, ..., 212-5) in a memory subsystem (110, 210); a register (113, 413) storing an address range outside of an existing address range associated with the memory component (112-1, ..., 112-N, 212-1, ..., 212-5), wherein the existing address range associated with the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) comprises an address range used by a host system (120) to access the memory component (112-1, ..., 112-N, 212-1, ..., 212-5); and A processing device (117, 402) operatively coupled to the memory components (112-1, ..., 112-N, 212-1, ..., 212-5) to: receiving a command from the host system (120) to transfer data in a portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) to a restored portion (221-5, 223-6, 224-1, 225-10) of a different memory component (112-1, ..., 112-N, 212-1, ..., 212-5) within the memory subsystem (110, 210), wherein the portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) is associated with a portion (222-3) of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) that has failed; and Responding to receiving the command, recovering the data in the portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) by using addresses within the address range outside the existing address range associated with the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) and transferring the data to the different memory component (112-1, ..., 112-N, 212-1, ..., 212-5) , 212-5) within the memory subsystem (110, 210) without moving or processing the data through the host system (120), wherein the address provides an indication that the data is to be recovered and transferred to the recovered portion (221-5, 223-6, 224-1, 225-10) of the different memory components (112-1, . . . , 112-N, 212-1, . . . , 212-5) within the memory subsystem (110, 210).

2. The system of claim 1, wherein the portion of the memory components (112-1, ..., 112-N, 212-1, ..., 212-5) is a Redundant Array of Independent Disks (RAID) stripe.

3. The system according to any one of claims 1 to 2, wherein the processing means (117, 402) is to: receiving a command from the host system (120) to transfer data in a portion of the memory components (112-1, ..., 112-N, 212-1, ..., 212-5) that did not fail; and In response to receiving the command, the data in the portion of the non-failed memory component (112-1, ..., 112-N, 212-1, ..., 212-5) is transferred to the recovery portion (221-5, 223-6, 224-1, 225-10) of the different memory component (112-1, ..., 112-N, 212-1, ..., 212-5) without moving or processing the data by the host system (120).

4. The system according to any one of claims 1 to 2, wherein the processing means (117, 402) is to: receiving, from the host system (120), additional commands to transfer data in an additional portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) to an additional recovery portion (221-5, 223-6, 224-1, 225-10) of the different memory component (112-1, ..., 112-N, 212-1, ..., 212-5), wherein the additional portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) is associated with the additional portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) that failed; and In response to receiving the additional command and while recovering the data in the portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) and transferring the data to the recovered portion (221-5, 223-6, 224-1, 225-10) of the different memory component (112-1, ..., 112-N, 212-1, ..., 212-5) without moving or processing the data by the host system (120).

5. The system of claim 1 , further comprising a switch operably coupled to the memory component and the different memory component, and wherein the processing device utilizes the switch to recover the data in the portion of the memory component and transfer the data to the recovered portion of the different memory component.

6. The system of any one of claims 1 to 2, wherein the processing device (117, 402) is to send a notification to the host system (120) that the portion (222-3) of the failed memory component (112-1, ..., 112-N, 212-1, ..., 212-5) has failed.

7. A method for data recovery, comprising: receiving, by a memory subsystem (110, 210) from a host system (120), a command to transfer data in a portion of a memory component (112-1, ..., 112-N, 212-1, ..., 212-5) of the memory subsystem (110, 210) to a recovery portion (221-5, 223-6, 224-1, 225-10) of a different memory component (112-1, ..., 112-N, 212-1, ..., 212-5) of the memory subsystem (110, 210), wherein the portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) is associated with a portion (222-3) of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) that has failed; and Recovering, by the memory subsystem (110, 210) in response to receiving the command from the host system (120), the data in the portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) by using an address within an address range outside of an existing address range associated with the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) and transferring the data to the recovered portion (221-5, 223-6, 224-1, 225-10) of the different memory component (112-1, ..., 112-N, 212-1, ..., 212-5) without passing through the host system (120) A system (120) moves or processes the data, wherein the existing address range associated with the memory components (112-1, ..., 112-N, 212-1, ..., 212-5) comprises an address range used by the host system (120) to access the memory components (112-1, ..., 112-N, 212-1, ..., 212-5), and the addresses provide an indication of the restored portions (221-5, 223-6, 224-1, 225-10) of the different memory components (112-1, ..., 112-N, 212-1, ..., 212-5) within the memory subsystem (110, 210).

8. The method of claim 7 , wherein recovering the data in the portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) and transferring the data to the recovered portion (221-5, 223-6, 224-1, 225-10) of the different memory component (112-1, ..., 112-N, 212-1, ..., 212-5) comprises performing an XOR operation on the data.

9. The method of claim 7, further comprising using a switch (114, 414) of the memory subsystem (110, 210) to recover the data in the portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) and transfer the data to the recovered portion (221-5, 223-6, 224-1, 225-10) of the different memory component (112-1, ..., 112-N, 212-1, ..., 212-5).

10. The method of any one of claims 7 to 9, wherein the portion (222-3) of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) that has failed comprises the entire memory component (112-1, ..., 112-N, 212-1, ..., 212-5).

11. The method of any one of claims 7 to 9, wherein the portion (222-3) of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) that has failed comprises less than the entire memory component (112-1, ..., 112-N, 212-1, ..., 212-5).

12. The method of any one of claims 7 to 9, further comprising sending a notification to the host system (120) after restoring the data in the portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) and transferring the data to the restored portion (221-5, 223-6, 224-1, 225-10) of the different memory component (112-1, ..., 112-N, 212-1, ..., 212-5).

13. The method according to any one of claims 7 to 9, further comprising: Receiving, by the memory subsystem (110, 210) from the host system (120), a command to transfer data in a portion of the non-failed memory components (112-1, ..., 112-N, 212-1, ..., 212-5); and by the memory subsystem (110, 210) in response to receiving the command and in restoring the data in the portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) and transferring the data to the restored portion (221-5, 223-6, 224-1, 225-10) of the different memory component (112-1, ..., 112-N, 212-1, ..., 212-5) Recovering the data in the portion of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) that did not fail and transferring the data to an additional recovered portion (221-5, 223-6, 224-1, 225-10) of the different memory component (112-1, ..., 112-N, 212-1, ..., 212-5) without moving or processing the data by the host system (120).

14. A non-transitory computer-readable storage medium (424) comprising instructions that, when executed by a processing device (117, 402), cause the processing device (117, 402): receiving, from a host system (120), an address range outside of an existing address range associated with a memory component (112-1, ..., 112-N, 212-1, ..., 212-5), wherein the existing address range associated with the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) comprises an address range used by the host system (120) to access the memory component (112-1, ..., 112-N, 212-1, ..., 212-5); receiving a command from the host system (120) to transfer data in a Redundant Array of Independent Disks (RAID) stripe of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) to a recovery portion (221-5, 223-6, 224-1, 225-10) of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5), wherein the RAID stripe is associated with a portion (222-3) of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) that has failed; and In response to receiving the command, recovering the data in the RAID stripes of the memory components (112-1, ..., 112-N, 212-1, ..., 212-5) using addresses within the received address range outside the existing address range associated with the memory components (112-1, ..., 112-N, 212-1, ..., 212-5) and transferring the data to the recovery portion of the memory components (112-1, ..., 112-N, 212-1, ..., 212-5) (221-5, 223-6, 224-1, 225-10), wherein the address provides an indication that the data is to be recovered and transferred to the recovery portion (221-5, 223-6, 224-1, 225-10) of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) within the memory subsystem (110, 210), so that the data is recovered and transferred without moving or processing the data through the host system (120).

15. The non-transitory computer-readable storage medium (424) of claim 14, wherein the processing device (117, 402) is further caused to store the received address range in a register (113, 413).

16. The non-transitory computer-readable storage medium (424) of any one of claims 14-15, wherein the processing device (117, 402) is further caused to: After recovering the data in the RAID stripe of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) and transferring the data to the recovered portion (221-5, 223-6, 224-1, 225-10) of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5), the addresses associated with the recovered and transferred data are changed to addresses within the existing address range associated with the memory component (112-1, ..., 112-N, 212-1, ..., 212-5).

17. The non-transitory computer-readable storage medium (424) of any one of claims 14-15, wherein the recovery portion (221-5, 223-6, 224-1, 225-10) of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) comprises one of a plurality of recovery portions (221-5, 223-6, 224-1, 225-10) of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5).

18. The non-transitory computer-readable storage medium (424) of any one of claims 14-15, wherein the command from the host system (120) comprises: identifying the RAID stripes of the memory components (112-1, ..., 112-N, 212-1, ..., 212-5); and The restored portion (221-5, 223-6, 224-1, 225-10) of the memory component (112-1, ..., 112-N, 212-1, ..., 212-5) is identified.

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