Method of controlling initialization of a non-volatile memory device and memory system

Abstract

To control initialization of a nonvolatile memory device, information data for initialization of a first nonvolatile memory device is stored in the first nonvolatile memory device before assembling a memory system including the first nonvolatile memory device and a second nonvolatile memory device. After assembling the memory system, the information data is moved from the first nonvolatile memory device to the second nonvolatile memory device. The first nonvolatile memory device is initialized based on the information data stored in the second nonvolatile memory device. By moving the information data from the first nonvolatile memory device to the second nonvolatile memory device having a fast read operation speed and using the information data read from the second nonvolatile memory device, initialization time of the first nonvolatile memory device is effectively reduced.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0121430 filed on October 1, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments generally relate to semiconductor integrated circuits. For example, at least some example embodiments relate to a method of controlling initialization of a nonvolatile memory device and / or a memory system including the nonvolatile memory device. Background Art

[0004] A nonvolatile memory device (such as a flash memory device or a resistive memory device) can store data by programming each memory cell to have one of a threshold voltage distribution or a resistance distribution corresponding to a different logical state. Initializing a nonvolatile memory device may involve moving the information stored in the nonvolatile memory device to another memory component. Three-dimensional nonvolatile memory devices, such as vertical NAND flash memory devices, have been developed to increase the integration density of memory cells. As the integration density and memory capacity of nonvolatile memory devices increase, the time required to initialize the nonvolatile memory device may increase. Summary of the Invention

[0005] Some example embodiments may provide a method of controlling initialization of a nonvolatile memory device, which is capable of efficiently performing initialization.

[0006] Some example embodiments may provide a memory system including a nonvolatile memory device, which is capable of efficiently performing initialization.

[0007] According to example embodiments, a method of controlling initialization of a first nonvolatile memory device included in a memory system includes: storing information data for initialization of the first nonvolatile memory device in the first nonvolatile memory device before assembling the memory system; moving the information data from the first nonvolatile memory device to a second nonvolatile memory device included in the memory system after assembling the memory system; and initializing the first nonvolatile memory device based on the information data stored in the second nonvolatile memory device.

[0008] According to an example embodiment, a memory system includes a first nonvolatile memory device configured to store information data for initialization of the first nonvolatile memory device before the first nonvolatile memory device is assembled in the memory system, a second nonvolatile memory device, and a controller configured to move the information data from the first nonvolatile memory device to the second nonvolatile memory device after the memory system is assembled, and to initialize the first nonvolatile memory device based on the information data stored in the second nonvolatile memory device.

[0009] According to an example embodiment, a method of controlling initialization of a NAND flash memory device included in a memory system includes providing information data for initialization of the NAND flash memory device through wafer testing after the NAND flash memory device is integrated in a wafer and before the NAND flash memory device is cut from the wafer, storing the information data in the NAND flash memory device before the memory system is assembled, moving the information data from the NAND flash memory device to a PRAM device included in the memory system after the memory system is assembled, initializing the NAND flash memory device based on the information data stored in the PRAM device, and converting a storage area of the NAND flash memory device associated with storing the information data to a storage area storing user data after the information data is moved from the NAND flash memory device to the PRAM device.

[0010] The method and memory system according to an example embodiment can effectively reduce initialization time of a first nonvolatile memory device by moving information data from the first nonvolatile memory device to a second nonvolatile memory device having a relatively higher read operation speed and using the information data read from the second nonvolatile memory device.

[0011] In addition, the method and memory system according to some example embodiments can effectively utilize storage space of a first nonvolatile memory device and reduce system cost by converting a storage area of the first nonvolatile memory device storing information data to a storage area storing user data. BRIEF DESCRIPTION OF DRAWINGS

[0012] Example embodiments of the present disclosure will become more fully understood from the detailed description given herein below, taken in conjunction with the accompanying drawings.

[0013] Figure 1 FIG. 1 is a flowchart illustrating a method of controlling initialization of a nonvolatile memory device according to an example embodiment.

[0014] Figure 2 FIG. 2 is a diagram for describing testing according to a manufacturing process of a memory system.

[0015] Figure 3 is a diagram showing a relationship between the test and a method of controlling initialization of a nonvolatile memory device according to an example embodiment. Figure 2

[0016] Figure 4 is a block diagram showing a memory system according to an example embodiment.

[0017] Figure 5 is a diagram for describing cost reduction of a memory system according to an example embodiment.

[0018] Figure 6 is a block diagram showing a first nonvolatile memory device included in a memory system according to an example embodiment.

[0019] Figure 7 is a block diagram showing an example of a memory cell array included in the first nonvolatile memory device of Figure 6

[0020] Figure 8 is a circuit diagram showing an equivalent circuit of a memory block in Figure 7

[0021] Figure 9 is a diagram showing a first nonvolatile memory device included in a memory system according to an example embodiment.

[0022] Figure 10 Figure 11 and Figure 12 are diagrams for describing example embodiments of a verification operation applicable to a method of controlling initialization of a nonvolatile memory device according to an example embodiment.

[0023] Figure 13 is a diagram showing an example embodiment of a resistance cell array of a second nonvolatile memory device included in a memory system according to an example embodiment.

[0024] Figure 14 and Figure 15 are diagrams showing example embodiments of a resistance memory cell included in the second nonvolatile memory device of Figure 13

[0025] Figure 16 is a diagram showing an example embodiment of a resistance cell array of a second nonvolatile memory device included in a memory system according to an example embodiment.

[0026] Figure 17 and Figure 18 are diagrams showing example embodiments of a resistance memory cell included in the second nonvolatile memory device of Figure 16 ​​​​​FIG. 1 is a diagram illustrating an example embodiment of a resistance memory cell in a resistance cell array.

[0027] Figure 19 FIG. 2 is a diagram illustrating a relationship between current and voltage of a resistance memory cell.

[0028] Figure 20 FIG. 3 is a diagram for describing a size of a storage area in which information data is stored.

[0029] Figure 21 Figure 22 Figure 23 FIG. 4 is a diagram illustrating a method of storing information data according to an example embodiment.

[0030] Figure 24 FIG. 5 is a flowchart illustrating a method of controlling initialization of a nonvolatile memory device according to an example embodiment.

[0031] Figures 25 to 29 FIG. 6 is a block diagram illustrating a memory system according to an example embodiment.

[0032] Figure 30 FIG. 7 is a block diagram illustrating a solid state disk or a solid state drive (SSD) according to an example embodiment. DETAILED DESCRIPTION

[0033] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. Like numbers refer to like elements throughout. Repeated description can be omitted.

[0034] Figure 1 FIG. 5 is a flowchart illustrating a method of controlling initialization of a nonvolatile memory device according to an example embodiment.

[0035] Referring to FIG. 1, Figure 1 Before assembling a memory system including a first nonvolatile memory device and a second nonvolatile memory device, information data for initialization of the first nonvolatile memory device can be stored in the first nonvolatile memory device in operation S100.

[0036] After assembling the memory system, the information data can be moved from the first nonvolatile memory device to the second nonvolatile memory device in operation S200.

[0037] The first nonvolatile memory device is initialized based on the information data stored in the second nonvolatile memory device in operation S300.

[0038] ​​The speed of a read operation of the second nonvolatile memory device can be higher than the speed of a read operation of the first nonvolatile memory device. In some example embodiments, the first nonvolatile memory device can be a NAND flash memory device as will be described below with reference to Figures 6 to 8 and the second nonvolatile memory device can be a Phase Change Random Access Memory (PRAM) device as will be described below with reference to Figures 13 to 19 .

[0039] As such, the method and memory system according to example embodiments can effectively reduce the initialization time of the first nonvolatile memory device by moving the information data from the first nonvolatile memory device to the second nonvolatile memory device having a fast read operation speed and using the information data read from the second nonvolatile memory device.

[0040] In some example embodiments, as will be described below with reference to Figure 5 , after moving the information data from the first nonvolatile memory device to the second nonvolatile memory device, the storage area of the first nonvolatile memory device storing the information data can be converted to a storage area storing user data.

[0041] As such, the method and memory system according to example embodiments can effectively utilize the storage space of the first nonvolatile memory device and reduce system cost by converting the storage area of the first nonvolatile memory device storing the information data to a storage area storing user data.

[0042] Figure 2 is a diagram for describing a test according to a manufacturing process of a memory system, and Figure 3 is a diagram illustrating Figure 2 a test and a method of controlling initialization of a nonvolatile memory device according to example embodiments.

[0043] Referring to Figure 2 and Figure 3 , a semiconductor wafer WF can include a plurality of semiconductor dies SD in which circuits corresponding to a nonvolatile memory device are integrated. Each semiconductor die SD can correspond to the first nonvolatile memory device NVM1 described above.

[0044] At the wafer stage before the semiconductor dies SD comprising the integrated circuit are cut from the wafer WF, in an operation Sll, a wafer test TSTl for estimating the optimization of the semiconductor dies SD on the wafer WF can be performed using a test device TDl. By the wafer test TSTl, in an operation S12, information about core timing, DC regulator, etc. can be obtained and information data DINF for the initialization of the first non-volatile memory device NVMl can be provided. In this way, the information data DINF can be provided by the wafer test TSTl after the first non-volatile memory device NVMl is integrated in the wafer WF and before the first non-volatile memory device NVMl is cut from the wafer WF.

[0045] Thereafter, each semiconductor die SD is cut from the wafer WF by a sawing process and a packaging process is performed to place the semiconductor dies SD in a package PKG.

[0046] At the single device stage, in an operation S21, an information data write operation IDW can be performed to store the information data DINF in the first non-volatile memory device NVMl and, in an operation S22, an information data read operation IDR can be performed to read the information data DINF from the first non-volatile memory device NVMl to initialize the first non-volatile memory device NVMl in the state of a single device. After the first non-volatile memory device NVMl is initialized, in an operation S23, single device tests TST2 and TST3 of the first non-volatile memory device NVMl can be performed using test devices TD2 and TD3 and, in an operation S24, special data DSPC for the operation of the first non-volatile memory device NVMl can be provided based on the single device tests TST2 and TST3. The single device tests can comprise a pre-package test TST2 and a post-package test TST3. For example, the special data DSPC can comprise bad block information of the first non-volatile memory device NVMl.

[0047] At the assembly stage, in an operation S31, the packaged first non-volatile memory device NVMl and the second non-volatile memory device NVM2 as described above can be mounted on a motherboard MB by, for example, a soldering process to assemble a memory system. Thereafter, in an operation S32, an information data read operation IDR can be performed to read the information data DINF from the first non-volatile memory device NVMl and, in an operation S33, an information data write operation IDW can be performed to store the information data DINF in the second non-volatile memory device NVM2. In this way, after the assembly of the memory system, the information data DINF can be moved and stored from the first non-volatile memory device NVMl to the second non-volatile memory device NVM2.

[0048] After the memory system is assembled, the system test TST4 can be performed using the test device TD4. When the memory system is powered on in operation S41, an information data read operation IDR can be performed in operation S42 to read information data DINF from the second nonvolatile memory device NVM2 and initialize the first nonvolatile memory device NVM1 in an assembled state. After the first nonvolatile memory device NVM1 is initialized, normal operations of the first nonvolatile memory device NVM1 can be performed in operation S43. In this way, by moving the information data DINF from the first nonvolatile memory device NVM1 to the second nonvolatile memory device NVM2 having a fast read operation speed and initializing the first nonvolatile memory device NVM1 using the information data DINF read from the second nonvolatile memory device NVM2, the initialization time of the first nonvolatile memory device NVM1 can be effectively reduced.

[0049] Figure 4 is a block diagram illustrating a memory system according to an example embodiment.

[0050] Reference will now be made to Figure 4 The memory system 1000 includes a first nonvolatile memory device NVM1, a second nonvolatile memory device NVM2, and a controller 1300. The first nonvolatile memory device NVM1 can be a NAND flash memory device and can be used as a main storage of the memory system 1000. The first nonvolatile memory device NVM1 can include a memory cell array 400 and an electrically fusible circuit 300, such as a latch circuit LAT. The NAND flash memory device will be further described with reference to Figures 6 to 8 The first nonvolatile memory device NVM1 can receive a command CMD and a control signal CTRL and exchange data DATA with the controller 1300.

[0051] The second nonvolatile memory device NVM2 can be a phase change random access memory (PRAM) device and can be used as a main storage, an auxiliary storage, a buffer memory, or a cache memory of the memory system 1000. The second nonvolatile memory device NVM2 can include a memory cell array 500. The PRAM device will be further described with reference to Figures 13 to 19 The second nonvolatile memory device NVM2 can receive a command CMD and a control signal CTRL and exchange data DATA with the controller 1300.

[0052] The controller 1300 can control overall operations of the first nonvolatile memory device NVM1 and the second nonvolatile memory device NVM2. According to an example embodiment, after the memory system 1000 is assembled, the controller 1300 can move the information data DINF and the special data DSPC from the first nonvolatile memory device NVM1 to the second nonvolatile memory device NVM2. The controller 1300 can initialize the first nonvolatile memory device NVM1 based on the information data DINF stored in the second nonvolatile memory device NVM2. The controller 1300 can set values of the electric fuse circuit 300 during the initialization process, and control operations of the first nonvolatile memory device NVM1 based on the set values of the electric fuse circuit 300.

[0053] Figure 5 is a diagram for describing cost reduction of a memory system according to an example embodiment.

[0054] Figure 5 The top of shows a state in which the information data DINF and the special data DSPC are stored in the first nonvolatile memory device NVM1 before the memory system is assembled, and the bottom of shows a state in which the information data DINF and the special data DSPC are moved and stored in the second nonvolatile memory device NVM2 after the memory system is assembled. Figure 5 The bottom of shows a state in which the information data DINF and the special data DSPC are moved and stored in the second nonvolatile memory device NVM2 after the memory system is assembled.

[0055] As shown in Figure 5 , after the information data DINF and the special data DSPC are moved to the second nonvolatile memory device NVM2, a storage area REG_R in which the first nonvolatile memory device NVM1 stores the information data DINF and the special data DSPC can be converted into a storage area REG_U that stores user data. For example, when the first nonvolatile memory device NVM1 is a NAND flash memory device, the reserved storage area REG_R can be converted into the storage area REG_U for user data by adding a physical address of the reserved area REG_R in a mapping table of metadata managed by a flash translation layer (FTL).

[0056] For example, in a 512 Gb NAND flash memory device, the reserved storage area REG_R includes about 16 memory blocks to store the information data DINF and the special data DSPC with respect to 912 memory blocks. By converting the storage area REG_R in which the first nonvolatile memory device NVM1 stores the information data DINF into the storage area REG_U that stores user data, the storage space of the first nonvolatile memory device can be effectively utilized, and the system cost can be reduced.

[0057] As described above, the information data DINF is data for initialization of the NAND flash memory device determined through testing before assembling the memory system. The information data DINF can be set in the electrically fusible circuit during a booting process or just after the booting process is completed. The information data DINF is different from data such as metadata determined according to use of the NAND flash memory device. Also, the information data DINF is different from data provided from a host device to control operation of the NAND flash memory device.

[0058] The information data DINF does not allow a single error, and thus the information data DINF can be stored as a plurality of write information data WSD in a plurality of storage regions as will be described below with reference to Figure 9 Even if the same information data DINF is stored in the plurality of storage regions, the read information data can be distorted and different from the write information data WSD due to bias of a programming operation, bias of a read operation, degradation of a memory cell, etc. Thus, when the read information data from one storage region has an uncorrectable error, the read information data can be loaded from another storage region.

[0059] The replication scheme of the information data DINF differs according to products. Generally, the information data DINF can include plane copy data for correcting a bit line defect and SSL copy data for correcting a String Selection Line (SSL) defect.

[0060] The initialization sequence or the IDR sequence can include: "sensing" to read out the information data from the memory cell to the page buffer circuit; "dump-down" to verify validity of the data stored in the page buffer circuit and store valid information data in a buffer; and "follow-up processing" to set an operating condition of the nonvolatile memory device based on the valid information data in the buffer. For example, the "follow-up processing" can include setting a level of an operating voltage, WOR scan to exclude a failed column from pass / fail operation, etc.

[0061] As the integration and memory capacity of the NAND flash memory device increase, the amount of the set data or the information data DINF can increase, and thus the initialization time will increase. In particular, in a NAND flash product employing a Plane Independent Read (PIR) scheme or a Plane Independent Core (PIC) scheme, a core operation is performed independently per plane, and the information data increases due to the set per plane, and the initialization time further increases. The booting time of the product is directly affected by the initialization time, and reducing the initialization time is important.

[0062] According to example embodiments, information data is moved from a first non-volatile memory device (such as a NAND flash memory device) to a second non-volatile memory device (e.g., a PRAM device) having a fast read operation speed, the information data read from the second non-volatile memory device is used to initialize the first non-volatile memory device, and thus initialization time can be effectively reduced.

[0063] Figure 6 is a block diagram illustrating a first non-volatile memory device included in a memory system according to an example embodiment.

[0064] Referring to Figure 6 , the first non-volatile memory device 1100 can include a plurality of memory planes 401, 402, and 403 each including a respective memory cell array and a page buffer circuit PBC. The first non-volatile memory device 1100 can also include a row decoder 430, a plurality of column gates Y-GATEs 411, 412, and 413, a data input-output circuit IOC, a control circuit 450, and a voltage generator 460.

[0065] Each memory cell array can be coupled to the row decoder 430 by a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL. In addition, each memory cell array can be coupled to a respective page buffer circuit PBC by a plurality of bit lines (not shown). Each memory cell array can include a plurality of memory cells coupled to the plurality of word lines WL and the plurality of bit lines (described in greater detail later). In some example embodiments, the memory cell array can be a three-dimensional memory cell array as will be described below with reference to Figure 8 In some example embodiments, each memory cell array can include a plurality of NAND strings or a plurality of cell strings oriented vertically such that at least one memory cell is located above another memory cell.

[0066] The control circuit 450 can receive a command from a host (not shown) via the data input-output circuit IOC. The command can include a read command, a write command, or an initialization command. The control circuit 450 can control the voltage generator 460 to generate a voltage for a read operation or a write operation based on the command received from the host. The control circuit 450 can also control the row decoder 430 to decode a row address included in the command received from the host. Figure 4The controller 1300 in the memory system 1000 receives a command (signal) CMD and an address (signal) ADD, and controls an erase, program, write, and / or read operation of the first nonvolatile memory device 1100 based on the command signal CMD and the address signal ADD. Based on the command signal CMD, the control circuit 450 can generate a control signal VCTL for controlling the voltage generator 460, and can generate a page buffer control signal PCTL for controlling the page buffer circuit PBC. Based on the address signal ADD, the control circuit 450 can generate a row address R_ADDR and a column address C_ADDR. The control circuit 450 can provide the row address R_ADDR to the row decoder 430, and provide the column address C_ADDR to the column gates 411, 412, and 413. The row decoder 430 can be coupled to the memory cell array through a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL.

[0067] During a program operation or a read operation, the row decoder 430 can determine that one of the word lines WL is a selected word line and that the remaining word lines WL other than the selected word line are unselected word lines based on the row address R_ADDR. Also, during the program operation or the read operation, the row decoder 430 can determine that one of the string select lines SSL is a selected string select line and that the remaining string select lines SSL other than the selected string select line are unselected string select lines based on the row address R_ADDR.

[0068] The voltage generator 460 can generate a word line voltage VWL required for an operation of the memory cell array of the first nonvolatile memory device 1100 based on the control signal VCTL. The voltage generator 460 can receive power from the memory controller. The word line voltage VWL can be applied to the word lines WL through the row decoder 430.

[0069] Each of the page buffer circuits PBC can be coupled to the memory cell array through a bit line. The page buffer circuit PBC can include a plurality of page buffers. The page buffer circuit PBC can temporarily store data to be programmed in a selected page or data read out from a selected page of the memory cell array.

[0070] Each of the data input-output circuits IOC can be coupled to a corresponding page buffer circuit PBC through a data line. During a program operation, the data input-output circuit IOC can receive data to be programmed in a selected page from the page buffer circuit PBC through the data line. During a read operation, the data input-output circuit IOC can output data read out from a selected page of the memory cell array to the page buffer circuit PBC through the data line. Figure 4The controller 1300 in the first non-volatile memory device receives the program data DATA and provides the program data DATA to the page buffer circuit PBC based on the column address C_ADDR received from the control circuit 450. During a read operation, the data input-output circuit can provide read data DATA that has been read from the memory cell array and stored in the page buffer circuit PBC to the controller 1300 based on the column address C_ADDR received from the control circuit 450.

[0071] The control circuit 450 can include a dump circuit DDC 100, a buffer BUFF 200, and a fuse circuit 300. The dump circuit 100 can be configured to perform a method of controlling initialization of a non-volatile memory device as described with reference to Figure 1 The buffer 200 can be implemented with volatile memory to store data required for the first non-volatile memory device 1100. During initialization of the first non-volatile memory device 1100, the value of the fuse circuit 300 can be set based on the information data DINF.

[0072] Figure 7 is a block diagram illustrating an example of a memory cell array included in the first non-volatile memory device of Figure 6 and Figure 8 is a circuit diagram illustrating an equivalent circuit of a memory block in Figure 7 .

[0073] As shown in Figure 7 , the memory cell array or memory plane 401 can include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz are selected by the row decoder 430 in the first non-volatile memory device. For example, the row decoder 430 can select a particular memory block BLK corresponding to a block address among the memory blocks BLK1 to BLKz. Figure 6

[0074] Figure 8 The memory block BLKi of the first non-volatile memory device can be formed in a three-dimensional structure (or a vertical structure) on a substrate. For example, a plurality of NAND strings or cell strings included in the memory block BLKi can be formed in a first direction D1 perpendicular to a second direction D2 and a third direction D3 (i.e., perpendicular to an upper surface of the substrate). Referring to Figure 8 , the memory block BLKi includes NAND strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the NAND strings NS11 to NS33 includes a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. In Figure 8 ​In the example, each of the NAND strings NS11 to NS33 is shown to include eight memory cells MC1 to MC8. However, example embodiments are not limited thereto. In some example embodiments, each of the NAND strings NS11 to NS33 can include any number of memory cells.

[0075] Each string selection transistor SST can be connected to a corresponding string selection line (one of SSL1 to SSL3). The plurality of memory cells MC1 to MC8 can be connected to a plurality of gate lines GTL1 to GTL8, respectively. The gate lines GTL1 to GTL8 can be word lines, and some of the gate lines GTL1 to GTL8 can be dummy word lines. Each ground selection transistor GST can be connected to a corresponding ground selection line (one of GSL1 to GSL3). Each string selection transistor SST can be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground selection transistor GST can be connected to a common source line CSL.

[0076] Word lines (e.g., WL1) having the same height (i.e., level) can be commonly connected, and the ground selection lines GSL1 to GSL3 and the string selection lines SSL1 to SSL3 can be separated. In Figure 8 In the example, the storage block BLKi is shown to be coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, example embodiments are not limited thereto.

[0077] Figure 9 is a diagram illustrating a first non-volatile memory device included in a memory system according to an example embodiment. Figure 9 One component associated with initialization is illustrated, and with Figure 6 , Figure 7 and Figure 8 Repetitive description is omitted.

[0078] Referring to Figure 9 , the first non-volatile memory device 1101 can include a first memory plane MPL1, a second memory plane MPL2, a dump circuit 101, and a buffer 200. The first non-volatile memory device 1101 can correspond to the first non-volatile memory device 1100 of Figure 6 illustrating details of the dump circuit 100 and the memory planes 401-403.

[0079] In Figure 6Data can be stored in or read from the first memory plane MPL1 and the second memory plane MPL2 under the control of the control circuit 450. Each of the first memory plane MPL1 and the second memory plane MPL2 can be divided into a region for storing the write information data WSD and a region for storing user data.

[0080] The first memory plane MPL1 can include a first memory cell array MCA1, a first row decoder RDEC1, and a first page buffer circuit PBC1. In a write operation, the first row decoder RDEC1 selects a word line of the first memory cell array MCA1. The first page buffer circuit PBC1 transfers data to the first memory cell array MCA1 through a bit line to store the data in memory cells connected to the selected word line. In a read operation, the first row decoder RDEC1 selects a word line of the first memory cell array MCA1, and the first page buffer circuit PBC1 senses and stores data stored in memory cells connected to the selected word line.

[0081] The second memory plane MPL1 can include a second memory cell array MCA2, a second row decoder RDEC2, and a second page buffer circuit PBC2. In a write operation, the second row decoder RDEC2 selects a word line of the second memory cell array MCA2. The second page buffer circuit PBC2 transfers data to the second memory cell array MCA2 through a bit line to store the data in memory cells connected to the selected word line. In a read operation, the second row decoder RDEC2 selects a word line of the second memory cell array MCA2, and the second page buffer circuit PBC2 senses and stores data stored in memory cells connected to the selected word line.

[0082] In this way, the write information data WSD can be stored in the first memory cell MC1 of the first memory plane MPL1 and the second memory cell MC2 of the second memory plane MPL2. Further, the write information data WSD can be stored in the third memory cell MC3 of the first memory plane MPL1 and the fourth memory cell MC4 of the second memory plane MPL2. A first sensing operation can be performed to sense the write information data WSD stored in the first memory cell MC1 and store first read information data RSD1 in the first page buffer circuit PBC1, and a second sensing operation can be performed to sense the write information data WSD stored in the second memory cell MC2 and store second read information data RSD2 in the second page buffer circuit PBC2. The first sensing operation and the second sensing operation can be performed simultaneously or sequentially.

[0083] When power is supplied to a system including the first nonvolatile memory device 1101, an initialization operation of the first nonvolatile memory device 1101 can be performed. Figure 6 The control circuit 450 in the first nonvolatile memory device 1101 can receive a power-on signal and perform a first sensing operation and a second sensing operation in response to the power-on signal to store first read information data RSD1 and second read information data RSD2 in the first page buffer circuit PBC1 and the second page buffer circuit PBC2, respectively.

[0084] Although, for ease of illustration and description, Figure 9 Two memory planes are shown, but the first nonvolatile memory device 1101 can include three or more memory planes.

[0085] The dump circuit 101 can include a first verify circuit VRFC1, a second verify circuit VRFC2, and dump control logic DDCL.

[0086] The first verify circuit VRFC1 is connected to the first page buffer circuit PBC1. The first verify circuit VRFC1 can verify the validity of the first read information data RSD1 to provide a first verify signal SVRF1 and first valid data DVAL1. The second verify circuit VRFC2 is connected to the second page buffer circuit PBC2. The second verify circuit VRFC2 can verify the validity of the second read information data RSD2 to provide a second verify signal SVRF2 and second valid data DVAL2.

[0087] The dump control logic DDCL can determine valid data DVAL as one of the first read information data RSD1 and the second read information data RSD2 based on a validity verification result of the first read information data RSD1 and a validity verification result of the second read information data RSD2. The validity verification result of the first read information data RSD1 and the validity verification result of the second read information data RSD2 can be represented by logic levels of the first verify signal SVRF1 and the second verify signal SVRF2, respectively. The valid data DVAL can correspond to one of the first valid data DVAL1 and the second valid data DVAL2. Also, the dump control logic DDCL can provide a write pointer WPTR or a write address indicating a location of the buffer 200 corresponding to the valid data DVAL currently provided to the buffer 200.

[0088] The dump control logic DDCL can generate a first enable signal EN1 and a second enable signal EN2 based on the first verify signal SVRF1 and the second verify signal SVRF2. The first verify circuit VRFC1 can be enabled in response to activation of the first enable signal EN1, and the second verify circuit VRFC2 can be enabled in response to activation of the second enable signal EN2.

[0089] If the dump operation based on the first read information data RSD1 and the second read information data RSD2 is determined to fail, a third sensing operation can be performed to sense the written information data WSD stored in the third memory cell MC3 and store third read information data RSD3 in the first page buffer circuit PBC1, and a fourth sensing operation can be performed to sense the written information data WSD stored in the fourth memory cell MC4 and store fourth read information data RSD4 in the second page buffer circuit PBC2.

[0090] As such, the third read information data RSD3 and the fourth read information data RSD4 can replace the first read information data RSD1 and the second read information data RSD2 in the first page buffer circuit PBC1 and the second page buffer circuit PBC2, and the above-described dump operation can be performed based on the third read information data RSD3 and the fourth read information data RSD4.

[0091] Figure 10 、 Figure 11 and Figure 12 are diagrams for describing a verification operation of a method applicable to controlling initialization of a non-volatile memory device according to an example embodiment.

[0092] For ease of explanation and description, Figure 10 、 Figure 11 and Figure 12 only one data unit of the original information data OSD and the written information data WSD is shown. It should be understood that the original information data OSD and the written information data WSD can include a plurality of data units.

[0093] In an initialization sequence of a non-volatile memory device, information data stored in a memory cell is read out, verified, and stored in a buffer. As described above, column repair information is reflected in a WOR scan phase, and column defects must be overcome by another scheme during a dump operation. To overcome column defects, written information data WSD can be obtained by copying each bit of original information data OSD into a plurality of copy bits, and the written information data WSD having the copy bits can be stored in the non-volatile memory device. In this case, Figure 9 Each of the first verification circuit VRFC1 and the second verification circuit VRFC2 in can include a majority voter circuit, wherein the majority voter circuit is configured to determine whether a number of bits having an equal value among a plurality of copy bits corresponding to each bit of the original information data OSD is equal to or greater than a reference number.

[0094] For example, as Figure 10As shown, each bit of the original information data OSD (e.g., in Figure 10 FFh) can be copied and expanded into eight replica bits WSD[i] to form the write information data WSD. The WSD is written, and then read as the RSD shown in Figure 11 Each of the eight bits corresponding to each bit RSD[i] of the read information data RSD can be compared with a reference number. For example, if the reference number is set to six, each bit RSD[i] can be determined to be valid (PASS) when six or more bits among the eight replica bits are identical, and each bit RSD[i] can be determined to be invalid (FAIL) when five or less bits among the eight replica bits are identical. For example, assuming that the replica bits of FFh shown in Figure 10 are written as WSD, and then read as RSD[i] shown in Figure 11 The top data shows RSD[i] that is valid (PASS) because only one bit is zero 0. The bottom data shows RSD[i] that is invalid (FAIL) because three bits are zero 0. In other words, in the top data, it can be determined that OSD[i] is 1, whereas in the bottom data, it cannot be determined that OSD[i] is 1.

[0095] As another example of the verification operation, Figure 12 an example embodiment of parity check bits C1~Ck using a Cyclic Redundancy Check (CRC) scheme is shown. The CRC scheme is known, and a detailed description thereof is omitted for the sake of brevity. In this case, each of the first and second verification circuits VRFC1 and VRFC2 can use the CRC parity check bits to verify the validity of the first and second read information data RSD1 and RSD2.

[0096] Figure 13 is a diagram showing an example embodiment of a resistance cell array of a second nonvolatile memory device included in a memory system according to an example embodiment.

[0097] Referring to Figure 13 , the memory cell array 501 includes a plurality of memory cells MC arranged at positions where word lines WL0~WLn and bit lines BL0~BLm cross. As will be described below with reference to Figure 14 and Figure 15As described, each memory cell MC can include a resistive element. When a corresponding word line is selected and enabled by the row selection circuit, a programming operation or a read operation can be performed with respect to the resistive memory cell connected to the selected word line. Each memory cell MC is coupled between one of the word lines WL0~WLn and one of the bit lines BL0~BLm. In this case, a bias voltage applied to each memory cell MC can be a voltage difference between the voltages applied to the bit line and the word line.

[0098] In some example embodiments, the memory cells MC can be implemented with a phase change random access memory (PRAM) cell using a phase change material, a resistance random access memory (RRAM) cell using a composite metal oxide of a variable resistance, a ferroelectric random access memory (FRAM) cell using a ferroelectric material, and a magneto-resistive random access memory (MRAM) cell using a ferromagnetic material. Such a resistive material of the resistive element can have a resistance value depending on the magnitude and / or direction of an applied current or voltage, and have a non-volatile characteristic of maintaining the resistance value even after power-off.

[0099] Figure 14 and Figure 15 is a diagram illustrating an example embodiment of a resistive memory cell included in a second non-volatile memory device of Figure 13 .

[0100] Referring to Figure 14 , the resistive memory cell MCa can include a resistive element CR1 connected between a word line WL and a bit line BL. Ends of the resistive element CR1 are coupled to the word line WL and the bit line BL, respectively, to selectively enable writing data to and / or reading data from the resistive memory cell MCa.

[0101] In some example embodiments, the resistive element CR1 can include: an Ovonic Threshold Switch (OTS) to selectively isolate the resistive memory cell MCa from conducting current; a first electrode E1; a resistive material RM to hold a state representing a particular stored data value; and / or a second electrode E2. In some example embodiments, the resistive element CR1 can be formed from a series of layers between or in other geometric relationship to the word line WL and the bit line BL. The resistive material or phase change material RM can be a material having an electrical property such as resistance, capacitance, or other electrical characteristic that can be changed by the application of energy such as, for example, heat, light, electric potential, or current. Various phase change material types having substantially different properties can be selected for the resistive material RM. In some example embodiments, the resistive material RM can include a chalcogenide material.

[0102] In some example embodiments, the resistive material RM can locally remain stable in one of two phases or a combination of two phases over a range of operating temperatures. The resistive material RM can exhibit different electrical properties in the amorphous phase than in the crystalline phase. In various example embodiments, the resistive material RM can include either or both of the following two properties: (a) it can locally exist in the amorphous phase for a long period of time such as years without crystallizing at room temperature, and / or (b) the amorphous phase can quickly crystallize if the temperature is raised.

[0103] In some example embodiments, the characteristics of the resistive material RM can depend on the type of material and / or the phase of the material used. In some example embodiments, the resistive material RM can be placed in a high resistance state or a low resistance state. In some example embodiments, the high resistance state can be referred to as a reset state and the low resistance state can be referred to as a set state; in other example embodiments, the terminology can be reversed. The second non-volatile memory device NVM2 according to example embodiments can not be limited to a particular resistive material RM.

[0104] The OTS can be used to access the resistive material RM during programming or reading of the resistive material RM. The OTS can include a bi-directional material to operate as a switch, where the switch is open or closed depending on a voltage applied across the bi-directional material. The open state can be a substantially non-conductive state, and the closed state can be a substantially conductive state.

[0105] Reference is made to Figure 15 The resistive memory cell MCb can include a resistive element CR2 and a diode DD in series between the word line WL and the bit line BL. Figure 15 The resistive memory cell MCb of Figure 14 The resistive memory cell MCb of is substantially the same as the resistive memory cell MCa of except that the OTS used for switching operations is replaced by the diode DD, and the repeated description is omitted.

[0106] Figure 16 is a diagram illustrating an example embodiment of a resistance cell array of a second nonvolatile memory device included in a memory system according to an example embodiment. Hereinafter, repeated descriptions with Figure 13 are omitted.

[0107] Referring to Figure 16 , the memory cell array 502 includes a plurality of memory cells MC arranged at positions where word lines WL0~WLn and bit lines BL0~BLm cross.

[0108] Each memory cell MC can include a cell transistor CT and a resistance element CR. In this case, a bias voltage applied to each memory cell MC can be a voltage difference between a voltage applied to a bit line and a voltage applied to a source line. The plurality of memory cells MC can be coupled to a common source line SL. In some example embodiments, the memory cell array 502 can be partitioned into at least two cell regions, and the cell regions can be coupled to different source lines.

[0109] Figure 17 and Figure 18 is a diagram illustrating an example embodiment of a resistance memory cell included in a resistance cell array of Figure 16 .

[0110] Referring to Figure 17 , the resistance memory cell MCc can include a resistance material RM2 and a cell transistor CT connected between a bit line BL and a source line SL. The cell transistor CT is selectively turned on in response to a voltage applied to a word line WL. If the cell transistor CT is turned on, a bias voltage corresponding to a voltage difference between the bit line BL and the source line SL can be applied to the resistance material RM2. Figure 17 The resistance element CR2 of Figure 15 is substantially the same as that of , and repeated descriptions are omitted.

[0111] Referring to Figure 18, the resistive memory cell MCd can include a resistive material RM3 and a cell transistor CT connected between the bit line BL and the source line SL. In response to a voltage applied to the word line WL, the cell transistor CT is selectively turned on. If the cell transistor CT is turned on, a bias voltage corresponding to a voltage difference between the bit line BL and the source line SL can be applied to the resistive material RM3. The resistive element CR3 can include a first electrode E1, a second electrode E2, a Non-Ohmic Material (NOM) between the electrode E1 and the electrode E2, and a Resistive Material (RM). In this case, a set state and a reset state can be programmed or written by applying opposite voltages to the electrode E1 and the electrode E2 and / or based on a direction of an induced current through the electrode E1 and the electrode E2. In other words, the set state and the reset state can be determined according to a polarity of the applied voltage and / or a direction of the induced current.

[0112] Figure 19 is a graph illustrating a relationship between a current and a voltage of a resistive memory cell.

[0113] In Figure 19 , the curve GRs indicates a cell current with respect to a bias voltage applied across the resistive memory cell MC when a resistive material in the resistive memory cell is in a set state, and the curve GRr represents a cell current with respect to a bias voltage applied across the resistive memory cell MC when the resistive material in the resistive memory cell is in a reset state.

[0114] In Figure 19 , a set threshold voltage VTHs of the set state corresponds to an inflection point in the curve GRs, where for a small change in a cell voltage, the resistive memory cell MC in the set state begins to exhibit a change in a cell current that is greater in magnitude than a change in the threshold current la. For example, in a low voltage or low electric field mode where a bias voltage applied across the resistive memory cell MC is less than the set threshold voltage VTHs, the resistive memory cell MC can be in an off state, where the off state exhibits lower conductivity and / or higher resistance than in an on state. The resistive memory cell MC can remain effectively non-conductive until a voltage at least equal to about the set threshold voltage VTHs is applied, where the voltage can switch the resistive memory cell MC to an on state, where the on state exhibits higher conductivity and / or lower resistance than in the off state. If a bias voltage greater than about the set threshold voltage VTHs is applied across the resistive memory cell MC, a current carried by the resistive memory cell MC can change in magnitude greater than a magnitude of a change in the applied bias voltage. As can be seen in Figure 19the high conductive region HCR of the curve GRs in FIG. 6A. Similarly, the reset threshold voltage VTHr can correspond to the inflection point in the curve GRr, where for a small change in the cell voltage, the resistance memory cell MC in the reset state begins to exhibit a very large change in the cell current that is larger than the threshold current la. If a bias voltage of at least about the reset threshold voltage VTHr is applied across the resistance memory cell, the current carried by the resistance memory cell MC can change in a magnitude that is larger than the magnitude of the change in the bias voltage, as Figure 19 the high conductive region HCR of the curve GRr in FIG. 6A.

[0115] In the following, an example embodiment will be described in which the first nonvolatile memory device NVM1 is a NAND flash memory device and the second nonvolatile memory device NVM2 is a PRAM device. The kind or type of the first nonvolatile memory device NVM1 and the second nonvolatile memory device NVM2 can be determined differently on the condition that the read speed of the second nonvolatile memory device NVM2 is higher than the read speed of the first nonvolatile memory device NVM1.

[0116] Figure 20 is a diagram for describing the size of a storage region in which information data is stored.

[0117] Referring to Figure 20 The information data DINF can include a plurality of sub-data D1-D4. Generally, a PRAM device is accessed in units of bytes, while a NAND flash memory device is accessed in units of data blocks that are much larger than bytes. Therefore, a large portion of the storage region in which data is stored can remain as an unused region.

[0118] As a result, the size of the storage region REG_R2 in which the second nonvolatile memory device (such as a PRAM device) stores the information data DINF is smaller than the size of the storage region REG_R1 in which the first nonvolatile memory device (such as a NAND flash memory device) stores the information data DINF.

[0119] Figure 21 , Figure 22 and Figure 23 is a diagram showing a method of storing information data according to an example embodiment.

[0120] Referring to Figure 21, the size of the information data DINF stored in the PRAM device is equal to the size of the information data DINF stored in the NAND flash memory device. In other words, before the memory system is assembled, the information data DINF can be repeatedly stored N times as N write information data WSD in the memory cells MC1~MC4 of the NAND flash memory device, where N is an integer greater than one (e.g., as shown in Figure 21 , the size of the information data DINF stored in the PRAM device is equal to the size of the information data DINF stored in the NAND flash memory device. In other words, before the memory system is assembled, the information data DINF can be repeatedly stored N times as N write information data WSD in the memory cells MC1~MC4 of the NAND flash memory device, where N is an integer greater than one (e.g., as shown in

[0121] In some example embodiments, when the information data DINF is moved from the NAND flash memory device to the PRAM device, the information data DINF can be read from the NAND flash memory device, and the read information data RSD read from the NAND flash memory device can be stored in the PRAM device without verifying the validity of the read information data RSD read from the NAND flash memory device along the first path PTH1. In this case, as indicated by the first path PTH1 in Figure 22 , the size of the information data DINF stored in the PRAM device is equal to the size of the information data DINF stored in the NAND flash memory device. In other words, before the memory system is assembled, the information data DINF can be repeatedly stored N times as N write information data WSD in the memory cells MC1~MC4 of the NAND flash memory device, where N is an integer greater than one (e.g., as shown in

[0122] In other example embodiments, when the information data DINF is moved from the NAND flash memory device to the PRAM device, the dump circuit DDC can read the information data DINF from the NAND flash memory device, correct errors of the read information data RSD from the NAND flash memory device by verifying the validity of the read information data RSD, and store the error-corrected information data RSD' in the PRAM device along the second path PTH2. In this case, as indicated by the second path PTH2 in Figure 22 , the size of the information data DINF stored in the PRAM device is equal to the size of the information data DINF stored in the NAND flash memory device. In other words, before the memory system is assembled, the information data DINF can be repeatedly stored N times as N write information data WSD in the memory cells MC1~MC4 of the NAND flash memory device, where N is an integer greater than one (e.g., as shown in

[0123] Referring to Figure 23 , the size of the information data DINF stored in the PRAM device is equal to the size of the information data DINF stored in the NAND flash memory device. In other words, before the memory system is assembled, the information data DINF can be repeatedly stored N times as N write information data WSD in the memory cells MC1~MC4 of the NAND flash memory device, where N is an integer greater than one (e.g., as shown inFigure 22 shown, N=4), and after the memory system is assembled, the information data DINF can be repeatedly stored M times as M write information data WSD in the memory cells MC1' and MC2' of the PRAM device, where M is an integer less than N (e.g., as shown, M=2). Figure 22

[0124] Figure 24 is a flowchart illustrating a method of controlling initialization of a nonvolatile memory device according to an example embodiment.

[0125] Referring to Figure 24 In operation S1000, information data for initialization of a NAND flash memory device can be provided through wafer testing after the NAND flash memory device is integrated in a wafer and before the NAND flash memory device is cut from the wafer.

[0126] In operation S2000, information data can be stored in a NAND flash memory device before a memory system including the NAND flash memory device and a phase change random access memory (PRAM) device is assembled.

[0127] In operation S3000, the information data can be moved from the NAND flash memory device to the PRAM device after the memory system is assembled.

[0128] In operation S4000, the NAND flash memory device can be initialized based on the information data stored in the PRAM device. Operations S2000, S3000, and S4000 can be substantially the same as operations S100, S200, and S300, respectively.

[0129] In operation S5000, a storage area of the NAND flash memory device in which the information data is stored can be converted to a storage area in which user data is stored after the information data is moved from the NAND flash memory device to the PRAM device.

[0130] Figures 25 to 29 is a block diagram illustrating a memory system according to an example embodiment. Hereinafter, repeated descriptions are omitted and only differences from the memory system 1000 of Figure 4 Figure 4

[0131] Referring to Figure 25 ​​​The memory system 2000 can include a NAND flash memory device 2100 corresponding to the first nonvolatile memory device NVM1, a PRAM device 2200 corresponding to the second nonvolatile memory device NVM2, and a controller 2300. The PRAM device 2200 can output a control signal CTRL and data DATA to the NAND flash memory device 2100. For example, the PRAM device 2200 can provide information data DINF as the data DATA to the NAND flash memory device 2100. The PRAM device 2200 can output the control signal CTRL (e.g., a data strobe signal DQS) to the NAND flash memory device 2100.

[0132] Referring to FIG. 4, Figure 26 The memory system 3000 can include a NAND flash memory device 3100 corresponding to the first nonvolatile memory device NVM1, a PRAM device 3200 corresponding to the second nonvolatile memory device NVM2, and a controller 3300. The NAND flash memory device 3100 can include a PRAM controller 3120, and the PRAM device 3200 can be operated under control of the PRAM controller 3120. The PRAM device 3200 can not communicate with the controller 3300. That is, the PRAM device 3200 can receive a control signal CTRL and a command CMD from the NAND flash memory device 3100, and can exchange data with the NAND flash memory device 3100.

[0133] Referring to FIG. 4, Figure 27 The memory system 4000 can include a NAND flash memory device 4100 corresponding to the first nonvolatile memory device NVM1, a PRAM device 4200 corresponding to the second nonvolatile memory device NVM2, and a controller 4300. The controller 4300 can control the NAND flash memory device 4100 and the PRAM device 4200 via a common bus. The NAND flash memory device 4100 and the PRAM device 4200 can communicate with the controller 4300 in a time-division scheme. Information data DINF stored in the PRAM device 4200 can be directly transferred to the NAND flash memory device 4100 without passing through the controller 4300.

[0134] Referring to FIG. 4, Figure 28The memory system 5000 can include a NAND flash memory device 5100 corresponding to the first non-volatile memory device NVM1, a PRAM device 5200 corresponding to the second non-volatile memory device NVM2, and a controller 5300. The NAND flash memory device 5100 can communicate with the controller 5300 via a plurality of channels CH1 to CHk. Each channel can be connected with a plurality of NAND flash memory chips.

[0135] Referring to Figure 29 The memory system 6000 can include a plurality of memory units MU and a controller 6300. The memory units MU can communicate with the controller 6300 via a plurality of channels CH1 to CHk. Each of the memory units MU can include at least one NAND flash memory device 6100 and a PRAM device 6200. In each memory unit MU, the NAND flash memory device 6100 and the PRAM device 6200 can communicate with the controller 6300 via a common channel. In each memory unit MU, the NAND flash memory device 6100 and the PRAM device 6200 can occupy the common channel in a time-division scheme.

[0136] Figure 30 is a block diagram illustrating a solid state disk or drive (SSD) according to an example embodiment.

[0137] Referring to Figure 30 The SSD 7000 includes a plurality of non-volatile memory devices (NVM) 7100 and an SSD controller 7200.

[0138] The non-volatile memory devices 7100 can be configured to receive a high voltage VPP. The non-volatile memory devices 7100 can be NAND flash memory devices corresponding to the first non-volatile memory devices as described above.

[0139] The SSD controller 7200 is connected to the non-volatile memory devices 7100 through a plurality of channels CH1 to CHi, respectively. The SSD controller 7200 includes one or more processors 7210, a buffer memory 7220, an error correction code (ECC) circuit 7230, a host interface 7250, a non-volatile memory interface 7260, and a PRAM device corresponding to the second non-volatile memory device NVM2 as described above.

[0140] The buffer memory 7220 stores data used to drive the SSD controller 7200. The ECC circuit 7230 calculates error correction code values for data to be programmed at write operations and uses the error correction code values to correct errors in read data at read operations. In a data recovery operation, the ECC circuit 7230 corrects errors in data recovered from the non-volatile memory device 7100.

[0141] According to example embodiments, the processor 7210 can move information data from the non-volatile memory device 7100 to the PRAM device 7270 after the memory system is assembled and initialize the non-volatile memory device 7100 based on the information data stored in the PRAM device 7270.

[0142] Although Figure 30 Example embodiments are shown in which the SSD controller 7200 includes one PRAM device 7270, but the location of the PRAM device, the number of PRAM devices, and the interface of the PRAM device to other components can be implemented differently as described with reference to Figures 25 to 29

[0143] ​Some of the components of the aforementioned memory system, such as controllers 1300, 2300, 3300, 4300, 5300, and 6300, and the control circuit 450 of the first non-volatile memory including the dump circuit 100 including verification circuits VRFC1 and VRFC2 and dump control logic DDCL, may be implemented as processing circuits (such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination of these and memory). For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like. The processing circuit may be a dedicated processing circuit configured to, after assembling the memory system 1000, move information data DINF and special data DSPC from a storage area of ​​the first nonvolatile memory device NVM1 to the second nonvolatile memory device NVM2, initialize the first nonvolatile memory device NVM1 based on the information data DINF stored in the second nonvolatile memory device NVM2 by setting a value of an e-fuse circuit, and control the operation of the first nonvolatile memory device NVM1 based on the set value of the e-fuse circuit 300. In some example embodiments, the dedicated processing circuit may also convert a storage area of ​​the first nonvolatile memory device storing information data into a storage area for storing user data. In this way, the processing circuit may improve the operation of the memory system by effectively reducing the initialization time of the first nonvolatile memory device. Furthermore, by converting the storage area of ​​the first nonvolatile memory device storing information data into a storage area for storing user data, the storage space of the first nonvolatile memory device may be efficiently utilized, thereby reducing system costs.

[0144] Example embodiments of the present inventive concept can be applied to any electronic device and system. For example, the present inventive concept can be applied to devices such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash storage (UFS), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, and the like.

[0145] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the inventive concept.

Claims

1. A method of controlling initialization of a first non-volatile memory device included in a memory system, the method comprising: Before assembling the memory system, storing information data for initialization of the first non-volatile memory device in the first non-volatile memory device; After assembling the memory system, moving the information data from the first nonvolatile memory device to a second nonvolatile memory device included in the memory system; as well as initializing the first nonvolatile memory device based on the information data stored in the second nonvolatile memory device, The speed of a read operation of the second non-volatile memory device is greater than the speed of a read operation of the first non-volatile memory device.

2. The method according to claim 1, wherein The first non-volatile memory device is a NAND flash memory device, and the second non-volatile memory device is a phase change random access memory (PRAM) device.

3. The method according to claim 1, further comprising: After the information data is moved from the first nonvolatile memory device to the second nonvolatile memory device, a storage area of ​​the first nonvolatile memory device associated with storing the information data is converted into a storage area for storing user data.

4. The method according to claim 1, wherein The moving moves the information data to a storage area of ​​the second nonvolatile memory device such that a size of the storage area of ​​the second nonvolatile memory device storing the information data is smaller than a size of a storage area of ​​the first nonvolatile memory device associated with storing the information data.

5. The method according to claim 1, wherein The moving moves the information data to the second nonvolatile memory device so that a size of the information data stored in the second nonvolatile memory device is equal to a size of the information data previously stored in the first nonvolatile memory device.

6. The method according to claim 1, wherein The storing includes repeatedly storing the information data N times in the first nonvolatile memory device before assembling the memory system, where N is an integer greater than one, and The moving includes repeatedly storing the information data N times in the second nonvolatile memory device after assembling the memory system.

7. The method according to claim 1, wherein The moving moves the information data to the second nonvolatile memory device such that a size of the information data stored in the second nonvolatile memory device is smaller than a size of the information data previously stored in the first nonvolatile memory device.

8. The method according to claim 1, wherein The storing includes repeatedly storing the information data N times in the first nonvolatile memory device before assembling the memory system, where N is an integer greater than one, and The moving includes repeatedly storing the information data M times in the second nonvolatile memory device after assembling the memory system, where M is an integer smaller than N.

9. The method according to claim 1, wherein Moving the information data includes: reading the information data from the first nonvolatile memory device; and The information data read from the first nonvolatile memory device is stored in the second nonvolatile memory device without verifying validity of the information data read from the first nonvolatile memory device.

10. The method according to claim 1, wherein Moving the information data includes: reading the information data from the first non-volatile memory device; verifying validity of the information data read from the first nonvolatile memory device to generate error-corrected information data; and The error-corrected information data is stored in the second nonvolatile memory device.

11. The method according to claim 1 , further comprising: The information data is received through a wafer test after the first nonvolatile memory device is integrated in a wafer and before the first nonvolatile memory device is cut from the wafer.

12. The method according to claim 11, further comprising: After dicing the first nonvolatile memory device from the wafer and before assembling the first nonvolatile memory device in the memory system, pre-assembly initializing the first nonvolatile memory device based on the information data stored in the first nonvolatile memory device; After pre-assembly initialization of the first non-volatile memory device, performing a single device test of the first non-volatile memory device; as well as Based on the result of the single device test, first data is provided for operation of the first non-volatile memory device.

13. The method according to claim 12, further comprising: The first data is stored in the second non-volatile memory device.

14. The method according to claim 13, wherein Storing the first data includes: storing the first data from a test device in the first non-volatile memory device before assembling the memory system; and After assembling the memory system, the first data is moved from the first nonvolatile memory device to the second nonvolatile memory device.

15. A memory system comprising: a first nonvolatile memory device configured to store information data for initialization of the first nonvolatile memory device before the first nonvolatile memory device is assembled in the memory system; a second non-volatile memory device; as well as The controller is configured to After assembling the memory system, moving the information data from the first nonvolatile memory device to the second nonvolatile memory device, and initializing the first nonvolatile memory device based on the information data stored in the second nonvolatile memory device, The speed of a read operation of the second non-volatile memory device is greater than the speed of a read operation of the first non-volatile memory device.

16. The memory system according to claim 15, wherein: The first non-volatile memory device is a NAND flash memory device, and the second non-volatile memory device is a phase change random access memory (PRAM) device.

17. The memory system according to claim 15, wherein: The memory system is configured to communicate with a test device configured to provide the information data through a wafer test after the first nonvolatile memory device is integrated in a wafer and before the first nonvolatile memory device is cut from the wafer.

18. A method of controlling initialization of a NAND flash memory device included in a memory system, the method comprising: providing information data for initialization of the NAND flash memory device through wafer testing after the NAND flash memory device is integrated into a wafer and before the NAND flash memory device is cut from the wafer; Before assembling the memory system, storing the information data in the NAND flash memory device; After assembling the memory system, moving the information data from the NAND flash memory device to a PRAM device included in the memory system; initializing the NAND flash memory device based on the information data stored in the PRAM device; as well as After the information data is moved from the NAND flash memory device to the PRAM device, a storage area of ​​the NAND flash memory device associated with storing the information data is converted into a storage area storing user data.

19. The method according to claim 18, wherein Providing the information data includes: The wafer test is performed after the NAND flash memory devices are integrated in the wafer and before the NAND flash memory devices are cut from the wafer.

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