Semiconductor structure and method for forming the same

Abstract

An embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising: receiving a structure having a dielectric layer above a conductive component; etching a hole through the dielectric layer and exposing the conductive component; depositing a first metal into the hole and directly contacting the dielectric layer and the conductive component; depositing a second metal over the first metal; and annealing the structure including the first metal and the second metal. An embodiment of the present application also provides a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing the ICs.

[0003] For example, via plugs with bulk metals such as tungsten (W) with barrier or seed layers such as titanium, titanium nitride, and tantalum nitride have traditionally been used as via plugs in IC interconnects. As scaling down continues, the via plugs become smaller and smaller, and conventional via plugs exhibit increased resistance and become unsuitable in some cases. Improvements are needed in these areas. Summary of the invention

[0004] An embodiment of the present application provides a method for forming a semiconductor structure, comprising: receiving a structure having a dielectric layer above a conductive component; etching a hole through the dielectric layer and exposing the conductive component; depositing a first metal into the hole and directly contacting the dielectric layer and the conductive component; depositing a second metal above the first metal; and annealing the structure including the first metal and the second metal.

[0005] An embodiment of the present application provides a method for forming a semiconductor structure, comprising: receiving a structure having a dielectric layer above a conductive component; etching a hole through the dielectric layer and exposing the conductive component; depositing a first metal into the hole and directly contacting the dielectric layer and the conductive component; injecting ions of a second metal into the first metal; and annealing the structure including the first metal and the second metal.

[0006] An embodiment of the present application provides a semiconductor structure, comprising: a conductive component; a dielectric layer located above the conductive component; and a plug located above the conductive component and at least partially surrounded by the dielectric layer, wherein the plug comprises a first metal and a second metal different from the first metal, wherein the second metal is distributed along an interface between the first metal and the dielectric layer.

[0007] Embodiments of the present application provide methods and structures for a non-blocking plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0009] Figure 1A shows a cross-sectional view of a semiconductor structure constructed in accordance with aspects of the present invention; Figure 1B , Figure 1C , and 1D show Figure 1A Examples of semiconductor structures;

[0010] Figure 2 A method for forming a Figures 1A to 1D A flow chart of a method for forming a semiconductor structure as shown;

[0011] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E ,and Figure 3F According to some embodiments, Figure 2 cross-sectional views of a semiconductor structure during various fabrication steps of the method;

[0012] Figure 4 A method for forming a Figures 1A to 1D A flowchart of another method of forming a semiconductor structure is shown;

[0013] Figure 5A , Figure 5B , Figure 5C ,and Figure 5D According to some embodiments, Figure 4 cross-sectional views of a semiconductor structure during various fabrication steps of the method;

[0014] Figure 6 A method for forming a Figures 1A to 1D A flowchart of another method of forming a semiconductor structure is shown;

[0015] Fig. 7A , Figure 7B ,and Figure 7C According to some embodiments, Figure 6 cross-sectional views of a semiconductor structure during various fabrication steps of the method;

[0016] Fig. 8A and Figure 8B A cross-sectional view of a semiconductor structure of the present invention is shown. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0018] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Further, when "about," "approximately," etc. are used to describe a number or a range of numbers, unless otherwise stated, the term is intended to cover numbers within + / - 10% of the described number. For example, the term "about 5nm" covers a size range of 4.5nm to 5.5nm.

[0019] The present invention relates generally to semiconductor devices and manufacturing methods, and more specifically to plugs for interconnecting conductive features between different layers of an integrated circuit (IC). Plugs are sometimes referred to as vias, via plugs, or contact plugs. Conventional plugs have a barrier layer or seed layer surrounding a bulk metal layer. The barrier layer protects the bulk metal layer from surrounding structures such as (some) interlayer dielectric layers. As ICs continue to scale down, plugs are also scaled down, so that the volume of bulk metal in the plug becomes smaller. Therefore, the resistance of conventional plugs increases. As the critical dimension of the plug is reduced to 10nm or less, a new plug structure is needed. An object of the present invention is to provide a non-blocking plug with lower resistance than conventional plugs. As the name implies, a non-blocking plug has no barrier layer or seed layer between the (some) metal layers of the plug and the structures surrounding the (some) metal layers of the plug. Therefore, for the same via, a non-blocking plug can provide a larger metal volume than a conventional plug, thereby providing a lower resistance than a conventional plug. In order to stabilize the interface between the non-blocking plug and the surrounding structure, the non-blocking plug of the present invention includes two metals. The first metal is deposited to fill the through hole, and the second metal is introduced into the grain boundaries between multiple grains of the first metal, and / or into the interface between the first metal and those surrounding structures. The role of the second metal is to stabilize (or pin) the grains of the first metal and increase the thermal stability of the non-blocking plug for subsequent processes. Without the second metal, the non-blocking plug may deform (such as pitting or grooves) during the subsequent heat treatment process, which will cause quality and reliability problems of the IC.

[0020] Figure 1A FIG. 1 is a cross-sectional view of a semiconductor device (or semiconductor structure) 100 constructed according to aspects of the present invention. Figure 1A, the device 100 includes a substrate 102, which may include a silicon substrate (e.g., a silicon wafer) or another semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, indium aluminum phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide; or a combination thereof. In an embodiment, the substrate 102 may include indium tin oxide (ITO) glass, include a silicon-on-insulator (SOI) substrate, be strained and / or stressed to improve performance, include epitaxial regions, doped regions, and / or include other suitable features and layers. In particular, the substrate 102 may include active regions (e.g., fin-shaped active regions) and isolation structures as well as various active and passive devices, such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs such as FinFETs and gate-all-around (GAA) FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, static random access memory (SRAM) cells, other memory cells, resistors, capacitors, and inductors.

[0021] Still reference Figure 1A , the semiconductor structure 100 also includes a conductive component 112 located above the substrate 102. In some embodiments, the conductive component 112 can be part of an electrode of a transistor, such as a source electrode, a drain electrode, or a gate electrode. The source (or drain) electrode can include n-type doped silicon for NFET, p-type doped silicon germanium for PFET, or other suitable materials. The source (or drain) electrode can also include a silicide, such as nickel silicide, titanium silicide, cobalt silicide, or other suitable silicide or germanium silicide. The gate electrode can include aluminum, tungsten, cobalt, and / or other suitable materials. In some embodiments, the conductive component 112 can be part of a contact component such as a source contact, a drain contact, or a gate contact, and can include cobalt, tungsten, ruthenium, rhodium, iridium, molybdenum, other metals, metal nitrides such as titanium nitride or tantalum nitride, or combinations thereof. In some embodiments, the conductive feature 112 may be part of an interconnect structure, such as a metal line or a metal plug, and may include copper, cobalt, tungsten, ruthenium, rhodium, iridium, molybdenum, other metals, metal nitrides such as titanium nitride or tantalum nitride, or combinations thereof.

[0022] In the present embodiment, the semiconductor structure 100 further includes an etch stop layer 114 located above the conductive component 112. The etch stop layer 114 may include silicon nitride, aluminum oxide, silicon carbide, silicon oxycarbide, or other suitable materials. The etch stop layer 114 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition techniques. The etch stop layer 114 is optional and may be omitted in some embodiments.

[0023] Still reference Figure 1A , the semiconductor structure 100 further includes a dielectric layer 116 located above the etch stop layer 114. The dielectric layer 116 may include a dielectric material (e.g., a semiconductor oxide such as silicon dioxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, etc.), a low-k dielectric material, tetraethoxysilane (TEOS), spin-on glass (SOG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), xerogel, aerogel, amorphous fluorinated carbon, polyparaxylene, and / or other suitable dielectric materials. The dielectric layer 116 may be formed by plasma enhanced CVD (PECVD), flowable CVD (FCVD), or other suitable methods.

[0024] Still reference Figure 1A , the semiconductor structure 100 also includes a non-blocking plug 110. The plug 110 is surrounded by a conductive component 112, an etch stop layer 114, and a dielectric layer 116 on its bottom and sidewalls, and is in direct contact with it. In the present embodiment, the plug 110 includes a first metal 118 and a second metal 120. The first metal 118 includes one or more grains, two grains 118a and 118b are shown in this example. The boundary between the grains of the first metal 118 is represented by a dotted line 118-GB. In some embodiments, the depth "D" of the grain boundary 118-GB from the top surface of the plug 110 is equal to or less than 60% of the height "H" of the plug 110, both of which are measured along the "Y" direction. For example, in some embodiments, the ratio of D to H can be in the range of 20% to 50%. The interface between the first metal 118 and the surrounding structures 112, 114 and 116 is represented by a dotted line 118-INT. In this embodiment, the second metal 120 is distributed along the grain boundary 118-GB and the interface 118-INT. In some embodiments, the plug 110 has only one grain of the first metal 118, for example, the grain 118a; the second metal 120 is distributed along the interface 118-INT. Figure 1A, but the second metal 120 may also be distributed within (some) grains of the first metal 118. In some embodiments, the ratio of the second metal 120 to the first metal 118 along the grain boundaries 118-GB and the interfaces 118-INT is higher than the ratio of the second metal 120 to the first metal 118 inside the second metal 118. For example, the ratio along the grain boundaries 118-GB and the interfaces 118-INT may be 10% to 90%, while the ratio inside the grains of the second metal 118 may be 5% to 40%. The second metal 120 is used to stabilize the grain boundaries 118-GB and the interfaces 118-INT during thermal treatment. Without the second metal 120, the first metal 118 may deform along the grain boundaries 118-GB and / or the interfaces 118-INT, causing quality and reliability issues.

[0025] In some embodiments, the second metal 120 has a lower melting point than the first metal 118, so that the second metal 120 can flow and diffuse along the grain boundary 118-GB and the interface 118-INT during the annealing process. For further embodiments of this embodiment, the second metal 120 can be introduced into the plug 110 by depositing the second metal 120 above or below the first metal 118 and then performing an annealing process. In one example, the first metal 118 includes ruthenium, and the second metal 120 includes cobalt, nickel, or rhodium. In another example, the first metal 118 includes one of ruthenium, iridium, molybdenum, and tungsten; the second metal 118 includes a metal different from the first metal and having a lower melting point, such as cobalt, nickel, or rhodium.

[0026] In some embodiments, the second metal 120 may have a lower or higher melting point than the first metal 118. For further embodiments, the second metal 120 may be introduced into the plug 110 by implanting ions of the second metal 120 into the first metal 118, followed by an annealing process so that the implanted species may diffuse along the grain boundary 118-GB and the interface 118-INT. In one example of this embodiment, the first metal 118 includes ruthenium, and the second metal 120 includes one of cobalt, nickel, rhodium, iridium, molybdenum, and tungsten. Other materials for the first metal and the second metal are also possible.

[0027] Figure 1B An example of the structure 100 is shown, in which the plug 110 is disposed above the source / drain. In other words, in this example, the plug 110 is a source / drain contact. Figure 1B, the conductive feature 112 is a transistor source / drain region (also referred to as source / drain region 112) of the structure 100. The source / drain region 112 is adjacent to the gate structure 111. A gate sidewall spacer 113 is disposed over the sidewall of the gate structure 111. A contact etch stop layer 114 is disposed over the source / drain region 112 and the gate sidewall spacer 113. In some embodiments, the source / drain region 112 may include a lightly doped source / drain (LDD) feature, a heavily doped source / drain (HDD) feature, and / or an epitaxially grown semiconductor feature. Each gate structure 111 includes a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include silicon oxide (SiO2) or a high-k dielectric material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal oxides, or combinations thereof. The gate electrode layer may include polysilicon, or one or more metals, such as titanium (Ti), aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials. The gate sidewall spacer 113 may include one or more dielectric materials, such as silicon dioxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof.

[0028] Figure 1C and 1D Two examples of the structure 100 are shown, in which the plug 110 is disposed over a source / drain electrode including a silicide feature 112-1. The silicide feature 112-1 may include nickel silicide, titanium silicide, cobalt silicide, or other suitable silicides or germanium silicides, and may be formed by depositing a metal or metal compound over the source / drain 112 including one or more semiconductor materials, annealing the structure to react the metal or metal compound with the one or more semiconductor materials, and removing the unreacted metal or metal compound. Figure 1C to Figure 1D Other aspects of Figure 1B The interface between the first metal 118 and the silicide feature 112 - 1 is a portion of the interface 118 -INT. Figure 1C An example is shown in which the silicide feature 112 - 1 is formed before the etch stop layer 114 is formed, and the silicide feature 112 - 1 covers the entire top surface of the source / drain 112 . Figure 1D An example is shown in which the silicide feature 112 - 1 is formed after the etch stop layer 114 and the dielectric layer 116 are formed, and the silicide feature 112 - 1 covers a portion of the top surface of the source / drain 112 exposed during the contact hole formation.

[0029] Figure 2A flow chart of a method 200 for forming a semiconductor device 100 according to some embodiments is shown. The method 200 is merely an example and is not intended to limit the content of the present invention beyond the scope expressly recited in the claims. Additional operations may be provided before, during, and after the method 200, and some of the operations described may be replaced, removed, or moved for additional embodiments of the method. FIG. 3A to FIG. 3F The method 200 is described with reference to FIG. 2 , which shows various cross-sectional views of the semiconductor device 100 during fabrication steps according to the method 200 .

[0030] refer to Figure 2 At operation 202, method 200 provides (or is provided with) a structure (or workpiece) 100 having a substrate, a conductive component located above the substrate, an optional etch stop layer located above the conductive component, and a dielectric layer located above the etch stop layer. An example of structure 100 is shown in FIG. Figure 3A Reference Figure 3A , structure 100 includes a substrate 102, a conductive feature 112 located above substrate 102, an etch stop layer 114 located above conductive feature 112, and a dielectric layer 116 located above etch stop layer 114. Exemplary materials and compositions of the various layers 102, 112, 114, and 116 have been described with reference to Figure 1A For the sake of simplicity, this is omitted. Figure 3A 1 , but the substrate 102 may include active devices (e.g., transistors) and / or passive devices. The conductive feature 112 may be a source electrode, a drain electrode, a gate electrode, a source contact, a drain contact, a gate contact, an interconnect line, an interconnect via plug, or other suitable conductive element of an IC.

[0031] At operation 204, method 200 etches structure 100 to form vias therein. An example of the resulting structure 100 is shown in FIG. Figure 3B Reference Figure 3B, forming a through hole 117 by etching the dielectric layer 116 and the etch stop layer 114 to expose the conductive component 112. In the present embodiment, the method 200 also partially etches the conductive component 112. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, the dry etching process may be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr, and / or CHBR3), an iodine-containing gas, other suitable gases, and / or plasma, and / or combinations thereof. For example, the wet etching process may include etching in the following materials: dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. In some embodiments, operation 204 may include two etching operations. The first etching operation is selective to (some) materials of the dielectric layer 116 and stops at the etch stop layer 114, and the second etching operation is selective to (some) materials of the etch stop layer 114. Operation 204 may also include a post-etch cleaning process to clean the via 117 and prepare for a subsequent metal filling process. For example, the cleaning process may be a wet cleaning process, such as an SC1 (standard clean 1) or SC2 (standard clean 2) process. In some embodiments, the critical dimension of the via 117 (e.g., the dimension along the "X" direction, e.g., measured at the lower portion of the via 117) is about 10 nm or less, which may be too small to be filled with a conventional plug with a barrier layer.

[0032] At operation 206, method 200 deposits a first metal layer 118 into via 117. An example of the resulting structure 100 is shown in FIG. Figure 3C . The first metal layer 118 substantially fills the through hole 117. Unlike conventional processes, method 200 does not deposit a barrier layer before filling the through hole 117 with the first metal layer 118. This is because the through hole 117 is very small and does not have enough space to accommodate both the barrier layer and the metal filling layer while still providing low resistance. In various embodiments, the first metal layer 118 may include ruthenium, rhodium, iridium, molybdenum, tungsten, or another suitable metal for low resistance and hole filling capability. Operation 206 may use any suitable deposition technique, such as CVD, PVD, and plating (e.g., electrochemical plating or ECP).

[0033] In various embodiments, the deposition (or growth) of the first metal 118 starts from the bottom of the via 117 and from the sidewalls of the via 117. This causes multiple grains of the first metal 118 to grow from different sites and in different directions. These grains eventually meet each other in the via 117, forming various grain boundaries 118-GB. Figure 3C In the example shown, the first metal 118 has four grains: 118a, 118b, 118c, and 118d, with example boundaries between them shown by dashed line 118-GB. In various embodiments, the grains of the first metal 118 can be arranged from bottom to top, side by side, or a mixture of bottom to top and side by side within the via 117. Fig. 8A and 8B Some examples of first metal 118 having multiple grains in via 117 after operation 212 (CMP) are shown. In particular, Fig. 8A Three dies 118a, 118b, and 118c are shown stacked from bottom to top. Figure 8B Five grains of a mixed configuration from bottom to top and side by side are shown. Moreover, depending on the metal type and deposition conditions, the grains of the first metal 118 can have different sizes and / or shapes. For example, when the first metal 118 is mainly ruthenium, the grains at a deposition temperature of 400°C or less are smaller than the grains at a deposition temperature of more than 400°C. When the grains are larger, they tend to be stacked from bottom to top in the through hole 117. When the grains are smaller, they tend to be distributed from bottom to top while being side by side. Figure 3C Also shown is an interface 118-INT between the first metal 118 and surrounding structures, including, for example, a dielectric layer 116, an etch stop layer 114, and a conductive component 112. The inventors of the present invention have discovered that if not properly treated, the grain boundaries 118-GB and the interface 118-INT are susceptible to manufacturing defects, such as pitting defects or slotting defects caused by subsequent heat treatment. For example, the grains of the first metal 118 may shrink or move, and the material of the dielectric layer 116 (e.g., silicon dioxide) may diffuse into the grain boundaries 118-GB, each of which is undesirable. The method 200 of the present invention treats the first metal 118 to avoid or reduce the above-mentioned problems.

[0034] At operation 208, method 200 ( Figure 2 ) A second metal 120 is deposited over the first metal 118. An example of the resulting structure 100 is Figure 3D. In the present embodiment, the second metal 120 has a lower melting point than the first metal 118. For example, the first metal 118 may include one of ruthenium, iridium, molybdenum, and tungsten; the second metal 120 may include a metal different from the first metal 118 and having a lower melting point, such as cobalt, nickel, or rhodium. The second metal 120 may be deposited using any suitable technique such as CVD, PVD, ALD, or plating. For example, cobalt may be deposited using CVD with a precursor selected from CCTBA (dicobalt hexacarbonyl tert-butyl acetylene or its derivatives), CCTMSA (dicobalt hexacarbonyl trimethyl silyl acetylene), or CCBTMSA (carbonyl cobalt bis (trimethyl silyl acetylene)). Cobalt may also be deposited using ECP (electrochemical plating), ALD, or PVD. For example, nickel may be deposited using ECP, PVD, ALD, or CVD with (some) suitable precursors. For example, rhodium can be deposited using CVD with a precursor selected from Di-μ-chloro-tetrakis(trifluorophosphine)rhodium(I) ((PF3)2RhCl)2 or RhCl3 or hydrogenated tetrakis(trifluorophosphine) complex, [RhCl(PF3)2]2, or [RhXL2](2) (X = Cl, Br, or I; L = CO, PH3, or PF3). Rhodium can also be deposited using ECP, PVD, or ALD.

[0035] At operation 210, method 200 ( Figure 2) anneal the structure 100 so that the atoms of the second metal 120 diffuse into the grain boundaries 118-GB and the interfaces 118-INT. In some embodiments, the atoms of the second metal 120 also diffuse into the grains of the first metal 118. In one embodiment, the annealing is performed in a temperature range of one eighth (1 / 8) to one half (1 / 2) of the melting point of the second metal 120, for example, one quarter (1 / 4) to one half (1 / 2) of the melting point of the second metal 120. For example, when the second metal 120 includes cobalt, nickel, or rhodium, the annealing can be performed in a temperature range of 300°C to 500°C (for example, 400°C to 500°C, or about 450°C). Reaching these temperatures or temperature ranges can effectively move (or diffuse) the atoms of the second metal 120 without negatively affecting the structure 100. If the annealing temperature is higher than the specified range, certain conductive components of the structure 100 (for example, gate electrodes, source / drain contacts, metal lines, and / or the first metal 118) may be deformed. If the annealing temperature is below the specified range, the atoms of the second metal 120 may not diffuse well. Therefore, it has been found that the above-mentioned specified temperature range is particularly suitable for operation 210. In addition, the annealing is performed using a generally inactive carrier gas to prevent oxidation of the first metal and the second metal. The carrier gas can be an inert gas, such as argon (Ar), nitrogen (N2), hydrogen (H2), nitrogen-hydrogen (N2H2), ammonia (NH3), other suitable gases, or mixtures thereof. The annealing can be performed for several minutes, such as about 3 minutes to 6 minutes.

[0036] During the annealing, atoms of the second metal 120 diffuse along the grain boundaries 118-GB and the interfaces 118-INT. Figure 3E 118-GB(120) and 118-INT(120) to indicate the presence of the second metal 120 therein. In various embodiments, the ratio of the second metal 120 to the first metal 118 along the grain boundary 118-GB (in terms of metal volume or atomic number) is in the range of 10% to 90%. Moreover, in various embodiments, the ratio of the second metal 120 to the first metal 118 along the interface 118-INT is in the range of 10% to 90%, indicating that both the first metal 118 and the second metal 120 are in direct contact with surrounding structures such as the dielectric layer 116, the etch stop layer 114, and the conductive feature 112. Due to the presence of the second metal 120 in the grain boundary 118-GB and the interface 118-INT, the unobstructed plug 110 ( Figures 1A to 1D or Figure 3F) becomes more stable in subsequent heat treatments, thereby preventing or reducing defects therein. In one embodiment, atoms of the second metal 120 also diffuse into the grains of the first metal 118. In some other embodiments, the ratio of the second metal 120 to the first metal 118 within the grains of the first metal 118 is lower than the ratio of the second metal 120 to the first metal 118 along the grain boundaries 118-GB and the interfaces 118-INT. For example, in various embodiments, the ratio of the second metal 120 to the first metal 118 within the grains of the first metal 118 can be in the range of 5% to 40%.

[0037] At operation 212, method 200 ( Figure 2 ) A chemical mechanical planarization (CMP) process is performed to remove excess material from the structure 100, including the second metal 120 and the portion of the first metal 118 located above the dielectric layer 116. In this embodiment, the CMP process can also remove a portion of the first dielectric layer 116 and a portion of the second metal 120 and the first metal 118 within the via to achieve a desired height for the via plug 110. An example of the resulting structure 100 is shown in FIG. Figure 3F Reference Figure 3F , the unobstructed plug 110 is reduced to only two grains 118a and 118b of the first metal 118. The second metal 120 is distributed along the grain boundary 118-GB and the interface 118-INT. In the present embodiment, the two grains 118a and 118b are stacked on each other. In an alternative embodiment, the two grains 118a and 118b can be arranged laterally side by side (although not shown). In another embodiment, the structure 100 includes only one grain of the first metal 118 (e.g., 118a), and the second metal 120 is distributed along the interface 118-INT. In some embodiments, the structure 100 may include more than two grains of the first metal 118, and these grains may be arranged vertically from bottom to top and / or laterally side by side.

[0038] At operation 214, method 200 ( Figure 2) The device 100 is further processed to form a semiconductor device such as an IC. For example, the method 200 can form an interconnect wiring layer located above the non-blocking plug 110 and electrically connected to the non-blocking plug 110. This can involve a variety of operations, such as depositing an interlayer dielectric layer (ILD) above the dielectric layer 116 and the non-blocking plug 110, etching the ILD to form a trench and exposing the non-blocking plug 110 in the trench, filling the trench with one or more metals, and performing a CMP process on the one or more metals and the ILD. The remaining portion of the one or more metals becomes an interconnect layer electrically connected to the non-blocking plug 110. During various operations, the structure 100 may undergo one or more thermal treatments. Stabilizing the first metal 118 with the second metal 120 can enable the non-blocking plug 110 to maintain its integrity during these processes.

[0039] Figure 4 A flow chart of a method 400 for forming a semiconductor device 100 according to another embodiment is shown. The method 400 is merely an example and is not intended to limit the content of the present invention beyond the scope explicitly recited in the claims. Additional operations may be provided before, during, and after the method 400, and some of the operations described may be replaced, removed, or moved for additional embodiments of the method. FIG. 5A to FIG. 5D Method 400 is described with reference to FIG. 4 , which shows various cross-sectional views of semiconductor device 100 during fabrication steps according to method 400 .

[0040] refer to Figure 4 In this embodiment, method 400 includes operations 202, 204, 206, 210, 212, and 214, which have been referred to in Figure 2 After operation 206, the method 400 further includes an operation 408 for implanting ion species of the second metal 120 into the first metal 118. The method 400 is further described below.

[0041] At operation 202, method 400 provides (or is provided with) a structure (or workpiece) 100 having a substrate, a conductive component located above the substrate, an optional etch stop layer located above the conductive component, and a dielectric layer located above the etch stop layer. At operation 204, method 400 etches structure 100 to form a through hole therein. At operation 206, method 400 deposits a first metal layer 118 into the through hole. After operations 202, 204, and 206 of method 400, the resulting structure 100 is Figure 5A Reference Figure 5A , the structure 100 includes a substrate 102, a conductive component 112, an etch stop layer 114, a dielectric layer 116, and a first metal layer 118. The first metal layer 118 fills the via 117 (see Figure 3B ), the through hole 117 is located in layers 116, 114, and 112 and directly contacts the various layers. The interface between the first metal layer 118 and the surrounding structure is represented by the dotted line 118-INT. The first metal layer 118 includes a plurality of grains, such as grains 118a, 118b, 118c, and 118d. The boundaries between the grains are represented by the dotted lines 118-GB. If not properly processed, the grain boundaries 118-GB and the interfaces 118-INT may cause manufacturing defects of the structure 100, such as pitting defects or groove defects. The method 400 of the present invention processes the first metal 118 to avoid or reduce the above-mentioned problems.

[0042] In operation 408, if Figure 5B As shown, method 400( Figure 4 ) Ions of the second metal 120 are implanted into the first metal 118. Figure 5B , for example, using a tilted ion implantation process, ions of the second metal 120 are implanted into the first metal 118. In one embodiment, the ion implantation process uses a tilt angle in the range of 0 to 30 degrees and an implantation energy in the range of 2 keV to 15 keV. The selection of the tilt angle and the implantation energy depends on the through hole 117 ( Figure 3B ) height and critical dimensions, and the final plug 110 (eg Figure 5D The height and critical dimensions of the first metal 118 are shown in Figure 1. For through holes with a high aspect ratio (tall and narrow), a smaller tilt angle and / or a higher implantation energy can be used so that the ions can reach the middle and lower parts of the first metal 118. For through holes with a low aspect ratio (short and wide), a larger tilt angle and / or a lower implantation energy can be used. In various embodiments, the second metal 120 may have a higher or lower melting point than the first metal 118. For example, the first metal 118 may be ruthenium, and the second metal 120 may be one of cobalt, nickel, rhodium, iridium, molybdenum, and tungsten. Other materials for the first metal and the second metal are also possible. The implanted ion species may be distributed in the grains of the first metal 118 along the grain boundaries 118-GB and / or along the interfaces 118-INT.

[0043] At operation 210, method 400 ( Figure 4 ) annealing the structure 100 so that the second metal 120 can further diffuse into the grain boundary 118-GB and the interface 118-INT and stabilize the grains of the first metal. Figure 5C. In one embodiment, annealing is performed in a temperature range of one eighth (1 / 8) to one half (1 / 2) (e.g., one quarter (1 / 4) to one half (1 / 2)) of the lower melting point of the first metal 118 and the second metal 120. For example, when the first metal 118 includes ruthenium and the second metal 120 includes cobalt, nickel, or rhodium, annealing can be performed in a temperature range of 300° C. to 500° C. (e.g., 400° C. to 500° C., or about 450° C.). Reaching these temperatures or temperature ranges can effectively move (or diffuse) atoms of the second metal 120 without negatively affecting the structure 100. In addition, annealing is performed using a generally inactive carrier gas to prevent oxidation of the first metal and the second metal. The carrier gas can be an inert gas, such as argon (Ar), nitrogen (N2), hydrogen (H2), nitrogen-hydrogen (N2H2), ammonia (NH3), other suitable gases, or mixtures thereof. Annealing can be performed for several minutes, such as about 5 minutes. In various embodiments, a first ratio of the second metal 120 to the first metal 118 (in terms of metal volume or number of atoms) along the grain boundaries 118-GB and the interfaces 118-INT is in the range of 10% to 90%, and a second ratio of the second metal 120 to the first metal 118 within the grains of the first metal 118 is lower than the first ratio and may be in the range of 5% to 40%.

[0044] At operation 212, method 400 ( Figure 4 ) performs a chemical mechanical planarization (CMP) process to remove excess material from the structure 100. For example, the method 400 can remove a portion of the first dielectric layer 116 and a portion of the second metal 120 and the first metal 118 within the via to achieve a desired height for the via plug 110. An example of the resulting structure 100 is shown in FIG. Figure 5D It is shown in Figure 3F The structure 100 shown is substantially the same. At operation 214, the method 400 ( Figure 4 ) The device 100 is further processed to form a semiconductor device such as an IC. For example, the method 400 may form an interconnect wiring layer located above and electrically connected to the unblocked plug 110, which is similar to operation 212 of the method 200.

[0045] Figure 6 A flow chart of a method 600 for forming a semiconductor device 100 according to yet another embodiment is shown. The method 600 is merely an example and is not intended to limit the content of the present invention beyond the scope explicitly recited in the claims. Additional operations may be provided before, during, and after the method 600, and some of the operations described may be replaced, removed, or moved for additional embodiments of the method. 7A to 7C6 , which illustrates various cross-sectional views of the semiconductor device 100 during fabrication steps according to the method 400 , is described.

[0046] refer to Figure 6 , method 600 includes operations 202, 204, and 206, which have been referred to in Figure 2 After operation 206, the resulting structure 100 is Fig. 7A Reference Fig. 7A , structure 100 includes a substrate 102, a conductive component 112 located above substrate 102, an optional etch stop layer 114 located above conductive component 112, a dielectric layer 116 located above etch stop layer 114, and a first metal layer 118. The first metal layer 118 includes one or more grains, four grains 118a, 118b, 118c, and 118d are shown in this example. The boundaries between the grains are represented by 118-GB. The interface between the first metal layer 118 and the surrounding structure is represented by 118-INT, and the surrounding structure includes, for example, dielectric layer 116, etch stop layer 114, and conductive component 112.

[0047] In this embodiment, the conductive component 112 includes (some) metals having a lower melting point than the first metal 118, so that during the subsequent annealing process, the metal elements from the conductive component 112 can diffuse into the grain boundaries 118-GB and the interface 118-INT. The metal elements from the conductive component 112 can also be grains of the first metal 118. For example, the first metal 118 can include one of ruthenium, iridium, molybdenum, and tungsten; the conductive component 112 can include a metal different from the first metal 118 and having a lower melting point, such as cobalt, nickel, or rhodium. In one embodiment, the conductive component 112 is a contact component, such as a source contact or a drain contact.

[0048] At operation 210, method 600 ( Figure 6 ) annealing the structure 100 to diffuse the atoms of the conductive component 112 into the grain boundaries 118-GB and the interface 118-INT. In some embodiments, the atoms of the conductive component 112 also diffuse into the grains of the first metal 118. This operation has been described with reference to Figure 2 A discussion was held.

[0049] At operation 212, method 600 ( Figure 6 ) A chemical mechanical planarization (CMP) process is performed to remove excess material from the structure 100, including a portion of the first metal 118 located above the dielectric layer 116. In this embodiment, the CMP process also removes a portion of the first dielectric layer 116 and a portion of the first metal 118 within the via to achieve a desired height for the via plug 110. An example of the resulting structure 100 is shown in FIG. Figure 7C It is shown in Figure 3F The structures shown are substantially the same or similar. In operation 214, method 600 ( Figure 6 ) The device 100 is further processed to form a semiconductor device such as an IC. Aspects of operations 212 and 214 have been described with reference to Figure 2 A discussion was held.

[0050] Fig. 8A and 8B Some examples of first metal 118 having multiple grains in via 117 after operation 212 (CMP) are shown. In particular, Fig. 8A Three dies 118a, 118b, and 118c are shown stacked from bottom to top. Figure 8B Five grains 118a, 118b, 118c, 118d, and 118e are shown in a hybrid configuration from bottom to top and side by side. Figures 1A to 1D , Figure 3F , Figure 5D ,and Figure 7C The first metal 118 in each embodiment shown in FIG. 1 may be replaced by Fig. 8A , Figure 8B or other forms shown in .

[0051] Although not intended to be limiting, one or more embodiments of the present invention provide many benefits for semiconductor devices and their formation. For example, embodiments of the present invention provide a non-blocking plug and a method for forming the same. The non-blocking plug has a low resistance and a stable interface with the surrounding (some) dielectric layer. The non-blocking plug includes a first metal and a second metal. The first metal occupies most of the non-blocking plug and may have one or more grains. The second metal is distributed along the grain boundaries (if any) of the first metal and along the interface between the first metal and the surrounding structure. The second metal stabilizes (some) grains of the first metal and reduces pitting or groove defects associated with the first metal during heat treatment. The second metal can be introduced into the first metal by a deposition process or an ion implantation process, followed by an annealing process. Embodiments of the present invention can be easily integrated into existing or future mid-end (MOEL) processes of a production line or back-end (BEOL) processes of a production line, and are particularly useful for manufacturing plugs of 10nm or less.

[0052] In one aspect, the present invention is directed to a method comprising: receiving a structure having a dielectric layer above a conductive feature; etching a hole through the dielectric layer and exposing the conductive feature; depositing a first metal into the hole and directly contacting the dielectric layer and the conductive feature; depositing a second metal over the first metal; and annealing the structure including the first metal and the second metal.

[0053] In one embodiment, the method further comprises performing a chemical mechanical planarization process to remove at least a portion of the second metal. In some embodiments, the first metal comprises ruthenium and the second metal comprises cobalt, nickel, or rhodium. In some other embodiments, the dielectric layer comprises silicon dioxide and the conductive component comprises copper, cobalt, tungsten, ruthenium, rhodium, iridium, molybdenum, silicide, or metal nitride.

[0054] In one embodiment, the first metal includes one of ruthenium, rhodium, iridium, molybdenum, and tungsten; and the second metal includes cobalt or nickel. In one embodiment, the first metal has a melting point higher than the melting point of the second metal. In one embodiment, the annealing is performed at a temperature range of one eighth to one half of the melting point of the second metal.

[0055] In one embodiment, the second metal includes cobalt, nickel, or rhodium, and the annealing is performed at a temperature range of 300° C. to 500° C. In one embodiment, the annealing is performed using a carrier gas having an inert gas, nitrogen (N2), hydrogen (H2), nitrogen-hydrogen (N2H2), or ammonia (NH3). In one embodiment, the deposition of the second metal includes a chemical vapor deposition process, a physical vapor deposition process, or a plating process.

[0056] In another aspect, the present invention is directed to a method comprising: receiving a structure having a dielectric layer above a conductive feature; etching a hole through the dielectric layer and exposing the conductive feature; depositing a first metal into the hole and directly contacting the dielectric layer and the conductive feature; implanting ions of a second metal into the first metal; and annealing the structure comprising the first metal and the second metal.

[0057] In one embodiment, the first metal comprises ruthenium and the second metal comprises one of cobalt, nickel, rhodium, iridium, molybdenum, and tungsten. In one embodiment, the implantation is performed using a tilt angle in the range of 0 to 30 degrees. In another embodiment, the implantation is performed using an energy in the range of 2 keV to 15 keV. In one embodiment, the method further comprises performing a chemical mechanical planarization process to remove a portion of the first metal.

[0058] In another aspect, the present invention is directed to a semiconductor structure comprising: a conductive component; a dielectric layer located above the conductive component; and a plug located above the conductive component and at least partially surrounded by the dielectric layer. The plug comprises a first metal and a second metal different from the first metal, wherein the second metal is distributed along an interface between the first metal and the dielectric layer.

[0059] In one embodiment, the second metal is further distributed along another interface between the first metal and the conductive component. In one embodiment, the plug includes a plurality of grains of the first metal, and the second metal is further distributed along one or more boundaries of the plurality of grains. In one embodiment, the first metal includes ruthenium, rhodium, iridium, molybdenum, or tungsten; and the second metal includes cobalt, nickel, or rhodium. In one embodiment, the first metal includes ruthenium, and the second metal includes cobalt, nickel, rhodium, iridium, molybdenum, and tungsten.

[0060] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: receiving a structure having a dielectric layer over the conductive member; etching a hole through the dielectric layer and exposing the conductive feature; a first metal deposited into the hole and directly contacting the dielectric layer and the conductive feature; depositing a second metal over the first metal; as well as annealing the structure including the first metal and the second metal, The first metal includes a plurality of crystal grains, and the second metal is distributed along boundaries between the plurality of crystal grains.

2. The method according to claim 1, further comprising: A chemical mechanical planarization process is performed to remove at least a portion of the second metal.

3. The method according to claim 1, wherein: The first metal includes ruthenium, and the second metal includes cobalt, nickel, or rhodium.

4. The method according to claim 3, wherein: The dielectric layer includes silicon dioxide, and the conductive feature includes copper, cobalt, tungsten, ruthenium, rhodium, iridium, molybdenum, silicide, or metal nitride.

5. The method according to claim 1, wherein: The first metal includes one of ruthenium, rhodium, iridium, molybdenum, and tungsten; and the second metal includes cobalt or nickel.

6. The method according to claim 1, wherein: The first metal has a melting point higher than a melting point of the second metal.

7. The method according to claim 1, wherein: The annealing is performed at a temperature ranging from one eighth to one half of the melting point of the second metal.

8. The method according to claim 1, wherein: The second metal includes cobalt, nickel, or rhodium, and the annealing is performed at a temperature ranging from 300°C to 500°C.

9. The method according to claim 1, wherein: The annealing is performed using a carrier gas having an inert gas, nitrogen (N2), hydrogen (H2), nitrogen-hydrogen (N2H2), or ammonia (NH3).

10. The method according to claim 1, wherein: The depositing of the second metal includes a chemical vapor deposition process, a physical vapor deposition process, or a plating process.

11. A method of forming a semiconductor structure, comprising: receiving a structure having a dielectric layer over the conductive member; etching a hole through the dielectric layer and exposing the conductive feature; depositing a first metal into the hole and directly contacting the dielectric layer and the conductive feature, wherein the first metal completely fills the hole; implanting ions of a second metal into the first metal; and annealing the structure including the first metal and the second metal; The first metal includes a plurality of crystal grains, and the annealing causes the second metal to be distributed along boundaries between the plurality of crystal grains.

12. The method according to claim 11, wherein: The first metal includes ruthenium, and the second metal includes one of cobalt, nickel, rhodium, iridium, molybdenum, and tungsten.

13. The method according to claim 11, wherein: The implantation was performed using a tilt angle ranging from 0 to 30 degrees.

14. The method according to claim 13, wherein: The implantation is performed using an energy in the range of 2 keV to 15 keV.

15. The method according to claim 11, further comprising: A chemical mechanical planarization process is performed to remove a portion of the first metal.

16. A semiconductor structure comprising: Conductive parts; a dielectric layer located above the conductive component; as well as a plug located above the conductive component and at least partially surrounded by the dielectric layer, wherein the plug comprises a first metal and a second metal different from the first metal, wherein the second metal is distributed along an interface between the first metal and the dielectric layer, The plug includes a plurality of crystal grains of the first metal, and the second metal is further distributed along boundaries between the plurality of crystal grains, wherein the second metal comes from a metal element of the conductive component.

17. The semiconductor structure according to claim 16, wherein: The second metal is also distributed along another interface between the first metal and the conductive component.

18. The semiconductor structure according to claim 16, wherein: The ratio of the second metal to the first metal along the boundary and the interface is higher than the ratio of the second metal to the first metal within the first metal.

19. The semiconductor structure according to claim 16, wherein: The first metal includes ruthenium, rhodium, iridium, molybdenum, or tungsten; and the second metal includes cobalt, nickel, or rhodium.

20. The semiconductor structure of claim 16, wherein: The first metal includes ruthenium, and the second metal includes cobalt, nickel, rhodium, iridium, molybdenum, and tungsten.

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