Semiconductor device structure and method for forming the same

Abstract

Various embodiments disclosed herein relate to a semiconductor device structure including a bump structure overlying a bonding pad. The bonding pad is disposed on a semiconductor substrate. An etch stop layer overlies the bonding pad. A buffer layer is disposed on the bonding pad and separates the etch stop layer from the bonding pad. The bump structure includes a base portion and an upper portion, the base portion contacts an upper surface of the bonding pad, and the upper portion extends through the etch stop layer and the buffer layer. The base portion of the bump structure has a first width or diameter and the upper portion of the bump structure has a second width or diameter. The first width or diameter is greater than the second width or diameter.

Description

Technical Field

[0001] The disclosed embodiments relate to semiconductor device structures and methods for forming the same. Background Art

[0002] Semiconductor chips are used in a wide variety of electronic and other devices and are well known. The widespread use of such chips today and consumer demand for more powerful and compact devices requires chip manufacturers to continue to reduce the physical size of these chips and continue to increase the functionality of these chips. This scaling-down process generally provides benefits by increasing production efficiency and reducing associated costs. However, as feature sizes continue to decrease, the manufacturing process continues to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices of increasingly smaller sizes. Summary of the invention

[0003] In the disclosed embodiment, a semiconductor device structure is provided. The semiconductor device structure includes: a bonding pad disposed on a semiconductor substrate; an etch stop layer overlying the bonding pad; a buffer layer disposed on the bonding pad and separating the etch stop layer from the bonding pad; and a bump structure including a base portion and an upper portion, the base portion contacts an upper surface of the bonding pad, and the upper portion extends through the etch stop layer and the buffer layer, wherein the base portion of the bump structure has a first width or diameter and the upper portion of the bump structure has a second width or diameter, and the first width or diameter is greater than the second width or diameter.

[0004] In the disclosed embodiment, a semiconductor device structure is further provided. The semiconductor device structure includes: an interconnect structure overlying a substrate, the interconnect structure including a topmost conductive wiring; a passivation structure overlying the interconnect structure; a bonding pad overlying the topmost conductive wiring, wherein the bonding pad extends through the passivation structure and directly contacts the top surface of the topmost conductive wiring, wherein the bonding pad has an upper surface located below the top surface of the bonding pad in a vertical direction, and wherein the upper surface of the bonding pad is located below the top surface of the passivation structure in a vertical direction; an etch stop layer overlying the bonding pad and the passivation structure; a buffer layer disposed on the between the etch stop layer and the bonding pad, wherein the bonding pad extends continuously along the lower side of the buffer layer and surrounds the lower side of the buffer layer in a cup shape; and a bump structure, including a base portion and an upper portion, the base portion contacts the upper surface of the bonding pad and is disposed in the buffer layer, the upper portion extends upward from the base portion and extends through the etch stop layer and the buffer layer, wherein the base portion has a first width defined in the buffer layer, and the upper portion has a second width defined above the top surface of the buffer layer, and wherein the first width is greater than the second width.

[0005] In the disclosed embodiment, a method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes: forming a passivation structure on a conductive wiring; forming a bonding pad on the conductive wiring, wherein the bonding pad is suspended on the passivation structure; depositing a buffer layer on the bonding pad; depositing an etch stop layer on the buffer layer and the passivation structure; depositing an upper dielectric structure on the etch stop layer; performing a dry etching process on the buffer layer, the etch stop layer and the upper dielectric structure, the dry etching process defining a bump structure opening overlying the upper surface of the bonding pad, wherein after the dry etching process, a portion of the buffer layer overlies the upper surface of the bonding pad; performing a wet etching process on the buffer layer, the wet etching process removing the portion of the buffer layer overlying the upper surface of the bonding pad, wherein the wet etching process enlarges the bump structure opening and exposes the upper surface of the bonding pad; and forming a bump structure in the bump structure opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1Cross-sectional views of some embodiments of complementary metal-oxide semiconductor (CMOS) chips having bump structures overlying bond pads overlying interconnect structures electrically coupled to the semiconductor device are shown.

[0008] Figure 2 A perspective view of some embodiments of bump structures overlying bond pads is shown.

[0009] Figure 3 Show Figure 1 Cross-sectional views of some alternative embodiments of bump structures.

[0010] Figure 4 Show Figure 3 A cross-sectional view of some embodiments of a close-up view of a section of a bump structure.

[0011] Figure 5A and Figure 5B Show Figure 1 Cross-sectional views of some alternative embodiments of bump structures.

[0012] Figure 6 Cross-sectional views of some embodiments of a complementary metal oxide semiconductor (CMOS) chip having a plurality of semiconductor devices disposed on a substrate, an interconnect structure overlying the substrate, and a bump structure overlying the interconnect structure are shown.

[0013] Figures 7 to 18 Cross-sectional views of some embodiments of methods of forming a bump structure overlying a bond pad are shown.

[0014] Fig.19 A method is shown in flow chart form that illustrates some embodiments of a method of forming a bump structure overlying a bond pad.

[0015] [Explanation of Symbols]

[0016] 100, 600: Complementary metal oxide semiconductor (CMOS) chip

[0017] 102: Substrate

[0018] 103, 624: Source / drain region

[0019] 104: Semiconductor devices

[0020] 105: Gate dielectric

[0021] 106: Inner Link Structure

[0022] 107: Interconnect dielectric structure

[0023] 108, 644b, 644c, 644d: vias

[0024] 109, 622: Side wall spacers

[0025] 110: Conductive wiring

[0026] 110a: Topmost conductive wiring

[0027] 111: Gate electrode

[0028] 112: Passivation structure

[0029] 114: Bonding pad

[0030] 114a: Upper bonding pad

[0031] 114b: Lower bonding pad

[0032] 114c: Central area

[0033] 114p: Outlying area

[0034] 114us, 116us, 302u: upper surface

[0035] 116: Buffer layer

[0036] 118: Etch stop layer

[0037] 118ls: lower surface

[0038] 120: Bump structure

[0039] 120a: Upper conductive structure

[0040] 120b: Lower conductive structure

[0041] 120bp: base part

[0042] 120cs: Curved outer sidewall / curved sidewall

[0043] 120cs1: First curved sidewall

[0044] 120cs2: Second curved sidewall

[0045] 120s1, 120s2: Side wall

[0046] 120ss1: First inclined side wall

[0047] 120ss2: Second inclined side wall

[0048] 120ss3: Third inclined side wall

[0049] 120u: Upper part

[0050] 120vs: Vertical outer wall / vertical side wall

[0051] 200: Stereograph

[0052] 300, 400, 500a, 500b, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800: Sectional view

[0053] 302: Lower dielectric layer

[0054] 304: Upper dielectric layer

[0055] 306: Dielectric Structure

[0056] 402: First Horizontal Line

[0057] 404: The Second Horizontal Line

[0058] 602: First semiconductor device region

[0059] 604: Second semiconductor device region

[0060] 608: Shallow Trench Isolation (STI) region

[0061] 610, 611, 612: Transistors

[0062] 614: Gate electrode

[0063] 618: Gate dielectric layer

[0064] 626a, 626b, 626c, 626d: Intermetal dielectric (IMD) layer

[0065] 626e: Intermetal Dielectric (IMD) layer / topmost IMD layer

[0066] 638a: Conductive wiring layer / bottom conductive wiring layer

[0067] 638b, 638c: Conductive wiring layer

[0068] 638d: Conductive wiring layer / uppermost conductive wiring layer

[0069] 640: Dielectric protective layer

[0070] 644a: Via / Bottom Via

[0071] 650: Deep Trench Isolation Structure

[0072] 660: Conductive bonding structure

[0073] 702, 906, 1102, 1404: masking layer

[0074] 802: Bonding pad opening

[0075] 902: Conductive layer

[0076] 904: Metal protective layer

[0077] 1202: Deep trench isolation structure opening

[0078] 1402: Upper dielectric structure

[0079] 1502: Bump structure opening

[0080] 1900: Methods

[0081] 1902, 1904, 1906, 1908, 1910, 1912, 1914, 1916: Action

[0082] α: first angle

[0083] β: Second angle

[0084] ф: third angle

[0085] d1: lateral distance

[0086] h1: first height

[0087] h2: Second height

[0088] h3: third height

[0089] h bs :high

[0090] t bl ,t bl’ ,t bp ,t el :thickness

[0091] w1: first width

[0092] w2: second width

[0093] v1: non-zero vertical distance DETAILED DESCRIPTION

[0094] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and also includes an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0095] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in a figure to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0096] A typical complementary metal oxide semiconductor (CMOS) die includes an interconnect structure overlying a substrate. One or more semiconductor devices (e.g., transistors, varactors, resistors, capacitors) are arranged in, on, or above the substrate and electrically coupled to one or more bonding pads through the interconnect structure. A bump structure directly overlies each bonding pad and is configured to facilitate electrical coupling to a printed circuit board (PCB) or another CMOS die through, for example, a metal bonding process.

[0097] A method for forming a bump structure includes forming a bonding pad directly on the topmost conductive layer in an interconnect structure. An etch stop layer is formed on the bonding pad, and an oxide layer is formed on the etch stop layer. A first etch (e.g., plasma etch) is performed according to a masking layer to remove a portion of the etch stop layer and a portion of the oxide layer, thereby defining a bump structure opening that exposes the upper surface of the bonding pad. In order to ensure that the first etch clears the etch stop layer from the upper surface of the bonding pad, the first etch will etch slightly into the bonding pad. Unfortunately, as understood in some aspects of the present disclosure, when the bonding pad material (e.g., aluminum) is removed by the first etch, the bonding pad material and / or its byproducts may be re-deposited on the sidewalls of the etch stop layer and the sidewalls of the oxide layer in the bump structure opening. In addition, in some cases, this first etch may include fluorine free radicals. When the fluorine free radicals contact the material of the bonding pad, the fluorine and the bonding pad material may react to form byproducts on the upper surface of the bonding pad. These byproducts can then react with moisture in the surrounding environment to produce hydrofluoric acid (HF), which will corrode the upper surface of the bonding pad, causing the upper surface of the bonding pad to be damaged and roughened. An argon bombardment process can be performed to remove this corrosion, but this will increase the time and cost of the manufacturing process.

[0098] Then, a bump structure (e.g., a solder bump) is formed on the upper surface of the bonding pad. After the bump structure is formed, the remaining oxide layer is removed by a second etch (e.g., a vapor etch including an etchant (e.g., hydrofluoric acid). During the second etch, the redeposited material (e.g., aluminum) on the sidewall of the bump structure may fall off or peel off from the bump structure onto an adjacent structure. Since the redeposited material is conductive, these materials can electrically short-circuit adjacent conductive structures and / or adjacent bump structures together, thereby making the device on the CMOS die inoperable. In addition, even if the redeposited material is left in place, the damaged / rough upper surface of the bonding pad can cause long-term reliability problems, such as long-term reliability problems due to adhesion problems and / or increased resistance between the solder bump and the bonding pad.

[0099] In some embodiments of the present disclosure, in order to eliminate the redeposition of material from the bonding pad onto the sidewalls of the bump structure and to provide a good interface between the bonding pad and the solder bump, a buffer layer may be formed on the bonding pad before forming the etch stop layer. Therefore, after forming the buffer layer, an etch stop layer may be formed on the buffer layer, and an oxide layer may be formed on the etch stop layer. A first etch (e.g., a plasma etch comprising fluorine radicals) is performed to remove a portion of the oxide layer and a portion of the etch stop layer, thereby defining a bump structure opening that exposes the upper surface of the buffer layer. Since the first etch stops on the buffer layer, the first etch will not contact the bonding pad and will not cause the bonding pad material to be redeposited onto the sidewalls of the bump structure opening. A second etch (e.g., a wet etch) is then performed to extend the bump structure opening by removing the exposed portion of the buffer layer to expose the upper surface of the bonding pad. Because this second etch is a wet etch, it can undercut the etch stop layer and leave an extended bump structure opening with clean sidewalls (i.e., there is no redeposited material from the bond pad along the sidewalls of the bump structure opening). In addition, by virtue of the wet etch process, the upper bond pad surface is smooth and provides a good contact interface for the bump structure. Therefore, when the bump structure is subsequently formed over the bond pad and a third etch process (e.g., including an etchant such as hydrofluoric acid) is performed to remove the remaining oxide layer, the result is good physical and electrical contact between the bond pad and the bump structure.

[0100] Reference Figure 1 , a cross-sectional view of some embodiments of a complementary metal oxide semiconductor (CMOS) chip 100 is provided, which has a bump structure 120 overlying a bonding pad 114.

[0101] The CMOS chip 100 includes a substrate 102, an interconnect structure 106, and a bump structure 120 electrically coupled to the interconnect structure 106 through a bonding pad 114. A semiconductor device 104 is disposed on the substrate 102. The semiconductor device 104 may be, for example, a transistor. In the aforementioned example, the semiconductor device 104 may include: a source / drain region 103 disposed in the substrate 102; a gate dielectric 105 disposed between the source / drain regions 103; a gate electrode 111 overlying the gate dielectric 105; and a sidewall spacer 109 disposed around the sidewalls of the gate electrode 111 and the sidewalls of the gate dielectric 105. The semiconductor device 104 is electrically coupled to an overlying metal layer, an overlying electronic device (e.g., a memory cell, a metal-insulator-metal capacitor, a resistor, etc.), and / or another CMOS die through the interconnect structure 106.

[0102] The interconnect structure 106 includes a plurality of conductive vias 108, a plurality of conductive wires 110, and an interconnect dielectric structure 107. The conductive vias 108 and the conductive wires 110 are disposed within the interconnect dielectric structure 107 and are configured to electrically couple the semiconductor device 104 to an overlying conductive structure. The topmost conductive wire 110a is directly below the bonding pad 114.

[0103] A passivation structure 112 is overlaid on the interconnect structure 106. A bonding pad 114 extends from the top surface of the passivation structure 112 to the topmost conductive wiring 110a. A buffer layer 116 is overlaid on the upper surface 114us of the bonding pad 114. An etch stop layer 118 extends continuously over the passivation structure 112, the bonding pad 114, and the buffer layer 116. A bump structure 120 is directly overlaid on the bonding pad 114. The bump structure 120 is configured to electrically couple the bonding pad 114 to another CMOS die (not shown). In some embodiments, the upper surface 114us of the bonding pad 114 includes a peripheral region 114p and a central region 114c; and the upper portion of the peripheral region 114p of the bonding pad 114 is suspended over the passivation structure 112. The upper surface of the peripheral region 114p has a first height h1 measured from the upper surface of the substrate 102, and the upper surface of the central region 114c has a second height h2 measured from the upper surface of the substrate 102. The first height h1 is greater than the second height h2.

[0104] The bump structure 120 includes a base portion 120bp and an upper portion 120u, wherein the base portion 120b is in direct contact with the upper surface 114us of the bonding pad 114, and the upper portion 120u extends upward through the etch stop layer 118. In some cases, the base portion 120bp of the bump structure 120 intersects with the upper portion 120u of the bump structure 120 at a third height h3, wherein the third height h3 is less than the first height h1 and greater than the second height h2. The base portion 120bp is defined between curved outer side walls (also referred to as curved side walls) 120cs; and the upper portion 120u is defined between vertical outer side walls (also referred to as vertical side walls) 120vs. The curved side walls 120cs are disposed within the buffer layer 116. The vertical side walls 120vs extend from the top surface of the buffer layer 116 to a point corresponding to the top surface of the bump structure 120. In some embodiments, the opposite sidewalls 120s1, 120s2 of the bump structure 120 are defined according to a cross-sectional view. For example, if the bump structure 120 is circular / elliptical when viewed from above, the opposite sidewalls 120s1, 120s2 are a single continuous sidewall when viewed from above, and thus when depicted in a cross-sectional view, the opposite "sidewalls" 120s1, 120s2 refer to the two sidewalls that would naturally appear as such a single continuous sidewall. Additionally, if the bump structure 120 is circular or elliptical when viewed from above, any length and / or width associated with a cross-sectional view of a structure and / or layer including the bump structure 120 corresponds to the diameter of a circle or the length defined between two vertices on the major axis of an ellipse, respectively.

[0105] By providing the curved sidewall 120cs in the buffer layer 116, the redeposition of the conductive material from the bonding pad 114 to the opposite sidewalls 120s1, 120s2 of the bump structure 120 is mitigated during the manufacture of the CMOS chip 100. By mitigating the redeposition of the conductive material from the bonding pad 114, the bump structure 120 is electrically isolated from the adjacent conductive structure, and thus the yield of the CMOS chip 100 is improved. In addition, by providing the buffer layer 116 between the etch stop layer 118 and the bonding pad 114, the number of processing steps for manufacturing the CMOS chip 100 is reduced and / or eliminated. This reduces the yield loss, time and cost associated with manufacturing the CMOS chip 100 to some extent.

[0106] Reference Figure 2 ,supply Figure 1 A perspective view 200 of some embodiments of the bump structure 120 is shown. Figure 2 As shown in FIG. 1 , the bump structure 120 has a cylindrical shape. Therefore, the base portion ( Figure 1 : base portion 120 bp) and the upper portion of the bump structure 120 ( Figure 1: The upper part 120u) is cylindrical, wherein the base part ( Figure 1 : The width or diameter of the base part (120 bp) is larger than that of the upper part ( Figure 1 : The width or diameter of the upper portion 120u). Although Figure 2 Not visible in the , but the binding pad ( Figure 1 : The bonding pad 114 has a rectangular / square shape, so that the bump structure 120 is arranged on the bonding pad ( Figure 1 The top surface of the bump structure 120 is located vertically between the inner sidewalls of the bonding pad ( Figure 1 : above the top surface of the bonding pad 114).

[0107] Reference Figure 3 ,supply Figure 1 A cross-sectional view 300 of some embodiments of the bump structure 120 is shown.

[0108] A dielectric structure 306 is disposed on the etch stop layer 118 and the bump structure 120. In some embodiments, the dielectric structure 306 may be, for example, or include an oxide (e.g., silicon dioxide, gold oxide, another suitable oxide, etc.). In some other embodiments, the dielectric structure 306 is omitted. The lower portion of the bonding pad 114 is disposed in the passivation structure 112. The passivation structure 112 includes an upper dielectric layer 304 and a lower dielectric layer 302. The upper dielectric layer 304 may be, for example, or include silicon dioxide, silicon glass, undoped silicon glass, etc., and / or may have a thickness in the range of about 5,500 angstroms to 6,500 angstroms. The lower dielectric layer 302 may be, for example, or include silicon carbide, silicon nitride, etc., and / or may have a thickness in the range of about 1,000 angstroms to 1,500 angstroms. An etch stop layer 118 is overlying the passivation structure 112. In some embodiments, the etch stop layer 118 may be, for example, or include aluminum oxide, another suitable oxide, etc. The etch stop layer 118 has a thickness t el , thickness t el It may be, for example, in the range of about 100 angstroms to 1,000 angstroms.

[0109] In some embodiments, bonding pad 114 may be, for example, or include aluminum, copper, aluminum copper, tantalum nitride, etc. In some embodiments, bonding pad 114 may have a thickness t defined between the bottom surface of lower dielectric layer 302 and the bottom surface of bump structure 120. bp . Thickness t bp For example, the thickness of the bonding pad 114 may be in the range of about 1,000 angstroms to 8,000 angstroms. In yet other embodiments, the bonding pad 114 may include, for example, a first conductive layer including a first material (e.g., aluminum copper) and a second conductive layer including a second material different from the first material (e.g., tantalum nitride). The first conductive layer directly overlies the second conductive layer, for example, see Figure 5B The upper bonding pad layer 114a and the lower bonding pad layer 114b are provided.

[0110] A buffer layer 116 is disposed between the etch stop layer 118 and the upper surface 114us of the bonding pad 114. In some embodiments, the buffer layer 116 may be, for example, or include a nitride (e.g., titanium nitride, tantalum nitride, silicon nitride, or silicon oxynitride), or an oxide (e.g., titanium oxide, silicon dioxide, or silicon oxynitride), titanium, etc., and / or may have a thickness t in the range of about 100 angstroms to 1,000 angstroms. bl In some embodiments, if the thickness t bl If the thickness t is 100 angstroms or greater, a wet etching process may be used to expose the upper surface 114us of the bonding pad 114 during the fabrication of the bump structure 120. In some further embodiments, if the thickness t bl If the thickness t is 1,000 angstroms or less, the upper surface 114us of the bonding pad 114 may be protected while performing a plasma etch (during the formation of the bump structure 120) to remove a portion of the etch stop layer 118. In some embodiments, if the thickness t bl Greater than 1,000 angstroms, the buffer layer 116 may be susceptible to damage due to particle defects during the deposition process. This may in turn lead to delamination between the buffer layer 116 and adjacent layers. bl and materials, during the fabrication of the bump structure 120, the redeposition of the conductive material from the bonding pad 114 to the opposite sidewalls 120s1, 120s2 of the bump structure 120 is reduced. In addition, the buffer layer 116 that protects the upper surface 114us of the bonding pad 114 during the plasma etching process reduces and / or eliminates the corrosion of the upper surface 114us of the bonding pad 114 (e.g., bonding pad defect issues). This reduces and / or omits the use of a treatment process (e.g., an argon bombardment process) on the upper surface 114us of the bonding pad 114, thereby reducing the yield loss, time, and cost associated with fabricating the bonding pad 114 and / or the bump structure 120. In some embodiments, the height of the curved sidewalls of the opposite sidewalls 120s1, 120s2 is equal to the thickness t bl .

[0111] In some embodiments, the bump structure 120 may be, for example, or include nickel, gold, or the like, and / or may have a height h in a range of about 3,000 angstroms to 10,000 angstroms. bsThe bump structure 120 has a first width w1 defined between the vertical sidewalls of the opposing sidewalls 120s1, 120s2. In some embodiments, the first width w1 is in a range of about 1 micron to 5 microns. The bump structure has a second width w2 defined between the curved sidewalls of the opposing sidewalls 120s1, 120s2. In some embodiments, the second width w2 is in a range of about 1.01 microns to 5.06 microns. In some further embodiments, the second width w2 is greater than the first width w1.

[0112] In some embodiments, the bump structure 120 has a lateral distance d1 defined between the vertical sidewalls of the opposing sidewalls 120s1, 120s2 and the outer side points of the curved sidewalls of the opposing sidewalls 120s1, 120s2. In some embodiments, the lateral distance d1 is in the range of about 50 angstroms to 300 angstroms. In some other embodiments, the value of the lateral distance d1 is related to the thickness t of the buffer layer 116. bl For example, if the thickness t bl is relatively thin (eg, approximately 100 angstroms), then the lateral distance d1 may be relatively small (eg, approximately 50 angstroms). In another example, if the thickness t bl is relatively thick (eg, approximately 1,000 angstroms), then lateral distance d1 may be relatively large (eg, approximately 300 angstroms).

[0113] Reference Figure 4 ,supply Figure 3 A section of the bump structure 120 (eg Figure 3 A cross-sectional view 400 of some embodiments of an enlarged view of the device (shown in the dashed box in FIG. 4 ).

[0114] like Figure 4As shown in , the bump structure 120 conforms to the undercut profile of the buffer layer 116 and the undercut profile of the etch stop layer 118. The sidewall 120s2 of the bump structure 120 includes a first inclined sidewall 120ss1, a second inclined sidewall 120ss2, a first curved sidewall 120cs1, a second curved sidewall 120cs2, and a third inclined sidewall 120ss3. The first inclined sidewall 120ss1 has a first angle α defined between the upper surface 114us of the bonding pad 114 and the bump structure 120. In some embodiments, the first angle α is in the range of approximately 10 degrees to 60 degrees. The second inclined sidewall 120ss2 has a second angle β defined between the bump structure 120 and the first horizontal line 402. In some embodiments, the second angle β is in the range of approximately 10 degrees to 80 degrees. In some other embodiments, the first angle α is less than the second angle β. The first curved sidewall 120cs1 is in direct contact with the curved undercut portion of the buffer layer 116. The second curved sidewall 120cs2 directly overlies the first curved sidewall 120cs1 and is in direct contact with the undercut portion of the etch stop layer 118. The third inclined sidewall 120ss3 has a third angle ф defined between the bump structure 120 and the second horizontal line 404. In some embodiments, the third angle ф is in a range of approximately 10 degrees to 90 degrees. The aforementioned sidewalls of the sidewall 120s2 of the bump structure 120 may be defined by one or more etching processes utilized during the fabrication of the bump structure 120.

[0115] Reference Figure 5A ,supply Figure 3 A cross-sectional view 500 a of an alternative embodiment of the bump structure 120 is shown.

[0116] The bump structure 120 includes an upper conductive structure 120a and a lower conductive structure 120b. In some embodiments, the upper conductive structure 120a includes a first material and the lower conductive structure 120b includes a second material different from the first material. For example, the first material of the upper conductive structure 120a may be or include gold and the second material of the lower conductive structure 120b may be or include nickel. The opposite sidewalls of the upper conductive structure 120a respectively include continuous, straight vertical sidewalls. The opposite sidewalls of the lower conductive structure 120b respectively include continuous, straight vertical sidewalls directly overlying the curved sidewalls.

[0117] Reference Figure 5B ,supply Figure 3 A cross-sectional view 500 b of an alternative embodiment of the bump structure 120 is shown.

[0118] The bonding pad 114 includes an upper bonding pad layer 114a and a lower bonding pad layer 114b located below the upper bonding pad layer 114a. The upper bonding pad layer 114a includes a first bonding pad material and the lower bonding pad layer 114b includes a second bonding pad material different from the first bonding pad material. In some embodiments, the first bonding pad material may be, for example, or include aluminum, copper, aluminum copper, etc. In some embodiments, the second bonding pad material may be, for example, or include tantalum, nitride, tantalum nitride, etc. The upper bonding pad layer 114a directly contacts the buffer layer 116 and the bump structure 120.

[0119] Reference Figure 6 , a cross-sectional view of a complementary metal oxide semiconductor (CMOS) chip 600 is provided, wherein the complementary metal oxide semiconductor chip 600 includes a plurality of bump structures 120 overlying an interconnect structure 106 .

[0120] The CMOS chip 600 includes a substrate 102. The substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. The illustrated embodiment depicts one or more shallow trench isolation (STI) regions 608 that may include dielectric-filled trenches within the substrate 102.

[0121] Transistors 610 and 611 are disposed between the STI regions 608 in the first semiconductor device region 602. A transistor 612 is disposed adjacent to the STI region 608 in the second semiconductor device region 604. In some embodiments, the first semiconductor device region 602 may be a memory array region (including memory cells disposed in the interconnect structure 106) and the second semiconductor device region 604 may be a logic region. In some further embodiments, the first semiconductor device region 602 is separated from the second semiconductor device region 604 by a deep trench isolation structure 650. The transistors 610, 611, and 612 include a gate electrode 614, a gate dielectric layer 618, a sidewall spacer 622, and a source / drain region 624, respectively. The source / drain region 624 is disposed on either side of each gate electrode 614 in the substrate 102 and is doped to have a first conductivity type (e.g., n-type) opposite to a second conductivity type (e.g., p-type) of a channel region below each gate dielectric layer 618. The gate electrode 614 may be, for example, doped polysilicon or a metal (e.g., tungsten), a silicide, or a combination thereof. The gate dielectric layer 618 may be, for example, each be or include an oxide (e.g., silicon dioxide), or a high-k dielectric material. As used herein, a high-k dielectric material is a dielectric material having a dielectric constant greater than 3.9. The sidewall spacer 622 may be, for example, made of silicon nitride.

[0122] The interconnect structure 106 is arranged on the substrate 102 and includes a plurality of inter-metal dielectric (IMD) layers 626a to 626e, a plurality of conductive wiring layers 638a to 638d, and a plurality of vias 644a to 644d. The IMD layers 626a to 626e may be made of, for example, a low-k dielectric material (e.g., undoped silicate glass) or an oxide (e.g., silicon dioxide), respectively. As used herein, a low-k dielectric material is a dielectric material having a dielectric constant less than 3.9. The conductive wiring layers 638a to 638d are formed in the trenches and may be made of a metal (e.g., copper, aluminum, etc.). The via (also referred to as the bottom via) 644a extends from the conductive wiring layer (also referred to as the bottom conductive wiring layer) 638a to the source / drain region 624 and / or the gate electrode 614; and the vias 644b to 644d extend between the conductive wiring layers 638b to 638d. The vias 644a to 644d extend through the dielectric protection layer 640 (which may be made of a dielectric material and / or may serve as an etch stop layer during manufacturing). The dielectric protection layer 640 may be made of, for example, a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxynitride), etc. The vias 644a to 644d may be made of, for example, a metal (e.g., copper, tungsten, etc.).

[0123] A passivation structure 112 is overlaid on the IMD layer (also referred to as the topmost IMD layer) 626e. A bonding pad 114 extends from the top surface of the passivation structure 112 to the conductive wiring layer (also referred to as the topmost conductive wiring layer) 638d. A buffer layer 116 is overlaid on each bonding pad 114 and an etch stop layer 118 is overlaid on the buffer layer 116. The etch stop layer 118 extends continuously from the passivation structure 112 to below the top surface of the substrate 102. The etch stop layer 118 surrounds the lower side of the deep trench isolation structure 650 in a cup shape. A bump structure 120 is overlaid on each bonding pad 114, so that the bump structure 120 is electrically coupled to the source / drain region 624 of the transistors 610, 611, and 612 through the interconnect structure 106. In some embodiments, the bump structures 120 are each configured to Figure 5A The bump structures 120 are each provided with an upper conductive structure 120a and a lower conductive structure 120b. The bump structures 120 are configured to facilitate coupling the transistors 610, 611, and 612 to another integrated chip (not shown). A conductive bonding structure 660 is disposed laterally between adjacent bump structures 120. The conductive bonding structure 660 is configured to facilitate bonding the bump structures 120 to another integrated chip (not shown). In some embodiments, the conductive bonding structure 660 may be, for example, or include the same material as the bonding pad 114.

[0124] Figures 7 to 18Cross-sectional views 700 through 1800 illustrate some embodiments of methods of forming a bump structure overlying a bonding pad. Figures 7 to 18 700 to 1800 shown in FIG. 1 , however, it should be understood that Figures 7 to 18 The structures shown in are not limited to the method, but can be independently separated from the method. Figures 7 to 18 It is described as a series of actions, but it should be understood that these actions are not restrictive, because the order of the actions can be changed in other embodiments, and the disclosed method can also be applied to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0125] like Figure 7 As shown in the cross-sectional view 700 of , an interconnect dielectric structure 107 overlying the substrate 102 is provided. The topmost conductive wire 110a is disposed in the interconnect dielectric structure 107 and the topmost conductive wire 110a overlies the substrate 102. A passivation structure 112 is formed over the topmost conductive wire 110a. In some embodiments, the passivation structure 112 includes an upper dielectric layer 304 and a lower dielectric layer 302. A masking layer 702 is formed over the upper dielectric layer 304 so that a portion of the upper dielectric layer 304 is exposed. The upper dielectric layer 304 may be, for example, or include silicon dioxide, silicon glass, undoped silicon glass, etc. and is formed to a thickness in the range of about 5,500 angstroms to 6,500 angstroms. The lower dielectric layer 302 may be, for example, or include silicon carbide, silicon nitride, etc. and is formed to a thickness in the range of about 1,000 to 1,500 angstroms. The upper dielectric layer 304 and / or the lower dielectric layer 302 may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, or another suitable deposition process. The masking layer 702 may be or include, for example, a hard mask layer, a photoresist, etc.

[0126] like Figure 8 As shown in the cross-sectional view 800, according to the masking layer ( Figure 7 The passivation structure 112 is patterned using a masking layer 702 (for example, a masking layer 702) to define a bonding pad opening 802 and expose the upper surface of the topmost conductive wire 110a. In some embodiments, the patterning process includes exposing the unmasked areas of the upper dielectric layer 304 and the lower dielectric layer 302 to one or more etchants. In still other embodiments, after forming the bonding pad opening 802, a removal process is performed to remove the masking layer ( Figure 7 masking layer 702).

[0127] In some embodiments, the patterning process includes a selective etching process, which includes performing a first etching (e.g., dry etching) on ​​the upper dielectric layer 304 until the upper surface 302u of the lower dielectric layer 302 is exposed. In some embodiments, the first etching may over-etch a portion of the lower dielectric layer 302 and remove the portion of the lower dielectric layer 302, so that the upper surface 302u of the lower dielectric layer 302 is disposed below the bottom surface of the upper dielectric layer 304. In addition, after performing the first etching, a second etching (e.g., wet etching) is performed on the lower dielectric layer 302 until the upper surface of the topmost conductive wiring 110a is exposed.

[0128] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , a conductive layer 902 and a metal protective layer 904 are formed on the passivation structure 112 and the topmost conductive wiring 110a. The conductive layer 902 and the metal protective layer 904 fill the bonding pad opening ( Figure 8 The bonding pad opening 802 is formed on the metal protection layer 904. A masking layer 906 is formed on the metal protection layer 904. In some embodiments, the masking layer 906 may be, for example, a photoresist, a hard mask layer, etc. The conductive layer 902 may be, for example, or include aluminum, copper, aluminum copper, tantalum nitride, etc. and is formed to a thickness ranging from about 1,000 angstroms to 8,000 angstroms. In some other embodiments, the conductive layer 902 may, for example, include a first conductive layer including a first material (e.g., aluminum copper) and a second conductive layer including a second material (e.g., tantalum nitride) different from the first material (not shown). In some embodiments, the metal protection layer 904 may be, for example, or include silicon oxynitride, silicon carbide, silicon nitride, etc. and is formed to a thickness ranging from about 250 angstroms to 350 angstroms.

[0129] like Fig.10 As shown in the cross-sectional view 1000, according to the masking layer ( Fig. 9 The masking layer 906) will be the conductive layer ( Fig. 9 The conductive layer 902 and the metal protection layer 904 are patterned to define the bonding pad 114 and the conductive bonding structure 660. The conductive bonding structure 660 and the bonding pad 114 are offset from each other by a non-zero distance in the lateral direction. In some embodiments, after forming the bonding pad 114 and the conductive bonding structure 660, a removal process is performed to remove the masking layer ( Fig. 9 masking layer 906).

[0130] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , a masking layer 1102 is formed over the passivation structure 112 and the bonding pad 114. The masking layer 1102 may be, for example, a photoresist, a hard mask, or the like.

[0131] like Fig.12As shown in the cross-sectional view 1200, according to the masking layer ( Fig.11 The passivation structure 112, the interconnect dielectric structure 107, and the substrate 102 are patterned using a masking layer 1102 (for example, a masking layer 1102) to define a deep trench isolation structure opening 1202. In some embodiments, the patterning process includes, for example, performing a high-power plasma etching process to remove dielectric materials located below the unmasked area of ​​the upper dielectric layer 304 and between the passivation structure 112 and the substrate 102. In some embodiments, the deep trench isolation structure opening 1202 is defined between a memory array region and a logic region of an integrated chip (not shown). In some embodiments, after performing the patterning process, a removal process is performed to remove the masking layer ( Fig.11 masking layer 1102).

[0132] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , the metal protective layer ( Fig.12 The metal protection layer 904 is formed so as to expose the upper surface of the bonding pad 114 and the upper surface of the conductive bonding structure 660.

[0133] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , a buffer layer 116 is formed on the upper surface of the bonding pad 114. In some embodiments, the buffer layer 116 may be, for example, or include a nitride (e.g., titanium nitride, tantalum nitride, silicon nitride, or silicon oxynitride), or an oxide (e.g., titanium oxide, silicon dioxide, or silicon oxynitride), titanium, etc., and / or may be formed with a thickness t ranging from about 100 angstroms to 1,000 angstroms. bl . In some embodiments, the buffer layer 116 may be deposited and / or grown by CVD, PVD, ALD, thermal oxidation, or another suitable deposition process. An etch stop layer 118 is formed over the buffer layer 116, the passivation structure 112, and the substrate 102. In some embodiments, the etch stop layer 118 may be, for example, or include aluminum oxide, silicon oxynitride, another suitable oxide, etc. and is formed to have a thickness ranging from about 100 angstroms to 1,000 angstroms. In some embodiments, the etch stop layer 118 has the same thickness as the buffer layer 116. The etch stop layer 118 is provided to the deep trench isolation structure opening ( Fig.13 The deep trench isolation structure opening 1202 is lined with the etch stop layer 118 so that the etch stop layer 118 extends continuously from above the bonding pad 114 to the trench of the substrate 102. In some embodiments, the etch stop layer 118 can be deposited and / or grown by CVD, PVD, ALD, thermal oxidation, or another suitable deposition process.

[0134] In addition, if Fig.14As shown in the cross-sectional view 1400 of FIG. 1 , an upper dielectric structure 1402 is formed on the etch stop layer 118. The upper dielectric structure 1402 may be or include, for example, gold oxide, silicon dioxide, another oxide, etc. The upper dielectric structure 1402 fills the deep trench isolation structure opening ( Fig.13 In some embodiments, the upper dielectric structure 1402 may be deposited and / or grown by CVD, PVD, ALD, thermal oxidation, or another suitable deposition process. A masking layer 1404 is formed over the upper dielectric structure 1402. In some embodiments, the masking layer 1404 may be, for example, a hard mask, a photoresist, etc. The masking layer 1404 defines an opening over the bonding pad 114.

[0135] like Fig.15 As shown in the cross-sectional view 1500, according to the masking layer 1404 Fig.14 The structure of the upper dielectric structure 1402 is patterned to define a bump structure opening 1502 above the buffer layer 116. The patterning process may include performing a dry etching process (e.g., a plasma etching process) on the unmasked portion of the upper dielectric structure 1402 and the unmasked portion of the etch stop layer 118. In some embodiments, the dry etching process includes exposing the upper dielectric structure 1402 and the etch stop layer 118 to one or more etchants, such as tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), sulfur hexafluoride (SF6), hexafluorocyclobutene (C4F6), octafluorocyclopentene (C5F8), octafluorocyclobutane (C4F8), etc. In some embodiments, the dry etching process may over-etch a portion of the buffer layer 116 and remove the portion of the buffer layer 116, so that the upper surface 116us of the buffer layer 116 and the lower surface 118ls of the etch stop layer 118 are offset in the vertical direction by a non-zero vertical distance v1. Therefore, the dry etching process may remove the thickness t of the buffer layer 116 directly above the upper surface of the bonding pad 114. bl Reduced to a reduced thickness t bl’ . Reduced thickness t bl’ For example, the thickness may be in the range of about 50 angstroms to about 900 angstroms. In some other embodiments, the sidewalls of the upper dielectric structure 1402 and the sidewalls of the etch stop layer 118 are sloped (not shown).

[0136] In some embodiments, the thickness t of the buffer layer 116 isbl and materials, the upper surface of the bonding pad 114 is protected from the dry etching process. For example, if the thickness t bl If the thickness of the buffer layer 116 is 100 angstroms or greater, at least a portion of the buffer layer 116 will remain on the upper surface of the bonding pad 114 after a portion of the etch stop layer 118 is removed during the dry etching process. This prevents the conductive material (e.g., aluminum) from being re-deposited from the bonding pad 114 onto the sidewalls of the etch stop layer 118 and the sidewalls of the upper dielectric structure 1402 to some extent, while reducing the material used to form the bump structure opening 1502. This prevents the conductive material (e.g., aluminum) from being re-deposited from the bonding pad 114 onto the sidewalls of the etch stop layer 118 and the sidewalls of the upper dielectric structure 1402 to some extent, while facilitating the use of high-power etching during the dry etching process (i.e., reducing the manufacturing time). In addition, the buffer layer 116 protecting the upper surface of the bonding pad 114 during the dry etching process can reduce and / or eliminate the use of a treatment process (e.g., using argon vapor) on the upper surface of the bonding pad 114. This reduces to some extent the complexity associated with fabricating the bonding pads 114 and the overlying bump structures (e.g., Fig.17 The time, cost and yield loss associated with the bump structure 120).

[0137] like Fig.16 As shown in the cross-sectional view 1600 of Fig.15 The structure of the present invention performs an etching process, thereby further expanding the bump structure opening 1502 and exposing the upper surface of the bonding pad 114. After the etching process, the buffer layer 116 includes a curved sidewall and / or an inclined sidewall (not shown) directly overlying the upper surface of the bonding pad 114. The etching process may include a wet etching process using one or more etchants. In some embodiments, the one or more etchants may, for example, be or contain hydrogen peroxide (H2O2). The wet etching process may, for example, reach a maximum temperature of 70 degrees Celsius. In some embodiments, the etching process is selective to the buffer layer 116, which means that the material of the buffer layer 116 is etched by the one or more etchants at a first removal rate, and the material of the etch stop layer 118, the material of the upper dielectric structure 1402 and / or the material of the bonding pad 114 are etched by the one or more etchants at a second removal rate, and the second removal rate is much less than the first removal rate. In some embodiments, during the etching process that exposes the upper surface of bonding pad 114, the conductive material (e.g., aluminum) from bonding pad 114 is not re-deposited on the sidewalls of buffer layer 116 defining bump structure opening 1502, on the sidewalls of etch stop layer 118, and / or on the sidewalls of upper dielectric structure 1402. In yet other embodiments, after the etching process is performed, a removal process is performed to remove masking layer 1404 (not shown).

[0138] like Fig.17 As shown in the cross-sectional view 1700, in the bump structure opening ( Fig.16 The bump structure 120 is formed in the bump structure opening 1502 of the bonding pad 114. In some embodiments, the process for forming the bump structure 120 may include: forming a lower conductive structure 120b directly on the bonding pad 114 so that the lower conductive structure 120b is conformal with and / or directly contacts the curved sidewalls and / or inclined sidewalls (not shown) of the buffer layer 116; and subsequently forming an upper conductive structure 120a on the lower conductive structure 120b. In some other embodiments, the upper conductive structure 120a includes a first material (e.g., gold) that is different from a second material (e.g., nickel) of the lower conductive structure 120b.

[0139] like Fig.18 As shown in the cross-sectional view 1800 of FIG. 1 , an etching process is performed to remove the upper dielectric structure ( Fig.17 In some embodiments, the etching process includes performing Fig.17 The structure is exposed to steam etching and / or wet etching of one or more etchants. The one or more etchants may, for example, be or include hydrofluoric acid. In some further embodiments, after the etching process is performed with the one or more etchants (e.g., hydrofluoric acid), the conductive material along the opposite side walls 120s1, 120s2 of the bump structure 120 will not be peeled off and / or electrically short-circuited with adjacent conductive structures (e.g., conductive bonding structure 660). Therefore, since the buffer layer 116 protects the upper surface of the bonding pad 114 and since the upper surface of the bonding pad 114 is exposed using a wet etching process, peeling of the conductive material from the opposite side walls 120s1, 120s2 is reduced and / or does not occur.

[0140] Fig.19 A method 1900 for forming a bump structure overlying a bonding pad is shown. Although method 1900 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, these actions can be performed in a different order than shown, and / or can be performed simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, which can be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown can be omitted, and other actions or events not shown can be included.

[0141] At act 1902, an interconnect structure is provided that includes a topmost conductive wiring layer overlying a substrate, and a passivation structure is formed over the topmost conductive wiring layer. Figure 7 Cross-sectional view 700 corresponding to some embodiments of act 1902 is shown.

[0142] At act 1904, a bonding pad is formed over the topmost conductive wiring layer. The bonding pad overhangs the passivation structure and directly contacts the topmost conductive wiring. Figures 8 to 10 Cross-sectional views 800 through 1000 are shown corresponding to some embodiments of act 1904 .

[0143] At act 1906, the interconnect structure and the substrate are patterned to define a deep trench isolation structure opening. The deep trench isolation structure opening is laterally offset from the bonding pad by a non-zero distance. Fig.11 and Fig.12 Cross-sectional view 1100 and cross-sectional view 1200 corresponding to some embodiments of act 1906 are shown.

[0144] At act 1908, a buffer layer is deposited over the bonding pad, an etch stop layer is deposited over the buffer layer, and an upper dielectric structure is deposited over the etch stop layer. The etch stop layer lines the deep trench isolation structure opening. Fig.14 Cross-sectional view 1400 corresponding to some embodiments of act 1908 is shown.

[0145] At act 1910 , a dry etch is performed on the buffer layer, the etch stop layer, and the upper dielectric structure to define a bump structure opening. Fig.15 Cross-sectional view 1500 corresponding to some embodiments of act 1910 is shown.

[0146] At act 1912, a wet etch is performed on the buffer layer to expand the bump structure opening and expose the upper surface of the bonding pad. Fig.16 Cross-sectional view 1600 corresponding to some embodiments of act 1912 is shown.

[0147] At activity 1914 , a bump structure is formed in the bump structure opening. Fig.17 Cross-sectional view 1700 corresponding to some embodiments of act 1914 is shown.

[0148] At act 1916 , the upper dielectric structure is patterned, exposing sidewalls of the bump structure. Fig.18 Cross-sectional view 1800 corresponding to some embodiments of act 1916 is shown.

[0149] Therefore, in some embodiments, the present disclosure relates to a semiconductor structure including a bonding pad overlying a conductive wire. The bonding pad cups around a lower surface of a buffer layer and a bump structure extends through the buffer layer to contact the bonding pad. The sidewall of the bump structure includes a vertical sidewall segment overlying a curved sidewall segment.

[0150] In some embodiments, the present disclosure provides a semiconductor device structure, which includes: a bonding pad disposed on a semiconductor substrate; an etch stop layer overlying the bonding pad; a buffer layer disposed on the bonding pad and separating the etch stop layer from the bonding pad; and a bump structure, including a base portion and an upper portion, the base portion contacting an upper surface of the bonding pad, the upper portion extending through the etch stop layer and the buffer layer, wherein the base portion of the bump structure has a first width or diameter and the upper portion of the bump structure has a second width or diameter, the first width or diameter being greater than the second width or diameter.

[0151] In the above semiconductor device structure, the base portion of the bump structure intersects the buffer layer at a curved sidewall, and the upper portion of the bump structure intersects the etch stop layer at a vertical sidewall.

[0152] In the above-mentioned semiconductor device structure, the semiconductor device structure also includes: an internal connection structure, including a conductive wiring arranged on the semiconductor substrate, wherein the bonding pad is arranged on the conductive wiring and coupled to the conductive wiring; and a passivation layer, overlying the internal connection structure and arranged along the side wall of the bonding pad.

[0153] In the above semiconductor device structure, the etch stop layer is made of a first material and the buffer layer is made of a second material different from the first material.

[0154] In the above semiconductor device structure, the first material is aluminum oxide and the second material is titanium nitride.

[0155] In the above semiconductor device structure, a bottom surface of the bump structure is aligned with a bottom surface of the buffer layer.

[0156] In the above semiconductor device structure, the upper portion of the bump structure includes: a lower conductive structure comprising a first conductive material; and an upper conductive structure disposed above the lower conductive structure, wherein the upper conductive structure comprises a second conductive material different from the first conductive material.

[0157] In the above semiconductor device structure, the first conductive material is nickel and the second conductive material is gold.

[0158] In the above-mentioned semiconductor device structure, the upper surface of the bonding pad includes a peripheral area and a central area, the peripheral area has a first height above the upper surface of the semiconductor substrate, and the central area has a second height above the upper surface of the semiconductor substrate, and the first height is greater than the second height; and wherein the base portion of the bump structure intersects with the upper portion of the bump structure at a third height, and the third height is less than the first height and greater than the second height.

[0159] In some embodiments, the present disclosure provides a semiconductor device structure, the semiconductor device structure comprising: an interconnect structure overlying a substrate, the interconnect structure comprising a topmost conductive wiring; a passivation structure overlying the interconnect structure; a bonding pad overlying the topmost conductive wiring, wherein the bonding pad extends through the passivation structure and directly contacts the top surface of the topmost conductive wiring, wherein the bonding pad has an upper surface located below the top surface of the bonding pad in a vertical direction, and wherein the upper surface of the bonding pad is located below the top surface of the passivation structure in a vertical direction; an etch stop layer overlying the bonding pad and the passivation structure on; a buffer layer disposed between the etch stop layer and the bonding pad, wherein the bonding pad extends continuously along the lower side of the buffer layer and surrounds the lower side of the buffer layer in a cup shape; and a bump structure, including a base portion and an upper portion, the base portion contacts the upper surface of the bonding pad and is disposed in the buffer layer, the upper portion extends upward from the base portion and extends through the etch stop layer and the buffer layer, wherein the base portion has a first width defined in the buffer layer, and the upper portion has a second width defined above the top surface of the buffer layer, and wherein the first width is greater than the second width.

[0160] In the above-mentioned semiconductor device structure, the base portion of the bump structure is defined between the bottom surface of the buffer layer and the upper surface of the buffer layer, the bottom surface of the buffer layer directly contacts the upper surface of the bonding pad, and the upper surface of the buffer layer directly contacts the etch stop layer, and the base portion of the bump structure has a curved outer side wall.

[0161] In the above semiconductor device structure, the upper portion of the bump structure is defined from the upper surface of the buffer layer to a point above the top surface of the bonding pad, wherein the upper portion of the bump structure has a vertical sidewall.

[0162] In the above semiconductor device structure, the base portion is composed of nickel and the upper portion includes a gold layer overlying the nickel layer.

[0163] In the above semiconductor device structure, the bump structures are spaced apart in the lateral direction between the inner sidewalls of the bonding pads.

[0164] In the above semiconductor device structure, the etch stop layer extends continuously over the outer sidewall, the top surface, the inner sidewall and the upper surface of the buffer layer.

[0165] In the above semiconductor device structure, the bonding pad includes an aluminum-copper layer overlying a tantalum nitride layer, wherein the bump structure directly contacts the aluminum-copper layer.

[0166] In the above semiconductor device structure, both the bonding pad and the buffer layer include nitride.

[0167] In some embodiments, the present disclosure provides a method for forming a semiconductor device structure, the method comprising: forming a passivation structure above a conductive wiring; forming a bonding pad above the conductive wiring, wherein the bonding pad is suspended above the passivation structure; depositing a buffer layer above the bonding pad; depositing an etch stop layer above the buffer layer and the passivation structure; depositing an upper dielectric structure above the etch stop layer; performing a dry etching process on the buffer layer, the etch stop layer and the upper dielectric structure, the dry etching process defining a bump structure opening overlying an upper surface of the bonding pad, wherein after the dry etching process, a portion of the buffer layer overlies the upper surface of the bonding pad; performing a wet etching process on the buffer layer, the wet etching process removing the portion of the buffer layer overlying the upper surface of the bonding pad, wherein the wet etching process enlarges the bump structure opening and exposes the upper surface of the bonding pad; and forming a bump structure in the bump structure opening.

[0168] In the above method of forming a semiconductor device structure, the wet etching process defines a curved inner sidewall in the buffer layer directly overlying the upper surface of the bonding pad.

[0169] In the above-mentioned method for forming a semiconductor device structure, forming the bump structure includes: forming a nickel layer directly on the upper surface of the bonding pad, wherein the nickel layer is conformal to the curved inner sidewall of the buffer layer, and wherein the nickel layer includes a sidewall having a vertical sidewall directly overlying the curved sidewall; and forming a gold layer directly on the nickel layer, wherein the gold layer includes a vertical sidewall directly in contact with the vertical sidewall of the nickel layer.

[0170] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, comprising: A bonding pad disposed on the semiconductor substrate; an etch stop layer overlying the bonding pad; a buffer layer, disposed on the bonding pad and separating the etch stop layer from the bonding pad; as well as A bump structure, comprising a base portion and an upper portion, wherein the base portion contacts the upper surface of the bonding pad, and the upper portion extends through the etch stop layer and the buffer layer, wherein the base portion of the bump structure has a first width or diameter and the upper portion of the bump structure has a second width or diameter, the first width or diameter is greater than the second width or diameter, wherein the base portion and the upper portion are a single conductive structure and include the same conductive material. 2 . The semiconductor device structure of claim 1 , wherein the base portion of the bump structure intersects the buffer layer at a curved sidewall, and the upper portion of the bump structure intersects the etch stop layer at a vertical sidewall.

3. The semiconductor device structure according to claim 1, further comprising: an interconnect structure including a conductive wire disposed on the semiconductor substrate, wherein the bonding pad is disposed on and coupled to the conductive wire; as well as A passivation layer is overlying the interconnect structure and disposed along the sidewall of the bonding pad. 4 . The semiconductor device structure according to claim 1 , wherein the etch stop layer is made of a first material and the buffer layer is made of a second material different from the first material. 5 . The semiconductor device structure of claim 4 , wherein the first material is aluminum oxide and the second material is titanium nitride. The semiconductor device structure according to claim 1 , wherein a bottom surface of the bump structure is aligned with a bottom surface of the buffer layer.

7. The semiconductor device structure according to claim 1, wherein An upper conductive structure is disposed over the upper portion of the bump structure, wherein the upper conductive structure includes a second conductive material different from the same conductive material.

8. The semiconductor device structure of claim 7, wherein the same conductive material is nickel and the second conductive material is gold.

9. The semiconductor device structure according to claim 1, wherein the upper surface of the bonding pad includes a peripheral region and a central region, the peripheral region has a first height above the upper surface of the semiconductor substrate, the central region has a second height above the upper surface of the semiconductor substrate, and the first height is greater than the second height; and Wherein the base portion of the bump structure meets the upper portion of the bump structure at a third height, the third height being less than the first height and greater than the second height.

10. A semiconductor device structure, comprising: an interconnect structure overlying the substrate, the interconnect structure including a topmost conductive wiring; a passivation structure overlying the interconnect structure; a bonding pad overlying the topmost conductive wire, wherein the bonding pad extends through the passivation structure and directly contacts a top surface of the topmost conductive wire, wherein the bonding pad has an upper surface vertically below a top surface of the bonding pad, and wherein the upper surface of the bonding pad is vertically below a top surface of the passivation structure; an etch stop layer, overlying the bonding pad and the passivation structure; a buffer layer disposed between the etch stop layer and the bonding pad, wherein the bonding pad extends continuously along the lower side of the buffer layer and surrounds the lower side of the buffer layer in a cup shape, wherein the buffer layer comprises a conductive material; as well as A bump structure includes a base portion and an upper portion, wherein the base portion contacts the upper surface of the bonding pad and is disposed within the buffer layer, and the upper portion extends upward from the base portion and extends through the etch stop layer and the buffer layer, wherein the base portion has a first width defined within the buffer layer, and the upper portion has a second width defined above the top surface of the buffer layer, and wherein the first width is greater than the second width.

11. A semiconductor device structure according to claim 10, wherein the base portion of the bump structure is defined between the bottom surface of the buffer layer and the upper surface of the buffer layer, the bottom surface of the buffer layer directly contacts the upper surface of the bonding pad, and the upper surface of the buffer layer directly contacts the etch stop layer, and the base portion of the bump structure has a curved outer side wall. 12 . The semiconductor device structure of claim 11 , wherein the upper portion of the bump structure is defined from the upper surface of the buffer layer to a point above the top surface of the bonding pad, wherein the upper portion of the bump structure has a vertical sidewall.

13. The semiconductor device structure of claim 12, wherein the base portion is comprised of nickel and the upper portion comprises a gold layer overlying the nickel layer. 14 . The semiconductor device structure of claim 10 , wherein the bump structures are laterally spaced apart between inner sidewalls of the bonding pads. 15 . The semiconductor device structure according to claim 10 , wherein the etch stop layer continuously extends over the outer sidewalls, the top surface, the inner sidewalls and the upper surface of the buffer layer. 16 . The semiconductor device structure of claim 10 , wherein the bonding pad comprises an aluminum-copper layer overlying a tantalum nitride layer, wherein the bump structure directly contacts the aluminum-copper layer. 17 . The semiconductor device structure according to claim 10 , wherein both the bonding pad and the buffer layer comprise nitride.

18. A method for forming a semiconductor device structure, comprising: forming a passivation structure on the conductive wiring; forming a bonding pad over the conductive wire, wherein the bonding pad overhangs the passivation structure; depositing a buffer layer over the bonding pad; depositing an etch stop layer on the buffer layer and the passivation structure; depositing an upper dielectric structure over the etch stop layer; performing a dry etching process on the buffer layer, the etch stop layer, and the upper dielectric structure, the dry etching process defining a bump structure opening overlying an upper surface of the bonding pad, wherein after the dry etching process, a portion of the buffer layer overlies the upper surface of the bonding pad; Performing a wet etching process on the buffer layer, the wet etching process removing the portion of the buffer layer overlying the upper surface of the bonding pad, wherein the wet etching process enlarges the bump structure opening and exposes the upper surface of the bonding pad; as well as A bump structure is formed in the bump structure opening.

19. The method of forming a semiconductor device structure of claim 18, wherein the wet etching process defines a curved inner sidewall in the buffer layer directly overlying the upper surface of the bonding pad.

20. The method for forming a semiconductor device structure according to claim 19, wherein forming the bump structure comprises: forming a nickel layer directly over the upper surface of the bond pad, wherein the nickel layer is conformal to the curved inner sidewall of the buffer layer, and wherein the nickel layer includes a sidewall having a vertical sidewall directly overlying the curved sidewall; and A gold layer is formed directly over the nickel layer, wherein the gold layer includes vertical sidewalls in direct contact with the vertical sidewalls of the nickel layer.

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