semiconductor devices

Abstract

The semiconductor device may include standard cells arranged in a first direction and a second direction intersecting the first direction. The first direction and the second direction may both be parallel to the upper surface of the substrate. Each of the standard cells may include a semiconductor element. The semiconductor device may further include a filling cell located between two standard cells, and each of the filling cells may include a filling active area and a filling contact connected to the filling active area and extending in the first direction. The semiconductor device may further include a lower wiring pattern electrically connected to at least one of the semiconductor elements and extending into at least one of the filling cells in the second direction, and the filling contact may include a wiring filling contact that is lower than the lower wiring pattern and connected to at least one of the lower wiring patterns.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0007272 filed on January 20, 2020, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2019-0122523 filed on October 2, 2019, in the Korean Intellectual Property Office, the disclosures of all of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device and a method of manufacturing the same. Background Art

[0004] A semiconductor device may include semiconductor elements provided on a semiconductor substrate and wirings for connecting the semiconductor elements to each other. As the integration density of semiconductor devices increases, research on reducing the size of these wirings has been actively conducted. Summary of the Invention

[0005] Some embodiments of the inventive concept provide a semiconductor device in which wirings for connecting semiconductor elements included in standard cells are laid out in a filling cell region between the standard cells.

[0006] According to some embodiments of the present invention, a semiconductor device may include standard cells arranged in a first direction and a second direction on a substrate. The first direction and the second direction may both be parallel to the upper surface of the substrate, and the second direction may intersect with the first direction. Each of the standard cells may include a semiconductor element and a lower wiring pattern that may be electrically connected to at least one of the semiconductor elements and may extend in the second direction. The semiconductor device may further include a plurality of filler cells located on the substrate. Each of the filler cells may be located between two standard cells adjacent to each other in the second direction among the standard cells, and may include a filler active region and a filler contact that may be connected to the filler active region and may extend in the first direction. The filler cells may include a first filler cell located between a first standard cell and a second standard cell adjacent to each other in the second direction among the standard cells, and the lower wiring pattern of the first standard cell may extend into the first filler cell and may be connected to the filler contact of the first filler cell, and the filler contact of the first filler cell may be located between the substrate and the lower wiring pattern of the first standard cell.

[0007] According to some embodiments of the present invention, a semiconductor device may include: a standard cell region and a filling cell region, the standard cell region and the filling cell region being adjacent to each other in a direction that may be parallel to the upper surface of a substrate; at least one semiconductor element, the at least one semiconductor element being located in the standard cell region; at least one dummy element, the at least one dummy element being located in the filling cell region; a lower wiring pattern, the lower wiring pattern being located above the at least one semiconductor element and extending in the one direction; and a via structure, the via structure being in contact with at least one of the lower wiring patterns and being in contact with a filling contact. The filling contact may be in contact with an active area of ​​the dummy element in the filling cell region and may extend in a different direction that may intersect with the one direction. The at least one lower wiring pattern may extend continuously in the one direction from the standard cell region to the filling cell region.

[0008] According to some embodiments of the present invention, a semiconductor device may include: a standard cell located on a substrate; and a filler cell. Each of the filler cells may be located between two of the standard cells, and each of the filler cells may include a filler active region and a filler contact connected to the filler active region and extending in a first direction that may be parallel to an upper surface of the substrate. At least one of the filler cells includes a first filler contact and a second filler contact, wherein the second filler contact is spaced apart from the first filler contact in a second direction intersecting the first direction, and the first filler contact and the second filler contact have different lengths.

[0009] According to some embodiments conceived in the present invention, a method for manufacturing a semiconductor device may include: forming an active area on a substrate, the substrate including a standard cell area and a filling cell area, the standard cell area including standard cells, and the filling cell area including filling cells; forming a gate line that intersects the active area and extends in a first direction, and the first direction may be parallel to the upper surface of the substrate; forming a filling contact including at least one wiring filling contact, the at least one wiring filling contact may be connected to at least one active area in the active area in the filling cell area and may extend in the first direction; forming a via structure that contacts the at least one wiring filling contact in the filling contact; and forming a lower wiring pattern that contacts the upper surface of the via structure and extends into the standard cell area in a second direction that intersects the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept;

[0012] Figure 2 and Figure 3 is a top view illustrating a semiconductor device according to some embodiments of the present inventive concept;

[0013] Figure 4 is a circuit diagram illustrating an example of a unit circuit provided by a standard cell included in a semiconductor device according to some embodiments of the inventive concept;

[0014] Figure 5 and Figure 6 is shown with Figure 4 A top view of a standard cell corresponding to the unit circuit shown in FIG.

[0015] Figure 7 and Figure 8 is a diagram showing a comparative example of a semiconductor device;

[0016] Figure 9 is a flowchart illustrating a method of designing a layout of a semiconductor device according to some embodiments of the present inventive concept;

[0017] Figures 10 to 13 is a diagram illustrating a semiconductor device according to some embodiments of the present inventive concept;

[0018] Figure 14 is a flowchart illustrating a method of designing a layout of a semiconductor device according to some embodiments of the present inventive concept;

[0019] Figure 15 and Figure 16 is a diagram illustrating a semiconductor device according to some embodiments of the present inventive concept;

[0020] Figures 17 to 19 is a diagram illustrating a semiconductor device according to some embodiments of the present inventive concept;

[0021] Figure 20 and Figure 21 is a diagram illustrating a semiconductor device according to some embodiments of the present inventive concept;

[0022] Figure 22 are diagrams illustrating semiconductor devices according to some embodiments of the inventive concept; and

[0023] Figures 23 to 30are diagrams illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0024] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0025] Figure 1 is a flowchart illustrating a method of fabricating a semiconductor device according to example embodiments of the inventive concepts.

[0026] Reference Figure 1 The method of manufacturing a semiconductor device may begin by designing a register transfer level (RTL) (S10). The RTL code generated by designing the RTL may define the functionality of the semiconductor device. As an example, the RTL code may be represented by a language such as VHSIC Hardware Description Language (VHDL), Verilog, etc.

[0027] Once the RTL code is generated, a logic synthesis process (S11) for generating a netlist data of a semiconductor device from the RTL code can be performed using the standard cells stored in the library. The netlist data may include standard cells and data defining the connection relationships between the standard cells, and may be generated by a semiconductor design tool.

[0028] A placement and routing process (S12) may be performed to generate layout data with reference to the netlist data. The placement and routing process in operation S12 may be performed with reference to the layout of the standard cells stored in the library. A semiconductor design tool for performing the placement and routing process may refer to the library in which the standard cells are stored and the netlist data to generate layout data including information related to the layout of the standard cells and routing information for connecting the laid-out standard cells.

[0029] Once the placement and routing process is completed, optical proximity correction may be performed on the layout data generated in operation S12 (S13). Once the optical proximity correction is completed, mask data for forming various patterns on multiple layers may be generated (S14). The mask data may be used to perform exposure on a photoresist or the like, and after the mask is generated, a semiconductor process using the mask may be performed (S15) to manufacture a semiconductor device.

[0030] An empty area can be formed between at least a portion of the standard cells in the standard cells laid out during the layout and wiring process. The empty area can be a filling cell area that can include (for example, can be filled with) a filling cell. Unlike a standard cell that includes a semiconductor element (for example, a gate electrode and a source / drain region) that actually works, a unit circuit implemented by a semiconductor element, etc., the filling cell area can be a dummy area. Wiring patterns for connecting at least a portion of the semiconductor elements included in the adjacent standard cells can be formed in the filling cell area respectively. As used herein, the term "connection" can mean "electrical connection" and / or "physical connection". Each semiconductor element of the standard cell can be electrically connected to or coupled to at least one element of the semiconductor device and can perform a function during the operation of the semiconductor device. In contrast, the filling cell area of ​​the semiconductor device can include elements (i.e., dummy elements) that may not be electrically connected to or coupled to any element and may not perform a function during the operation of the semiconductor device. For example, a standard cell includes an active area electrically coupled to a gate and serving as a channel region during operation, and a filled cell includes a dummy active area, which may have the same or similar structure as the active area of ​​the standard cell but is not electrically coupled to the gate and does not serve as a channel region during operation.

[0031] The wiring pattern for connecting the semiconductor elements of the standard cell can be provided only on the semiconductor elements. In some embodiments, the filling contact that contacts the filled active area in the filling cell area can be used as a wiring pattern for electrically connecting the semiconductor elements included in the standard cell to each other. For example, at least a portion of the lower wiring pattern provided above the semiconductor element in the standard cell and extending from the standard cell to the filling cell can be electrically connected to each other through the filling contact included in the filling cell. Therefore, space for connecting these wiring patterns to each other can be ensured above and below the wiring pattern of the standard cell, so that the integration density of the semiconductor device can be improved. In addition, the wiring patterns can be connected to each other in an efficient manner, so that the electrical performance of the semiconductor device can be improved.

[0032] Figure 2 and Figure 3 is a top view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0033] Figure 2 is a top view illustrating a semiconductor device according to some embodiments, Figure 3 yes Figure 2 FIG. 1 is a top view of the semiconductor device shown in FIG. 2 , to show power wiring patterns M1 (VDD) and M1 (VSS) and the gate pattern GL.

[0034] Reference Figure 2 and Figure 3The semiconductor device may include a standard cell region SC and a filling cell region FC. Standard cells may be provided in the standard cell region SC to implement a substantially operational semiconductor element or / and circuit, and filling cells may be provided in the filling cell region FC.

[0035] although Figure 2 and Figure 3 It is shown that the first to eighth standard cells SC1 to SC8 are arranged in the standard cell region SC, but the present invention is not limited thereto. Various other standard cells may be arranged in the standard cell region SC. Similarly, although Figure 2 and Figure 3 It is shown that the first to sixth filling cells FC1 to FC6 are disposed in the filling cell region FC, but the present inventive concept is not limited thereto. Various other filling cells may be disposed in the filling cell region FC.

[0036] The semiconductor device may include power wiring patterns M1(VDD) and M1(VSS) arranged along a first direction (Y-axis direction). In some embodiments, the power wiring patterns M1(VDD) and M1(VSS) may be spaced apart from each other in the Y-axis direction, as shown in FIG. Figure 3 As shown. The power wiring patterns M1 (VDD) and M1 (VSS) may extend along a second direction (X-axis direction) intersecting the first direction. In some embodiments, the power wiring patterns M1 (VDD) and M1 (VSS) may extend longitudinally along the X-axis direction, as shown. Figure 3 As shown. As an example, the power wiring patterns M1 (VDD) and M1 (VSS) may extend along the boundary between the standard cell region SC and the filling cell region FC. In some embodiments, at least one of the power wiring patterns M1 (VDD) and M1 (VSS) may cross at least one of the standard cell region SC and the filling cell region FC.

[0037] The gate patterns GL may extend along the first direction and may be spaced apart from each other in the second direction. In some embodiments, the gate patterns may extend lengthwise along the Y-axis direction and may be spaced apart from each other in the X-axis direction. Figure 3 As shown. The gate pattern GL may include a gate electrode for providing a semiconductor element and a dummy gate electrode. For example, the dummy gate electrode may be provided on a boundary between the standard cell region SC and the filling cell region FC.

[0038] Figure 4 is a circuit diagram illustrating an example of a unit circuit provided by a standard cell included in a semiconductor device according to some embodiments of the inventive concept. Figure 5 and Figure 6 is a diagram showing some embodiments of the present invention. Figure 4 FIG. 1 is a top view of a standard cell corresponding to the unit circuit shown in FIG.

[0039] Reference Figure 4 , the unit circuit can be configured as an inverter circuit. The inverter circuit may include a pull-up element TR1 that receives a first power supply voltage VDD and a pull-down element TR2 that receives a second power supply voltage VSS, and the gate of the pull-up element TR1 and the gate of the pull-down element TR2 may be connected to each other and may provide an input terminal IN. One source / drain region of the pull-up element TR1 and one source / drain region of the pull-down element TR2 may be connected to each other and may provide an output terminal OUT. An inverter circuit may be an example of a unit circuit provided by a standard cell. A standard cell may provide various other circuits other than an inverter circuit.

[0040] Figure 5 and Figure 6 1 is a top view showing a standard cell providing an inverter circuit. Figure 5 , the standard cell 100A may include: a pair of base regions 102 spaced apart from each other in a first direction (Y-axis direction), a pair of active regions 103 defined in the base regions 102 and extending in a second direction (X-axis direction), and gate lines 110 and 111 extending in the first direction. The gate lines 110 and 111 may include a gate electrode 110 and a dummy gate electrode 111, and the gate electrode 110 may intersect the active region 103. As used herein, "element A extends in direction B" (or similar language) may mean that element A extends longitudinally in direction B. The dummy gate electrode 111 may not function as a gate electrode during operation.

[0041] The gate electrode 110 may provide the pull-up element TR1 and the pull-down element TR2 of the inverter circuit together with the active region 103. Figure 4 In the inverter circuit, since the gate of the pull-up element TR1 and the gate of the pull-down element TR2 are connected to each other, the gate electrode 110 can be shared by the pair of active regions 103. The gate electrode 110 can be connected to one of the wiring patterns 120 through the lower via 109. The wiring pattern 120 can be a wiring provided on the active region 103 and the gate lines 110 and 111, and can extend in the second direction.

[0042] The active regions 103 may be connected to active contacts 107. For example, the active contacts 107 may be disposed between gate lines 110 and 111 and may extend in the first direction. To provide an inverter circuit, the active contact 107 connected to the first active region of the pair of active regions 103 may be connected to a first power wiring pattern 121 via a lower via 109, and the active contact 107 connected to the second active region of the pair of active regions 103 may be connected to a second power wiring pattern 122 via a lower via 109. The first power wiring pattern 121 may supply a first power supply voltage VDD, and the second power wiring pattern 122 may supply a second power supply voltage VSS. In some embodiments, the first power wiring pattern 121 and the second power wiring pattern 122 may be disposed at the same level and may extend in the second direction.

[0043] Figure 6 The area of ​​the standard cell 100B shown in FIG. 1 may be smaller than Figure 5 The area of ​​the standard cell 100A is shown in FIG. Figure 5 and Figure 6 , in the first direction, the height of the standard cell 100B may be smaller than that of the standard cell 100A. Therefore, the number of wiring patterns 120 included in the standard cell 100B may be smaller than the number of wiring patterns 120 included in the standard cell 100A.

[0044] Recently, as the integration density of semiconductor devices increases, the area of ​​each of the standard cells 100A and 100B has been reduced, and therefore, the height of the standard cells 100A and 100B in the first direction may be reduced. Figure 6 As shown, the standard cell 100B having a reduced height in the first direction may include a smaller number of wiring patterns 120. To increase integration density, the number of wiring patterns 120 may be increased by reducing the width of each wiring pattern 120 or / and the gaps between the wiring patterns 120. However, in this case, there may be problems associated with increased resistance of the wiring patterns 120 or / and increased parasitic capacitance between the wiring patterns 120.

[0045] In some embodiments, at least a portion of the wiring patterns 120 of the standard cells 100A and 100B can be connected to each other using fill contacts included in the fill cells located in the fill cell region. The fill contacts can be connected to the fill active area included in the fill cells and can be set at a level lower than the level of the wiring patterns 120. Therefore, space for connecting the wiring patterns 120 can be additionally ensured without changing the layout of the standard cells 100A and 100B, and the integration density of the semiconductor device can be increased (e.g., improved). In addition, the width of the wiring patterns 120 can be kept unchanged, or the width of the wiring patterns 120 can be not significantly reduced, thereby reducing the degradation of the resistance properties and improving the electrical properties of the semiconductor device. Because the width of the wiring patterns 120 is not significantly reduced, the increase in parasitic capacitance is limited. In addition, by connecting the wiring patterns 120 using fill contacts formed in the fill cell region, the electrical properties of the semiconductor device can be improved. As used herein, "element A is located at a level lower than the level of element B" (or similar language) can mean that element A is closer to the substrate than element B. For example, element A and element B each include a surface facing the substrate, and the surface of element A may be closer to the substrate than the surface of element B.

[0046] Figure 7 and Figure 8 is a diagram illustrating a comparative example of a semiconductor device according to some embodiments.

[0047] Reference Figure 7 , the semiconductor device 200 in the comparative example may include standard cells SC1 to SC4 and filler cells FC1 and FC2. The standard cells SC1 to SC4 may be arranged in a first direction (Y-axis direction) and a second direction (X-axis direction), and the gate lines 210, 211, and 212 may be arranged at a specific gap. In addition, power wiring patterns 221 and 222 may be arranged on the boundaries between the standard cells SC1 to SC4. The standard cells SC1 to SC4 may be arranged in a standard cell region, and the filler cells FC1 and FC2 may be arranged in the filler cell region.

[0048] The wiring patterns included in the standard cells SC1 to SC4 (e.g., lower wiring patterns 220) can be electrically connected to each other via wiring patterns (e.g., upper wiring patterns 240) disposed in the fill cell region. In other words, the lower wiring patterns 220 extending in the second direction (X-axis direction) can be disposed in the standard cell region, and the upper wiring patterns 240 extending in the first direction (Y-axis direction) can be disposed in the fill cell region. The upper wiring patterns 240 can be disposed on the lower wiring patterns 220 in the third direction (Z-axis direction) and can be connected to the lower wiring patterns 220 via upper vias 230.

[0049] Reference Figure 8 , that is, along Figure 7 In the cross-sectional view taken along line II' in FIG, the semiconductor device 200 may include a substrate 201, a base region 202 formed on the substrate 201, an active region 203 formed on the base region 202, and a substrate insulating layer 204 surrounding the active region 203. The active region 203 may be defined as a filled active region included in a filled cell. The active region 203 may include a fin structure, and a source / drain region 205 may be connected to the active region 203. An active contact 207 extending in a first direction may be connected to the source / drain region 205.

[0050] The lower wiring pattern 220, the upper via 230, and the upper wiring pattern 240 may be disposed on the source / drain region 205. The upper via 230 may connect the lower wiring pattern 220 to the upper wiring pattern 240. The source / drain region 205, the lower wiring pattern 220, the upper via 230, and the upper wiring pattern 240 may be located in interlayer insulating layers 251 to 255 (250).

[0051] In the comparative example, during the wiring process for interconnecting lower wiring patterns 220 of semiconductor elements connected to standard cells SC1 to SC4, upper wiring patterns 240 may be formed in the fill cell region where fill cells FC1 and FC2 are located. As the integration density of semiconductor device 200 increases and the area of ​​standard cells SC1 to SC4 decreases with the increase in integration density, the number of lower wiring patterns 220 included in each of standard cells SC1 to SC4 decreases. Therefore, in addition to the upper wiring patterns 240 disposed in the fill cell region as shown, it may be necessary to secure other resources for the process of wiring standard cells SC1 to SC4.

[0052] According to some embodiments of the present invention, active contacts (referred to herein as fill contacts) formed in the fill cell region may be used when wiring the standard cells SC1 to SC4. For example, the active contacts (e.g., fill contacts) in the fill cell region may be used when wiring the standard cells SC1 to SC4. Figure 11 and Figure 12 307 in the filler cell region may be formed at the same level as the active contacts (not shown) of the standard cells SC1 to SC4. To wire the standard cells SC1 to SC4, the active contacts in the filler cell region may have a length in the first direction that is different from the length of each active contact of the standard cells SC1 to SC4. In some embodiments, the lower wiring patterns (e.g., Figure 10At least a portion of the lower wiring patterns in 320) may be connected to each other using pre-formed active contacts having the same length in the first direction as that of each of the filling cells FC1 and FC2.

[0053] Subsequently, by wiring the standard cells SC1 to SC4 using active contacts disposed at a lower level than the lower wiring pattern 220 in the cell filling region and upper wiring patterns 240 disposed at a higher level than the lower wiring pattern 220, resources required for wiring can be secured. Therefore, the integration density of the semiconductor device 200 can be increased, and by efficiently securing wiring paths, electrical properties can be improved, and the performance of the semiconductor device 200 can be improved.

[0054] Figure 9 is a flowchart illustrating a method of designing a layout of a semiconductor device according to some embodiments of the inventive concept.

[0055] Reference Figure 9 The method for designing a layout of a semiconductor device may begin by laying out standard cells (S20). The standard cells may be pre-stored in a library and may provide a unit circuit for manufacturing a semiconductor device.

[0056] Once the standard cells are laid out, a wiring process (S21) may be performed in the filler cell regions defined between the standard cells. In some embodiments, while performing the wiring process of operation S21, a wiring extending in the same direction as the gate line extending in the filler cell regions may be formed. For example, the wiring may be an active contact located in the filler cell regions. In some embodiments, at least a portion of the active contacts provided in the filler cell regions may be designed differently and used during wiring.

[0057] Once the wiring process in operation S21 is completed, a filler cell may be inserted into the filler cell region (S22). The filler cell inserted in operation S21 may include active contacts pre-designed in the filler cell region in operation S21. In some embodiments, the filler cell inserted in operation S22 may include gate lines, source / drain regions, active contacts, etc., and the active contacts of the filler cell may be determined according to the design determined in operation S21.

[0058] Once the insertion of the filler cells is complete, the routing process for the remaining standard cells can be performed. Once the routing process is terminated, the layout data can be provided as a Graphic Design System (GDS) type or GDS II type data. Once the layout data is generated, a Design Rule Check (DRC) process can be performed on the layout data or / and a layout and schematic verification process for verifying whether the layout data matches the originally intended design circuit. Figure 1 When the layout data is confirmed through the above process, optical proximity correction can be performed on the layout data to generate mask design data, a mask can be produced according to the mask design data, and a semiconductor process can be performed on the semiconductor substrate.

[0059] Figures 10 to 13 is a diagram illustrating a semiconductor device according to some embodiments.

[0060] Reference Figure 10 , the semiconductor device 300 may include standard cells SC1 to SC4 and filling cells FC1 and FC2 arranged in the filling cell region between the standard cells SC1 to SC4. The standard cells SC1 to SC4 may be arranged in a first direction (Y-axis direction) and a second direction (X-axis direction), and a specific gap may be provided between the gate lines 310, 311, and 312. The gate lines 310 to 312 may extend in the first direction and may be spaced apart from each other in the second direction. In some embodiments, the gate lines 310, 311, and 312 may be spaced apart by a predetermined distance in the second direction, such as Figure 10 The gate lines 310 to 312 may include gate electrodes 310 disposed in the standard cells SC1 to SC4 , dummy gate electrodes 311 extending along boundaries of the standard cells SC1 to SC4 , and filling gate electrodes 312 disposed in the filling cells FC1 and FC2 .

[0061] The power wiring patterns 321 and 322 may be disposed on the boundaries of the standard cells SC1 to SC4. The power wiring patterns 321 and 322 may extend in the second direction and may be spaced apart from each other in the first direction. In some embodiments, the power wiring patterns 321 and 322 may be spaced apart from each other in the first direction.

[0062] The standard cells SC1 to SC4 may include lower wiring patterns 320 extending in the second direction. The number of lower wiring patterns 320 included in each of the standard cells SC1 to SC4 may vary. In some embodiments, the lower wiring patterns 320 may be disposed at the same level as the power wiring patterns 321 and 322, but the present invention is not limited thereto. In some embodiments, the lower wiring patterns 320 and the power wiring patterns 321 and 322 may be disposed at different levels.

[0063] In some embodiments, at least a portion of the lower wiring patterns 320 included in the standard cells SC1 to SC4 may be electrically connected to one another via at least one of the fill contacts 307 and 308 included in the fill cells FC1 and FC2. The fill contacts 307 and 308 may include a wiring fill contact 307 used in a layout process for connecting at least a portion of the lower wiring patterns 320 to one another, and a dummy fill contact 308 not used in the layout process. In some embodiments, the wiring fill contact 307 may be connected to the lower wiring pattern 320 via a lower via 309 extending in a third direction (Z-axis direction). In some embodiments, no lower via 309 may be connected to the dummy fill contact 308, and each dummy fill contact 308 may not be electrically connected to any element of the standard cells SC1 to SC4.

[0064] The filling contacts 307 and 308 included in the filling cell region may be designed based on the position of the lower wiring pattern 320 connected to the wiring filling contact 307. For example, the position and length of each wiring filling contact 307 may be determined according to the position of the lower wiring pattern 320 connected to the wiring filling contact 307. A dummy filling contact 308 may be provided in a region where no wiring filling contact 307 is provided.

[0065] In some embodiments, at least one of the filler cells FC1 and FC2 may include a first filler contact and a second filler contact disposed on both sides of the filler gate electrode 312. In some embodiments, at least one of the filler cells FC1 and FC2 may include a first filler contact and a second filler contact adjacent to opposite sides of the filler gate electrode 312, respectively. At least one of the first filler contact and the second filler contact may be provided as a wiring filler contact 307, and the position and length of the wiring filler contact 307 may vary depending on the position of the lower wiring pattern 320 connected by the wiring filler contact 307. Therefore, in at least one of the filler cells FC1 and FC2, the first filler contact and the second filler contact may have different lengths.

[0066] exist Figure 10In some embodiments shown in FIG, first filler cell FC1 may include a first wiring filler contact 307 disposed on the left side of filler gate electrode 312 and a second wiring filler contact 307 disposed on the right side of filler gate electrode 312. In the first direction, the length of first wiring filler contact 307 may be shorter than the length of second wiring filler contact 307, and second wiring filler contact 307 may span adjacent filler cells FC1 and FC2 in the first direction. Both first wiring filler contact 307 and second wiring filler contact 307 may be configured as wiring regions for connecting at least a portion of the various semiconductor elements included in standard cells SC1 to SC4 and disposed at different locations.

[0067] Reference Figure 10 One of the wiring fill contacts 307 can connect the lower wiring patterns 320 included in the first standard cell SC1 and the second standard cell SC2 to each other. In other words, the semiconductor elements of two or more standard cells SC1 and SC2, which are arranged at the same position in the first direction and at different positions in the second direction, can be electrically connected to each other through one of the wiring fill contacts 307. The other wiring fill contacts 307 can connect the lower wiring patterns 320 included in the second standard cell SC2 and the third standard cell SC3 to each other. In other words, the semiconductor elements of two or more standard cells SC2 and SC3, which are arranged at different positions in the first direction and the second direction, can be electrically connected to each other through the other wiring fill contacts 307.

[0068] According to the wiring design, the wiring filling contacts 307 included in the first filling cell FC1 may have different lengths in the first direction. At least one wiring filling contact 307 may span the filling cell regions (eg, Figure 10 FC1 and FC2 in the first and second standard cells SC1 to SC4 are provided.

[0069] In some embodiments, the designs of filler cells FC1 and FC2 stored in the library may not include filler contacts 307 and 308 connected to the source / drain regions. During the wiring process for laying out standard cells SC1 to SC4 and connecting lower wiring patterns 320 to one another, the position and length of each of filler contacts 307 and 308 may be designed, and filler cells FC1 and FC2 may be inserted into the filler cell region. Therefore, the designs of filler cells FC1 and FC2 may not include definitions of the position and length of each active contact.

[0070] At least a portion of the filling contacts 307 and 308 may be spaced apart from each other in the first direction in one of the filling cells FC1 and FC2. Figure 10 , the wiring fill contact 307 and the dummy fill contact 308 may be separated from each other in the first direction in the first fill cell FC1. A contact separation region CD may be defined between the wiring fill contact 307 and the dummy fill contact 308. In the first direction, the width of each contact separation region CD may be the same as or different from the width of each of the power wiring patterns 321 and 322. For example, the width of each contact separation region CD in the first direction may be smaller than the width of each of the power wiring patterns 321 and 322 in the first direction.

[0071] Reference Figure 11 , that is, along Figure 10 In the cross-sectional view taken along line II-II' in FIG, the semiconductor device 300 may include a substrate 301, a base region 302 formed on the substrate 301, an active region 303 formed on the base region 302, and a substrate insulating layer 304 surrounding the active region 303. The active region 303 may be configured as a filled active region included in a filled cell and may be a fin structure. Each active region 303 may have a fin-shaped active region. Source / drain regions 305 may be connected to the active region 303. Filling contacts 307 and 308 may be provided on the source / drain regions 305.

[0072] The filling contacts 307 and 308 may include a wiring filling contact 307 and a dummy filling contact 308. A lower via 309 and a lower wiring pattern 320 may be provided on the wiring filling contact 307. The filling contacts 307 and 308, the lower via 309, and the lower wiring pattern 320 may be covered by interlayer insulating layers 351, 352, and 353 (350). In some embodiments, the filling contacts 307 and 308, the lower via 309, and the lower wiring pattern 320 may be located in the interlayer insulating layers 351 to 353 (350). At least a portion of the lower wiring pattern 320 may be electrically connected to each other through the lower via 309 and the wiring filling contact 307. According to Figure 11In the embodiment shown in FIG. 5 , the lower wiring patterns 320 included in the first standard cell SC1 and the second standard cell SC2 may be electrically connected to each other through the lower via 309 and the wiring filling contact 307 .

[0073] like Figure 11 As shown, at least a portion of the lower wiring patterns 320 may be connected to each other using wiring filling contacts 307 provided in at least one of the filling cell regions in which the filling cells FC1 and FC2 are provided. To connect the lower wiring patterns 320 to each other, at least one of the filling contacts 307 and 308 in the filling cell region may extend further in the first direction than the source / drain region 305.

[0074] Reference Figure 12 , that is, along Figure 10 In the cross-sectional view taken along line III-III' in FIG, at least one wiring filling contact 307 may span the first filling cell FC1 and the second filling cell FC2 and may extend in the first direction. Therefore, in the first direction, the length of at least one wiring filling contact 307 may be greater than the length of the first filling cell FC1.

[0075] Wiring fill contact 307 can electrically connect the second standard cell SC2, which is adjacent to the first fill cell FC1 in the second direction, to the third standard cell SC3, which is adjacent to the second fill cell FC2 in the second direction. By ensuring that the wiring region connecting the second standard cell SC2 and the third standard cell SC3 to each other is located at a lower level than the level of the lower wiring pattern 320, the integration density of the semiconductor device 300 can be improved. In addition, by designing the wiring path in an efficient manner, the electrical properties of the semiconductor device 300 can also be improved.

[0076] Figure 13 It is along Figure 10 A cross-sectional view taken along line IV-IV'. Figure 13 The semiconductor device 300 may include a substrate 301, a body region 302, and an active region 303. The active region 303 may include a filling active region disposed in the first filling cell FC1 and a device active region disposed in the first standard cell SC1. The active region 303 may be connected to a channel region 303C in a third direction, and the channel region 303C may be covered by gate lines 310 to 312.

[0077] The channel region 303C may be connected to the source / drain region 305 in the second direction. The source / drain region 305 may include a lower region 305A and an upper region 305B. The lower region 305A may be grown from the active region 303, and the upper region 305B may be grown from the lower region 305A. Depending on the type of semiconductor element included in the semiconductor device 300, the source / drain region 305 may be doped with N-type impurities or P-type impurities.

[0078] Gate electrode 310 and source / drain region 305 may provide a semiconductor element between dummy gate electrode 311. Furthermore, filler gate electrode 312 may provide a dummy element together with source / drain regions 305 adjacent to each other in the second direction. Thus, semiconductor elements may be provided in standard cells SC1 to SC4, and dummy elements may be provided in filler cells FC1 and FC2.

[0079] In the first filling cell FC1, a wiring filling contact 307 may be connected to the source / drain region 305. In some embodiments, an intermediate conductive layer 306 formed of a metal silicide material, etc., may be provided between the wiring filling contact 307 and the source / drain region 305. The wiring filling contact 307 may include a first contact layer 307A and a second contact layer 307B, and the first contact layer 307A and the second contact layer 307B may be formed of a conductive material. For example, the first contact layer 307A and the second contact layer 307B may be formed of different conductive materials.

[0080] The wiring filling contact 307 may be connected to the lower wiring pattern 320 through the lower via 309. The lower via 309 may be in contact with the wiring filling contact 307, which is connected to the source / drain region 305 of the dummy element provided in the first filling cell FC1 and extends in the first direction. The lower via 309 may be in contact with the lower wiring pattern 320 extending in the second direction. Figure 13 In the example embodiment shown in FIG, the lower wiring pattern 320 may cross the first standard cell SC1 and the first filling cell FC1 in the second direction and may extend in the second direction, and may be connected to at least one of the semiconductor elements provided in the first standard cell SC1, for example.

[0081] exist Figure 13 , the lower wiring pattern 320 may be connected to one of the source / drain regions 305 of the semiconductor element provided in the first standard cell SC1, but the present inventive concept is not limited thereto. For example, the lower wiring pattern 320 may be connected to at least one of the gate electrodes 310 included in the first standard cell SC1 or other standard cells SC2 to SC4.

[0082] Each gate line 310 to 312 may include a gate insulating layer GOX, a gate spacer SPC, a first gate electrode GE1, a second gate electrode GE2, and a capping layer CAP. The first gate electrode GE1 and the second gate electrode GE2 may be formed of a conductive material, and may be formed of, for example, different conductive materials.

[0083] As reference Figures 10 to 13 As described, the lower wiring patterns 320 in the semiconductor device 300 can be electrically connected to each other through the wiring filling contacts 307 provided below the lower wiring patterns 320 located in the filling cell region. Figures 10 to 13 Although not shown, the lower wiring pattern 320 in the semiconductor device 300 may be formed by an upper wiring pattern (eg, Figure 7 and Figure 8 Therefore, it is possible to ensure that the wiring area for connecting the lower wiring patterns 320 included in the standard cells SC1 to SC4 is located at a level lower than that of the lower wiring patterns 320 and also at a level higher than that of the lower wiring patterns 320, and the integration density and electrical properties of the semiconductor device 300 can be improved.

[0084] Figure 14 is a flowchart illustrating a method of designing a layout of a semiconductor device according to some embodiments of the inventive concept.

[0085] Reference Figure 14 , the method for designing a semiconductor device may begin by laying out a standard cell (S30). Figure 9 The above-described example embodiments describe that standard cells may be pre-stored in a library and may provide a unit circuit for manufacturing a semiconductor device.

[0086] Once the standard cells are laid out, filler cells may be inserted into the filler cell regions defined between the standard cells (S31). The filler cells inserted in operation S31 may include a filler gate electrode, a source / drain region, and an active contact. As an example, the active contacts included in the filler cell may be provided on both sides of the filler gate electrode. In addition, the active contacts may extend within the filler cell.

[0087] Once the insertion of the filling cell is completed, a wiring process (S32) can be performed using the active contacts of the filling cell. The wiring process in operation S32 may include a process for connecting the active contacts included in the filling cell to the wiring pattern of the adjacent standard cell adjacent to the filling cell. For example, the active contacts of the filling cell can be connected to the lower wiring pattern extending from the standard cell using a lower path. The lower path can contact the upper surface of each active contact of the filling cell and the lower surface of each lower wiring pattern extending from the standard cell. When the wiring process using the active contacts of the filling cell is terminated, the remaining wiring processes can be performed and layout data can be generated.

[0088] Figure 15 and Figure 16 is a diagram illustrating a semiconductor device according to some embodiments.

[0089] Reference Figure 15 , the semiconductor device 400 may include standard cells SC1 to SC4 and filling cells FC1 and FC2 arranged in the filling cell area between the standard cells SC1 to SC4. The standard cells SC1 to SC4 may be arranged in a first direction (Y-axis direction) and a second direction (X-axis direction), and the gate lines 410, 411 and 412 may be arranged at specific gaps. The gate lines 410 to 412 may extend in the first direction and may be spaced apart from each other in the second direction. The gate lines 410 to 412 may include a gate electrode 410 arranged in the standard cells SC1 to SC4, a dummy gate electrode 411 extending along the boundary of the standard cells SC1 to SC4, and a filling gate electrode 412 arranged in the filling cells FC1 and FC2. In some embodiments, the gate lines 410, 411 and 412 may extend longitudinally in the first direction and may be spaced apart by a predetermined distance in the second direction, such as Figure 15 shown.

[0090] The power wiring patterns 421 and 422 may be provided on the boundaries of the standard cells SC1 to SC4. The power wiring patterns 421 and 422 may extend in the second direction and may be spaced apart in the first direction. In some embodiments, the power wiring patterns 421 and 422 may extend longitudinally in the second direction and may be spaced apart from each other at a predetermined distance in the first direction, such as Figure 15 shown.

[0091] The standard cells SC1 to SC4 may include lower wiring patterns 420 extending in the second direction. The number of lower wiring patterns 420 respectively included in the standard cells SC1 to SC4 may vary, and the present inventive concept is not limited thereto. Figure 15 The number of lower wiring patterns 420 shown in . Figure 15In the embodiment of the present invention, the number of lower wiring patterns 420 included in each of the standard cells SC1 to SC4 may be the same, but the number of lower wiring patterns 420 included in at least a portion of the standard cells SC1 to SC4 may be different. In some embodiments, the lower wiring pattern 420 may be arranged at the same level as the power wiring patterns 421 and 422 in the third direction (Z-axis direction). In some embodiments, the lower wiring pattern 420 and the power wiring patterns 421 and 422 may be arranged at different levels.

[0092] In some embodiments, at least a portion of the lower wiring patterns 420 included in the standard cells SC1 to SC4 may extend into the fill cell region and may be electrically connected to each other through at least one of the fill contacts 407 and 408 included in the fill cells FC1 and FC2. The fill contacts 407 and 408 may include wiring fill contacts 407 and dummy fill contacts 408, and at least a portion of the lower wiring patterns 420 may be electrically connected to each other through the wiring fill contacts 407. The fill contacts 407 and 408 disposed at the same position in the second direction may be separated from each other in the first direction by contact separation regions CD disposed below the power wiring patterns 421 and 422.

[0093] The lower wiring pattern 420 may be connected to the wiring filling contact 407 through a lower via 409 extending in the third direction, and the wiring filling contact 407 may extend in the first direction. The wiring filling contact 407 of the filling cells FC1 and FC2 may be provided as a routing wiring for connecting the lower wiring pattern 420 at a level lower than that of the lower wiring pattern 420.

[0094] The filling contacts 407 and 408 of the filling cells FC1 and FC2 may each have a shape according to a predetermined design rule. Figure 15 In the example embodiment shown in FIG, each of filling contacts 407 and 408 may have a length not exceeding that of each of filling cells FC1 and FC2 and may extend in the first direction. The length of each of filling contacts 407 and 408 may be the same as or less than the length of each of filling cells FC1 and FC2 in the first direction. Filling contacts 407 and 408 may not extend to standard cells SC1 to SC4.

[0095] In some embodiments, the wiring process of the filling contacts 407 and 408 using the filling cells FC1 and FC2 may include a process of specifying the position of each lower via 409. Figure 15As shown, by providing a lower via 409 in the first filling cell FC1, the first standard cell SC1 and the second standard cell SC2 can be electrically connected to each other. Figure 15 As shown, by providing a lower via 409 in the second filling cell FC2 , the third standard cell SC3 and the fourth standard cell SC4 may be electrically connected to each other.

[0096] By providing an upper wiring pattern (not shown) for connecting the lower wiring pattern 420 on the lower wiring pattern 420 and also providing lower vias 409 in the filling cells FC1 and FC2, respectively, the wiring filling contacts 407 of the filling cells FC1 and FC2 can be used as wiring lines for connecting the lower wiring patterns 420 to each other. Therefore, areas for connecting the lower wiring patterns 420 can be ensured above and below the lower wiring patterns 420, and the integration density of the semiconductor device 400 can be improved. In addition, by connecting the lower wiring patterns 420 in an efficient manner using the wiring filling contacts 407, the electrical properties and performance of the semiconductor device 400 can be improved. According to some embodiments of the present invention, multiple lower wiring patterns (e.g., Figure 15 and Figure 16 420 in) can be electrically connected to each other by conductive elements disposed above or below these lower wiring patterns. In other words, according to some embodiments of the present inventive concept, the two regions above and below the lower wiring patterns may include conductive elements for wiring these lower wiring patterns.

[0097] The dummy filling contact 408 may not be connected to the lower via 409, and thus, the dummy filling contact 408 may be electrically isolated from the lower wiring pattern 420. Figure 15 In the example embodiment shown in FIG, both fill cells FC1 and FC2 may include a wiring fill contact 407 and a dummy fill contact 408, but the present inventive concept is not limited thereto. For example, at least one of fill cells FC1 and FC2 may include only a wiring fill contact 407, and at least the other of fill cells FC1 and FC2 may include only a dummy fill contact 408.

[0098] Reference Figure 16 , that is, along Figure 15 In the cross-sectional view taken along line V-V' in FIG, semiconductor device 400 may include a substrate 401, a base region 402 formed on substrate 401, an active region 403 formed on base region 402, and a substrate insulating layer 404 surrounding active region 403. Active region 403 may be configured as a filled active region included in a filled cell. Active region 403 may be connected to source / drain region 405. Filling contacts 407 and 408 may be connected to source / drain region 405.

[0099] The filling contacts 407 and 408 may include a wiring filling contact 407 and a dummy filling contact 408, and Figure 16 In the cross-sectional view taken along line V-V' shown in FIG, only the wiring filling contact 407 may be shown. The wiring filling contact 407 may extend in the first direction between the power wiring patterns 421 and 422. The wiring filling contact 407 may have a length in the first direction that does not exceed the length of the power wiring patterns 421 and 422. In some embodiments, the length of the wiring filling contact 407 in the first direction may be equal to Figure 15 The distance between the power supply wiring patterns 421 and 422 in the first direction is shown to be equal to or shorter than the distance between the power supply wiring patterns 421 and 422 in the first direction.

[0100] The lower via 409 and the lower wiring pattern 420 may be provided on the wiring filling contact 407, and the wiring filling contact 407, the lower via 409, and the lower wiring pattern 420 may be covered by the interlayer insulating layers 451 to 453 (450). At least a portion of the lower wiring pattern 420 may be electrically connected to each other through the lower via 409 and the wiring filling contact 407.

[0101] Figures 17 to 19 is a diagram illustrating a semiconductor device according to some embodiments.

[0102] Reference Figure 17 , the semiconductor device 500 may include standard cells SC1 to SC4 and filler cells FC1 and FC2 disposed in a filler cell region between the standard cells SC1 to SC4. The standard cells SC1 to SC4 may be disposed in a first direction (Y-axis direction) and a second direction (X-axis direction), and may include gate lines 510, 511, and 512 disposed therebetween with a specific gap. Power supply wiring patterns 521 and 522 may be disposed on the boundaries between the standard cells SC1 to SC4 and the filler cells FC1 and FC2. The power supply wiring patterns 521 and 522 may be spaced apart from each other in the first direction and may extend in the second direction.

[0103] The semiconductor device 500 may include lower wiring patterns 520 extending in the second direction, and the number of the lower wiring patterns 520 may vary, and the present inventive concept is not limited to Figure 17At least a portion of the lower wiring patterns 520 may be electrically connected to each other through at least one of the filling contacts 507 and 508 included in the filling cells FC1 and FC2. The filling contacts 507 and 508 may include a wiring filling contact 507 for a wiring process for connecting at least a portion of the lower wiring patterns 520 and a dummy filling contact 508 that is not used in the wiring process. For example, the wiring filling contact 507 may be connected to the lower wiring pattern 520 through a lower via 509 extending in a third direction (Z-axis direction). In addition, as Figure 18 As shown, the wiring filling contact 507 , the lower via 509 , and the lower wiring pattern 520 may be covered by interlayer insulating layers 551 to 553 ( 550 ).

[0104] Filling contacts 507 and 508 can be designed according to the lower wiring pattern 520 connected to the wiring filling contact 507. For example, the position and length of each wiring filling contact 507 can be determined according to the position of the lower wiring pattern 520 connected to the wiring filling contact 507. The dummy filling contact 508 can be provided in an area where the wiring filling contact 507 is not provided. Therefore, a wiring area can be ensured above and below the lower wiring pattern 520. According to some embodiments of the present invention, multiple lower wiring patterns (e.g., Figures 17 to 19 520 in the figure) can be electrically connected to each other through conductive elements disposed above or below the lower wiring patterns. In other words, according to some embodiments, the two regions above and below the lower wiring patterns can include conductive elements for wiring the lower wiring patterns.

[0105] The contact separation regions CD1 and CD2 may be provided between the filling contacts 507 and 508. For example, referring to Figure 17 , the filling contacts 507 and 508 disposed at the same position in the second direction may be separated from each other in the first direction by the contact separation regions CD1 and CD2. For example, the contact separation regions CD1 and CD2 may include a first contact separation region CD1 and a second contact separation region CD2. The first contact separation region CD1 may be disposed at a position different from that of the power wiring patterns 521 and 522. In some embodiments, the first contact separation region CD1 may be disposed in one of the filling cells FC1 and FC2. The second contact separation region CD2 may be disposed at the same position as that of at least one of the power wiring patterns 521 and 522 in the first direction. The second contact separation region CD2 may be disposed below at least one of the power wiring patterns 521 and 522.

[0106] Figure 18 It is along Figure 17 A cross-sectional view taken along line VI-VI' in FIG. Figure 19 It is along Figure 17 The cross-sectional view taken along line VII-VII' in FIG. Figure 18 and Figure 19 , the semiconductor device 500 may include a substrate 501, a base region 502 formed on the substrate 501, an active region 503 formed on the base region 502, and a substrate insulating layer 504 surrounding the active region 503. Figure 18 and Figure 19 , the active region 503 may be a filling active region included in a filling cell.

[0107] Reference Figure 19 The channel region 505C of each semiconductor device included in the semiconductor device 500 may be spaced apart from the active region 503 in the third direction. The channel region 505C may connect the source / drain regions 505 to each other on the active region 503 and may be surrounded by gate lines 510 to 512.

[0108] Each of the gate lines 510 to 512 may include a gate spacer SPC, a gate electrode GE, and a capping layer CAP. Figure 18 and Figure 19 , the source / drain region 505 in each of the filling cells FC1 and FC2 may be connected to the filling contacts 507 and 508. Figure 19 In the example embodiment shown in FIG. 5 , upper surfaces of the filling contacts 507 and 508 may be coplanar with an upper surface of the capping layer CAP, but the inventive concept is not limited thereto.

[0109] Reference Figure 18 , the wiring fill contact 507 of the fill contacts 507 and 508 for connecting the lower wiring patterns 520 to each other can extend further in the first direction than each of the fill cells FC1 and FC2. Therefore, the wiring fill contact 507 can intersect at least one of the power wiring patterns 521 and 522. In some embodiments, the fill contacts 507 and 508 can be formed of a metal, a metal silicide material, or the like, and can be formed of a material different from that of the lower wiring pattern 520 and the power wiring patterns 521 and 522. For example, the fill contacts 507 and 508 can be formed of tungsten, tungsten silicide, or the like, and the lower wiring pattern 520 and the power wiring patterns 521 and 522 can be formed of copper.

[0110] Figure 20 and Figure 21 is a diagram illustrating a semiconductor device according to some embodiments.

[0111] Reference Figure 20, the semiconductor device 600 may include standard cells SC1 to SC4 and filling cells FC1 and FC2. The standard cells SC1 to SC4 and filling cells FC1 and FC2 may be arranged in a first direction (Y-axis direction) and a second direction (X-axis direction), and the size of each of the standard cells SC1 to SC4 and filling cells FC1 and FC2 and the arrangement of the standard cells SC1 to SC4 and filling cells FC1 and FC2 may vary. Power wiring patterns 621 and 622 may be provided on the boundaries between the standard cells SC1 to SC4 and filling cells FC1 and FC2. The semiconductor device 600 may include gate lines 610, 611, and 612 extending in the first direction.

[0112] The semiconductor elements included in the standard cells SC1 to SC4 may be electrically connected to each other through the lower wiring pattern 620. In some embodiments, the filling contacts 607 and 608 included in the filling cells FC1 and FC2 may function as wiring regions for electrically connecting the lower wiring patterns 620 to each other. The filling contacts 607 and 608 may connect at least a portion of the lower wiring patterns 620 to each other through the lower via 609.

[0113] Figure 21 It is along Figure 20 A cross-sectional view taken along line VIII-VIII'. Figure 20 and Figure 21 In the example embodiment shown in FIG, each of the filling contacts 607 and 608 may have a length that does not exceed the length of the filling cells FC1 and FC2 in the first direction. For example, the filling contacts 607 and 608 may not intersect with the power wiring patterns 621 and 622. In other words, the power wiring patterns 621 and 622 may not overlap with the filling contacts 607 and 608.

[0114] Reference Figure 21 , the semiconductor device 600 may include a substrate 601, a base region 602, an active region 603 formed on the base region 602, and a substrate insulating layer 604 surrounding the active region 603. The active region 603 may be configured as a filled active region included in a filling cell. The source / drain region 605 may extend from the active region 603 and may be connected to the filling contacts 607 and 608. In the filling cells FC1 and FC2, the source / drain regions 605 spaced apart from each other in the first direction may be connected to one of the filling contacts 607 and 608, regardless of the conductivity type of the impurities included in each source / drain region 605. In addition, as Figure 21 As shown, the filling contact 607 , the lower via 609 , and the lower wiring pattern 620 may be covered by interlayer insulating layers 651 to 653 ( 650 ).

[0115] Figure 22is a diagram illustrating a semiconductor device according to some embodiments.

[0116] Reference Figure 22 , the semiconductor device 700 may include standard cells SC1 to SC6 and filling cells FC1, FC2, and FC3. The standard cells SC1 to SC6 and the filling cells FC1 to FC3 may be arranged in a first direction (Y-axis direction) and a second direction (X-axis direction), and the size of each of the standard cells SC1 to SC6 and the filling cells FC1 to FC3 and the arrangement of the standard cells SC1 to SC6 and the filling cells FC1 to FC3 may be changed. Power wiring patterns 721 and 722 may be provided on the boundaries between the standard cells SC1 to SC6 and the filling cells FC1 to FC3. The semiconductor device 700 may include gate lines 710, 711, and 712 extending in the first direction and a lower wiring pattern 720 extending in the second direction.

[0117] The semiconductor elements included in the standard cells SC1 to SC6 can be electrically connected to each other through the lower wiring pattern 720. In some embodiments, the filling contacts 707 and 708 included in the filling cells FC1 and FC2 can serve as wiring regions for electrically connecting the lower wiring patterns 720 to each other. The filling contacts 707 and 708 can include wiring filling contacts 707 that are connected to the lower via 709 and connect at least a portion of the lower wiring patterns 720 to each other, and dummy filling contacts 708 that are not connected to the lower wiring patterns 720.

[0118] Filling cells FC1, FC2, and FC3 may include a first filling cell FC1, a second filling cell FC2, and a third filling cell FC3. In some embodiments, the first filling cell FC1 may include only a wiring filling contact 707, and the second filling cell FC2 may include both a wiring filling contact 707 and a dummy filling contact 708. In some embodiments, the wiring filling contact 707 and the dummy filling contact 708 included in the second filling cell FC2 may have equal lengths or unequal lengths in a first direction (e.g., the Y direction). The third filling cell FC3 may include only a dummy filling contact 708.

[0119] Figures 23 to 30 are diagrams illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0120] Reference Figure 23 and Figure 24 , a base region 802 , an active region 803 and a source / drain region 805 may be formed on a substrate 801 . Figure 24 It is along Figure 23 The active region 803 may include a fin structure, and Figure 24 The active region 803 shown in FIG. 1 may be a filled active region included in a filled cell. The substrate 801, the base region 802, and the active region 803 may be covered by a substrate insulating layer 804. In some embodiments, the active region 803 may be configured differently from the above-described example embodiments, for example, including nanosheets. The source / drain region 805 may be covered by a first interlayer insulating layer 851.

[0121] Gate lines 810, 811, and 812 extending in a first direction (Y-axis direction) may be disposed between source / drain regions 805. Gate lines 810 to 812 may include a gate electrode 810, a dummy gate electrode 811, and a fill gate electrode 812. Gate electrode 810 may provide a semiconductor element together with the source / drain region 805 in the standard cell region where standard cells SC1 to SC4 are disposed. Fill gate electrode 812 may provide a dummy element together with the source / drain region 805 in the fill cell region where fill cells FC1 and FC2 are disposed. Dummy gate electrode 811 may be disposed on a boundary between the standard cell region and the fill cell region. In some embodiments, at least a portion of gate lines 810 to 812 may have different lengths in the first direction.

[0122] Reference Figure 25 and Figure 26 , a plurality of trenches T1 to T4 can be formed by partially removing the first interlayer insulating layer 851. The position and length of each of the trenches T1 to T4 can be determined according to the design rules of the filling contact formed in the filling cell region and the design rules of the active contact formed in the standard cell region. In the trenches T1 to T4, at least a portion of the source / drain region 805 can be exposed.

[0123] At least a portion of the trenches T1 to T3 formed in the filling cell region may extend further than the trench T4 formed in the standard cell region. Figure 25 and Figure 26 In the example embodiment shown in FIG. 1 , the first trench T1 and the third trench T3 may extend further in the first direction than each of the filling cell regions. In some embodiments, the length of one or more of the trenches T1 to T3 in the filling cell region in the first direction may be longer than the length of the fourth trench T4 in the standard cell region in the first direction, as shown in FIG. Figure 25 shown.

[0124] Reference Figure 27 and Figure 28, filling contacts 807 and 808 and active contact 860 can be formed by filling trenches T1 to T4 with a conductive material. To form filling contacts 807 and 808 and active contact 860, trenches T1 to T4 can be filled with, for example, a metal or / and a metal silicide. By filling trenches T1 to T4 with a metal or / and a metal silicide, filling contacts 807 and 808 and active contact 860 can be formed simultaneously in the same process. In some embodiments, filling contacts 807 and 808 and active contact 860 can be formed of the same material.

[0125] Reference Figure 29 and Figure 30 , a process for forming a lower via 809, a lower wiring pattern 820, and power wiring patterns 821 and 822 can be performed. At least a portion of the active contacts 860 can be electrically connected to each other through the lower via 809, the lower wiring pattern 820, and the wiring fill contact 807. In the filling cell area, it can also be ensured that the wiring area for connecting the lower wiring patterns 820 to each other is located below the lower wiring pattern 820. Therefore, the integration density of the semiconductor device 800 can be improved, and the electrical connection path of the semiconductor element arranged in the standard cell area can be designed in an efficient manner, so that the electrical properties of the semiconductor device 800 can be improved. In some embodiments, the lower wiring patterns 820 can be electrically connected to each other through the wiring fill contact 807 arranged below the lower wiring pattern 820, such as Figure 30 shown.

[0126] Reference Figure 30 , the lower via 809, the lower wiring pattern 820, and the power wiring patterns 821 and 822 may be covered by the second interlayer insulating layer 852 and the third interlayer insulating layer 853. At least one of the lower wiring pattern 820 and the power wiring patterns 821 and 822 may intersect with at least one wiring filling contact 807 on a plane (XY plane) parallel to the upper surface of the substrate 801.

[0127] According to example embodiments of the present inventive concept, a semiconductor device including standard cells and filler cells disposed between the standard cells can be provided. At least a portion of the semiconductor devices included in the standard cells can be electrically connected to each other via filler contacts that contact the filled active regions in the filler cells. Therefore, by providing wiring for connecting semiconductor elements on a wiring pattern disposed on the semiconductor element and also located at the same level as the semiconductor element, the integration density and / or electrical properties of the semiconductor device can be improved.

[0128] Although example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the inventive concept. Therefore, the subject matter disclosed above is to be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, improvements, and other embodiments that fall within the scope of the inventive concept.

Claims

1. A semiconductor device, comprising: Standard cells are arranged in a first direction and a second direction on a substrate, wherein the first direction and the second direction are both parallel to an upper surface of the substrate, and the second direction intersects the first direction, wherein each of the standard cells includes a semiconductor element and a lower wiring pattern electrically connected to at least one of the semiconductor elements and extending in the second direction; and filling cells located on the substrate, wherein each of the filling cells is located between two standard cells adjacent to each other in the second direction and includes a filling active region and a filling contact connected to the filling active region and extending in the first direction. The filling unit includes a first filling unit located between a first standard unit and a second standard unit adjacent to each other in the second direction in the standard units, and The lower wiring pattern of the first standard cell extends into the first filling cell and is connected to the filling contact of the first filling cell, and the filling contact of the first filling cell is located between the substrate and the lower wiring pattern of the first standard cell.

2. The semiconductor device according to claim 1, wherein The standard cell further includes a third standard cell and a fourth standard cell adjacent to each other in the second direction, and the filling cell further includes a second filling cell located between the third standard cell and the fourth standard cell, and The filling contact of the second filling cell includes a dummy filling contact spaced apart from the lower wiring pattern of the first standard cell, the lower wiring pattern of the second standard cell, the lower wiring pattern of the third standard cell, and the lower wiring pattern of the fourth standard cell.

3. The semiconductor device according to claim 2, in, The standard cell further includes a fifth standard cell and a sixth standard cell adjacent to each other in the second direction, and the filling cell further includes a third filling cell located between the fifth standard cell and the sixth standard cell. wherein the filling contacts of the first filling cell include first wiring filling contacts, and each of the first wiring filling contacts is connected to at least one of the lower wiring pattern of the first standard cell, the lower wiring pattern of the second standard cell, the lower wiring pattern of the third standard cell, the lower wiring pattern of the fourth standard cell, the lower wiring pattern of the fifth standard cell, and the lower wiring pattern of the sixth standard cell, The filling contact of the second filling cell includes a second wiring filling contact and a second dummy filling contact, the second wiring filling contact is connected to at least one of the lower wiring pattern of the first standard cell, the lower wiring pattern of the second standard cell, the lower wiring pattern of the third standard cell, the lower wiring pattern of the fourth standard cell, the lower wiring pattern of the fifth standard cell, and the lower wiring pattern of the sixth standard cell, the second dummy filling contact is spaced apart from the lower wiring pattern of the first standard cell, the lower wiring pattern of the second standard cell, the lower wiring pattern of the third standard cell, the lower wiring pattern of the fourth standard cell, the lower wiring pattern of the fifth standard cell, and the lower wiring pattern of the sixth standard cell, and The third filling cell includes a third dummy filling contact, which is spaced apart from the lower wiring pattern of the first standard cell, the lower wiring pattern of the second standard cell, the lower wiring pattern of the third standard cell, the lower wiring pattern of the fourth standard cell, the lower wiring pattern of the fifth standard cell, and the lower wiring pattern of the sixth standard cell.

4. The semiconductor device according to claim 3, wherein The first wiring filling contacts included in the first filling cells have different lengths in the first direction.

5. The semiconductor device according to claim 3, wherein The second wiring filling contact and the second dummy filling contact included in the second filling cell have equal lengths in the first direction. The semiconductor device according to claim 3 , wherein: The third dummy filling contacts included in the third filling cells have equal lengths in the first direction.

7. The semiconductor device according to claim 3, wherein At least one of the first wiring filling contacts included in the first filling cell is electrically connected to the lower wiring pattern extending from two of the standard cells, and the two of the standard cells are misaligned in the first direction and in the second direction.

8. The semiconductor device according to claim 3, wherein At least one of the first wiring filling contacts included in the first filling cell is electrically connected to the lower wiring pattern extending from two of the standard cells, and the two of the standard cells are misaligned in the first direction and aligned in the second direction.

9. The semiconductor device according to claim 3, wherein The second wiring filling contact included in the second filling cell is electrically connected to the lower wiring pattern extending from two of the standard cells, and the two of the standard cells are misaligned in the first direction and aligned in the second direction.

10. The semiconductor device according to claim 1, further comprising: At least one via structure connects one of the filling contacts to one of the lower wiring patterns.

11. The semiconductor device according to claim 1, wherein The filling contact and the lower wiring pattern include different conductive materials.

12. The semiconductor device according to claim 1, further comprising: At least one contact separation region separates two filling contacts aligned in the first direction.

13. The semiconductor device according to claim 12, wherein The at least one contact separation region includes a first contact separation region spaced apart from the power wiring pattern in the first direction, and each of the power wiring patterns is located on a corresponding boundary between two of the filling cells adjacent to each other in the first direction.

14. The semiconductor device according to claim 13, wherein The at least one contact separation region further includes a second contact separation region different from the first contact separation region, and the second contact separation region is provided under at least one of the power wiring patterns.

15. A semiconductor device, comprising: a standard cell region and a filling cell region, the standard cell region and the filling cell region being adjacent to each other in a first direction parallel to an upper surface of the substrate; at least one semiconductor element, the at least one semiconductor element being located in the standard cell region; at least one dummy element, the at least one dummy element being located in the filling cell region; a lower wiring pattern located above the at least one semiconductor element and extending in the first direction; as well as a via structure contacting at least one of the lower wiring patterns and contacting a filling contact, wherein the filling contact contacts the active area of ​​the dummy element in the filling cell region and extends in a second direction intersecting the first direction, wherein the at least one lower wiring pattern continuously extends from the standard cell region to the filling cell region in the first direction.

16. The semiconductor device according to claim 15, in, The filling contacts of the filling cell region include wiring filling contacts in contact with the via structure and dummy filling contacts spaced apart from the via structure; and The dummy filling contact intersects the at least one lower wiring pattern in the filling cell region.

17. The semiconductor device according to claim 16, wherein The wiring filling contact and the dummy filling contact have different lengths in the second direction.

18. The semiconductor device according to claim 16, wherein The wiring filling contact is connected to a second lower wiring pattern different from the at least one lower wiring pattern.

19. A semiconductor device, comprising: A standard cell, wherein the standard cell is located on a substrate; as well as filling cells, wherein each of the filling cells is located between two of the standard cells, and each of the filling cells includes a filling active region and a filling contact connected to the filling active region and extending in a first direction parallel to the upper surface of the substrate, and At least one of the filling units includes a first filling contact and a second filling contact among the filling contacts, wherein the second filling contact is spaced apart from the first filling contact in a second direction intersecting the first direction, and the first filling contact and the second filling contact have different lengths.

20. The semiconductor device according to claim 19, in, In the first direction, the length of the first filling contact is smaller than the length of the second filling contact, and The second filling contact spans across two or more filling cells adjacent to each other in the first direction among the filling cells.

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