Silicon carbide power devices with improved robustness and corresponding methods of manufacture

Abstract

Embodiments of the present disclosure relate to silicon carbide power devices with improved robustness and corresponding methods of manufacture. An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a back surface, the front and back surfaces lying in a horizontal plane and opposing one another along a vertical axis transverse to the horizontal plane. The substrate includes an active region having a plurality of doped regions disposed therein and an edge region that is non-active, distinct from, and surrounds the active region. At least in the edge region, a dielectric region is disposed over the front surface. A passivation layer is disposed over the front surface of the substrate and in contact with the dielectric region in the edge region. The passivation layer includes at least one anchoring region that extends through a thickness of the dielectric region at the edge region so as to define a mechanical anchor for the passivation layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a silicon carbide (SiC) power device having improved robustness, especially with respect to thermal-mechanical stresses due to thermal cycling; moreover, the present disclosure relates to a method for manufacturing a power device. BACKGROUND

[0002] Integrated electronic devices are known, for example, diodes or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) for power electronics applications, manufactured starting from silicon carbide substrates.

[0003] Such devices are advantageous at least in part due to the advantageous chemical-physical properties of silicon carbide. For example, the bandgap of silicon carbide is generally wider than that of silicon, which is a commonly used material in electronic power devices. Therefore, silicon carbide has a higher breakdown voltage than silicon even with a relatively small thickness, and can therefore be advantageously used in high-voltage, high-power and high-temperature applications.

[0004] However, the manufacturing of advanced silicon carbide power devices is affected by some problems due to the dielectric properties of the passivation layer used together with the insulating function.

[0005] Due to the high operating temperature and the dielectric rigidity, a polyimide layer, i.e. a polymer of imide monomers, is generally used as a passivation and insulating material in current silicon carbide power devices, for example formed via deposition using a spin-coating technique. Currently, the adhesion problems of this passivation layer with the underlying silicon carbide substrate (or some other material layer) limit the reliability of such power devices, especially after thermal cycling (during electrical testing operation and during active operating life).

[0006] In particular, due to the possible delamination of the passivation layer caused by thermal-mechanical stresses after the above-mentioned thermal cycling, so-called electrical arcing phenomena can occur between the metal material regions of the power device under reverse bias, thus causing damage or breakdown of the same power device. SUMMARY

[0007] In various embodiments, the present disclosure provides an improved solution for silicon carbide power devices, thus allowing to overcome the outstanding drawbacks previously associated with known solutions, and in particular, providing a higher robustness with respect to thermal-mechanical stresses due to thermal cycling.

[0008] According to the present disclosure, therefore, a silicon carbide power device and a corresponding manufacturing method are provided.

[0009] In one or more embodiments, an electronic power device is provided, the electronic power device comprising a substrate of silicon carbide (SiC) having a front surface and a back surface, the front surface and the back surface lying in a horizontal plane and being opposite to each other along a vertical axis transverse to the horizontal plane. The substrate comprises an active region, a non-active edge region surrounding the active region, and a plurality of doped regions in the active region extending from the front surface into the substrate. A dielectric region is disposed over the front surface at least in the edge region. A passivation layer is disposed over the front surface of the substrate, and the passivation layer is in contact with the dielectric region in the edge region. The passivation layer comprises at least one anchoring region extending through a thickness of the dielectric region at the edge region and configured to define a mechanical anchoring for the passivation layer.

[0010] In one or more embodiments, a method for manufacturing an electronic power device is provided, the method comprising forming a dielectric region on a front surface of a substrate of silicon carbide (SiC) at an edge region of the substrate, the substrate having a front surface and a back surface, the front surface and the back surface lying in a horizontal plane and being opposite to each other along a vertical axis transverse to the horizontal plane, the substrate comprising an active region and a non-active edge region, a plurality of doped regions in the active region extending from the front surface into the substrate, and forming a passivation layer on the front surface of the substrate and in contact with the dielectric region in the edge region. Forming the passivation layer comprises forming an anchoring region extending through a thickness of the dielectric region at the edge region and configured to define a mechanical anchoring for the passivation layer. BRIEF DESCRIPTION OF DRAWINGS

[0011] For a better understanding of the present disclosure, preferred embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings in which:

[0012] Figures 1A-1H is a cross-sectional view of a silicon carbide power device in successive steps of a manufacturing method according to a first embodiment of the present disclosure;

[0013] Figures 2-4 is Figure 1H a schematic top view of the power device of

[0014] Figures 5A-5I is a cross-sectional view of a silicon carbide power device in successive steps of a manufacturing method according to a second embodiment of the present disclosure;

[0015] Figures 6-7 is Figure 5I a schematic top view of the power device of

[0016] Figures 8A-8His a cross-sectional view of a silicon carbide power device in a final step of a manufacturing method, according to a further variant of the present solution.

[0017] Figures 9-10 is Figure 8H schematic top views of a power device according to the respective variants; and

[0018] Figure 11 is a cross-sectional view of a silicon carbide power device in a final step of a manufacturing method, according to a further variant of the present solution. DETAILED DESCRIPTION

[0019] Reference is first made to Figure 1A A first embodiment of a method for manufacturing a silicon carbide power device is now disclosed.

[0020] The above manufacturing method envisages providing a wafer 1 comprising a silicon carbide substrate 2 having a front surface 2a and a back surface 2b, which front and back surfaces extend in a horizontal plane xy and are separated from each other and opposite to each other along a vertical axis z transverse to the horizontal plane xy.

[0021] In the embodiment shown, in which the power device is, for example, a power diode, on the back surface 2b of the substrate a back cathode contact is formed, which is constituted by a layer 3 of electrically conductive material (for example, a metallic material).

[0022] Furthermore, in the active region A' of the power device, at the front surface 2a of the substrate 2 a plurality of anode wells 4 is formed, which is constituted by suitably doped regions. In a known manner, each of the above anode wells 4, which can have a strip-like configuration (in a top view, in the horizontal plane xy), represents a cell of the power device.

[0023] Furthermore, at the front surface 2a of the substrate 2, in an edge region A" of the power device (different and separate from the active region A'), an edge anode region 5 is formed, which is also constituted by suitably doped regions, having a lateral extension (in the horizontal plane xy) greater than that of the above anode wells 4. Figure 1A In particular, in the above edge anode region 5, along a first axis x of the above horizontal plane xy, a plurality of edge anode wells 5a is formed, which is constituted by suitably doped regions.

[0024] In a known manner, once the manufacturing method is completed, the edge region A" ends at a scribeline SL, represented by a dashed line, along which the wafer 1 will be cut to shape the dies of the power device.

[0025] The edge anode region 5 is arranged externally with respect to the active area A' and the anode well 4, for example, is designed in shape like a ring surrounding the active area A'. In a not shown manner, the above mentioned edge anode region 5 can be connected to a ring-shaped injection region, which is also formed at the front surface 2a of the substrate 2 at the edge area A" (with the function of terminating the electric field in a known manner).

[0026] As shown above Figure 1A , a thick dielectric layer 8, in particular TEOS (tetraethyl orthosilicate), is formed by deposition on the substrate 2, which covers the entire front surface 2a of the substrate 2; the thickness of the thick dielectric layer 8 is for example between 0.5 pm and 2.5 pm.

[0027] As shown above Figure 1B , an overlying layer 10 is formed by deposition on the thick dielectric layer 8, which is for example made of polysilicon or a different material (for example, silicon nitride), which provides a chemical etching selectivity with respect to the material of the thick dielectric layer 8 (in the example, TEOS); the thickness of the overlying layer 10 is for example between 0.2 pm and 1.5 pm.

[0028] As shown above Figure 1C , the overlying layer 10 is defined (selectively with respect to the underlying thick dielectric layer 8) via a photolithographic method, i.e. via the formation of a photoresist mask (not shown here) and subsequent etching of the material (in the example, polysilicon).

[0029] In particular, the definition of the overlying layer 10 leads to the formation of a first overlying region 10a and a second overlying region 10b at the edge area A", which are laterally spaced apart (in the horizontal plane xy, along the axis x in Figure 1C ; and define an access window 12 between them. As will be shown below, these overlying regions 10a, 10b can have a ring-shaped shape in a top view and are arranged around and externally to the active area A' of the power device.

[0030] For example, the first overlying region 10a and the second overlying region 10b can have the same width in the horizontal plane xy (along the axis x in Figure 1C ; and the width of the access window 12 can be between 10 pm and 20 pm (in Figure 1C ; along the axis x; in general, in a direction transverse to the longitudinal extension direction).

[0031] In particular, the first overlying region 10a is laterally spaced apart (in the horizontal plane xy, along the axis x in Figure 1CThe first overlying region 10a is located at a distance along the axis x), so that, in use, it is arranged in an electrically non-active zone of the power device (in other words, a zone outside the zone involved by the electric field lines due to the operation of the power device).

[0032] As shown in Figure 1D , the thick dielectric layer 8 is then defined again by means of a photolithographic process so as to be removed in the active zone A' (thus exposing the front surface 2a of the substrate 2) (thus exposing the anode well 4 and at least partially exposing the edge anode region 5), and moreover, along the scribe line SL, leaving a residual dielectric region 8a over the edge zone A".

[0033] The anode electrical contact region can then be formed, in a known manner (not shown here), by means of a surface implantation in the above-mentioned anode well 4 and edge anode region 5 so as to improve the respective electrical contact properties.

[0034] As shown in Figure 1E , a front conductive layer 14, for example a metal layer, is then formed over the front surface 2a of the substrate 2 in a suitable manner (for example by means of a sputtering process).

[0035] Then, as shown in Figure 1F , the front conductive layer 14 is defined via a photolithographic process so as to be removed in the edge zone A" and to leave a residual portion of the front conductive layer 14 (denoted by 14a) over the active zone A', which in particular is in direct contact with the front surface 2a of the substrate 2, the anode well 4 and the edge anode region 5, thus forming an anode electrical contact of the power device.

[0036] As shown in the above-mentioned Figure 1F , at the boundary between the active zone A' and the edge zone A", the residual portion 14a also extends partially over the dielectric region 8a.

[0037] The outer end of the above-mentioned residual portion 14a is in any case sufficiently far from the first overlying region 10a so that, as mentioned previously, the first overlying region 10a is located in a non-active zone of the power device (for example, in the case where the electric field lines terminate at a distance of about 20 pm from the outer end of the residual portion 14a, the first overlying region 10a is arranged at a distance from the same outer end of the residual portion 14a which is sufficiently higher than 20 pm).

[0038] With reference to Figure 1G , the manufacturing method continues with the chemical etching (for example using hydrofluoric acid (HF)) of the dielectric region 8a through the access window 12 defined between the first overlying region 10a and the second overlying region 10b.

[0039] In particular, the etching operation is carried out via a photolithographic method, in which an etching mask 15 is schematically represented in the above-mentioned Figure 1G by a dashed line, which covers the entire surface of the wafer 1 and, in particular, covers a substantial portion of the same overlying regions 10a, 10b, except for the zone at the access window 12. In other words, the etching mask 15 has an opening 15a vertically corresponding to the access window 12, which has a size slightly greater than that of the access window 12 in the horizontal plane xy (along the axis x in the above-mentioned Figure 1G .

[0040] Therefore, during etching, the chemical etchant (HF in the example) penetrates through the dielectric region 8a through the access window 12, removing the underlying material (etching stops on the front surface 2a of the substrate 2), however, given the selective nature of the etching method with respect to the material of the same overlying regions 10a, 10b, the overlying regions 10a, 10b are not involved.

[0041] In particular, given that the wet etching is completely isotropic, an anchoring opening 16 is formed in the dielectric region 8a, which extends vertically (along the vertical axis z) over the entire thickness of the dielectric region 8a and which has, horizontally (in the horizontal plane xy, along the axis x in the above-mentioned Figure 1G .

[0042] In detail, in the embodiment shown, the cross section of the anchoring opening 16 is trapezoidal and the above-mentioned dimension W1 has, at the larger base of the trapezoid, a greater extension facing the access window 12, for example between 2 pm and 5 pm (in any case, depending on the thickness of the dielectric, the above-mentioned wet etching is isotropic).

[0043] Basically, after etching, the respective end portions of the first overlying region 10a and of the second overlying region 10b facing the access window 12 (indicated by 18a and 18b) are arranged as overhanging and protruding above the underlying anchoring opening 16.

[0044] As Figure 1H shown, then, a passivation layer 20 is formed over the entire surface of the wafer 1 (except for the zone of the scribe line SL), in particular a passivation layer of polyimide (it is possible to use other materials having, in any case, dielectric characteristics, for example photoresist and the like). For example, the passivation layer is formed using a fluid or viscous spin-on technique and is subsequently subjected to a curing step.

[0045] After the formation of the passivation layer 20, the passivation layer 20 has, in particular, an anchoring region 22 which extends in the anchoring opening 16, completely occupies the anchoring opening 16 and which has a first portion 22a inside the anchoring opening 16 which presents a corresponding conformation (in the example, with a trapezoidal cross section) and a second portion 22b inside the access window 12 which has a width less than that of the first portion (in the example, with a rectangular cross section) and which is arranged between the same end portions 18a, 18b. Figure 1H In particular, the above-mentioned first portion 22a of the anchoring region 22 is located directly below and in direct contact with the end portions 18a, 18b of the first 10a and second 10b overlying regions and the above-mentioned second portion 22b is arranged between the same end portions 18a, 18b.

[0046] In particular, the above-mentioned first portion 22a of the anchoring region 22 is located directly below and in direct contact with the end portions 18a, 18b of the first 10a and second 10b overlying regions and the above-mentioned second portion 22b is arranged between the same end portions 18a, 18b.

[0047] The wafer 1 is then cut along the scribe line SL to form the dies of the integrated power device, here indicated by 25 (in the example, power diodes).

[0048] The above-mentioned power device 25 therefore has a passivation layer 20 which is arranged at least over the (thick dielectric) dielectric region 8 in the edge zone A" and which is suitably anchored due to the presence of the corresponding anchoring region 22 and the related mechanical anchoring inside the anchoring opening 16.

[0049] Advantageously, even after thermal cycles (during electrical testing, or during effective operation of the power device 25), this anchoring region 22 allows the passivation layer 20 to remain mechanically anchored, eliminating or in any case significantly reducing the possibility of delamination of the passivation layer 20 from the underlying material and, consequently, the possibility of arcing phenomena.

[0050] Figure 2 is a simplified top view of the resulting power device 25 and of the corresponding die, indicated with 1'(in the top view, with a substantially square conformation), from which portions have been removed for the sake of clarity.

[0051] In the illustrated embodiment, the active region A' of the power device 25 has a substantially square configuration in the horizontal plane xy, corresponding to which is a substantially square configuration of the overlying anodic electrical contact (made up of the remaining portion 14a of the front conductive layer 14). In this case, the first overlying region 10a and the second overlying region 10b have a configuration of square rings in the horizontal plane xy and completely surround the active region A'. The passivation layer 20 extends over the front surface of the die 25' and in particular has an anchoring region 22 which also has the shape of a square ring (in plan view) and is in fact arranged at the access window 12 defined between the first overlying region 10a and the second overlying region 10b described above.

[0052] In Figure 3 In the variant embodiment illustrated, the first overlying region 10a and the second overlying region 10b do not form a complete ring around the active region A' of the power device 25, but are arranged in a distributed manner only at the corners of the active region A' and outside it. In this case, therefore, the anchoring region 22 is also present only at the corners described above in a distributed manner, on the other hand the anchoring region 22 is made in a manner completely analogous to that already discussed previously.

[0053] Figure 4 Another variant of the power device 25 is illustrated again in cross section, in which the second overlying region 10b has a width in the horizontal plane xy (in Figure 4 greater than the corresponding width of the first overlying region 10a.

[0054] In particular, the second overlying region 10b described above has a further end portion 18b' opposite the end portion 18b facing the access window 12, which protrudes from the underlying dielectric region 8a. The passivation layer 20, once formed, therefore has a further anchoring region (denoted by 22') arranged directly below the further end portion 18b' described above, which thus contributes to anchoring the passivation layer 20 with respect to the underlying substrate 2 and prevents delamination phenomena due to thermal-mechanical stresses.

[0055] In an obvious manner, also for this embodiment, the configurations discussed previously Figure 2 and Figure 3 can be envisaged.

[0056] Another embodiment of the manufacturing method of the power device is now discussed.

[0057] In this case, as Figure 5AAs shown, the first dielectric layer 30 (specifically the first dielectric layer of TEOS) is first deposited on the front surface 2a of the substrate 2 (where the anode well 4 and the edge anode region 5 have been pre-formed).

[0058] like Figure 5B As shown, the first dielectric layer 30 is then doped (e.g., As, Ar, or some other P-type dopant) through a suitable implantation mask 31 in such a way that it is confined and restricted to the outer region at the edge region A″ and near the scribing line SL to form a doped portion 30′ (as will be emphasized below, this doped portion 30′ is along the horizontal plane xy) Figure 5B The width of axis x in the figure roughly corresponds to the width W1 mentioned above.

[0059] The doped portion 30′ is arranged at a location that constitutes an electrically non-active region of the power device during operation (in other words, the doped portion 30′ is arranged outside the region involved by the electric field lines caused by the operation of the power device).

[0060] Next, as Figure 5C As shown, a second dielectric layer 32 (specifically, the second dielectric layer of TEOS) is deposited over the first dielectric layer 30 (and the corresponding doped portion 30′). The assembly consisting of the first dielectric layer 30 and the second dielectric layer 32 forms a thick dielectric layer (again denoted by 8), and the doped portion 30′ will be contained within this thick dielectric layer, as previously discussed.

[0061] In particular, after the above-mentioned implantation, the doped portion 30′ has an etch rate that is higher than the etch rate of the material constituting the second dielectric layer 32; for example, the ratio of the etch rate of the doped portion 30′ to the etch rate of the second dielectric layer 32 is greater than or equal to 2.

[0062] like Figure 5D As shown, a thick dielectric layer 8 is then defined by photolithography so as to remove the thick dielectric layer 8 in the active region A′ (thus exposing the front surface 2a of the substrate 2) (thus exposing the anode well 4 and at least partially exposing the edge anode region 5), and furthermore, the thick dielectric layer 8 is removed along the scribing line SL, thereby leaving a remaining dielectric region 8a above the edge region A″ (the aforementioned doped portion 30′ is contained in the remaining dielectric region 8a).

[0063] like Figure 5E As shown, a front conductive layer (again denoted by 14), such as a metal layer, is then formed on the front surface 2a of the substrate 2 in a suitable manner (e.g., by sputtering).

[0064] like Figure 5FThe front conductive layer 14 is then defined, via a photolithographic method, so as to be removed in the edge region A" and to leave a remaining portion of the front conductive layer 14 (again denoted by 14a) in the active region A', which in particular is in direct contact with the front surface 2a of the substrate 2, with the anode well 4 and with the edge anode region 5, thus forming the anode electrical contact of the power device.

[0065] As mentioned above Figure 5F The remaining portion 14a also extends partially on the dielectric region 8a at the border between the active region A' and the edge region A".

[0066] As Figure 5G The dielectric region 8a is then dry-etched, for example plasma etched, in the regions vertically corresponding to the respective doped portions 30'.

[0067] In particular, the etching is carried out through a suitable etching mask 33 (schematically represented in dashed lines) so as to dig a vertical trench 34, with respect to the respective doped portion 30', centrally on the entire thickness of the dielectric region 8a (it should be noted that the dry etching blurs the material of the dielectric region 8a, regardless of the doping, and therefore does not discriminate with respect to the respective doped portion 30').

[0068] As Figure 5H A second etching, in particular wet etching, for example using hydrofluoric acid HF, is carried out through the same etching mask 33, which has not yet been removed.

[0069] Due to the different etching rates, in the horizontal plane xy the etching penetrates more into the doped portion 30' than into the overlying material of the dielectric region 8a, thus causing the removal (in this example, complete removal) of the same doped portion 30' so as to form the portion again defined as anchoring opening 16 and access window 12, which overlies and fluidly communicates with the same anchoring opening 16, in this case also formed in the same dielectric region 8a. Thus, in the horizontal plane xy (in the Figure 5H The anchoring opening 16 again has a greater width Wi than the respective width W2 of the access window 12, along the axis x in the

[0070] It is noted that, in this embodiment, the end portions (again denoted by 18a, 18b) facing the access window 12 and overhanging and projecting above the underlying anchoring opening 16 are the result of the etching of the surface portion of the dielectric region 8a and are therefore composed of the material of the same dielectric region 8a.

[0071] As Figure 5IThe passivation layer 20 is then formed (for example, of polyimide) over the entire surface of the wafer 1 (except for the region of the scribe line SL) using a spin-coating technique.

[0072] After the formation of the passivation layer 20, the passivation layer 20 has, in particular, an anchoring region 22 which extends in the anchoring openings 16, completely occupies the anchoring openings 16, and which has, again, a first portion 22a within the same anchoring openings 16, having the respective configuration, and a second portion 22b within the access windows 12, having dimensions smaller than those of the first portion 22a in the horizontal plane xy (along the axis x in Figure 5I .

[0073] In particular, the above-mentioned first portion 22a of the anchoring region 22 is located directly below and in direct contact with the end portions 18a, 18b of the dielectric region 8a, and the above-mentioned second portion 22b is arranged between the same end portions 18a, 18b of the dielectric region 8a.

[0074] The wafer 1 is then cut along the scribe line SL to form a die (again denoted by 25) containing the power device.

[0075] Likewise, in this case, advantageously, even after thermal cycles and the resulting mechanical and electrical stresses, the anchoring region 22 enables the passivation layer 20 to remain anchored and fixed.

[0076] Figure 6 is a simplified top view of the resulting power device 25 (having a substantially square configuration in top view) and of the corresponding die 1', with parts removed for the sake of clarity.

[0077] In the embodiment shown, the active area A' of the power device 25 has a substantially square configuration in the horizontal plane xy, corresponding to which is the substantially square configuration of the remaining overlying portion 14a of the front conductive layer 14 (constituting the anodic electrical contact).

[0078] The anchoring openings 16 and the corresponding anchoring region 22 of the passivation layer 20 have, in the horizontal plane xy itself, the configuration of a square ring which completely surrounds the active area A'.

[0079] In the embodiment shown, the above-mentioned anchoring openings 16 and the above-mentioned anchoring region 22 do not form a complete ring around the active area A' of the power device 25, but are arranged only at the corners of the active area A' and outside the active area A' in a distributed manner. Figure 7

[0080] Another embodiment of a method for manufacturing a power device is now discussed. ​

[0081] In this case, as shown in Figure 8A , firstly a sacrificial region 40 is formed over the front surface 2a of the substrate 2 by deposition via a photolithographic method; the sacrificial region 40 is made of polysilicon or other suitable material (for example, silicon nitride), which provides a chemical etching selectivity with respect to a dielectric material (for example, TEOS) which will then form a thick dielectric layer 8.

[0082] The sacrificial region 40 is formed in the edge region A" and in the vicinity of the scribe line SL, in such a way as to be confined and limited to an outer region of the power device, and therefore the sacrificial region 40 is arranged in a portion which, during operation, constitutes an electrically non-active zone of the power device (in other words, the sacrificial region 40 is arranged in a zone which is outside the zone involved by the electric field lines due to the operation of the power device).

[0083] For example, the sacrificial region 40 has a width of approximately 30 μιη (in particular, the width of the sacrificial region 40 along the axis x in the horizontal plane xy corresponds substantially to the above-mentioned width Wl, on the other hand, which will be highlighted hereinafter). Figure 8A

[0084] Then (as shown in Figure 8B ), a thick dielectric layer 8 (for example, again of TEOS) is deposited over the front surface 2a of the substrate 2 and, in particular, over the sacrificial region 40, which is thus contained within the same thick dielectric layer 8.

[0085] As shown in Figure 8C , the thick dielectric layer 8 is then defined via a photolithographic method in a substantially similar manner to that already discussed previously, thus so as to remove the thick dielectric layer 8 in the active region A' and, in addition, along the scribe line SL, leaving a residual dielectric region 8a (in which the above-mentioned sacrificial region 40 is contained) over the edge region A".

[0086] As shown in Figure 8D , in this case, the manufacturing method continues with dry etching, for example, plasma etching, of the dielectric region 8a in a zone vertically corresponding to the sacrificial region 40.

[0087] In particular, the etching is performed using a suitable etching mask 42 (schematically represented with dashed lines) so as to dig a vertical trench 44 centrally with respect to the above-mentioned sacrificial region 40, on the entire thickness of the dielectric region 8a.

[0088] As shown in Figure 8E ​As shown, after removal of the etching mask 42, a second etching, in particular a wet etching, is performed for selectively removing the remaining sacrificial areas 40. In particular, the etchant penetrates into the vertical trenches 44 and laterally moves to remove the above-mentioned sacrificial areas 40 so as to form, in the dielectric region 8a and in the access window 12, which overlies and fluidly communicates with the same anchoring opening 16, a portion again defined as anchoring opening 16, which in this case is also formed in the same dielectric region 8a (the anchoring opening 16 again has, in the horizontal plane xy (in the case of the axis x) a width Wi greater than the corresponding width W2 of the access window 12). Figure 8E

[0089] In this case, the anchoring opening 16 has a substantially rectangular shape in cross section and the access window has a substantially trapezoidal cross section (with the smaller base facing the above-mentioned anchoring opening 16).

[0090] It is noted that, likewise, in the present embodiment, the end portions 18a, 18b facing the access window 12 and overhanging and projecting above the underlying anchoring opening 16 are the result of the etching of the surface portion of the dielectric region 8a and are integral with the same dielectric region 8a.

[0091] As Figure 8F shown, a front conductive layer (again denoted by 14), for example of a metallic material, is then formed on the front surface 2a of the substrate 2 in a suitable manner (for example by means of a sputtering method); it is noted that, in this case, the front conductive layer 14 also penetrates into the anchoring opening 16 and the access window 12, in the example filling the anchoring opening 16 and the access window 12.

[0092] Then, as Figure 8G shown, the front conductive layer 14 is defined via a photolithographic method so as to remove the front conductive layer 14 in the edge region A" and leave a remaining portion (again denoted by 14a) of the front conductive layer 14 over the active region A', which in particular is in direct contact with the front surface 2a of the substrate 2, the anode well 4 and the edge anode region 5, thus forming the anode electrical contact of the power device. As shown above Figure 8G at the boundary between the active region A' and the edge region A", the remaining portion 14a also extends partially on the dielectric region 8a. It is noted that the etching envisages the complete removal of the material within the anchoring opening 16 and the access window 12.

[0093] As Figure 8H shown, a passivation layer 20, for example of polyimide, is then formed over the entire surface of the wafer 1 (except for the region of the scribe line SL) using a spin-coating technique.

[0094] ​After the formation of the passivation layer 20, the passivation layer 20 has, in particular, an anchoring region 22 which extends in the anchoring opening 16, completely occupies the anchoring opening 16 and again has: a first portion 22a within the same anchoring opening 16, which has a respective conformation (also rectangular section in this case); and a second portion 22b within the access window 12, which has dimensions smaller than those of the first portion 22a in the horizontal plane xy (in this case, along the axis x). Figure 8H

[0095] In particular, in this case, the above-mentioned first portion 22a of the anchoring region 22 is also located directly below and in direct contact with the end portions 18a, 18b of the dielectric region 8a, and the above-mentioned second portion 22b is arranged between the same end portions 18a, 18b of the dielectric region 8a.

[0096] Then, the wafer 1 is cut along the scribe line SL to form the dies (again denoted by 25) of the integrated power device.

[0097] Likewise, in this case, advantageously, even after thermal cycles and the resulting mechanical and electrical stresses, the anchoring region 22 enables the passivation layer 20 to remain anchored in a fixed manner within the anchoring opening 16.

[0098] Figure 9 is a simplified top view of the resulting power device 25 and of the corresponding die 1'(with a substantially square conformation in the top view), with a portion removed for the sake of clarity. In the embodiment shown, the active area A' of the power device 25 has a substantially square conformation in the horizontal plane xy, corresponding to which is the substantially square conformation of the remaining overlying portion 14a of the front conductive layer 14 (which defines the anode electrical contact).

[0099] The anchoring opening 16 and the corresponding anchoring region 22 of the passivation layer 20 have a square ring conformation in the horizontal plane xy, which completely surrounds the active area A'.

[0100] In the embodiment shown, the above-mentioned anchoring opening 16 and the above-mentioned anchoring region 22 do not form a complete ring around the active area A' of the power device 25, but are arranged only at the corners of the active area A' and outside the active area A' in a distributed manner. Figure 10

[0101] From the foregoing description, the advantages of the present solution are clear.

[0102] ​​In particular, it is once again emphasized that, thanks to the presence of the anchoring regions 22, the passivation layer 20 is anchored and fixed in a reliable manner, preventing the possibility of delamination of the passivation layer 20 (i.e. detachment of the passivation layer 20 from the underlying material portion) due to thermal-mechanical stresses caused by thermal cycles.

[0103] The present solution thus makes it possible to maximize the reliability and robustness of the resulting power device 25, especially with respect to the corresponding edge termination obtained starting from the silicon carbide substrate 2, from which, in use, the above-mentioned delamination phenomenon starts.

[0104] In the described embodiment, the manufacturing method is facilitated and economically advantageous, comprising processing steps which are standard per se in the semiconductor industry.

[0105] Finally, it is clear that modifications and changes can be made to what has been described and shown herein without thereby departing from the scope of the present disclosure.

[0106] In particular, it should be emphasized that the present solution can find advantageous application in any electronic device, in particular for power applications, in which the anchoring of the passivation layer to the underlying material is advantageous for preventing delamination phenomena due to, for example, thermal-mechanical stresses.

[0107] Furthermore, it is necessary to emphasize that the present solution can envisage a desired number of anchoring regions 22 obtained in a manner fully corresponding to that discussed previously, especially in the edge region A" of the power device 25.

[0108] The provision of a plurality of anchoring regions 22 can in fact make it possible to further increase the anchoring of the passivation layer 20 and, therefore, the reliability of the resulting power device 25.

[0109] These anchoring regions 22 can have any desired arrangement; for example, in the above-mentioned edge region A", these anchoring regions 22 can be arranged according to a grid arrangement.

[0110] By way of example only, Figure 11 A cross section of a power device 25 (in particular, a power diode, but it is evident that what is shown can be applied to any different electronic device) is shown, which has two anchoring regions 22 in the edge region A", spaced apart at a suitable interval distance (in Figure 11 along the axis x) in the substrate 2.

[0111] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the detailed description. In general, the selected terminology is used to describe the embodiments, but a person skilled in the art will recognize that equivalents can be used in place of the selected terminology. The description is thus to be regarded as illustrative instead of limiting on the described embodiments.

Claims

1. An electronic power device, comprising: a substrate of silicon carbide, SiC, having a front surface and a back surface, the front surface and the back surface lying in a horizontal plane and facing each other along a vertical axis transverse to the horizontal plane, the substrate comprising an active region, and a non-active edge region surrounding the active region, a plurality of doped regions extending in the active region from the front surface into the substrate; a dielectric region over the front surface at least in the edge region; a passivation layer over the front surface of the substrate, the passivation layer being in contact with the dielectric region in the edge region, wherein the passivation layer comprises at least one anchoring region extending through a thickness of the dielectric region at the edge region, and configured to define a mechanical anchoring for the passivation layer, and wherein the anchoring region comprises: a first portion within the dielectric region, and having a first width along an axis of the horizontal plane; and a second portion overlying the first portion along the vertical axis transverse to the horizontal plane, the second portion having a second width smaller than the first width along the axis of the horizontal plane; and a first and a second abutment element on and in direct contact with the first portion, the first and the second abutment element being arranged laterally and on opposite sides of the second portion.

2. The device of claim 1, wherein the first portion is arranged in an underlayer of the dielectric region, and the first and the second abutment element are portions of an upper layer of the dielectric region interposed in vertical direction between the first portion of the anchoring region and the passivation layer.

3. The device of claim 1, wherein the first portion penetrates through an entire thickness of the dielectric region, and the first and the second abutment element are defined by respective end portions of a first overlying region and of a second overlying region overlying the dielectric region and interposed in vertical direction between the first portion of the anchoring region and the passivation layer.

4. The device of claim 3, wherein the first and the second abutment element comprise a material having a chemical etch selectivity with respect to a material of the dielectric region.

5. The device of claim 4, wherein the dielectric region is made of tetraethyl orthosilicate, TEOS, and the material having a chemical etch selectivity with respect to a material of the dielectric region is polysilicon.

6. The device of claim 4, wherein the second overlying region has an end opposite the second abutment element, the end extending horizontally beyond the dielectric region toward an outer edge of the electronic power device, and wherein at the outer edge of the electronic power device, the passivation layer is disposed laterally with respect to the dielectric region, an anchoring portion of the passivation layer interposed between the end of the second overlying region and an outer portion of the dielectric region in contact.

7. The device of claim 1, wherein the passivation layer comprises polyimide.

8. The device of claim 1, wherein the anchoring region is secured to the passivation layer in areas where there are no electric field lines resulting from operation of the electronic power device, and is coupled in contact with the front surface of the substrate at the edge region.

9. The device of claim 1, wherein the passivation layer includes other anchoring regions that extend through a thickness of the dielectric region at the edge region, and are collectively configured to define the mechanical anchoring for the passivation layer.

10. The device of claim 1, wherein the anchoring region extends continuously around the active region in the horizontal plane.

11. The device of claim 1, wherein the active region has a square or rectangular shape in the horizontal plane, and the anchoring region extends adjacent to corners of the active region in the horizontal plane.

12. A method for manufacturing an electronic power device, comprising: forming a dielectric region on a front surface of a substrate of silicon carbide (SiC) at an edge region of the substrate, the substrate having a front surface and a back surface, the front surface and the back surface lying in a horizontal plane and opposite one another along a vertical axis transverse to the horizontal plane, the substrate including an active region and the edge region, the edge region being non-active, a plurality of doped regions extending from the front surface into the substrate in the active region; forming a passivation layer over the front surface of the substrate and in contact with the dielectric region in the edge region, wherein forming the passivation layer includes forming an anchoring region that extends through a thickness of the dielectric region at the edge region, and the anchoring region is configured to define a mechanical anchoring for the passivation layer; forming an anchoring opening through the dielectric region, the anchoring opening having a first width along an axis of the horizontal plane; and forming an access window on and in communication with the anchoring opening along the vertical axis transverse to the horizontal plane, the access window having a second width that is less than the first width along the axis of the horizontal plane, the access window being defined between a first abutment element and a second abutment element, the first and second abutment elements being disposed laterally and on opposite sides of the access window; wherein forming the anchoring region comprises filling the anchoring opening and the access window, the anchoring region comprising a first portion formed within the anchoring opening and a second portion formed within the access window, the first and second abutment elements being on and in direct contact with the first portion, and being laterally arranged and arranged on opposite sides of the second portion, the anchoring region mechanically fixing the passivation layer with respect to the anchoring opening.

13. The method of claim 12, wherein forming the anchoring opening comprises: forming first and second overlying regions over the dielectric region by etching a layer of material having a chemical etch selectivity with respect to a material of the dielectric region, the first and second overlying regions defining the access window between the first and second overlying regions; and performing a chemical etch of the dielectric region through the access window, and etching respective end portions of the first and second overlying regions, the end portions being overhanging and protruding over the underlying anchoring opening, the end portions of the first and second overlying regions defining the first and second abutment elements, respectively.

14. The method of claim 13, wherein the dielectric region is made of tetraethyl orthosilicate (TEOS), and the material having a chemical etch selectivity with respect to a material of the dielectric region is polysilicon.

15. The method of claim 12, wherein forming the anchoring opening comprises: forming a doped portion by implanting dopants in an outer bottom portion of the dielectric region at the edge region, the doped portion being contained within the dielectric region in contact with the front surface of the substrate, the doped portion having an etch rate higher than an etch rate of a material of an overlying portion of the dielectric region; forming a trench through the dielectric region by performing a dry etch of the dielectric region at the doped portion with an etch mask, the trench being centrally located with respect to the doped portion; and removing the doped portion by performing a wet etch with the etch mask, portions of the dielectric region being overhanging and protruding over the underlying anchoring opening defining the first and second abutment elements.

16. The method of claim 12, wherein forming the anchoring opening comprises: forming a sacrificial region over the front surface at the edge region, wherein forming the dielectric region comprises forming the dielectric region on the sacrificial region, the sacrificial region being contained within the dielectric region; forming a trench through the dielectric region by performing a dry etch of the dielectric region at the sacrificial region with an etch mask, the trench being centrally located with respect to the sacrificial region; and removing the sacrificial region by performing a wet etch; portions of the dielectric region being overhanging and protruding over the underlying anchoring opening defining the first and second abutment elements. ​ 17. The method of claim 12, wherein the passivation layer comprises polyimide.

18. The method of claim 12, wherein the anchor region is secured to the passivation layer in areas where electric field lines due to operation of the electronic power device are not present and is coupled in contact with the front surface of the substrate at the edge region.

Images