Pad structure

Abstract

The present invention discloses a pad structure, which includes a conductive layer, a pad layer, a protective layer and a dielectric layer. The conductive layer is located on a substrate. The protective layer covers the pad layer and has an opening to expose a portion of the pad layer. The dielectric layer is formed between the conductive layer and the substrate and between the conductive layer and the pad layer. The conductive layer includes a plurality of effective blocks, and a ratio of a block area of ​​the effective blocks to a total block area of ​​the effective blocks is between 40% and 50%. The block has a hollow portion, the hollow portion has a hollow area, and the ratio of the hollow area to the block area is between 0.1 and 0.5.

Description

Technical Field

[0001] The invention relates to a pad structure, and in particular to a pad structure with a conductive layer. Background Art

[0002] In the process of the known CUP (Circuit Under Pad) structure, the force applied by the tool to the CUP structure during the wire bonding process and the force applied by the tool to the CUP structure during the circuit testing process can easily cause cracks in the dielectric layer between two conductive layers of the CUP structure or cracks in the metal-to-metal dielectric layer of the same conductive layer. Therefore, how to propose a new CUP structure to improve the above-mentioned problems is one of the directions of efforts of the personnel in this technical field. Summary of the invention

[0003] The present invention relates to a pad structure which can improve the above-mentioned known problems.

[0004] One embodiment of the present invention provides a pad structure. The pad structure includes multiple conductive layers, a pad layer, a protective layer and a dielectric layer. The conductive layer is a part of a circuit. The protective layer covers the pad layer and has an opening to expose a portion of the pad layer. The dielectric layer is formed between the conductive layer and the pad layer and completely separates the conductive layer and the pad layer in the area of ​​the opening. The conductive layer includes a plurality of effective blocks, and a ratio of a block area of ​​a first block of these effective blocks to a total block area of ​​these effective blocks is between 40% and 50%. The first block has at least one hollow portion, the hollow portion has a hollow area, and the ratio of the hollow area to the block area is between 0.1 and 0.5.

[0005] Another embodiment of the present invention provides a pad structure. The pad structure includes multiple conductive layers, a pad layer, a protective layer and a dielectric layer. The conductive layer is a part of a circuit. The protective layer covers the pad layer and has an opening to expose a portion of the pad layer. The dielectric layer is formed between the conductive layer and the pad layer and separates the conductive layer and the pad layer in the area of ​​the opening. The conductive layer includes a first block and a second block, the first block and the second block have a first width and a second width respectively, there is a first interval between the first block and the second block, the first width, the second width and the first interval are dimensions along the same direction, the first width and the second width are both greater than a threshold width, and the first interval is greater than a threshold interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings:

[0007] Figure 1A A schematic diagram of a pad structure according to an embodiment of the present invention is shown.

[0008] Figure 1B Draw Figure 1A A top view of the conductive layer of the pad structure.

[0009] Figure 2A to Figure 2H Schematic diagrams of hollow parts of other embodiments are shown.

[0010] Figure 3A to Figure 3B Schematic diagrams of conductive layers of other embodiments are shown.

[0011] Figure 4A to Figure 4B Draw Figure 1B Schematic diagram of the design process of the conductive layer of the pad structure.

[0012]

Explanation of symbols

[0013] 10: Substrate

[0014] 100: Pad structure

[0015] 110: Conductive layer

[0016] 111: First Block

[0017] 111a: Hollow part

[0018] 112: Second Block

[0019] 113: The third block

[0020] 114: Block 4

[0021] 114': Block

[0022] 120: pad layer

[0023] 130: Protective layer

[0024] 130a: Opening

[0025] 140: Dielectric layer

[0026] 145: Dielectric Materials

[0027] A1: Total block area

[0028] A2: Total hollow area

[0029] A3: Block area

[0030] S12: First interval

[0031] S34: Second interval

[0032] T1, T2: Minimum spacing

[0033] W1: First width

[0034] W2: Second width

[0035] W3: Third width

[0036] W4: fourth width

[0037] W4': Width DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0039] Please refer to Figure 1A and Figure 1B , Figure 1A A schematic diagram of a pad structure 100 according to an embodiment of the present invention is shown. Figure 1B Draw Figure 1A FIG. 1 is a top view of the conductive layer 110 of the pad structure 100 .

[0040] like Figure 1A As shown, the pad structure 100 can be formed on a substrate 10, such as a circuit board or a wafer. In one embodiment, at least one pad structure 100 and the substrate 10 are at least a part of a chip, such as a central processing unit (CPU).

[0041] like Figure 1A As shown, the pad structure 100 includes a plurality of conductive layers 110, a pad layer 120, a protective layer 130, and a plurality of dielectric layers 140. The protective layer 130 covers the pad layer 120 and has an opening 130a to expose a portion of the pad layer 120, so that a bonding wire (not shown) is formed on the pad layer 120 through the opening 130a. At least one of the dielectric layers 1405 is formed between the conductive layers 110 to separate the conductive layers 110. One of the dielectric layers 1405 is formed between the conductive layers 110 and the substrate 10 to separate the conductive layers 110 from the substrate 10. One of the dielectric layers 1405 is formed between the conductive layer 110 and the pad layer 120 to separate the conductive layer 110 from the pad layer 120.

[0042] The conductive layer 110 is formed on the substrate 10 and also includes a dielectric material 145 therein. In the present embodiment, the pad structure 100 is, for example, a CUP structure, and thus the multi-layer conductive layer 110 is a part of at least one circuit. Figure 1AAs shown, in the region of the opening 130a, the conductive layers 110 are separated from each other by the dielectric layer 140, but outside the top view region of the opening 130a, the two conductive layers 110 can be electrically connected through a conductive via (not shown) penetrating the dielectric layer 140. Similarly, in the region of the opening 130a, the pad layer 120 and the conductive layer 110 are separated from each other by the dielectric layer 140, but outside the top view region of the opening 130a, the pad layer 120 and the conductive layer 110 can be electrically connected through a conductive via (not shown) penetrating the dielectric layer 140.

[0043] like Figure 1B As shown, the conductive layer 110 includes a plurality of blocks (eg Figure 1B The first block 111, the second block 112, the third block 113 and the fourth block 114 are separated from each other, and each block is a continuously extended block. The first block 111, the second block 112, the third block 113 and the fourth block 114 are all the conductive layer 110 projected to the opening 130a (i.e. Figure 1B In addition, the embodiment of the present invention does not limit the number of blocks, which may be less than four or more than four.

[0044] like Figure 1B As shown, among these blocks, a block whose block area is greater than a threshold value may have at least one hollow portion 111a. For example, the block area of ​​the first block 111 is greater than the threshold value, so the first block 111 has at least one hollow portion 111a. The block area here refers to Figure 1B The top-view area shown is the area surrounded by the outer boundary of the first block 111 (the portion beyond the opening 130a is defined by the boundary of the opening 130a). Each hollow portion 111a can be filled with a dielectric material 145. The dielectric material 145 is an inter-metal dielectric (IMD). In addition, the dielectric material 145 can also be filled between the two blocks. Compared with the block without the hollow portion 111a, the first block 111 with the hollow portion 111a can improve the stiffness of the conductive layer 110, avoid deformation of the conductive layer 110 caused by the force applied during the wire bonding process, and avoid cracks in the dielectric layer 140 and the dielectric material 145.

[0045] The aforementioned threshold value may be a preset ratio of an area to the total block area A1 of the plurality of valid blocks, and the preset ratio is, for example, between 40% and 50%. Further, among these blocks, the block area of ​​the first block 111, the block area of ​​the second block 112, and the block area of ​​the third block 113 are greater than an effective block area, and thus the first block 111, the second block 112, and the third block 113 are defined as effective blocks. "Effective blocks" refer to blocks that are eligible to be included in the calculation of the total block area A1. The total block area A1 is the sum of the block area of ​​the first block 111, the block area of ​​the second block 112, and the block area of ​​the third block 113. Since the block area of ​​the fourth block 114 is smaller than the effective block area, it is not included in the calculation of the total block area A1. In one embodiment, the effective block area is, for example, 10% of the closed area of ​​the opening 130a.

[0046] Only effective blocks whose block area is between 40% and 50% of the total area A1 need to form the hollow portion 111a. In the present embodiment, among these effective blocks, only the block area of ​​the first block 111 is between 40% and 50% of the total area A1, so only the hollow portion 111a needs to be formed in the first block 111. In another embodiment, the threshold value may be higher than 50% or lower than 40%. When the threshold value is lower, the more parts of the conductive layer 110 are hollowed out, which will cause the resistance of the conductive layer 110 to increase. When the threshold value is higher, the hollow part of the conductive layer 110 is reduced, and the effect of improving the stiffness of the conductive layer 110 is not significant. Since the threshold value of the embodiment of the present invention is between 40% and 50%, the dual effects of excellent conductivity and stiffness improvement of the conductive layer 110 can be taken into account.

[0047] The sum of the areas of all hollowed-out portions 111a of the first block 111 is the total hollowed-out area A2. In an embodiment, the ratio (A2 / A3) of the total hollowed-out area A2 of the first block 111 to the block area A3 of the first block 111 is between 0.1 and 0.5. In this way, the conductive layer 110 has sufficient rigidity to avoid the force applied during the wire bonding process to prevent the dielectric material 145 in the hollowed-out portion 111a from cracking. The aforementioned block area A3 is, for example, the area surrounded by the outer boundary of the first block 111.

[0048] like Figure 1B As shown, the shape of the hollow portion 111a is, for example, a rectangle, and the minimum distance T1 between the hollow portion 111a and the outer boundary of the first block 111 is, for example, between 5 microns and 10 microns. The minimum distance T2 between two adjacent hollow portions 111a is, for example, between 5 microns and 10 microns.

[0049] like Figure 1BAs shown, the first block 111 and the second block 112 have a first width W1 and a second width W2, respectively, and a first interval S12 is provided between the first block 111 and the second block 112. The first width W1, the second width W2, and the first interval S12 are dimensions along the same direction. The first width W1 and the second width W2 are both greater than a threshold width, and the first interval S12 is greater than the threshold interval. In this way, the conductive layer 110 can provide sufficient rigidity to avoid the force applied during the wire bonding process and to avoid cracks in the dielectric material 145 due to deformation of the conductive layer 110. In one embodiment, the threshold width is, for example, equal to or greater than 10 microns, and the threshold interval is, for example, equal to or greater than 2 microns (minimum 2 microns).

[0050] In addition, if the width of a block is smaller than the threshold width, the interval between the two blocks may not be enlarged. Figure 1B As shown, the third block 113 and the fourth block 114 have a third width W3 and a fourth width W4, respectively, and a second interval S34 is provided between the third block 113 and the fourth block 114. The third width W3 and the fourth width W4 are both smaller than the threshold width, indicating that the blocks have a certain rigidity (the larger the width, the larger the block area, and the lower the rigidity of the block), so the second interval S34 may not be considered, for example, the second interval S34 may be smaller than the threshold interval.

[0051] Please refer to Figure 2A to Figure 2H , which depicts schematic diagrams of hollow portions 111a of other embodiments. As can be seen from these figures, in the same block, the shape of one of the multiple hollow portions 111a can be a polygon, such as a square, rectangle, strip, trapezoid, etc., but can also be a circle or an ellipse. In addition, the shapes of any two of the multiple hollow portions 111a can be the same or different. The multiple hollow portions 111a can be arranged parallel to each other. The hollow portions 111a can be arranged obliquely or parallel to the side of the block.

[0052] Please refer to Figure 3A to Figure 3B , which are schematic diagrams of the conductive layer 110 of other embodiments. As can be seen from these figures, the width W4 ′ of the block 114 ′ is smaller than the threshold width, so the interval S14 between two adjacent blocks 114 ′ and the first block 111 can be smaller than the threshold interval.

[0053] Although the above embodiment is described by taking one of the conductive layers 110 as an example, this is not intended to limit the embodiment of the present invention. Any of the above conductive layers 110 may have the above structure, which will not be described in detail herein.

[0054] Please refer to Figure 4A to Figure 4B , which shows Figure 1B FIG. 1 is a diagram of the design process of the conductive layer 110 of the pad structure 100. The design process of each conductive layer 110 of the pad structure 100 is the same as the following process.

[0055] First, if Figure 4A As shown, a preliminary design of a pattern of the conductive layer 110 ′ is provided. The pattern of the conductive layer 110 ′ may be determined according to the circuit function of the pad structure 110 and / or the substrate 10 , and the embodiment of the present invention is not limited thereto.

[0056] Then, the area of ​​the opening 130a is defined.

[0057] Then, multiple blocks of the conductive layer 110' are determined, each block is a continuously extended block, and any two blocks are separated from each other. Based on this principle, the first block 111', the second block 112, the third block 113 and the fourth block 114 are determined in the conductive layer 110'. Next, the block area of ​​each block is calculated. For example, the block area of ​​the first block 111', the block area of ​​the second block 112, the block area of ​​the third block 113 and the block area of ​​the fourth block 114 are calculated. Then, blocks whose block area is smaller than the effective block area are excluded. In this example, the block area of ​​the fourth block 114 is smaller than the effective block area, so the fourth block 114 is not considered in the subsequent design process.

[0058] Then, among these blocks, blocks whose block area is greater than a threshold value are selected. For example, the total block area of ​​the first block 111', the second block 112 and the third block 113 is A1, and the threshold value is, for example, 40% to 50%. Among the first block 111', the second block 112 and the third block 113, only the block area of ​​the first block 111' is between 40% and 50% of the total block area A1, so the first block 111 is selected as the object for forming the hollow portion 111a.

[0059] Then, if Figure 4B As shown, at least one hollow portion 111a is formed in the first block 111' to form the first block 111. In actual semiconductor processes, the hollow portion 111a is filled with dielectric material 145. Since the first block 111 has the hollow portion 111a and the hollow portion 111a is filled with dielectric material 145, the rigidity of the first block 111 can be improved.

[0060] Then, the rigidity of the conductive layer 110 can be enhanced by increasing the interval between the two blocks to avoid the dielectric layer 140 (shown in FIG. Figure 1A In the pad structure 100 of FIG. 1 , cracks occur during the bonding process. For example, in any two adjacent blocks, it is determined whether the width of each block is greater than the threshold width, wherein the width direction of each block is in the same direction; if so, it is determined whether the interval between the two blocks is less than the threshold interval. If the interval between the two blocks is less than the threshold interval, then increasing the interval between the two blocks is actually equal to or greater than the threshold interval.

[0061] For example, Figure 4B As shown, the first width W1 of the first block 111 and the second width W2 of the second block 112 are greater than the threshold width, and the interval S12' between the first block 111 and the second block 112 is less than the threshold interval, so the interval S12' between the first block 111 and the second block 112 can be enlarged to Figure 1B The interval S12 is shown, wherein the interval S12 is actually equal to or greater than the threshold interval.

[0062] In another embodiment, if the interval between the first block 111 and the second block 112 is greater than the threshold interval, a block with a width less than the threshold width may be added between the first block 111 and the second block 112, for example Figure 3A A fourth block 114' is shown.

[0063] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A pad structure formed on a substrate and comprising: a conductive layer, which is part of a circuit; A cushion layer; a protective layer, covering the pad layer and having an opening to expose a portion of the pad layer; a dielectric layer formed between the conductive layer and the pad layer and completely isolating the conductive layer and the pad layer in the region of the opening; Among them, the conductive layer includes multiple effective blocks, the area of ​​each effective block is greater than 10% of an opening area of ​​the opening, a ratio of a block area of ​​a first block of these effective blocks to a total block area of ​​these effective blocks is between 40% and 50%, the first block has a hollow portion, the hollow portion has a hollow area, and the ratio of the hollow area to the block area is between 0.1 and 0.

5.

2. A pad structure formed on a substrate and comprising: a conductive layer, which is part of a circuit; A cushion layer; a protective layer, covering the pad layer and having an opening to expose a portion of the pad layer; a dielectric layer formed between the conductive layer and the pad layer and completely separating the conductive layer and the pad layer in the region of the opening; The conductive layer includes a plurality of effective blocks, the area of ​​each effective block is greater than 10% of an opening area of ​​the opening, a ratio of a block area of ​​a first block of the effective blocks to a total block area of ​​the effective blocks is between 40% and 50%, and the first block has a hollow portion; Wherein, the conductive layer includes a first block and a second block, the first block and the second block have a first width and a second width respectively, there is a first interval between the first block and the second block, the first width, the second width and the first interval are dimensions along the same direction, the first width and the second width are both greater than a threshold width, and the first interval is greater than a threshold interval.

3. The pad structure according to claim 1 or 2, characterized in that: The first block is a portion of the conductive layer projected onto the opening.

4. The pad structure according to claim 1 or 2, characterized in that: The block area is the area surrounded by the outer boundary of the first block.

5. The pad structure according to claim 1, characterized in that: The minimum distance between the hollow portion and the outer boundary of the first block is between 5 micrometers and 10 micrometers.

6. The pad structure according to claim 1, characterized in that: The first block includes a plurality of the hollow portions, and a minimum distance between two adjacent hollow portions is between 5 micrometers and 10 micrometers.

7. The pad structure according to claim 1, characterized in that: The first block includes a plurality of hollow portions, and the hollow portions are parallel to each other.

8. The pad structure according to claim 1, characterized in that: The hollow portion is inclined relative to a side of the first block.

9. The pad structure according to claim 1, characterized in that: The shape of the hollow portion is polygonal, circular or elliptical.

10. The pad structure according to claim 2, characterized in that: The first block and the second block are portions of the conductive layer projected onto the opening.

11. The pad structure according to claim 2, characterized in that: The conductive layer also includes a third block and a fourth block, the third block and the fourth block have a third width and a fourth width respectively, there is a second interval between the third block and the fourth block, the third width and the fourth width are both smaller than the threshold width, and the second interval is smaller than the threshold interval.

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