Electronic device and method for operating the same

Abstract

An electronic device may include a semiconductor memory. The semiconductor memory may include: a first variable resistance layer including antimony (Sb); a second variable resistance layer including antimony (Sb) at a different content from that of the first variable resistance layer, and a crystallization speed of the second variable resistance layer being different from that of the first variable resistance layer; and a first electrode between the first variable resistance layer and the second variable resistance layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0123112, filed on October 4, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to an electronic device, and more particularly, to an electronic device including a semiconductor memory and an operating method of the electronic device. Background Art

[0004] Recently, as electronic devices or equipment tend to be miniaturized, low-power, high-performance, and multifunctional, semiconductor devices capable of storing information are required in various electronic devices or equipment such as computers and portable communication devices. Therefore, research has been conducted on semiconductor devices capable of storing data using the following characteristics, that is, the semiconductor device switches between different resistance states according to the voltage or current applied thereto. Examples of semiconductor devices are resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and E-fuse, etc. Summary of the invention

[0005] The embodiment provides an electronic device capable of improving its operating characteristics and reliability and an operating method of the electronic device.

[0006] According to one aspect of the present disclosure, an electronic device including a semiconductor memory is provided, wherein the semiconductor device includes: a first variable resistance layer containing antimony (Sb); a second variable resistance layer containing antimony (Sb) at a content different from that of the first variable resistance layer, and a crystallization rate of the second variable resistance layer is different from that of the first variable resistance layer; and a first electrode disposed between the first variable resistance layer and the second variable resistance layer.

[0007] According to another aspect of the present disclosure, an electronic device including a semiconductor memory is provided, wherein the semiconductor memory includes: a first variable resistance layer containing antimony (Sb); a second variable resistance layer containing antimony (Sb) at a higher content than the first variable resistance layer, and a crystallization rate of the second variable resistance layer is higher than a crystallization rate of the first variable resistance layer; a third variable resistance layer containing antimony (Sb) at a higher content than the second variable resistance layer, and a crystallization rate of the third variable resistance layer is higher than a crystallization rate of the second variable resistance layer; a first electrode disposed between the first variable resistance layer and the second variable resistance layer; and a second electrode disposed between the second variable resistance layer and the third variable resistance layer.

[0008] According to another aspect of the present disclosure, an electronic device including a semiconductor memory is provided, wherein the semiconductor memory includes: a first variable resistance layer; a second variable resistance layer whose crystallization speed is different from that of the first variable resistance layer; and a first electrode, which is located between the first variable resistance layer and the second variable resistance layer, wherein the first variable resistance layer or the second variable resistance layer or both include: a first doping element that reduces the crystallization speed of the variable resistance material or a second doping element that increases the crystallization speed.

[0009] According to another aspect of the present disclosure, a method for operating an electronic device including a semiconductor memory is provided, wherein the semiconductor memory includes: a first variable resistance layer containing antimony (Sb); a second variable resistance layer containing antimony (Sb) at a higher content than the first variable resistance layer; and a first electrode between the first variable resistance layer and the second variable resistance layer, wherein the method includes selectively crystallizing the second variable resistance layer by applying a first partial setting pulse. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0011] In the accompanying drawings, the dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being between two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the text, similar reference numerals refer to similar elements.

[0012] Figure 1 is a diagram showing a structure of an electronic device according to an embodiment of the present disclosure.

[0013] Figure 2A , Figure 2B and Figure 2C are diagrams each illustrating a structure of an electronic device according to an embodiment of the present disclosure.

[0014] Figure 3 is a diagram illustrating a cross section of an electronic device according to an embodiment of the present disclosure.

[0015] Figure 4A , Figure 4B , Figure 4C and Figure 4D are diagrams respectively illustrating an operating method of an electronic device according to an embodiment of the present disclosure.

[0016] Figure 5 is a diagram illustrating operational characteristics of an electronic device according to one embodiment of the present disclosure.

[0017] Figure 6 is a configuration diagram of a microprocessor in which a memory device according to an embodiment of the present disclosure is implemented.

[0018] Figure 7 is a configuration diagram of a processor implementing a memory device according to one embodiment of the present disclosure.

[0019] Figure 8 is a configuration diagram of a system in which a memory device according to an embodiment of the present disclosure is implemented.

[0020] Fig. 9 is a configuration diagram of a data storage system in which a storage device according to an embodiment of the present disclosure is implemented.

[0021] Fig.10 is a configuration diagram of a memory system in which a memory device according to an embodiment of the present disclosure is implemented. DETAILED DESCRIPTION

[0022] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0023] The drawings may not necessarily be drawn to scale, and in some cases, the proportions of at least some structures in the drawings may be exaggerated in order to clearly illustrate certain features of the described examples or embodiments. When a specific example in a drawing or description having two or more layers is shown in a multilayer structure, the relative positioning relationship of these layers or the arrangement order of these layers shown reflects the specific embodiment of the described or shown example, and different relative positioning relationships or the arrangement order of these layers are possible. In addition, the example of the described or shown multilayer structure may not reflect all the layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two shown layers). In a specific example, when the first layer in the described or shown multilayer structure is referred to as being "above" or "above" the second layer or "above" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, or may represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate. Throughout this disclosure, in the various figures and embodiments of the present disclosure, similar reference numerals refer to similar parts.

[0024] Figure 1 is a diagram showing a structure of an electronic device according to an embodiment of the present disclosure.

[0025] refer to Figure 1 , an electronic device according to an embodiment of the present disclosure may include a semiconductor memory. The semiconductor memory may be a nonvolatile memory device, and may be a variable resistance memory device. The semiconductor memory may include row lines and column lines crossing the row lines. The row lines may be word lines, and the column lines may be bit lines. Word lines and bit lines are relative concepts. For example, the row lines may be bit lines, and the column lines may be word lines. In the following, it is assumed and described that the row lines are word lines and the column lines are bit lines.

[0026] The cell array 100 may include memory cells MC11 to MC33 respectively arranged between column lines BL1 to BL3 and row lines WL1 to WL3. The memory cells MC11 to MC33 may be arranged at respective intersections of the column lines BL1 to BL3 and the row lines WL1 to WL3. Each of the memory cells MC11 to MC33 may include a corresponding one of the selection elements S11 to S33 or a corresponding one of the storage elements M11 to M33, or both. For example, each of the memory cells MC11 to MC33 may include a corresponding selection element among the selection elements S11 to S33 and a corresponding storage element among the storage elements M11 to M33, the two being connected in series. The selection elements S11 to S33 may be electrically connected to the row lines WL1 to WL3, and the storage elements M11 to M33 may be electrically connected to the column lines BL1 to BL3.

[0027] Each of the storage elements M11 to M33 is a storage node for storing data, and may include a variable resistance material. The variable resistance material may be a resistance material, a magnetic tunnel junction (MTJ), or a phase change material, etc. Each of the selection elements S11 to S33 is used to select a corresponding one of the storage cells MC11 to MC33, and may include a switch material. Each of the selection elements S11 to S33 may be a diode, a PNP diode, a bipolar junction transistor (BJT), a metal insulator transition (MIT) element, a mixed ion electron conduction (MIEC) element, or a bidirectional threshold switch (OST) element, etc.

[0028] The shape and configuration of each of the memory cells MC11 to MC33 may be variously modified. For example, the selection elements S11 to S33 may be omitted, or the storage elements M11 to M33 may be omitted. Alternatively, the positions of the selection elements S11 to S33 and the storage elements M11 to M33 may be reversed. For example, the selection elements S11 to S33 may be electrically connected to the column lines BL1 to BL3, and the storage elements M11 to M33 may be electrically connected to the row lines WL1 to WL3.

[0029] In addition, the semiconductor memory may further include a column circuit 110 for controlling the column lines BL1 to BL3 and a row circuit 120 for controlling the row lines WL1 to WL3 .

[0030] The row circuit 120 may be a row decoder, a word line decoder, or a word line driver, etc. The row circuit 120 may select the row line WL2 from among the row lines WL1 to WL3 according to the row address R_ADD. The column circuit 110 may be a column decoder, a bit line decoder, or a bit line driver, etc. The column circuit 110 may select the column line BL2 from among the column lines BL1 to BL3 according to the column address C_ADD. Therefore, the memory cell MC22 connected between the selected column line BL2 and the selected row line WL2 may be selected.

[0031] Despite Figure 1 , but this is only for convenience of description and the embodiments of the present disclosure are not limited thereto. If necessary, the number of column lines BL1 to BL3 and row lines WL1 to WL3 included in the cell array 100 may be changed.

[0032] Figure 2A , Figure 2B and Figure 2C are diagrams each illustrating a structure of an electronic device according to an embodiment of the present disclosure. Figure 2A is a layout diagram of the electronic device, Figure 2B is along Figure 2A A cross-sectional view of the line AA' shown, and Figure 2Cis along Figure 2A A cross-sectional view along line BB' is shown.

[0033] refer to FIG. 2A to FIG. 2C According to an embodiment of the present disclosure, an electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells MC. The semiconductor memory device may be a nonvolatile memory device, and may be a variable resistance memory device.

[0034] Each memory cell MC may include a first electrode 11, a switching layer 12, a second electrode 13, a variable resistance layer 14, and a third electrode 15. Furthermore, protection layers 17 and 19 may be formed on sidewalls of the memory cells MC, and insulating layers 18 and 20 may be filled between the memory cells MC.

[0035] The variable resistance layer 14 may include a phase change material. The phase change material has a low resistance characteristic in a crystalline state and a high resistance characteristic in an amorphous state. Therefore, data can be stored by performing a set operation of switching the state of the phase change material from a high resistance amorphous state to a low resistance crystalline state, and by performing a reset operation of switching the state of the phase change material from a low resistance crystalline state to a high resistance amorphous state. When the variable resistance layer 14 has a low resistance state, data "1" can be stored. When the variable resistance layer 14 has a high resistance state, data "0" can be stored.

[0036] The variable resistance layer 14 may include a chalcogenide-based material such as germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi) or tin (Sn), or may include any combination thereof. The variable resistance layer 14 may include Ge-Sb-Te (GST), and may include Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4 or Ge1Sb4Te7, etc. The chemical composition ratio of the variable resistance layer 14 may be determined by considering properties such as melting point and crystallization temperature. Moreover, the variable resistance layer 14 may further include doping elements such as boron (B), carbon (C), nitrogen (N), oxygen (O), silicon (Si), zinc (Zn), gallium (Ga), arsenic (As), selenium (Se), silver (Ag), indium (In), or may include any combination thereof.

[0037] The variable resistance layer 14 may have a multi-layer structure, and the memory cell MC may have a structure in which the variable resistance layer and the electrode are alternately stacked. Figure 3 This is described in detail.

[0038] The switch layer 12 may be a selection element that controls the flow of current according to the magnitude of the voltage or current applied thereto. When the magnitude of the applied voltage and current is a threshold value or less, almost no current flows in the switch layer 12. When the magnitude of the applied voltage and current exceeds the threshold value, a rapidly increasing current flows in the switch layer 12.

[0039] When the switching layer 12 is a metal insulator transition (MIT) element, the switching layer 12 may include VO2, NbO2, TiO2, WO2, TiO2, etc. When the switching layer 12 is a mixed ion electron conduction (MIEC) element, the switching layer 12 may include ZrO2 (Y2O3), Bi2O3-BaO, (La2O3) x (CeO2) 1-x Etc. In addition, when the switch layer 12 is a bidirectional threshold switch (OST) element, the switch layer 12 may include a chalcogenide-based material such as AsTe, AsSe, AsTeSe, AsTeGe, AsSeGe, or AsTeGeSe.

[0040] The first electrode 11 may be electrically connected to the row line 10, the second electrode 13 may be interposed between the switch layer 12 and the variable resistance layer 14, and the third electrode 15 may be electrically connected to the column line 16. The first electrode 11, the second electrode 13, and the third electrode 15 may include a conductive material such as a metal or a metal nitride. For example, each of the first electrode 11, the second electrode 13, and the third electrode 15 may include tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), titanium (Ti), titanium nitride (WNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), platinum (Pt), etc., or may include any combination thereof.

[0041] According to the above structure, the first electrode 11, the switch layer 12 and the second electrode 13 can constitute a selection element. The second electrode 13, the variable resistance layer 14 and the third electrode 15 can constitute a memory element. In addition, the selection element and the memory element can share the second electrode 13.

[0042] Figure 3 is a diagram showing a cross section of a portion of an electronic device according to an embodiment of the present disclosure. The electronic device may include a semiconductor memory, and Figure 3 may be a cross-sectional view of a memory cell MC included in a semiconductor memory.

[0043] refer to Figure 3, a memory cell MC according to an embodiment of the present disclosure may include a plurality of variable resistance layers 31 to 33 and a plurality of electrodes 41 to 44. The plurality of variable resistance layers 31 to 33 and the plurality of electrodes 41 to 44 may be alternately stacked. The memory cell MC may include a first variable resistance layer 31, a second variable resistance layer 32, and a third variable resistance layer 33, and may include a first electrode 41, a second electrode 42, a third electrode 43, and a fourth electrode 44 alternately stacked with the first variable resistance layer 31, the second variable resistance layer 32, and the third variable resistance layer 33. Although Figure 3 Although not shown in the figure, the memory cell MC may further include a switching layer.

[0044] The memory cell MC may include a plurality of variable resistance layers 31 to 33, and the plurality of variable resistance layers 31 to 33 contain different contents of antimony (Sb). The crystallization speed of the variable resistance layer having a high antimony content (Sb) may be higher than the crystallization speed of the variable resistance layer having a low antimony content (Sb). In other words, the setting operation speed of the variable resistance layer having a high antimony (Sb) content may be higher than the setting operation speed of the variable resistance layer having a low antimony (Sb) content. Therefore, the content of antimony (Sb) is adjusted so that the plurality of variable resistance layers 31 to 33 in the same memory cell MC can be controlled to have different crystallization speeds or different setting operation speeds.

[0045] The first to third variable resistance layers 31 to 33 may contain different contents of antimony (Sb). The second variable resistance layer 32 may contain a higher content of antimony (Sb) than the first variable resistance layer 31, and may have a higher crystallization speed or set operation speed than the first variable resistance layer 31. The third variable resistance layer 33 may contain a higher content of antimony (Sb) than the second variable resistance layer 32, and may have a higher crystallization speed or set operation speed than the second variable resistance layer 32.

[0046] In one embodiment, the first variable resistance layer 31 may contain 10at% (atomic percentage) to 20at% germanium (Ge), 20at% to 25at% antimony (Sb), and 45at% to 55at% tellurium (Te). The second variable resistance layer 32 may contain 10at% to 20at% germanium (Ge), 25at% to 30at% antimony (Sb), and 45at% to 55at% tellurium (Te). The third variable resistance layer 33 may contain 10at% to 20at% germanium (Ge), 30at% to 35at% antimony (Sb), and 45at% to 55at% tellurium (Te).

[0047] One or more of the first to third variable resistance layers 31 to 33 may contain a doping element. One or more of the first to third variable resistance layers 31 to 33 may contain 0 to 25 at% of the doping element or may contain 0 to 10 at%. The doping element may include one or more of B, C, N, O, Si, Zn, Ga, As, Se, Ag, In, and Sn.

[0048] In one embodiment, the doping element may accelerate the crystallization of the variable resistance layer, and may include one or more of B, Zn, Ag, In, and Sn. The crystallization rate of the variable resistance layer including the doping element that accelerates crystallization may be higher than the crystallization rate of the variable resistance layer not including the doping element. In addition, the crystallization rate of the variable resistance layer having a high content of the doping element may be higher than the crystallization rate of the variable resistance layer having a low content of the doping element.

[0049] In one embodiment, the doping element may hinder the crystallization of the variable resistance layer, and may include one or more of C, N, O, Si, Ga, As, and Se. The crystallization speed of the variable resistance layer including the doping element that hinders crystallization may be lower than the crystallization speed of the variable resistance layer that does not include the doping element. In addition, the crystallization speed of the variable resistance layer having a high content of the corresponding doping element may be lower than the crystallization speed of the variable resistance layer having a low content of the doping element.

[0050] The crystallization speed of the first variable resistance layer 31 to the third variable resistance layer 33 may be adjusted according to the chemical composition ratio of Ge-Sb-Te (GST), may be adjusted according to the content of the doping element, or may be adjusted by a combination of the chemical composition ratio and the content. The first variable resistance layer 31 to the third variable resistance layer 33 may be formed to include GST having different chemical composition ratios, so that the crystallization speed of each of the first variable resistance layer 31 to the third variable resistance layer 33 may be adjusted. Doping elements may be added to the first variable resistance layer 31 to the third variable resistance layer 33 having different chemical composition ratios, so that the crystallization speed of each of the first variable resistance layer 31 to the third variable resistance layer 33 may be more finely adjusted. Alternatively, the first variable resistance layer 31 to the third variable resistance layer 33 may be formed to include GST having substantially the same chemical composition ratio, and the doping element may be used to control the crystallization speed of each of the variable resistance layers 31 to 33.

[0051] At the same time, despite Figure 3, the first variable resistance layer 31 to the third variable resistance layer 33 are sequentially stacked, but the embodiments of the present disclosure are not limited thereto. The stacking order of the first variable resistance layer 31 to the third variable resistance layer 33 may be changed. The variable resistance layers may be sequentially stacked starting from the variable resistance layer with the lowest crystallization speed, sequentially stacked starting from the variable resistance layer with the highest crystallization speed, or randomly stacked regardless of the crystallization speed.

[0052] According to the above structure, one memory cell MC may include a plurality of variable resistance layers 31 to 33. By utilizing the difference in crystallization speed or setting operation speed among the variable resistance layers 31 to 33, multi-bit data may be stored in one memory cell MC.

[0053] Figure 4A , Figure 4B , Figure 4C and Figure 4D are diagrams respectively illustrating an operating method of an electronic device according to one embodiment of the present disclosure. Hereinafter, a method for storing multi-bit data in one memory cell MC including a plurality of variable resistance layers will be described.

[0054] refer to FIG. 4A to FIG. 4D The electronic device can perform a reset operation, a partial set operation, or a full set operation according to the written data. Table 1 shows the states of the first variable resistance layer PCM1, the second variable resistance layer PCM2, and the third variable resistance layer PCM3 according to the value of the written data.

[0055] Table 1

[0056] Settings(00) Partial settings (01) Partial settings (10) Full settings (11) PCM1 Reset Reset Reset set up PCM2 Reset Reset set up set up PCM3 Reset set up set up set up

[0057] In one embodiment, the first variable resistance layer PCM1 to the third variable resistance layer PCM3 may have different set operation speeds according to the chemical composition ratio. The first variable resistance layer PCM1 may contain 20at% to 25at% antimony (Sb), the second variable resistance layer PCM2 may contain 25at% to 30at% antimony (Sb), and the third variable resistance layer PCM3 may contain 30at% to 35at% antimony (Sb). Therefore, the crystallization speed of the second variable resistance layer PCM2 may be higher than the crystallization speed of the first variable resistance layer PCM1, and the crystallization speed of the third variable resistance layer PCM3 may be higher than the crystallization speed of the second variable resistance layer PCM2. In addition, one or more of the first variable resistance layer PCM1 to the third variable resistance layer PCM3 may further include a doping element that hinders the crystallization of the variable resistance material or a doping element that accelerates the crystallization.

[0058] In one embodiment, the first variable resistance layer PCM1 to the third variable resistance layer PCM3 may have different setting operation speeds depending on the doping elements. In addition, the speed of the setting operation may be fine-tuned according to the type, content, etc. of the doping elements contained in each of the first variable resistance layer PCM1 to the third variable resistance layer PCM3. The first variable resistance layer PCM1 may contain one or more doping elements among C, N, O, Si, Ga, As and Se, and the third variable resistance layer PCM3 may contain one or more doping elements among B, Zn, Ag, In and Sn. Therefore, the crystallization speed of the second variable resistance layer PCM2 may be higher than the crystallization speed of the first variable resistance layer PCM1, and the crystallization speed of the third variable resistance layer PCM3 may be higher than the crystallization speed of the second variable resistance layer PCM2. The first variable resistance layer PCM1 to the third variable resistance layer PCM3 may have the same chemical composition ratio or may have different chemical composition ratios.

[0059] refer to Figure 4A and Table 1, at S41, a reset pulse is applied to the memory cell (e.g., Figure 3 100μA or more reset pulse is applied to the memory cell MC for 10ns to 50ns. Through the reset operation, the first variable resistance layer PCM1 to the third variable resistance layer PCM3 all have a high resistance amorphous state. The first variable resistance layer PCM1 to the third variable resistance layer PCM3 all have a reset state. Therefore, at S42, the reset data (00) can be written into the memory cell.

[0060] refer to Figure 4B and Table 1, at S43, a first partial set pulse is applied to the memory cell MC. Through the first partial set operation, one of the first variable resistance layer PCM1 to the third variable resistance layer PCM3 has a low resistance crystalline state. For example, the third variable resistance layer PCM3 having the highest set operation speed or set operation speed among the first variable resistance layer PCM1 to the third variable resistance layer PCM3 can be selectively crystallized to have a low resistance state. The third variable resistance layer PCM3 has a set state, and the first variable resistance layer PCM1 and the second variable resistance layer PCM2 maintain a reset state.

[0061] The peak level of the first partial set pulse may be lower than the peak level of the reset pulse and may be applied longer than the reset pulse. For example, a first partial set pulse of 50 μA or less is applied to the memory cell MC for 100 ns to 200 ns. Therefore, at S44, the partial set data (01) may be written into the memory cell.

[0062] refer to Figure 4Cand Table 1, at S45, the second partial set pulse is applied to the memory cell MC. Through the second partial set operation, two of the first variable resistance layer PCM1 to the third variable resistance layer PCM3 have a low resistance crystal state. For example, the second variable resistance layer PCM2 and the third variable resistance layer PCM3 having a relatively high set operation speed or a set operation speed among the first variable resistance layer PCM1 to the third variable resistance layer PCM3 can be selectively crystallized to have a low resistance state. The second variable resistance layer PCM2 and the third variable resistance layer PCM3 have a set state, and the first variable resistance layer PCM1 maintains a reset state.

[0063] The peak level of the second partial setting pulse may be equal to or close to the peak level of the first partial setting pulse, and may be applied longer than the first partial setting pulse. The peak level of the second partial setting pulse may be lower than the peak level of the reset pulse, and may be applied longer than the reset pulse. For example, a second partial setting pulse of 50 μA or less is applied to the memory cell MC for 300 ns to 600 ns. Therefore, at S46, the partial setting data (10) may be written into the memory cell MC.

[0064] refer to Figure 4D As shown in Table 1, at S47, a full set pulse is applied to the memory cell MC. Through the full set operation, the first to third variable resistance layers PCM1 to PCM3 all have a low resistance crystalline state. The first to third variable resistance layers PCM1 to PCM3 have a set state.

[0065] The peak level of the full set pulse may be equal to or close to the peak level of the second partial set pulse, and may be applied longer than the second partial set pulse. For example, a full set pulse of 50 μA or less is applied to the memory cell MC for 800 ns to 1000 ns. Thus, at S48, the set data (11) may be written to the memory cell MC.

[0066] Figure 5 is a graph showing operating characteristics of an electronic device according to an embodiment of the present disclosure. The X-axis represents a programming current or voltage applied to a memory cell, and the Y-axis represents a resistance value R or a threshold voltage Vth of the memory cell.

[0067] refer to Figure 5 As shown in the graph, the threshold voltage Vth or the resistance value R of the memory cell is changed when the reset operation, the first partial set operation, the second partial set operation, and the full set operation are performed.

[0068] Reset data (00) can be written into the storage cell through a reset operation, partial set data (01) can be written into the storage cell through a first partial set operation, partial set data (10) can be written into the storage cell through a second partial set operation, and set data (11) can be written into the storage cell through a full set operation.

[0069] The reset operation may use a programming current or voltage whose level is higher than the first partial set operation, the second partial set operation, and the full set operation. The first partial set operation, the second partial set operation, and the full set operation may use a programming current or voltage whose level is lower than the reset operation. The first partial set operation, the second partial set operation, and the full set operation may have different waveforms. The first partial set operation, the second partial set operation, and the full set operation may use programming currents or voltages whose levels are substantially equal or close to each other, and may have different periods of applying the programming currents or voltages. The reset pulse may be applied for a period of 100ns or less, the first partial set pulse may be applied for a period of about 100ns, the second partial set pulse may be applied for a period of about 300ns, and the full set pulse may be applied for a period of about 1000ns.

[0070] Depending on the data written therein, the memory cells may have different threshold voltages Vth or different resistance values ​​R. A memory cell to which reset data (00) is written may have the highest threshold voltage Vth or resistance value R. A memory cell to which set data (11) is written may have the lowest threshold voltage Vth or resistance value R. A memory cell to which partial set data (10 or 01) is written may have a threshold voltage Vth or resistance value R between a set state and a reset state. A memory cell to which partial set data (01) is written may have a higher threshold voltage Vth or resistance value R than a memory cell to which partial set data (10) is written.

[0071] Figure 6 is a configuration diagram of a microprocessor in which a memory device according to an embodiment of the present disclosure is implemented.

[0072] refer to Figure 6 , the microprocessor 1000 may perform tasks to control and regulate a series of processes of receiving data from various external devices, processing data, and outputting processing results to external devices. The microprocessor 1000 may include a memory 1010, an operation component 1020, a controller 1030, etc. The microprocessor 1000 may be various data processing units such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0073] The memory 1010 is a part that stores data in the microprocessor 1000, such as a processor register or register, etc. The memory 1010 may include a data register, an address register, a floating point register, etc. In addition, the memory 1010 may include various registers. The memory 1010 may perform the following functions: temporarily storing data to be operated by the operation component 1020, result data of performing the operation, and an address where the data for performing the operation is stored.

[0074] The memory 1010 may include one or more of the semiconductor devices described above according to the embodiments. For example, the memory 1010 may include a semiconductor memory including: a first variable resistance layer including antimony (Sb); a second variable resistance layer including an antimony (Sb) content different from that of the first variable resistance layer, and a crystallization speed of the second variable resistance layer different from that of the first variable resistance layer; and a first electrode between the first variable resistance layer and the second variable resistance layer. Thus, the characteristics of the memory 1010 may be improved. Therefore, the operating characteristics of the microprocessor 1000 may be improved.

[0075] The operation component 1020 may perform several arithmetic operations or logic operations according to the result of decoding the command by the controller 1030. The operation component 1020 may include at least one arithmetic logic unit (ALU) and the like.

[0076] The controller 1030 may receive signals from the memory 1010 , the operation component 1020 , and external devices of the microprocessor 1000 , perform extraction and decoding of commands, and control input and output of signals of the microprocessor 1000 , and execute a process represented by a program.

[0077] The microprocessor 1000 according to the present embodiment may further include a cache memory 1040, which may temporarily store data to be input from an external device other than the memory 1010 or data to be output to an external device. The cache memory 1040 may exchange data with the memory 1010, the operation component 1020, and the controller 1030 through the bus interface 1050.

[0078] Figure 7 is a configuration diagram of a processor implementing a memory device according to one embodiment of the present disclosure.

[0079] refer to Figure 7, the processor 1100 can improve performance and realize multi-functions by including various functions in addition to the functions of a microprocessor, and the microprocessor performs tasks for controlling and regulating a series of processes for receiving data from various external devices, processing data, and outputting processing results to the external devices. The processor 1100 may include a core unit 1110 used as a microprocessor, a cache memory 1120 for temporarily storing data, and a bus interface 1130 for transmitting data between internal and external devices. The processor 1100 may include various systems on chip (SoCs), such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

[0080] The core unit 1110 of the present embodiment is a part that performs an arithmetic logic operation on data input from an external device, and may include a memory 1111 , an operation component 1112 , and a controller 1113 .

[0081] The memory 1111 is a part that stores data in the processor 1100, such as a processor register or registers, etc. The memory 1111 may include a data register, an address register, a floating point register, etc. In addition, the memory 1111 may include various registers. The memory 1111 may perform the following data functions of temporarily storing: data to be operated by the operation component 1112, the result data of performing the operation, and the address where the data for performing the operation is stored. The operation component 1112 is a part that performs operations in the processor 1100. The operation component 1112 may perform several arithmetic operations, logical operations, etc. according to the result of the controller 1113 decoding the command. The operation component 1112 may include at least one arithmetic logic unit (ALU), etc. The controller 1113 may receive signals from the memory 1111, the operation component 1112, and the external device of the processor 1100, perform the extraction and decoding of the command, and control the input and output of the signal of the processor 1100, and execute the processing process represented by the program.

[0082] The cache memory 1120 is a component that temporarily stores data to compensate for the difference in data processing speed between the core unit 1110 operating at a high speed and the external device operating at a low speed. The cache memory 1120 may include a primary storage part 1121, a secondary storage part 1122, and a tertiary storage part 1123. Generally, the cache memory 1120 includes a primary storage part 1121 and a secondary storage part 1122, and may include a tertiary storage part 1123 in the case where a high storage capacity is required. As required by the situation, the cache memory 1120 may include an increased number of storage parts. That is, the number of storage parts included in the cache memory 1120 may be changed according to the design. The speeds of storing and distinguishing data in the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 may be the same or different. In the case where the speeds of the respective storage parts 1121, 1122, and 1123 are different, the speed of the primary storage part 1121 may be the largest. At least one of the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 of the cache memory 1120 may include one or more of the semiconductor devices described above according to the embodiments. For example, the cache memory 1120 may include a semiconductor memory including: a first variable resistance layer containing antimony (Sb); a second variable resistance layer containing antimony (Sb) at a different content from that of the first variable resistance layer, the second variable resistance layer having a different crystallization speed from that of the first variable resistance layer; and a first electrode between the first variable resistance layer and the second variable resistance layer.

[0083] Despite Figure 7 11 shows a case where the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 are all configured inside the cache memory 1120, but the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 of the cache memory 1120 may be configured outside the core unit 1110, and the difference in data processing speed between the core unit 1110 and the external device may be compensated. Alternatively, the primary storage part 1121 of the cache memory 1120 may be set inside the core unit 1110, and the secondary storage part 1122 and the tertiary storage part 1123 may be configured outside the core unit 1110 to enhance the function of compensating for the difference in data processing speed. Alternatively, the primary storage part 1121 and the secondary storage part 1122 may be set inside the core unit 1110, and the tertiary storage part 1123 may be set outside the core unit 1110.

[0084] The bus interface 1130 is a component that connects the core unit 1110 , the cache memory 1120 , and external devices and allows data to be efficiently transferred.

[0085] The processor 1100 according to this embodiment may include a plurality of core units 1110, and the plurality of core units 1110 may share a cache memory 1120. The plurality of core units 1110 and the cache memory 1120 may be directly connected or connected through a bus interface 1130. The plurality of core units 1110 may be configured in the same manner as the configuration of the core unit 1110 described above. In the case where the processor 1100 includes a plurality of core units 1110, a primary storage portion 1121 of the cache memory 1120 may be configured in each core unit 1110 corresponding to the number of the plurality of core units 1110, and a secondary storage portion 1122 and a tertiary storage portion 1123 may be configured outside the plurality of core units 1110 in a manner of being shared through the bus interface 1130. The processing speed of the primary storage portion 1121 may be greater than the processing speeds of the secondary storage portion 1122 and the tertiary storage portion 1123. In another embodiment, the primary storage part 1121 and the secondary storage part 1122 can be configured in each core unit 1110 corresponding to the number of multiple core units 1110, and the tertiary storage part 1123 can be configured outside the multiple core units 1110 in a manner shared through the bus interface 1130.

[0086] The processor 1100 according to this embodiment may further include: an embedded memory 140 that stores data; a communication module 1150 that can send data to and receive data from an external device in a wired or wireless manner; a memory controller 1160 that drives an external storage device; and a media processor 1170 that processes data processed in the processor 1100 or data input from an external input device, and outputs the processed data to an external interface device, etc. In addition, the processor 1100 may include a plurality of various modules and devices. The additional plurality of modules may exchange data with the core unit 1110 and the cache memory 1120 and with each other through the bus interface 1130.

[0087] The embedded memory 1140 may include not only volatile memory but also non-volatile memory. Volatile memory may include DRAM (dynamic random access memory), mobile DRAM, SRAM (static random access memory), and memory with similar functions to the above memory, etc. Non-volatile memory may include ROM (read-only memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), and memory with similar functions.

[0088] The communication module 1150 may include a module that can be connected to a wired network, a module that can be connected to a wireless network, and both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), and various devices such as sending and receiving data through a transmission line. The wireless network module may include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), and various devices such as sending and receiving data without a transmission line.

[0089] The memory controller 1160 is used to manage and process data transmitted between the processor 1100 and an external storage device operating according to different communication standards. The memory controller 1160 may include various memory controllers, for example, devices that can control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), SSD (Solid State Disk), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus), Secure Digital (SD) Card, Mini Secure Digital (mSD) Card, Micro Secure Digital (micro SD) Card, Secure Digital High Capacity (SDHC) Card, Memory Stick Card, Smart Media (SM) Card, Multimedia Card (MMC), Embedded MMC (eMMC), and Compact Flash (CF) Card, etc.

[0090] The media processor 1170 may process data processed in the processor 1100 or data input from an external input device in the form of images, voices, and other forms, and output the data to an external interface device. The media processing unit 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio device (HD audio), and a high-definition multimedia interface (HDMI) controller, etc.

[0091] Figure 8 is a configuration diagram of a system in which a memory device according to an embodiment of the present disclosure is implemented.

[0092] refer to Figure 8 , the system 1200 as a device for processing data can perform input, processing, output, communication, storage, etc. to perform a series of operations on data. The system 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, and an interface device 1240, etc. The system 1200 of this embodiment may be various electronic systems that use a processor to operate, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a network tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a recorder, a car information system, an audio-visual (AV) system, and a smart TV, etc.

[0093] The processor 1210 may decode input commands, process operations, comparisons, etc. for data stored in the system 1200, and control these operations. The processor 1210 may include a microprocessor unit (MPU), a central processing unit (CPU), a single / multi-core processor, a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and the like.

[0094] The main memory device 1220 is a memory that can temporarily store, call and execute program codes or data from the auxiliary memory device 1230 when executing a program and can maintain the stored content even when the power is cut off. The main memory device 1220 may include one or more of the above-mentioned semiconductor devices according to the embodiment. For example, the main memory device 1220 may include a semiconductor memory, which includes: a first variable resistance layer, which contains antimony (Sb); a second variable resistance layer, the content of antimony (Sb) contained in it is different from that of the first variable resistance layer, and the crystallization speed of the second variable resistance layer is different from that of the first variable resistance layer; and a first electrode, between the first variable resistance layer and the second variable resistance layer. Therefore, the operating characteristics of the system 1200 can be improved.

[0095] In addition, the main memory device 1220 may also include a static random access memory (SRAM) and a dynamic random access memory (DRAM) of a volatile memory type in which all contents are erased when the power is turned off, etc. Different from this, the main memory device 1220 may not include the semiconductor device according to the embodiment, but may include a static random access memory (SRAM) and a dynamic random access memory (DRAM) of a volatile memory type in which all contents are erased when the power is turned off, etc.

[0096] The auxiliary memory device 1230 is a memory device for storing program code or data. Although the auxiliary memory device 1230 is slower than the main memory device 1220, the auxiliary memory device 1230 can store a larger amount of data. The auxiliary memory device 1230 may include one or more of the above-mentioned semiconductor devices according to the embodiment. For example, the auxiliary memory device 1230 may include a semiconductor memory including: a first variable resistance layer containing antimony (Sb); a second variable resistance layer containing antimony (Sb) having a different content from the first variable resistance layer, and a crystallization speed of the second variable resistance layer being different from the crystallization speed of the first variable resistance layer; and a first electrode between the first variable resistance layer and the second variable resistance layer. Therefore, the operating characteristics of the system 1200 can be improved.

[0097] In addition, the auxiliary storage device 1230 may also include a data storage system (see Fig. 9 1300), such as, using a magnetic tape, a magnetic disk, using an optical laser disk, using both magnetic and optical magneto-optical disks, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card. Different from this, the auxiliary storage device 1230 may not include the semiconductor device according to the embodiment, but may include a data storage system (see Fig. 9 1300), such as magnetic tapes, magnetic disks, optical laser disks, magneto-optical disks that utilize both magnetic and optical properties, solid-state disks (SSDs), USB memories (Universal Serial Bus memories), secure digital (SD) cards, mini secure digital (mSD) cards, micro secure digital (micro SD) cards, secure digital high-capacity (SDHC) cards, memory stick cards, smart media (SM) cards, multimedia cards (MMCs), embedded MMCs (eMMCs), and compact flash (CF) cards, etc.

[0098] The interface device 1240 can be used to perform the exchange of commands and data between the system 1200 of this embodiment and external devices. The interface device 1240 can be a keypad, a keyboard, a mouse, a speaker, a microphone, a display, various human-computer interaction devices (HIDs), and communication devices, etc. The communication device may include a module that can be connected to a wired network, a module that can be connected to a wireless network, and may include both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), and various devices such as sending and receiving data through a transmission line. The wireless network module can include infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB), and various devices such as those that can send and receive data without a transmission line.

[0099] Fig. 9 is a configuration diagram of a data storage system implementing a memory device according to an embodiment of the present disclosure.

[0100] refer to Fig. 9 , the data storage system 1300 may include a storage device 1310 having a non-volatile characteristic as a component for storing data, a controller 1320 for controlling the storage device 1310, an interface 1330 for connecting with an external device, and a temporary storage device 1340 for temporarily storing data. The data storage system 1300 may be a disk type such as a hard disk drive (HDD), a compact disk read-only memory (CDROM), a digital versatile disk (DVD), and a solid state disk (SSD), etc., and may be a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card, etc.

[0101] The storage device 1310 may include a nonvolatile memory that stores data semi-permanently. The nonvolatile memory may include ROM (Read Only Memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), etc.

[0102] The controller 1320 may control data exchange between the storage device 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 to perform operations such as processing a command input from the outside of the data storage system 1300 through the interface 1330, and the like.

[0103] Interface 1330 is used to perform the exchange of commands and data between data storage system 1300 and external devices. In the case where data storage system 1300 is a card type, interface 1330 can be compatible with interfaces used in the following devices, such as USB memory (universal serial bus memory), secure digital (SD) card, micro secure digital (mSD) card, micro secure digital (micro SD) card, secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC) and compact flash (CF) card, etc., or can be compatible with interfaces used in devices similar to the above devices. In the case where data storage system 1300 is a disk type, interface 1330 can be compatible with interfaces such as IDE (integrated device electronics), SATA (serial advanced technology attachment), SCSI (small computer system interface), eSATA (external SATA), PCMCIA (personal computer memory card international association) and USB (universal serial bus), etc., or can be compatible with interfaces similar to the above interfaces. Interface 1330 can be compatible with one or more interfaces having different types from each other.

[0104] The temporary storage device 1340 can temporarily store data according to the diversity and high performance of the interface with the external device, the controller and the system to effectively transmit data between the interface 1330 and the storage device 1310. The temporary storage device 1340 for temporarily storing data may include one or more of the above-mentioned semiconductor devices according to the embodiment. For example, the temporary storage device 1340 may include a semiconductor memory including: a first variable resistance layer containing antimony (Sb); a second variable resistance layer containing antimony (Sb) of a different content from the first variable resistance layer, and a crystallization speed of the second variable resistance layer is different from the crystallization speed of the first variable resistance layer; and a first electrode between the first variable resistance layer and the second variable resistance layer. Therefore, the operating characteristics of the temporary storage device 1340 can be improved. Thus, the operating characteristics of the data storage system 1300 can be improved.

[0105] Fig.10 is a configuration diagram of a memory system in which a memory device according to an embodiment of the present disclosure is implemented.

[0106] refer to Fig.10, the storage system 1400 may include: a memory 1410 having a non-volatile characteristic as a component for storing data, a memory controller 1420 for controlling the memory 1410, and an interface 1430 for connecting with an external device, etc. The storage system 1400 may be a card type such as a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital card (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card, etc.

[0107] The memory 1410 for storing data may include one or more of the above-mentioned semiconductor devices according to the embodiment. For example, the memory 1410 may include a semiconductor memory including: a first variable resistance layer containing antimony (Sb); a second variable resistance layer containing antimony (Sb) at a different content from that of the first variable resistance layer, and a crystallization speed of the second variable resistance layer is different from that of the first variable resistance layer; and a first electrode between the first variable resistance layer and the second variable resistance layer. Therefore, the operating characteristics of the memory 1410 can be improved. Thus, the operating characteristics of the storage system 1400 can be improved.

[0108] In addition, the memory 1410 of this embodiment may also include ROM (read-only memory) with non-volatile characteristics, NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM) and magnetic random access memory (MRAM), etc.

[0109] The memory controller 1420 may control data exchange between the memory 1410 and the interface 1430. To this end, the memory controller 1420 may include a processor 1421 for performing an operation of processing a command input through the interface 1430 from the outside of the memory system 1400.

[0110] The interface 1430 is used to perform command and data exchange between the storage system 1400 and an external device. The interface 1430 may be compatible with interfaces used in the following devices, such as USB memory (universal serial bus memory), secure digital (SD) card, mini secure digital (mSD) card, micro secure digital (micro SD) card, secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC) and compact flash (CF) card, etc., or may be compatible with interfaces used in devices similar to the above devices. The interface 1430 may be compatible with one or more interfaces of different types from each other.

[0111] The memory system 1400 of this embodiment may further include a buffer memory 1440 for efficiently transmitting data between the interface 1430 and the memory 1410 according to the diversity and high performance of the interface with the external device, the memory controller, and the memory system. The buffer memory 1440 for temporarily storing data may include one or more of the above-mentioned semiconductor devices according to the embodiment. For example, the buffer memory 1440 may include a semiconductor memory including: a first variable resistance layer containing antimony (Sb); and a second variable resistance layer containing antimony (Sb) having a different content from the first variable resistance layer, and a crystallization speed of the second variable resistance layer being different from the crystallization speed of the first variable resistance layer; and a first electrode, which is between the first variable resistance layer and the second variable resistance layer. Therefore, the operating characteristics of the memory system 1400 can be improved.

[0112] In addition, the buffer memory 1440 of the present embodiment may further include SRAM (static random access memory) and DRAM (dynamic random access memory) with volatility, etc., and phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), etc. with non-volatile characteristics. Different from this, the buffer memory 1440 may not include the semiconductor device according to the embodiment, but may include SRAM (static random access memory) and DRAM (dynamic random access memory) with volatility, etc., and phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), etc. with non-volatile characteristics.

[0113] According to the embodiments of the present disclosure, the operating characteristics and reliability of the electronic device can be improved. For example, the storage unit (e.g., Figure 3The memory cell MC in the embodiment includes a plurality of variable resistance layers (eg, Figure 3 The memory cell MC according to the embodiment of the present disclosure may be programmed with a plurality of variable resistance layers 31, 32, and 33) to store multi-bit data therein. The plurality of variable resistance layers of the memory cell according to the embodiment of the present disclosure have different crystallization speeds or set operation speeds from each other. As a result, the magnitude of the current or voltage used to program the memory cell MC according to the embodiment of the present disclosure may be reduced compared to the magnitude of the current or voltage used to program the conventional memory cell.

[0114] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art at the time of filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. An electronic device comprising a semiconductor memory, wherein: The semiconductor memory comprises: a first variable resistance layer comprising antimony; a second variable resistance layer including antimony at a higher content than that of the first variable resistance layer, wherein a crystallization speed of the second variable resistance layer is different from that of the first variable resistance layer according to the antimony content; and The first electrode is disposed between the first variable resistance layer and the second variable resistance layer.

2. The electronic device according to claim 1, wherein: The first variable resistance layer includes 10 at % to 20 at % of germanium, 20 at % to 25 at % of antimony, and 45 at % to 55 at % of tellurium, and The second variable resistance layer contains 10 at % to 20 at % of germanium, 25 at % to 30 at % of antimony, and 45 at % to 55 at % of tellurium.

3. The electronic device according to claim 2, wherein: A crystallization speed of the second variable resistance layer is higher than a crystallization speed of the first variable resistance layer.

4. The electronic device according to claim 1, wherein: One or both of the first variable resistance layer and the second variable resistance layer contain 0at% to 25at% of doping elements, and the doping elements include one or more of B, C, N, O, Si, Zn, Ga, As, Se, Ag, In and Sn.

5. The electronic device according to claim 1, wherein: The second variable resistance layer is selectively crystallized by applying a first partial set pulse.

6. The electronic device according to claim 5, wherein: The first and second variable resistance layers are crystallized by applying a second partial set pulse, wherein the second partial set pulse is applied for a longer period than the first partial set pulse.

7. The electronic device according to claim 6, wherein: The first portion setting pulse and the second portion setting pulse have different waveforms.

8. The electronic device according to claim 1, further comprising: a third variable resistance layer including antimony in a content different from that of the first variable resistance layer and the second variable resistance layer; and The second electrode is disposed between the second variable resistance layer and the third variable resistance layer.

9. The electronic device according to claim 8, wherein: The first variable resistance layer, the second variable resistance layer, and the third variable resistance layer have different crystallization speeds.

10. The electronic device according to claim 8, wherein: The first variable resistance layer includes 10 at % to 20 at % of germanium, 20 at % to 25 at % of antimony, and 45 at % to 55 at % of tellurium, wherein the second variable resistance layer comprises 10 at % to 20 at % of germanium, 25 at % to 30 at % of antimony, and 45 at % to 55 at % of tellurium, and The third variable resistance layer contains 10 at % to 20 at % of germanium, 30 at % to 35 at % of antimony, and 45 at % to 55 at % of tellurium.

11. The electronic device according to claim 10, wherein: The first variable resistance layer further includes one or more of C, N, O, Si, Ga, As, and Se, and the third variable resistance layer further includes one or more of B, Zn, Ag, In, and Sn.

12. An electronic device comprising a semiconductor memory, wherein: The semiconductor memory comprises: a first variable resistance layer comprising antimony; a second variable resistance layer including an antimony content higher than that of the first variable resistance layer, wherein a crystallization speed of the second variable resistance layer is higher than that of the first variable resistance layer according to the antimony content of the first variable resistance layer and the second variable resistance layer; a third variable resistance layer including an antimony content higher than that of the second variable resistance layer, wherein according to the antimony content of the second variable resistance layer and the third variable resistance layer, a crystallization speed of the third variable resistance layer is higher than a crystallization speed of the second variable resistance layer; A first electrode disposed between the first variable resistance layer and the second variable resistance layer; and The second electrode is disposed between the second variable resistance layer and the third variable resistance layer.

13. The electronic device according to claim 12, wherein: One or more of the first variable resistance layer, the second variable resistance layer, and the third variable resistance layer further includes 0 at % to 25 at % of a doping element.

14. The electronic device according to claim 13, wherein: The doping elements include one or more of B, C, N, O, Si, Zn, Ga, As, Se, Ag, In and Sn.

15. The electronic device according to claim 12, wherein: The first variable resistance layer further includes one or more of C, N, O, Si, Ga, As, and Se, and the third variable resistance layer further includes one or more of B, Zn, Ag, In, and Sn.

16. The electronic device according to claim 12, wherein: The third variable resistance layer is selectively crystallized by applying a first partial set pulse, the second variable resistance layer and the third variable resistance layer are selectively crystallized by applying a second partial set pulse, wherein the second partial set pulse is applied for a longer period of time than the first partial set pulse is applied, and the first variable resistance layer, the second variable resistance layer and the third variable resistance layer are crystallized by applying a full set pulse, wherein the full set pulse is applied for a longer period of time than each of the first partial set pulse and the second partial set pulse is applied.

17. The electronic device according to claim 12, wherein: The first variable resistance layer, the second variable resistance layer, and the third variable resistance layer are reset by applying a reset pulse.

18. An electronic device comprising a semiconductor memory, wherein: The semiconductor memory comprises: a first variable resistance layer; a second variable resistance layer having a different crystallization speed from that of the first variable resistance layer; and a first electrode disposed between the first variable resistance layer and the second variable resistance layer, wherein the content of antimony contained in the second variable resistance layer is higher than the content of antimony contained in the first variable resistance layer, and The first variable resistance layer or the second variable resistance layer or both of them include: a first doping element that reduces the crystallization speed of the variable resistance material according to the antimony content or a second doping element that increases the crystallization speed.

19. The electronic device according to claim 18, wherein: The first variable resistance layer includes the first doping element, and a crystallization speed of the second variable resistance layer is higher than a crystallization speed of the first variable resistance layer.

20. The electronic device according to claim 19, wherein: The first doping element of the first variable resistance layer includes one or more of C, N, O, Si, Ga, As, and Se.

21. The electronic device according to claim 18, wherein: The second variable resistance layer includes the second doping element and has a higher crystallization speed than the first variable resistance layer.

22. The electronic device according to claim 21, wherein: The second doping element of the second variable resistance layer includes one or more of B, Zn, Ag, In, and Sn.

23. A method for operating an electronic device including a semiconductor memory, wherein: The semiconductor memory comprises: a first variable resistance layer comprising antimony; a second variable resistance layer comprising an antimony content higher than that of the first variable resistance layer; and a first electrode disposed between the first variable resistance layer and the second variable resistance layer, the method comprising: The second variable resistance layer is selectively crystallized by applying a first partial set pulse.

24. The method according to claim 23, wherein: The semiconductor memory further includes: a third variable resistance layer including antimony at a higher content than that of each of the first variable resistance layer and the second variable resistance layer; and a second electrode interposed between the second variable resistance layer and the third variable resistance layer, and the method further includes: selectively crystallizing the second variable resistance layer and the third variable resistance layer by applying a second partial set pulse, wherein the second partial set pulse is applied for a longer period than the first partial set pulse; and The first variable resistance layer, the second variable resistance layer, and the third variable resistance layer are crystallized by applying a full set pulse for a period longer than a period during which each of the first partial set pulse and the second partial set pulse is applied. 25 . The method of claim 24 , further comprising resetting the first variable resistance layer, the second variable resistance layer, and the third variable resistance layer by applying a reset pulse.

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