A method and readable storage medium for parallel extraction of instructions

Abstract

The present application relates to the technical field of processor, and particularly relates to a method for parallel extracting instructions and a readable storage medium, generating an extracting instruction effective vector according to an end position vector s_mark_end of the instruction, performing parallel decoding of each position instruction, calculating an instruction address and a branch instruction target address operation through logical AND and logical OR operation, and finally extracting multiple instructions in parallel, the present application generates an extracting instruction effective vector according to an end position vector s_mark_end of the instruction, extracts multiple instructions in parallel through logical AND and logical OR operation, and is a method for extracting multiple instructions in parallel. Multiple instructions can be extracted in parallel, there is no serial dependence relationship between each instruction, timing is easy to converge, and a higher main frequency can be obtained. The present application is particularly suitable for high-performance processors extracting more than 8 instructions per clock cycle.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and more specifically to a method for parallel instruction fetching and a readable storage medium. Background Technology

[0002] Over the past 50 years, microprocessors have undergone tremendous development, with their architecture evolving alongside semiconductor technology. From single-core to physical and logical multi-core; from sequential to out-of-order execution; from single-issue to multi-issue; and especially in the server field, there has been a continuous pursuit of higher processor performance.

[0003] Currently, server chips are mostly based on superscalar out-of-order execution architecture, and processors have increasingly higher processing bandwidth, reaching the point where they can process 8 or even more instructions per clock cycle.

[0004] In the instruction fetch unit, when fetching multiple instructions simultaneously, each instruction is fetched sequentially, resulting in a relatively long logical link. Currently, high-performance processors require fetching 8 or even higher bandwidth instructions per clock cycle, and the clock frequency requirements are quite high. Current implementation methods cannot meet these requirements. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention discloses a method for parallel instruction fetching and a readable storage medium. This method solves the problem of long logical links caused by sequentially fetching each instruction sequentially when multiple instructions are fetched simultaneously in the instruction fetch unit. Currently, high-performance processors require fetching 8 or even higher bandwidth instructions per clock cycle, and the clock frequency requirements are relatively high. Current implementation methods cannot meet these requirements.

[0006] This invention is achieved through the following technical solution:

[0007] In a first aspect, the present invention discloses a method for parallel instruction extraction, characterized in that the method generates an effective instruction extraction vector based on the instruction end position vector s_mark_end, and performs parallel decoding of the instruction at each position, calculates the instruction address and the branch instruction target address through logical AND and logical OR operations, and finally extracts multiple instructions in parallel.

[0008] When writing instructions, the end position vector s_mark_end of each instruction is calculated. Instructions returned from the writer are in units of cache lines, each cache line being 64 bytes. The end position vectors of the instruction are calculated separately for the high and low 32 bytes. The end position vectors s_mark_end_0 and s_mark_end_1 of the high 32-byte instruction are calculated with offsets of 0 and 2, respectively. Based on the end position vector of the low 32-byte instruction, a high 32-byte vector is selected as the final end vector of the high 32-byte instruction. The end position vector of the instruction and the instruction are written simultaneously.

[0009] Furthermore, in the method, the lower 2 bits of the first instruction are first determined. If the lower 2 bits are 00, 01, or 10, then the length of the first instruction is 16 bits. If the lower 2 bits are 11, then the length of the first instruction is 32 bits. Then, starting from the next byte after the end position of the first instruction, the second instruction is determined. The determination process is similar to that of the first instruction to obtain the length of the second instruction. This process is repeated to obtain the length of each instruction in the cacheline. After obtaining the length of each instruction, the end position vector s_mark_end of each instruction in the instruction stream is obtained.

[0010] Furthermore, in the method, when the instruction fetch unit starts fetching instructions, it simultaneously reads the instruction end position vector to verify the BPU's prediction information and extract instructions. The instruction end position vector s_mark_end indicates whether the position is the end of an instruction. A value of 1 indicates that it is the end position of an instruction; a value of 0 indicates that it is not the end position of an instruction.

[0011] Furthermore, in this method, the bandwidth of the instruction fetch unit is 32 bytes per clock cycle. While fetching the instruction, branch instruction jump prediction is performed based on the high 2 bytes of the branch instruction. If a branch instruction is predicted to cause a jump, then the jump proceeds to the target address. After the instruction is fetched from the target address, an instruction alias error check is performed to determine whether the predicted branch instruction is indeed a branch instruction and whether the branch instruction types are consistent.

[0012] Furthermore, the method supports multiple threads, and all threads share the BPU prediction unit. Therefore, the prediction information between threads will interfere with each other, and the results of this interference include:

[0013] The BPU will take the middle part of an instruction, that is, the end of the branch instruction, as the end position of the branch instruction where the jump occurs.

[0014] The branch instruction type does not match. If this BPU information is written by a JA, a JALR instruction will be predicted based on the JAL information.

[0015] Furthermore, in the method, the BPU information includes the BPU's prediction offset pred_offset and instruction type pred_type. The BPU generates a refresh based on the target predicted by the BPU and fetches instructions again. When fetching instructions, it checks whether s_mark_end

[20] is 1. If not, the position predicted by pred_offset is not the end position of a branch instruction, but the middle of an instruction. Then, it generates a refresh from the address of the nearest instruction ending in pred_offset plus 1, and fetches instructions again. At the same time, it clears the erroneous prediction information in the BPU.

[0016] Furthermore, in the method, if pred_offset is the end position of a branch instruction, and during instruction fetching, it is also determined that the position corresponding to s_mark_end is a branch instruction. If the type of the branch instruction is different from the type pred_type predicted by the BPU, then it is an aliasing error. The predicted instruction that will cause the jump is not wrong, but the predicted target address is incorrect. In this case, the instruction is fetched again from the position pred_offset plus 1, and the error information corresponding to the position in the BPU is cleared. Only when the position and type predicted by the BPU are correct is the prediction information of the BPU correct. Otherwise, a refresh is required to fetch the instruction again from the correct address.

[0017] Furthermore, in the method, when each instruction has been extracted from the instruction stream, the BPU's prediction information is used to determine whether there are branch instructions in the instruction and whether a jump has occurred. If there are multiple branch instructions in the instruction, the first instruction has the highest priority, followed by the second instruction, and so on. A refresh is generated based on the target address of the branch instruction, and the instruction fetch unit fetches instructions again based on this new address. If there are no branch instructions, all instructions are written into the instruction queue.

[0018] In a second aspect, the present invention discloses a readable storage medium, including a memory storing execution instructions, wherein when a processor executes the execution instructions stored in the memory, the processor hardware executes the parallel instruction fetching method described in the first aspect.

[0019] The beneficial effects of this invention are as follows:

[0020] This invention generates an effective instruction extraction vector based on the instruction end position vector s_mark_end, and extracts multiple instructions in parallel through logical AND and OR operations. It allows for the simultaneous parallel extraction of multiple instructions without serial dependencies between them, resulting in easier timing convergence and potentially higher clock frequencies. It is particularly suitable for high-performance processors that extract more than 8 instructions per clock cycle. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the RISC V instruction mode of the present invention;

[0023] Figure 2 This is a top-level diagram of the instruction fetching unit in an embodiment of the present invention;

[0024] Figure 3 This is an instruction boundary identification diagram according to an embodiment of the present invention;

[0025] Figure 4 This is a vector diagram showing the end-of-instruction position in an embodiment of the present invention;

[0026] Figure 5 This is a diagram showing the jump caused by cross-boundary instructions in an embodiment of the present invention;

[0027] Figure 6 This is an alias error checking diagram of an embodiment of the present invention;

[0028] Figure 7 This is a diagram of parallel extraction instructions according to an embodiment of the present invention;

[0029] Figure 8 This is the logic diagram for generating the second instruction in this embodiment of the invention;

[0030] Figure 9 This is a diagram showing the calculation of instruction addresses and branch target addresses in an embodiment of the present invention;

[0031] Figure 10 This is a cross-boundary instruction diagram according to an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Example 1

[0034] This embodiment is a method for generating an extractable instruction valid vector based on the instruction end position vector s_mark_end, and extracting multiple instructions in parallel through logical AND and OR operations.

[0035] This embodiment is not limited to CPU, GPU, DSP, or other chips; nor is it limited to any instruction set or implementation process.

[0036] To facilitate the explanation of the principle of this method, the RISC-V instruction set will be used as an example.

[0037] The RISC V instruction set supports instruction lengths of 16-bit, 32-bit, 48-bit, and 64-bit, such as... Figure 1 As shown. This article mainly uses 16-bit and 32-bit instructions as examples to describe the method proposed in this paper. To facilitate the explanation of the principle of this method, it is assumed that the instruction fetching bandwidth is 32 bytes each time, and 8 instructions are fetched each time.

[0038] The lowest 2 bits of a 16-bit instruction are 00, 01, or 10. The lowest 2 bits of a 32-bit instruction are 11. Therefore, to determine the length of the current instruction, only the lowest 2 bits need to be checked. First, check the lowest 2 bits of the first instruction. If the lowest 2 bits are 00, 01, or 10, then the length of the first instruction is 16 bits. If the lowest 2 bits are 11, then the length of the first instruction is 32 bits. Then, starting from the byte after the end of the first instruction, check the second instruction. The process is similar to that of the first instruction to obtain the length of the second instruction. Continue in this manner to obtain the length of each instruction in the cacheline, such as... Figure 2 As shown. After obtaining the length of each instruction, the end position vector s_mark_end of each instruction in the instruction stream is obtained.

[0039] When instructions are written from L2 to L1, the end-of-line vector s_mark_end for each instruction is calculated. Instructions returned from L2 are in cache lines, such as... Figure 3As shown, each cacheline is 64 bytes. The high and low 32 bytes of an instruction are used to calculate the instruction's end-of-instruction vector. The high 32-byte instruction is used to predict two possible end-of-instruction vectors, s_mark_end_0 and s_mark_end_1, with offsets of 0 and 2 respectively. Based on the low 32-byte instruction's end-of-instruction vector, one high 32-byte vector is selected as the final instruction end-of-instruction vector for the high 32-byte instruction, as shown below. Figure 3 As shown, the instruction's end-position vector and the instruction itself are written to L1 simultaneously.

[0040] Example 2

[0041] This embodiment is not limited to CPU, GPU, DSP, or other chips; nor is it limited to any instruction set or implementation process. It primarily uses the RISC-V instruction set as an example. When the instruction fetch unit begins fetching instructions, while reading the instructions from the L1 cache, the instruction end-of-position vector is simultaneously read out to verify the BPU's prediction information and fetch the instructions.

[0042] The instruction end position vector s_mark_end indicates whether the position is the end of an instruction. A value of 1 indicates the end of an instruction; a value of 0 indicates that it is not the end of an instruction, meaning it could be the opcode of an instruction or an immediate value within the instruction.

[0043] exist Figure 4 The first instruction LUI is 4 bytes long, and s_mark_end

[28] is 1; the second instruction is C.ADDI, which is a 16-bit compressed instruction, and s_mark_end

[26] is 1; the third instruction AUIPC is 4 bytes long, and s_mark_end

[22] is 1; the fourth instruction JAL is 4 bytes long, and s_mark_end

[18] is 1; the fifth instruction LB is 4 bytes long, and s_mark_end

[14] is 1; the sixth instruction LH is 4 bytes long, and s_mark_end

[10] is 1; the seventh instruction ADDI is 4 bytes long, and s_mark_end[6] is 1; the eighth instruction SRAI is 4 bytes long, and s_mark_end[2] is 1; the ninth instruction BNE is 4 bytes long. This instruction spans 32 bytes, so the end position of instruction BNE is not in the current instruction block, such as Figure 4 As shown.

[0044] The instruction fetch unit has a bandwidth of 32 bytes per clock cycle. Because it supports mixed 16-bit / 32-bit instructions, a branch instruction can potentially span two adjacent instruction blocks. The lower two bytes of a branch instruction end at the end of a 32-byte instruction block (block 0), while the higher two bytes begin at the beginning of the adjacent instruction block (block 1), as shown below. Figure 5 As shown.

[0045] While fetching instructions, branch instruction jump prediction is performed. Prediction is based on the high 2 bytes of the branch instruction; if a jump is predicted, the jump proceeds to the target address. After fetching the instruction from the target address, instruction alias error checking is performed to determine if the predicted branch instruction is indeed a branch instruction and if its type is consistent with the target instruction.

[0046] Because multiple threads are supported and all threads share the BPU prediction unit, the prediction information between threads can interfere with each other.

[0047] The consequences of interference include: 1. The BPU may take the middle part of an instruction, that is, not the end of a branch instruction, as the end position of the branch instruction where the jump occurs.

[0048] 2. The branch instruction type does not match. If this BPU information is written by a JA, a JALR instruction will be predicted based on the JAL information.

[0049] BPU prediction information includes the BPU prediction offset `pred_offset` and the instruction type `pred_type`, such as... Figure 6 As shown, pred_offset is 5'd11, which means that the position in the BPU prediction graph is the end position of a branch instruction, and a jump occurs.

[0050] The BPU refreshes the instruction based on the target predicted by the BPU and fetches instructions again. When fetching instructions, it checks whether s_mark_end

[20] is 1. It was found that s_mark_end

[20] was 0, that is, the position predicted by pred_offset is not the end position of a branch instruction, but the middle of an instruction.

[0051] At this point, a refresh needs to be performed at the address 1 above the end of the most recent instruction in `pred_offset`, and the instruction needs to be fetched again. Simultaneously, the erroneous prediction information in the BPU needs to be cleared. Similarly, if `pred_offset` is the end of a branch instruction, and during instruction fetching, it's also determined that the position corresponding to `s_mark_end` is a branch instruction. If the type of the branch instruction is different from the type `pred_type` predicted by the BPU, then this is an aliasing error.

[0052] The predicted instruction that caused the jump is correct, but the predicted target address is incorrect. The instruction needs to be fetched again from the address specified by `pred_offset + 1`, and the error message at that address in the BPU needs to be cleared. The BPU's prediction information is only correct if both the predicted location and type are correct; otherwise, a refresh is required to fetch the instruction again from the correct address.

[0053] This embodiment generates eight valid instruction vectors in parallel based on the instruction end vector. Simultaneously, 32-byte instructions are deduced in parallel, and instruction addresses and target addresses are calculated. Then, the eight valid instruction vectors are subjected to AND and OR logical operations with the deduced instructions, calculated instruction addresses, and calculated target addresses to obtain the extracted instructions and related attributes, such as... Figure 7 As shown.

[0054] Example 3

[0055] This embodiment uses the generation logic of the valid vector of the second instruction as an example. `s_prt` represents the offset of the first instruction in the 32-byte instruction stream. `s_mark_end` represents the instruction end position vector in the 32-byte instruction stream; each bit of `s_mark_end` being 1 indicates the end position of an instruction. `Inst_2_val` represents the valid vector of the second instruction in the 32-byte instruction stream; a position of 1 indicates the starting byte of the second instruction. Taking 4 bytes from this position yields a complete instruction (if it is a 16-bit compressed instruction, it has already been decoded into a 32-bit instruction). The valid vector of the second instruction, `inst_2_val`, is first ANDed with the 16 instructions obtained from the speculative decoding, and then ORed to obtain the second instruction.

[0056] S_ptr and s_mark_end together form a 35-bit instruction location identifier vector, which is mapped to another one-hot vector inst_2_val. The logical mapping relationship for generating the valid vector of the second instruction is shown in the table below:

[0057] Table 1, Item 2: Valid Vector Mapping

[0058]

[0059]

[0060]

[0061] Similarly, the effective vectors for the remaining instructions can be obtained.

[0062] The instruction fetch unit decodes 32 bytes at a time. The RISC-V instruction length is 2 or 4 bytes. Therefore, the opcode of the instruction starts at even positions 0, 2, 4, ... 30. Similarly, the instruction ends at odd positions 1, 3, 5, ... 31.

[0063] If the instruction starts from position 0, then the effective vector inst_2_val[0] of the instruction is 1; at the same time, the instruction inst0 obtained by speculative decoding is taken, and its length is 4 bytes. When the instruction is a C extended instruction, it has been decoded into an instruction with a length of 4 bytes during speculative decoding.

[0064] If the instruction starts from position 2, then the effective vector of the instruction, inst_2_val[2], is 1; at the same time, the instruction inst1 obtained by speculative decoding is taken.

[0065] If the instruction starts from position 4, then the effective vector of the instruction, inst_2_val[4], is 1; at the same time, the instruction inst2 obtained by speculative decoding is taken.

[0066] If the instruction starts from position 6, then the effective vector inst_2_val[6] of the instruction is 1; at the same time, the instruction inst3 obtained by speculative decoding is taken.

[0067] If the instruction starts from position 8, then the effective vector of the instruction, inst_2_val[8], is 1; at the same time, the instruction inst4 obtained by speculative decoding is taken.

[0068] If the instruction starts from position 10, then the effective vector of the instruction, inst_2_val

[10] , is 1; at the same time, the instruction inst5 obtained by speculative decoding is taken.

[0069] If the instruction starts from position 12, then the effective vector of the instruction, inst_2_val

[12] , is 1; at the same time, the instruction inst6 obtained by speculative decoding is taken.

[0070] If the instruction starts from position 14, then the effective vector of the instruction, inst_2_val

[14] , is 1; at the same time, the instruction inst7 obtained by speculative decoding is taken.

[0071] If the instruction starts from position 16, then the effective vector of the instruction, inst_2_val

[16] , is 1; at the same time, the instruction inst8 obtained by speculative decoding is taken.

[0072] If the instruction starts from position 18, then the effective vector of the instruction, inst_2_val

[18] , is 1; at the same time, the instruction inst9 obtained by speculative decoding is taken.

[0073] If the instruction starts from position 20, then the effective vector of the instruction, inst_2_val

[20] , is 1; at the same time, the instruction inst10 obtained by speculative decoding is taken.

[0074] If the instruction starts from position 22, then the effective vector of the instruction, inst_2_val

[22] , is 1; at the same time, the instruction inst11 obtained by speculative decoding is taken.

[0075] If the instruction starts from position 24, then the effective vector of the instruction, inst_2_val

[24] , is 1; at the same time, the instruction inst12 obtained by speculative decoding is taken.

[0076] If the instruction starts from position 26, then the effective vector of the instruction, inst_2_val

[26] , is 1; at the same time, the instruction inst13 obtained by speculative decoding is taken.

[0077] If the instruction starts from position 28, then the effective vector of the instruction, inst_2_val

[28] , is 1; at the same time, the instruction inst14 obtained by speculative decoding is taken.

[0078] If the instruction starts from position 30, and the current instruction does not cross the boundary, then the effective vector inst_2_val

[30] of the instruction is 1; at the same time, the instruction inst15 obtained by speculative decoding is taken.

[0079] If the current instruction crosses a boundary, then the current instruction is invalid and will not be fetched until the next 32-byte instruction stream becomes valid.

[0080] If the offset of the first instruction is not 0, but starts from a non-zero offset, then the starting position of the first instruction is at that offset. The positions of other instructions then begin at the same offset.

[0081] The logical expression for obtaining the second instruction is:

[0082] Inst_2=({32{inst_2_val[0]}}&inst0)|

[0083] ({32{inst_2_val[2]}}&inst1)|

[0084] ({32{inst_2_val[4]}}&inst2)|

[0085] ({32{inst_2_val[6]}}&inst3)|

[0086] ({32{inst_2_val[8]}}&inst4)|

[0087] ({32{inst_2_val

[10] }}&inst5)|

[0088] ({32{inst_2_val

[12] }}&inst6)|

[0089] ({32{inst_2_val

[14] }}&inst7)|

[0090] ({32{inst_2_val

[16] }}&inst8)|

[0091] ({32{inst_2_val

[18] }}&inst9)|

[0092] ({32{inst_2_val

[20] }}&inst10)|

[0093] ({32{inst_2_val

[22] }}&inst11)|

[0094] ({32{inst_2_val

[24] }}&inst12)|

[0095] ({32{inst_2_val

[26] }}&inst13)|

[0096] ({32{inst_2_val

[28] }}&inst14)|

[0097] ({32{inst_2_val

[30] }}&inst15));

[0098] Inst0, inst1, ..., inst15 are 16 speculatively generated instructions. The circuit implemented by the second instruction is implemented using logical AND and OR gates, such as... Figure 8 As shown. Other instructions, based on the same principle, can yield logical expressions and logic circuit diagrams.

[0099] Example 4

[0100] In this embodiment, the calculation of the instruction address and target address is also speculative. The instruction fetch unit fetches 32 bytes at a time, and the fetch address is fetch_address, which is the base address for calculating the instruction address. Since the length of a RISC V instruction is 2 or 4 bytes, the speculative calculation of the instruction addresses at the 16 locations is as follows: base_address, base_address+2, base_address+4, base_address+8, base_address+10, base_address+12, base_address+14, base_address+16, base_address+18, base_address+20, base_address+22, base_address+24, base_address+28, and base_address+30. The address of the second instruction, inst_2_addr, is also obtained using a similar logic to that used to generate the second instruction, as shown below:

[0101] Inst_2_addr=({64{inst_2_val[0]}}&base_address)|

[0102] ({64{inst_2_val[2]}}&(base_address+2))|

[0103] ({64{inst_2_val[4]}}&(base_address+4))|

[0104] ({64{inst_2_val[6]}}&(base_address+6))|

[0105] ({64{inst_2_val[8]}}&(base_address+8))|

[0106] ({64{inst_2_val

[10] }}&(base_address+10))|

[0107] ({64{inst_2_val

[12] }}&(base_address+12))|

[0108] ({64{inst_2_val

[14] }}&(base_address+14))|

[0109] ({64{inst_2_val

[16] }}&(base_address+16))|

[0110] ({64{inst_2_val

[18] }}&(base_address+18))|

[0111] ({64{inst_2_val

[20] }}&(base_address+20))|

[0112] ({64{inst_2_val

[22] }}&(base_address+22))|

[0113] ({64{inst_2_val

[24] }}&(base_address+24))|

[0114] ({64{inst_2_val

[26] }}&(base_address+26))|

[0115] ({64{inst_2_val

[28] }}&(base_address+28))|

[0116] ({64{inst_2_val

[30] }}&(base_address+30)));

[0117] The instructions fetched from the instruction fetch unit include branch instructions such as JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, C.JAL, CJ, C.BEQZ, C.BNEZ, C.JR, and C.JALR. The destination addresses of instructions JAL, BEQ, BNE, BLT, BGE, BLTU, BGEU, C.JAL, CJ, C.BEQZ, and C.BNEZ are the instruction address plus an offset. Similarly, assuming a branch instruction occurs every 2 bytes, it is inferred that the target address of each instruction is calculated in parallel. The target addresses for the 16 locations are presumably calculated as follows: base_address+offset, base_address+2+offset, base_address+4+offset, base_address+8+offset, base_address+10+offset, base_address+12+offset, base_address+14+offset, base_address+16+offset, base_address+18+offset, base_address+20+offset, base_address+22+offset, base_address+24+offset, base_address+28+offset, and base_address+30+offset. Offset represents the branch instruction offset. Inst represents the instruction.

[0118] The immediate conditional value cond_imm for a 32-bit instruction is: cond_imm: {inst

[31] ,inst[7],inst[30:25],inst[11:8],1'b0};

[0119] The unconditional immediate value of a 32-bit instruction is: uncond_imm: {inst

[31] ,inst[19:12],inst

[20] ,inst[30:21],1'b0};

[0120] The immediate conditional instruction cond_imm_c for the 16-bit compressed instruction is: cond_imm_c: {inst

[12] ,inst[6:5],inst[2],inst[11:10],inst[4:3],1'b0};

[0121] The unconditional immediate value of the 16-bit compressed instruction uncond_imm_c is: uncond_imm_c: {inst

[12] ,inst[8],inst[10:9],inst[6],inst[7],inst[2],inst

[11] ,inst[5:3],1'b0};

[0122] Each location could potentially contain one of these four branch instructions. Therefore, for each location, the instruction type is first determined, and then the offset for each type is calculated. The target address of the second instruction, Inst_2_target_addr, can also be obtained using a similar logical expression to Inst_2_addr, such as... Figure 9 As shown.

[0123] Example 5

[0124] In this embodiment, the specific branch instruction type br_type for each position is determined. br_type[0] is a conditional instruction for a 32-bit instruction; br_type[1] is an unconditional instruction for a 32-bit instruction; br_type[2] is a conditional instruction for a 16-bit instruction; and br_type[3] is an unconditional instruction for a 16-bit instruction. Therefore, the offset of the branch instruction is obtained based on br_type and cond_imm, uncond_imm, cond_imm_c, and uncond_imm_c.

[0125] Because both 16-bit and 32-bit instructions are supported, the instruction stream contains mixed 16-bit and 32-bit instructions. Each 32-byte instruction consists of 8-16 instructions; therefore, a single 32-bit instruction may span consecutive 32-byte instruction streams. In the instruction fetch module, a 2-byte register stores the high 2 bytes of the 32-byte instruction stream, which serve as the 2 bytes for cross-boundary instructions.

[0126] Simultaneously, it checks whether a cross-boundary instruction has occurred in the current 32-byte instruction stream. If so, a cross-boundary instruction validity indicator signal needs to be generated. When an adjacent 32-byte instruction block reaches the instruction fetch pipeline stage, if the cross-boundary instruction validity indicator signal is 1, it indicates that the first instruction has a cross-boundary condition. At this time, the first instruction consists of two parts, such as... Figure 10 As shown.

[0127] If the cross-boundary instruction validity indicator signal is 0, it means that the first instruction does not cross a boundary. The first instruction is the first instruction in the current 32-byte instruction block. Other instructions are retrieved sequentially from the subsequent instruction stream of the first instruction. When an instruction is a branch instruction that crosses a boundary, the instruction's BPU prediction information also needs to be saved until the adjacent instruction stream is valid, at which point the prediction information of the first instruction is obtained, similar to the processing method used to obtain the first instruction.

[0128] Once each instruction has been fetched from the instruction stream, the BPU's prediction information is used to determine if there are branch instructions among the eight instructions and whether a jump should occur. If multiple branch instructions exist, the first instruction has the highest priority, followed by the second, and so on. A refresh is generated based on the target address of the branch instruction, and the instruction fetch unit fetches instructions again using this new address. If no branch instructions exist, all instructions are written to the instruction queue.

[0129] Example 6

[0130] This embodiment discloses a readable storage medium, including a memory storing execution instructions. When a processor executes the execution instructions stored in the memory, the processor hardware executes a method for parallel instruction fetching.

[0131] In summary, this invention generates an effective instruction extraction vector based on the instruction end position vector s_mark_end, and extracts multiple instructions in parallel through logical AND and OR operations. It allows for the simultaneous parallel extraction of multiple instructions, with no serial dependencies between them, resulting in easier timing convergence and potentially higher clock frequencies. It is particularly suitable for high-performance processors that extract more than 8 instructions per clock cycle.

[0132] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for parallel instruction extraction, characterized in that, The method generates an effective instruction extraction vector based on the instruction end position vector s_mark_end, and performs parallel decoding of instructions at each position, calculates instruction addresses and branch instruction target addresses through logical AND and OR operations, and finally extracts multiple instructions in parallel. When writing instructions, the end position vector s_mark_end of each instruction is calculated. Instructions returned from the writer are in units of cache lines, each cache line being 64 bytes. The end position vectors of the instruction are calculated separately for the high and low 32 bytes. The end position vectors s_mark_end_0 and s_mark_end_1 of the high 32-byte instruction are calculated with offsets of 0 and 2, respectively. Based on the end position vector of the low 32-byte instruction, a high 32-byte vector is selected as the final end vector of the high 32-byte instruction. The end position vector of the instruction and the instruction are written simultaneously.

2. The method for parallel instruction extraction according to claim 1, characterized in that, In the method described above, the lower 2 bits of the first instruction are first determined. If the lower 2 bits are 00, 01, or 10, then the length of the first instruction is 16 bits. If the lower 2 bits are 11, then the length of the first instruction is 32 bits. Then, starting from the next byte after the end position of the first instruction, the length of the second instruction is determined. The determination process is similar to that of the first instruction. This process is repeated to obtain the length of each instruction in the cacheline. After obtaining the length of each instruction, the end position vector s_mark_end of each instruction in the instruction stream is obtained.

3. The method for parallel instruction extraction according to claim 1, characterized in that, In the method, when the instruction fetch unit starts fetching instructions, it reads the instruction end position vector at the same time to verify the BPU's prediction information and extract instructions. The instruction end position vector s_mark_end indicates whether the position is the end of an instruction. When it is 1, it means that it is the end position of an instruction; when it is 0, it means that it is not the end position of an instruction.

4. The method for parallel instruction extraction according to claim 3, characterized in that, In the method, the bandwidth of the instruction fetch unit is 32 bytes per clock cycle. While fetching instructions, branch instruction jump prediction is performed. The prediction is based on the high 2 bytes of the branch instruction. If the predicted branch instruction jump occurs, then the jump is performed to the target address. After retrieving the instruction from the target address, an instruction alias error check is required, that is, to determine whether the predicted jump branch instruction is a branch instruction and whether the branch instruction type is consistent.

5. The method for parallel instruction extraction according to claim 1, characterized in that, The method supports multiple threads, and all threads share the BPU prediction unit. Therefore, the prediction information between threads will interfere with each other, and the results of this interference include: The BPU will take the middle part of an instruction, that is, the end of the branch instruction, as the end position of the branch instruction where the jump occurs. The branch instruction type does not match. If this BPU information is written by a JA, a JALR instruction will be predicted based on the JAL information.

6. The method for parallel instruction extraction according to claim 5, characterized in that, In the method, the BPU information includes the BPU's prediction offset pred_offset and instruction type pred_type. The BPU generates a refresh based on the target predicted by the BPU and fetches instructions again. When fetching instructions, it checks whether s_mark_end[20] is 1. If not, the position predicted by pred_offset is not the end position of a branch instruction, but the middle of an instruction. Then, it generates a refresh from the address of the nearest instruction end in pred_offset plus 1 and fetches instructions again. At the same time, it clears the incorrect prediction information in the BPU.

7. The method for parallel instruction extraction according to claim 6, characterized in that, In the method described above, if pred_offset is the end position of a branch instruction, and during instruction fetching, it is also determined that the position corresponding to s_mark_end is a branch instruction. If the type of the branch instruction is different from the type pred_type predicted by the BPU, then it is an aliasing error. The predicted instruction that will cause the jump is not wrong, but the predicted target address is incorrect. In this case, the instruction is fetched again from the position pred_offset plus 1, and the error information corresponding to the position in the BPU is cleared. Only when the position and type predicted by the BPU are correct is the prediction information of the BPU correct. Otherwise, a refresh is required to fetch the instruction again from the correct address.

8. The method for parallel instruction extraction according to claim 1, characterized in that, In the method, when each instruction has been extracted from the instruction stream, the BPU's prediction information is used to determine whether there is a branch instruction and whether a jump has occurred. If there are multiple branch instructions in the instruction, the first instruction has the highest priority, followed by the second instruction, and so on. The target address is refreshed according to the branch instruction, and the instruction fetch unit fetches instructions again according to this new address. If there are no branch instructions, all instructions are written to the instruction queue.

9. A readable storage medium comprising a memory storing executable instructions, wherein when a processor executes the executable instructions stored in the memory, the processor hardware performs the parallel instruction fetching method as described in any one of claims 1-8.

Images