Apparatus and method for semiconductor layout

Abstract

The present application relates to apparatus and methods for semiconductor layout. Embodiments of the present invention relate to apparatus and methods for trench walls including widened portions and / or conductive structures including constricted portions. In some examples, the trench walls may include multiple widened portions spaced along the length of the trench walls. Similarly, in some examples, the conductive structures may include multiple constricted portions spaced along the length of the conductive structures. In some examples, the size of the widened portions and / or the spacing between the widened portions may be based on the properties of the trench walls.

Description

Technical Field

[0001] The present invention relates generally to conductive structures (eg, wires, wiring layers), and more particularly to conductive structures in semiconductor devices. Background Art

[0002] For example, the conductive structure may be used in a memory device, including volatile memory, such as a dynamic random access memory (DRAM). The DRAM may be included in a high bandwidth memory (HBM). The HBM may include a die (e.g., chip) stack having one or more core dies and one or more interface (IF) dies. Each core die may include one or more memory arrays consisting of one or more memory cells. The memory cells and / or other structures in the core die and / or IF die may be coupled to each other by one or more conductive structures. For example, the conductive structure may couple one or more memory cells to a voltage source. Summary of the invention

[0003] In one aspect, the present application relates to an apparatus comprising: a groove wall extending a first length in a first dimension and having a first width in a second dimension, wherein the groove wall includes a first widened portion, wherein the first widened portion: extends a second length in the first dimension, wherein the second length is less than the first length; and has a second width in the second dimension, wherein the second width is greater than the first width.

[0004] On the other hand, the present application relates to a device comprising: a conductive structure extending a first length in a first dimension and having a first width in a second dimension, wherein the conductive structure includes a first contraction portion, wherein the first contraction portion: extends a second length in the first dimension, wherein the second length is less than the first length; and has a second width in the second dimension, wherein the second width is less than the first width.

[0005] On the other hand, the present application relates to a method comprising: etching a plurality of trenches in a dielectric material to form a plurality of trench walls extending in a first dimension between individual ones of the plurality of trenches, wherein the plurality of trench walls have a first width in a second dimension equal to the spacing between the plurality of trenches, wherein at least one of the plurality of trench walls comprises: a first length in the first dimension; and a widened portion, wherein the widened portion extends a second length in the first dimension and has a second width in the second dimension, wherein the second length is less than the first length and the second width is greater than the first width. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1is a description of a portion of a damascene process that may be used to fabricate a semiconductor device according to an embodiment of the present invention.

[0007] Figure 2 is a schematic diagram of a semiconductor system including a semiconductor device including an interface chip and a plurality of core chips according to an embodiment of the present invention.

[0008] Figure 3 is a description of a semiconductor device according to an embodiment of the present invention.

[0009] Figure 4 yes Figure 3 An enlarged view of a portion of a semiconductor device shown in FIG.

[0010] Figure 5 is a flow chart of a method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0011] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the invention or its application or use. In the following detailed description of the embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof and show in an illustrative manner the specific embodiments of the described system and method that can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present invention. In addition, for the purpose of clarity, the detailed description of certain features will no longer be discussed when it will be obvious to those skilled in the art so as not to obscure the description of the embodiments of the present invention. Therefore, the following detailed description should not be understood in a limiting sense, and the scope of the present invention is defined only by the appended claims.

[0012] Conductive structures can be used in a variety of semiconductor devices, such as controllers and memories. Some conductive structures can be used to couple two or more components. For example, an operational amplifier can be coupled to a power supply via a conductive structure (e.g., a wire). In order to couple components, in some applications, a conductive structure can extend a certain distance across the device. Typically, a device includes a large number of conductive structures extending various distances across the device. The conductive structures can be placed closely together in a device to save space. However, as the spacing between the conductive structures decreases, the risk of the conductive structures accidentally contacting each other and causing a short circuit increases. The longer length of the conductive structure can also increase the risk of a short circuit.

[0013] Figure 11 is an illustration of a portion of a damascene process that may be used to fabricate a semiconductor device according to an embodiment of the present invention. In a first step 100, trenches 102 are disposed in a dielectric material (e.g., oxide). The dielectric material forms trench walls 104 between the trenches 102. In a second step 110, a conductive material is deposited in the trenches 102 to form conductive structures 106. In some examples, the conductive material may be a metallic material such as copper or tungsten, or an alloy of multiple metallic materials.

[0014] As shown in step 100, when the trenches 102 are empty, the trench walls 104 are not supported. In some cases, when adjacent trenches 102 extend longer distances and / or the trenches 102 are closely spaced (e.g., the trench walls 104 are narrow), the trench walls 104 may be at risk of collapsing. If the trench walls 104 collapse, when the metal material is deposited in step 110, the conductive structures 106 intended to be formed in different trenches 102 may overlap, thereby creating a short circuit in the circuit including one or more of the conductive structures 106.

[0015] In some devices, the spacing between trenches 102 may increase as the conductive structures 106 extend longer distances. That is, the trench walls 104 may be wider. While this may reduce the risk of trench wall 104 collapse, it may also reduce the number of conductive structures 106 that may be included in the device. This may reduce the number of components that may be included in the device and / or require an increase in the size of the device.

[0016] The present invention describes a layout of trench walls and conductive structures that can reduce the risk of trench wall collapse. Reducing the risk of trench wall collapse can allow longer conductive structures to be formed and / or allow conductive structures to be spaced more closely together.

[0017] Figure 2 2 is a schematic diagram of a semiconductor system including a semiconductor device including an interface chip and a plurality of core chips according to an embodiment of the present invention. For example, the semiconductor system 201 may include: a semiconductor device 200, which may be a three-dimensional (3D) memory device; and a central processing unit (CPU) and a memory controller 271, which may be a controller chip, on an interposer 272 on a package substrate 273. The interposer 272 may include one or more power lines 275 that supply a power supply voltage from the package substrate 273. The interposer 272 includes a plurality of channels 279 that may interconnect the CPU and memory controller 271 with the semiconductor device 200.

[0018] In some embodiments, semiconductor device 200 may be a high bandwidth memory (HBM). Semiconductor device 200 may include a plurality of chips (e.g., bare die) 220 including an interface (IF) chip 203 and a core chip 204 stacked on each other. In this example, each core chip 204 may be a memory chip. Each of core chips 204 may include a plurality of memory cells that may be arranged into a memory array. Core chip 204 may further include a circuit for accessing memory cells. In some examples, the memory cells may be DRAM memory cells. IF chip 203 may include a circuit for accessing memory cells on core chip 204 for memory operations. For example, IF chip 203 may include a command / address input circuit for receiving commands and addresses from memory controller 271. In some examples, IF chip 203 may include an internal clock generator for providing clock signals to core chips 204 and 230 and / or other components of IF chip 203. In some examples, IF chip 203 may include an internal voltage generator that may receive power from power line 275 and provide various voltages (e.g., VSS, VDD) to core chip 204 and / or other components of IF chip 203. In some examples, various components of core chip 204 and / or IF chip 203 may include and / or be coupled by one or more conductive structures in accordance with the principles of the present invention.

[0019] The semiconductor device 200 may include conductive vias TSV 225 (e.g., through substrate electrodes) that couple the IF chip 203 and the core chip 204 by penetrating the IF chip 203 and the core chip 204. The IF chip 203 may be coupled to the interposer 272 via interconnects such as bumps 274. For example, the bumps 274 may be micro bumps having a bump pitch of less than about or less than one hundred microns and exposed to the outside of the IF chip 203. A portion of the bumps 274 may be coupled to one or more power lines 275. Another portion of the bumps 274 may be coupled to a plurality of channels 279.

[0020] Although the examples provided herein relate to HBM, the principles of the present invention are not limited to this application. That is, the conductive structures, trenches and / or trench wall layouts described herein may be disposed in other memory types (e.g., DDR, LPDDR) and / or other semiconductor devices (e.g., memory controller, CPU).

[0021] Figure 33 is an illustration of a semiconductor device 300 according to an embodiment of the present invention. In some embodiments, the semiconductor device 300 may be included in the semiconductor device 200. The semiconductor device 300 may include trench walls 304 and a conductive structure 306 disposed between the trench walls 304 in the trench 302. In some embodiments, the trench walls 304 may be formed of a dielectric material such as an oxide, and the conductive structure 306 may be formed of a conductive material such as a metallic material (e.g., copper, tungsten, alloy). In some embodiments, the conductive structure 306 may be included in a wiring layer / metallization layer (e.g., a second metallization layer).

[0022] The trench walls 304 and the conductive structures 306 may extend a certain length along the Y dimension and be spaced apart from each other in the X dimension, as indicated in the coordinate system 301. The trench walls 304 may be spaced apart such that the trench 302 (at Figure 3 306) is disposed between the trench walls 304. The trench walls 304 and the conductive structures 306 may have a length / distance in the Y dimension and a width / thickness in the X dimension. It should be noted that Figure 3 Not drawn to scale as the sizes of some features have been exaggerated to illustrate examples of the present invention. The X and Y dimensions may be vertical and may be oriented in any manner.

[0023] like Figure 3 , the trench wall 304 may include one or more "regular" portions 316. In some embodiments, the regular portions 316 of the trench wall 304 may correspond to "regular" portions 318 of the conductive structure 306. A regular portion means that the portion has a width that is consistent for most of the length of the trench wall 304 and / or the conductive structure 306. In some embodiments, the trench wall 304 may include one or more widened portions 308. Figure 3 In the example shown in FIG. 1 , the widened portion 308 is placed at the end of the regular portion 316 and / or between the regular portions 316. In some embodiments, the widened portion 308 of the trench wall 304 may correspond to the constricted portion 310 of the conductive structure 306. In some embodiments, for example Figure 3 , the trench wall 304 and the conductive structure 306 may include a plurality of widened portions 308 and / or contracted portions 310. In some embodiments, the widened portions 308 and / or contracted portions 310 may be spaced at regular intervals along the trench wall 304 and / or the conductive structure 306. In some embodiments, the widened portions 308 of the trench wall 304 may reduce the risk of the trench wall 304 collapsing, which in some embodiments may allow the conductive structures 306 to be spaced closer together and / or extend a greater distance in the semiconductor device 300.

[0024] In some embodiments, the distance 312 between the widened portions 308 and / or the constricted portions 310 (e.g., the length of the regular portions 316 and / or 318) may be based at least in part on a maximum distance defined by one or more design parameters. For example, in some embodiments, the width of the regular portion 316 and / or the height of the groove wall 304 may at least in part determine how long the groove wall 304 can extend before the risk of collapse becomes too great for manufacturing tolerances. For example, in some embodiments, the distance 312 between two widened portions 308 may be based at least in part on the width of the regular portion 316. Other design parameters may also be used, such as the properties of the (several) materials included in the groove wall 304 (e.g., stiffness). In other embodiments, the distance 312 may be less than the maximum distance defined by one or more design parameters. Although increasing the number of widened portions 308 and / or constricted portions 310 may reduce the risk of groove wall 304 collapse, the increase in constricted portions 310 may result in an increase in resistance in the conductive structure 306. The increase in resistance may be undesirable in some applications. However, in other applications, increasing the number of constrictions 310 by decreasing distance 312 may be used to tune the resistance of conductive structure 306 to a desired value.

[0025] Despite Figure 3 In the example shown in , all widening portions 308 and contraction portions 310 are aligned along line 314 in the X dimension, but in other examples, some widening portions 308 and / or contraction portions 310 may be located at different positions along the Y dimension. For example, different placement of widening portions 308 and / or contraction portions 310 may be desirable when the conductive structure 306 has different starting points and / or end points within the device 300. In another example, some groove walls 304 may have different widths, which may allow or require different spacing between widening portions 308. Moreover, in some embodiments, some widening portions 308 and / or contraction portions 310 may have different sizes than other widening portions 308 and / or contraction portions 310. Furthermore, although Figure 3 The widened portion 308 of the trench wall 304 is illustrated as being centered along the longitudinal axis, and the regular portion 316 is also centered along the longitudinal axis, but in some embodiments, the widened portion 308 may be offset to one side or the other of the regular portion 316. Similarly, the constricted portion 310 need not be centered relative to the regular portion 308 of the conductive structure 306. Additionally, in some embodiments, instead of every trench wall 304 and conductive structure 306 including a widened portion 308 and a constricted portion 310, respectively, every other trench wall 304 and conductive structure 306 may include a widened portion 308 and a constricted portion 310, respectively.

[0026] Figure 4 Is Figure 3 FIG. 3 is an enlarged view of a portion of the device 300 indicated by the box 303 shown in FIG. Figure 4 , portions of two conductive structures 306 and a portion of the trench wall 304 are shown. Figure 4 Not drawn to scale as the size of some features have been exaggerated to illustrate examples of the present invention.

[0027] like Figure 4 , the trench wall 304 may have a width 402 at the regular portion 316 and a width 404 at the widened portion 308. The width 402 may be less than the width 404. In some embodiments, the width 402 may be the minimum spacing and / or the desired spacing between the conductive structures 306. In some embodiments of the present invention, the minimum spacing corresponds to and / or is related to the minimum feature size of the semiconductor manufacturing process. The conductive structure 306 may have a width 406 at the regular portion 318 and a width 408 at the contraction portion 310. The width 406 may be greater than the width 408. In some embodiments, the width 408 may be the minimum width that allows the conductive structure 306 to operate effectively. The width 408 and / or the width 406 may be based at least in part on the purpose of the conductive structure 306 (e.g., high voltage line, low voltage signal line). As described herein, all widths are along the X dimension.

[0028] Widened portion 308 and / or constricted portion 310 may extend a distance 410 in the Y dimension. In some examples, width 408, width 404, and / or distance 410 may be based at least in part on a tradeoff between a desire to reduce trench wall collapse and increasing resistance of conductive structure 306.

[0029] The width of the conductive structure 306 and / or the trench wall 304 and / or the distance 410 of the widened portion 308 and / or the constricted portion 310 may have a range of values ​​that may result in reduced trench wall collapse. For example, in some embodiments, the width 408 of the constricted portion 310 may vary between approximately 33%-80% or less of the width 406. Similarly, in some embodiments, the width 404 of the widened portion 308 may vary between approximately 150%-300% or more of the width 402. In some embodiments, the distance 410 may be based at least in part on the width 404 and / or the distance 312. For example, in some embodiments, the distance 410 may be approximately 0.05% or more of the distance 312. In some examples, the width 408, the width 404, and / or the distance 410 may be based at least in part on the properties of the material(s) forming the trench wall 304 (e.g., stiffness, material, etc.).

[0030] Although the constricted portion 310 has been described with reference to the conductive structure 306 , it should be understood that the features of the constricted portion 310 may also apply to the trench 302 between the trench walls 304 , at least because the conductive structure 306 is conformally deposited within the trench 302 .

[0031] Figure 5 is a flow chart of a method 500 according to an embodiment of the present invention. In some embodiments, the method 500 may be used to form the trench 302, the trench wall 304, and / or the conductive structure 306. In some embodiments, the method 500 may be a damascene process or may be part of a damascene process.

[0032] At block 502, a step of "etching trenches in a dielectric material" may be performed. Etching of the trenches (e.g., trench 302) may form trench walls (e.g., trench walls 304) extending a distance in the Y dimension between the trenches. The trench walls may have a width in the X dimension equal to the spacing between the trenches in the X dimension. As a result of the etching, at least one of the trench walls may include at least one widened portion (e.g., widened portion 308).

[0033] At block 504, a step of depositing a conductive material in the trench may be performed. The deposition of the conductive material may form conductive structures (e.g., conductive structures 306) within the trench. At least one of the conductive structures may include at least one constriction (e.g., constriction 310). In some embodiments, the constriction may be attributable to a widened portion of the trench wall.

[0034] As disclosed herein, in some embodiments, trench walls having widened portions can be used to reduce the risk of trench wall collapse. In some embodiments, conductive structures having constricted portions can be used, which can allow the widened portions of the trench walls to reduce the risk of trench wall collapse. Reducing the risk of trench wall collapse can allow the conductive structures to be spaced closer together and / or the length of the conductive structures to be increased.

[0035] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes and / or may be separated and / or performed in separate devices or device portions according to the present systems, devices, and methods.

[0036] Finally, the above discussion is intended to be merely illustrative and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, although various embodiments of the present invention have been described in particular detail, it should also be understood that a person of ordinary skill in the art may devise numerous modifications and alternative embodiments without departing from the spirit and scope of the present invention as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. An apparatus for coupling two or more components used in a semiconductor device, the apparatus comprising: A groove wall extending a first length in a first dimension and having a first width in a second dimension and a height in a third dimension, wherein the groove wall comprises a first widened portion, wherein the first widened portion: extends a second length in the first dimension, wherein the second length is less than the first length; and The trench has a second width in the second dimension, wherein the second width is greater than the first width, wherein a trench partially defined by the trench walls is filled with a conductive material.

2. The apparatus of claim 1, wherein the trench walls comprise a dielectric material. 3 . The apparatus of claim 1 , wherein the groove wall includes a first end and a second end opposite the first end in the first dimension and the first widened portion is between the first end and the second end. 4 . The apparatus of claim 1 , wherein the groove wall further comprises a second widened portion spaced a distance from the first widened portion along the first dimension. 5 . The apparatus of claim 4 , wherein the distance between the first widened portion and the second widened portion is based at least in part on the first width of the groove wall.

6. The apparatus of claim 4, wherein the distance between the first widened portion and the second widened portion is based at least in part on properties of a material contained in the groove wall.

7. The apparatus of claim 1 , further comprising a second groove wall extending a third length in the first dimension, wherein the second groove wall has a third width in the second dimension, wherein the second groove wall includes a second widened portion, wherein the groove wall and the second groove wall are spaced apart in the second dimension and the groove is between the groove wall and the second groove wall.

8. An apparatus according to claim 7, wherein the groove wall and the second groove wall each include a first end and a second end opposite the first end in the first dimension and extend the same length in the first dimension, wherein the first widened portion is positioned at the same distance from the first end of the groove wall as the second widened portion is positioned at the same distance from the first end of the second groove wall.

9. The apparatus of claim 7, wherein the second widened portion has a width equal to the second width of the first widened portion and a length equal to the second length of the first widened portion.

10. An apparatus for coupling two or more components used in a semiconductor device, the apparatus comprising: A conductive structure extending a first length in a first dimension and having a first width in a second dimension and a height in a third dimension, wherein the conductive structure comprises a first constricted portion, wherein the first constricted portion: extends a second length in the first dimension, wherein the second length is less than the first length; and The conductive structure has a second width in the second dimension, wherein the second width is less than the first width, wherein the conductive structure is in a trench formed in a dielectric material. The apparatus of claim 10 , wherein the conductive structure comprises a metallic material.

12. The apparatus of claim 11, wherein the metal material comprises at least one of copper or tungsten.

13. The apparatus of claim 10, wherein the conductive structure includes a first end and a second end opposite the first end in the first dimension and the first constricted portion is located between the first end and the second end.

14. The apparatus of claim 10, wherein the conductive structure further comprises a second constriction portion spaced a distance from the first constriction portion along the first dimension.

15. The apparatus of claim 14, wherein the second constricted portion has a width equal to the second width of the first constricted portion and a length equal to the second length of the first constricted portion.

16. The apparatus of claim 10, further comprising a second conductive structure extending a third length in the first dimension, wherein the second conductive structure has a third width in the second dimension, wherein the second conductive structure includes a second constricted portion, wherein the conductive structure and the second conductive structure are separated in the second dimension with a groove wall between the conductive structure and the second conductive structure.

17. A method for coupling two or more components for use in a semiconductor device, the method comprising: etching a plurality of trenches in a dielectric material to form a plurality of trench walls extending in a first dimension between individual ones of the plurality of trenches, wherein the plurality of trench walls have a first width in a second dimension equal to the spacing between the plurality of trenches, wherein at least one of the plurality of trench walls comprises: a first length in the first dimension and a height in the third dimension; and a widened portion, wherein the widened portion extends a second length in the first dimension and has a second width in the second dimension, wherein the second length is less than the first length and the second width is greater than the first width; and A conductive material is deposited in the plurality of trenches to form a plurality of conductive structures, wherein at least one of the plurality of conductive structures includes a constriction.

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