Silicon carbide device structure, preparation method thereof and chip

Abstract

The invention belongs to the technical field of power devices, and provides a silicon carbide device structure, a preparation method thereof and a chip, a P-type heavily doped region is isolated from a junction field effect transistor region at an adjacent position by a P-type well region, and an N-type heavily doped region is isolated from the junction field effect transistor region at an adjacent position by the P-type well region. The adjacent junction field effect transistor regions are isolated by the P-type well regions, so that a super-junction-like structure is formed, the junction field effect transistor regions can have donor doping with higher doping concentration, corner arrangement is avoided, a depletion region can be completely closed, the on resistance of the device is reduced, and the reliability of the device is improved.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and particularly relates to a silicon carbide device structure, its fabrication method, and a chip. Background Technology

[0002] Silicon carbide (SiC), as a new generation of wide bandgap semiconductor material, is widely used in electric vehicles, charging piles, and data electronics due to its advantages such as wide bandgap, high critical breakdown electric field, and high saturation drift velocity. Compared with traditional silicon-based metal-oxide-semiconductor (MOS) devices, SiC MOSFETs have better electrical performance, such as lower on-resistance, higher breakdown voltage, and better thermal stability.

[0003] However, the gate oxide of SiC MOSFET devices is prone to degradation under high electric fields, leading to excessively high electric field strength within the gate oxide layer and affecting device reliability. In traditional SiC MOSFET structures, the JFET region is often designed with a wide width to achieve low on-resistance, but this design may cause the gate oxide layer to withstand excessively high voltage under reverse bias, triggering premature device breakdown. On the other hand, while existing square, staggered square, and hexagonal layout structures optimize the electric field distribution to some extent, they still suffer from problems such as high on-resistance, low current density, and poor short-circuit characteristics. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a silicon carbide device structure, its fabrication method, and a chip, aiming to reduce on-resistance and improve device reliability and short-circuit characteristics.

[0005] The first aspect of this application provides a silicon carbide device structure, the silicon carbide device structure comprising: silicon carbide substrate; An N-type drift region is formed on the front side of the silicon carbide substrate; A P-type well region is formed on the N-type drift region; Multiple junction field-effect transistor regions are formed on the N-type drift region, and adjacent junction field-effect transistor regions are isolated by the P-type well region; Multiple P-type heavily doped regions are formed on the N-type drift region; wherein the P-type heavily doped regions are isolated from the adjacent junction field-effect transistor regions by the P-type well regions; Multiple N-type heavily doped regions are formed on the P-type well region; wherein the N-type heavily doped regions are isolated from the adjacent junction field-effect transistor regions by the P-type well region, and the thickness of the N-type heavily doped regions is less than the thickness of the P-type well region; A gate dielectric layer is formed on the junction field-effect transistor region and the P-type well region, and the gate dielectric layer covers the P-type well region; A gate layer enclosed by the gate dielectric layer; A first electrode covering the gate dielectric layer and the P-type heavily doped region; A second electrode is formed on the back side of the silicon carbide substrate.

[0006] In some embodiments, a plurality of junction field-effect transistor regions are arranged sequentially according to a first direction and a second direction, wherein the angle between the first direction and the second direction is greater than 30°.

[0007] In some embodiments, a P-type heavily doped region is provided on both sides of each junction field-effect transistor region, and an N-type heavily doped region is provided on both sides of each P-type heavily doped region; wherein, the first direction is perpendicular to the second direction.

[0008] In some embodiments, the N-type heavily doped region and the P-type heavily doped region are located on opposite sides of the junction field-effect transistor region, and the intersection point of the line connecting two adjacent N-type heavily doped regions and the line connecting two adjacent P-type heavily doped regions is located in the region between adjacent junction field-effect transistor regions; wherein, the first direction is perpendicular to the second direction.

[0009] In some embodiments, the plurality of junction field-effect transistor regions are arranged sequentially in a first direction, a second direction and a third direction on a horizontal cross section, wherein the angle between the first direction and the second direction is 120° and the angle between the first direction and the third direction is 120°.

[0010] In some embodiments, the N-type heavily doped region is disposed around the P-type heavily doped region in a horizontal cross section.

[0011] In some embodiments, the plurality of junction field-effect transistor regions are arranged in multiple directions, and a P-type blocking region is provided at the intersection of the multiple directions.

[0012] In some embodiments, the central region of the P-type blocking region is further provided with a JFET region.

[0013] A second aspect of this application also provides a method for fabricating a silicon carbide device structure, the method comprising: An N-type drift region and a top epitaxial region are sequentially formed on the front side of a silicon carbide substrate; After depositing polycrystalline silicon material, the polycrystalline silicon material is etched to form a preset pattern, and a P-type well region is formed in the top epitaxial region by ion implantation process; A thermal oxide layer is formed, and an N-type heavily doped region is formed by ion implantation under the protection of the thermal oxide layer. A junction field-effect transistor region extending into the N-type drift region is formed by ion implantation under the first mask coverage, and then a heavily doped P-type region is formed by ion implantation under the second mask coverage; the heavily doped P-type region and the junction field-effect transistor region are isolated by the P-type well region. Remove the second mask and form a gate dielectric layer covering the P-type well region and the junction field-effect transistor region, as well as a gate layer included by the gate dielectric layer; A first electrode is formed covering the gate dielectric layer and the P-type heavily doped region, and a second electrode is formed on the back side of the silicon carbide substrate.

[0014] A third aspect of this application also provides a chip including the silicon carbide device structure as described in any of the above embodiments.

[0015] The beneficial effects of the embodiments of this application are as follows: by setting the P-type heavily doped region to be isolated from the adjacent junction field-effect transistor region by a P-type well region, the N-type heavily doped region to be isolated from the adjacent junction field-effect transistor region by a P-type well region, and the adjacent junction field-effect transistor regions to be isolated from each other by a P-type well region, a superjunction-like structure is formed, which allows the junction field-effect transistor region to have a higher doping concentration of donor doping, avoids corner setting, allows the depletion region to be completely closed, reduces the on-resistance of the device, and improves the reliability of the device. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a horizontal cross-section of the silicon carbide device structure provided in the embodiments of this application; Figure 2 yes Figure 1 A schematic diagram of section B in the diagram; Figure 3 yes Figure 1 A schematic diagram of section A in the diagram; Figure 4 yes Figure 1 A schematic diagram of section C in the diagram; Figure 5a This is a partial cross-sectional schematic diagram of the silicon carbide device structure provided in the embodiments of this application; Figure 5b This is a partial cross-sectional schematic diagram of the silicon carbide device structure provided in the embodiments of this application; Figure 5c This is a partial cross-sectional schematic diagram of the silicon carbide device structure provided in the embodiments of this application; Figure 5d This is a partial cross-sectional schematic diagram of the silicon carbide device structure provided in the embodiments of this application; Figure 5eThis is a partial cross-sectional schematic diagram of the silicon carbide device structure provided in the embodiments of this application; Figure 5f This is a partial cross-sectional schematic diagram of the silicon carbide device structure provided in the embodiments of this application; Figure 5g This is a partial cross-sectional schematic diagram of the silicon carbide device structure provided in the embodiments of this application; Figure 6 This is a schematic flowchart of the method for fabricating a silicon carbide device structure provided in the embodiments of this application; Figure 7 This is a partial schematic diagram of the method for fabricating the silicon carbide device structure provided in the embodiments of this application; Figure 8 This is a partial schematic diagram of the method for fabricating the silicon carbide device structure provided in the embodiments of this application; Figure 9 This is a partial schematic diagram of the method for fabricating the silicon carbide device structure provided in the embodiments of this application; Figures 10a-10c This is a partial schematic diagram of the fabrication method of the IGBT structure provided in the embodiments of this application; Figure 11 This is a partial schematic diagram of the method for fabricating the silicon carbide device structure provided in the embodiments of this application; Figure 12 This is a partial schematic diagram of the method for fabricating the silicon carbide device structure provided in the embodiments of this application; Figure 13 This is a partial schematic diagram of the method for fabricating the silicon carbide device structure provided in the embodiments of this application; Figure 14 This is a partial schematic diagram of the method for fabricating the silicon carbide device structure provided in the embodiments of this application; Figure 15 and Figure 16 This is a schematic diagram of the test parameters of the silicon carbide device structure provided in the embodiments of this application. Detailed Implementation

[0017] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0018] The gate oxide of SiC MOSFET devices is prone to degradation under high electric fields, leading to excessively high electric field strength within the gate oxide layer and affecting device reliability. In traditional SiC MOSFET structures, the JFET region is often designed with a wide width to achieve low on-resistance, but this design may cause the gate oxide layer to withstand excessively high voltage under reverse bias, triggering premature device breakdown. On the other hand, while existing square, staggered square, and hexagonal layout structures optimize the electric field distribution to some extent, they still suffer from problems such as high on-resistance, low current density, and poor short-circuit characteristics.

[0019] To address the aforementioned technical problems, this application provides a silicon carbide device structure, see [link to relevant documentation]. Figure 1 , Figure 2 , Figure 3 as well as Figure 4 As shown, the silicon carbide device structure in this embodiment includes: a silicon carbide substrate 110, an N-type drift region 120, a P-type well region 310, a junction field-effect transistor region 210, a heavily doped P-type region 410, a heavily doped N-type region 510, a gate dielectric layer 610, a gate layer 620, a first electrode 710, and a second electrode 720.

[0020] Combination Figure 2 , Figure 3 as well as Figure 4 As shown, an N-type drift region 120 is formed on the front side of a silicon carbide substrate 110, a P-type well region 310 is formed on the N-type drift region 120, and multiple junction field-effect transistor regions 210 are formed on the N-type drift region 120. Adjacent junction field-effect transistor regions 210 are isolated by P-type well regions 310. Multiple P-type heavily doped regions 410 are formed on the N-type drift region 120, and the P-type heavily doped regions 410 are isolated from the adjacent junction field-effect transistor region 210 by a P-type well region 310; multiple N-type heavily doped regions 510 are formed on the P-type well region 310, and the N-type heavily doped regions 510 are isolated from the adjacent junction field-effect transistor region 210 by a P-type well region 310, and the thickness of the N-type heavily doped regions 510 is less than the thickness of the P-type well region 310; a gate dielectric layer 610 is formed on the junction field-effect transistor region 210 and the P-type well region 310, and the gate dielectric layer 610 covers the P-type well region 310; a gate layer 620 is wrapped by the gate dielectric layer 610, a first electrode 710 covers the gate dielectric layer 610 and the P-type heavily doped regions 410, and a second electrode 720 is formed on the back side of the silicon carbide substrate 110.

[0021] In this embodiment, by setting the P-type heavily doped region 410 to be isolated from the adjacent junction field-effect transistor region 210 by the P-type well region 310, the N-type heavily doped region 510 to be isolated from the adjacent junction field-effect transistor region 210 by the P-type well region 310, and adjacent junction field-effect transistor regions 210 to be isolated from each other by the P-type well region 310, a superjunction-like structure is formed. This allows the junction field-effect transistor region 210 to have a higher doping concentration of donor doping, avoids corner settings, allows the depletion region to be completely closed, reduces the on-resistance of the device, and improves the reliability of the device.

[0022] In some embodiments, a plurality of junction field-effect transistor regions 210 are arranged sequentially according to a first direction and a second direction, wherein the angle between the first direction and the second direction is greater than 30°.

[0023] In some embodiments, the first direction is perpendicular to the second direction, and the angle between the first direction and the second direction is 90°.

[0024] In some embodiments, combined with Figure 1 As shown, a P-type heavily doped region 410 is provided on both long sides of the junction field-effect transistor region 210 arranged along the first direction. An N-type heavily doped region 510 is provided on both sides of each P-type heavily doped region 410. The boundary region between the P-type heavily doped region 410 and the N-type heavily doped region 510 on both sides forms a PN junction. The length of the two long sides of the junction field-effect transistor region 210 arranged along the first direction is greater than the sum of the widths of the P-type heavily doped region 410 and the N-type heavily doped region 510.

[0025] In some embodiments, combined with Figure 1 As shown, the P-type heavily doped region 410 and the N-type heavily doped region 510 are rectangular. The long side of the junction field-effect transistor region 210 arranged along the first direction is perpendicular to the long side of the P-type heavily doped region 410, and the long side of the junction field-effect transistor region 210 arranged along the first direction is perpendicular to the long side of the N-type heavily doped region 510. The junction field-effect transistor region 210 and the P-type heavily doped region 410 are isolated by the P-type well region 310, and the junction field-effect transistor region 210 and the N-type heavily doped region 510 are isolated by the P-type well region 310.

[0026] In some embodiments, combined with Figure 1 As shown, the P-type well region 310 is square or rectangular, and the area between adjacent P-type well regions 310 is an N-type JFET region.

[0027] In some embodiments, combined with Figure 1 As shown, the cross-shaped area of ​​the JFET region is filled with a small P-type blocking region 311, i.e., the block region.

[0028] In some embodiments, the P-type blocking region 311 (block region) and the P-type trap region 310 can be integrally formed.

[0029] In some embodiments, the silicon carbide substrate 110 can be N-type doped, and the silicon carbide device structure can be a MOS structure, with the first electrode 710 as the source and the second electrode 720 as the drain.

[0030] In some embodiments, the silicon carbide substrate 110 can be P-type doped, and the silicon carbide device structure can be an IGBT structure, with the first electrode 710 being the emitter and the second electrode 720 being the collector.

[0031] In some embodiments, the area of ​​the P-type blocking region 311 (block region) is approximately 10-30% of the area of ​​the P-type well region 310.

[0032] In some embodiments, combined with Figure 3 and Figure 4 As shown, the junction field-effect transistor region 210 and the P-type well region 310 form a transverse PN junction structure, that is, a superjunction-like structure in which the P-type well region 310 surrounds the N-type JFET region.

[0033] In this embodiment, the superjunction-like structure allows for higher donor impurity doping in the JFET region, thus effectively reducing on-resistance while maintaining ideal BVDSS. The current density of the silicon carbide device structure in this embodiment is 34-40% higher than that of the strip layout, and 10% higher than that of the square, staggered square, or hexagonal layouts.

[0034] In some embodiments, the width of the junction field-effect transistor region 210 is 1.0-2.4 μm, the depth of the junction field-effect transistor region 210 is 1.0-1.4 μm, and the total doping dose of the junction field-effect transistor region 210 is 2E12-8E12 cm⁻¹. -2 .

[0035] In some embodiments, the depth of the P-type well region 310 is 0.6-0.7 μm, and the total doping dose of the P-type well region 310 is 4E12-2E13 cm⁻¹. -2 .

[0036] In some embodiments, the depth of the heavily doped P-type region 410 is greater than 1 μm, and the total doping dose of the heavily doped P-type region 410 is 3E15-8E15 cm⁻¹. -2 .

[0037] In some embodiments, the doping concentrations of the P-type well region 310, the JFET region, and the heavily doped P-type region 410 are all approximately box-shaped.

[0038] In some embodiments, the P-type heavily doped region 410 and the N-type heavily doped region 510 are arranged in a single direction, that is, they can be arranged in the manner of N-type heavily doped region 510 / P-type heavily doped region 410 / N-type heavily doped region 510.

[0039] In this embodiment, compared to square, staggered square or hexagonal layouts, the P-type well region 310 of the silicon carbide device structure in this embodiment has no corners, and the depletion region can be completely closed. Therefore, its IDSS is lower (two orders of magnitude lower than conventional), BVDSS is higher, and its room temperature / high temperature reliability is better.

[0040] In some embodiments, combined with Figure 1 As shown, in this embodiment, the area of ​​the P-type well region 310 in the silicon carbide device structure is increased, and the depletion region capacitance is increased. Compared with the square structure layout, its Qgd is reduced, and the switching speed is faster. The P-type blocking region 311 and the P-type well region 310 enclose the JFET region, which has a stronger depletion effect than other layouts. Therefore, it reduces the reverse leakage current IDSS. In addition, the device can enter the saturation region earlier when turned on, clamping the saturation current and optimizing the short-circuit characteristics of the device. Furthermore, in the fabrication process, the P-type blocking region 311 and the conventional P-type well region 310 use the same photomask, and the process is the same, requiring no additional cost.

[0041] In some embodiments, combined with Figure 5a As shown, each junction field-effect transistor region 210 has a P-type heavily doped region 410 on both sides, and each P-type heavily doped region 410 has an N-type heavily doped region 510 on both sides.

[0042] In this embodiment, the first direction is perpendicular to the second direction, and a P-type well region 310 is provided at the intersection of the junction field-effect transistor region 210 arranged along the first direction and the junction field-effect transistor region 210 arranged along the second direction.

[0043] In some embodiments, combined with Figure 5b As shown, the N-type heavily doped region 510 has an annular cross-sectional shape and is arranged around the P-type heavily doped region 410 in the horizontal cross-section.

[0044] In this embodiment, the N-type heavily doped region 510 has a ring-shaped square structure in the horizontal cross-section.

[0045] In some embodiments, combined with Figure 5c As shown, the intersection area of ​​the junction field-effect transistor region 210 arranged along the first direction and the junction field-effect transistor region 210 arranged along the second direction is the P-type blocking region 311 (block region).

[0046] In some embodiments, the P-type blocking area 311 (block area) is a hollow square structure.

[0047] In some embodiments, a smaller JFET region 211 is also provided in the central area within the P-type blocking region 311 (block region).

[0048] In some embodiments, combined with Figure 5d As shown, the N-type heavily doped region 510 and the P-type heavily doped region 410 are located on both sides of the junction field-effect transistor region 210, respectively. The intersection of the line connecting two adjacent N-type heavily doped regions 510 and the line connecting two adjacent P-type heavily doped regions 410 is located in the region between adjacent junction field-effect transistor regions 210.

[0049] In this embodiment, the junction field-effect transistor (JFET) region 210 has a rectangular shape in its horizontal cross-section. The long sides of the plurality of JFET regions 210 arranged along a first direction are parallel to the first direction, and the long sides of the plurality of JFET regions 210 arranged along a second direction are perpendicular to the second direction. A P-type heavily doped region 410 is disposed on one long side of the JFET region 210, and an N-type heavily doped region 510 is disposed on the other long side of the JFET region 210. Thus, the N-type heavily doped region 510 and the P-type heavily doped region 410 are arranged diagonally opposite each other.

[0050] In some embodiments, such as Figure 5e As shown, the cell can be a rectangular structure, and three junction field-effect transistor regions 210 are arranged in the second direction. The long side of the three junction field-effect transistor regions 210 is parallel to the second direction. Each junction field-effect transistor region 210 in the second direction has an N-type heavily doped region 510 / P-type heavily doped region 410 / N-type heavily doped region 510 structure on both sides. A junction field-effect transistor region 210 arranged in the first direction is also arranged between each adjacent N-type heavily doped region 510 / P-type heavily doped region 410 / N-type heavily doped region 510 structure.

[0051] In some embodiments, such as Figure 5f As shown, the horizontal cross-section of the P-type heavily doped region 410 can be hexagonal, and the N-type heavily doped region 510 is also hexagonal.

[0052] In some embodiments, a plurality of junction field-effect transistor regions 210 are arranged sequentially in a first direction, a second direction and a third direction on a horizontal cross section, with the angle between the first direction and the second direction being 120° and the angle between the first direction and the third direction being 120°.

[0053] In some embodiments, a plurality of junction field-effect transistor regions 210 are arranged in a plurality of directions, and a junction field-effect transistor region 210 is provided at the intersection of the plurality of directions.

[0054] In some embodiments, the cross-sectional shape of the junction field-effect transistor region 210 in the intersection region of multiple directions is square or triangular.

[0055] In some embodiments, such as Figure 5g As shown, in the case of a hexagonal cell layout, the block region is a hollow triangle, that is, the intersection area of ​​the first direction, the second direction and the third direction is filled by the triangular junction field-effect transistor region 210.

[0056] In some embodiments, combined with Figure 5c As shown, multiple junction field-effect transistor (JFET) regions 210 are arranged sequentially in a first direction and a second direction on a horizontal cross section. The first direction and the second direction are perpendicular. A square JFET region 210 is provided in the intersection area between the multiple JFET regions 210 arranged along the first direction and the multiple JFET regions 210 arranged along the second direction. The area of ​​the square JFET region 210 is smaller than the area of ​​the adjacent JFET region 210, and the width of the square JFET region 210 is smaller than the width of the adjacent JFET region 210.

[0057] In some embodiments, combined with Figure 5c As shown, the P-type heavily doped region 410 has a square shape in horizontal cross-section, the N-type heavily doped region 510 has a rectangular shape in horizontal cross-section, and the junction field-effect transistor region 210 has a rectangular shape in horizontal cross-section. The long sides of the P-type heavily doped region 410, the N-type heavily doped region 510, and the junction field-effect transistor region 210 are arranged in parallel. An N-type heavily doped region 510 is provided on each of the two long sides of the P-type heavily doped region 410.

[0058] This application also provides a method for fabricating a silicon carbide device structure, participating in... Figure 6 As shown, the preparation method includes steps S100 to S700.

[0059] In step S100, an N-type drift region 120 and a top epitaxial region are sequentially formed on the front side of the silicon carbide substrate 110.

[0060] In this embodiment, combined with Figure 7 As shown, the silicon carbide substrate 110 can be a highly doped substrate, and a double lightly doped epitaxial layer is formed on the silicon carbide substrate 110. The first lightly doped epitaxial layer can serve as an N-type drift region 120, and the second lightly doped epitaxial layer can serve as a top epitaxial region.

[0061] In some embodiments, the doping concentration of the top epitaxial region is 1.3-3E16 cm⁻¹. -3 The thickness of the top epitaxial region is 1-3 μm.

[0062] In some embodiments, the doping concentration of the N-type drift region 120 is 3E15-1.5E16 cm⁻¹. -3 The thickness and concentration of the N-type drift region 120 depend on the device's voltage rating.

[0063] In step S200, after depositing polycrystalline silicon material, the polycrystalline silicon material is etched to form a preset pattern, and a P-type well region 310 is formed in the top epitaxial region by ion implantation.

[0064] In this embodiment, combined with Figure 8 As shown, a self-aligned process is used to deposit polycrystalline silicon material as a hard mask 621. A P-type well region 310 and a block region are formed through ion implantation. The implantation depth is 0.6-0.8 μm, which is 0.3-0.4 μm shallower than conventional structures. The number of ion implantations is 3-5, with the energy decreasing sequentially. The doping concentration is 1E16-2E18 cm⁻¹. -3 The overall structure is box-shaped.

[0065] In some embodiments, the implantation energy for forming the P-type well region 310 and the block region by the ion implantation process decreases sequentially, with doping concentrations ranging from 1E16 to 2E18 cm⁻¹. -3 Within the specified range, the overall distribution resembles a box.

[0066] In step S300, a thermal oxide layer is formed, and under the protection of the thermal oxide layer, an N-type heavily doped region 510 is formed by ion implantation.

[0067] In this embodiment, combined with Figure 9 As shown, by widening the hard mask 621 through oxidation, the channel is masked, and an N-type heavily doped region 510 is formed through ion implantation.

[0068] In some embodiments, combined with Figure 10a , 10b As shown in 10c, the silicon carbide substrate 110 is P-type doped, and the silicon carbide device structure is an IGBT structure. In the fabrication process of the IGBT structure, a hard mask 111 can be formed by isotropic CVD deposition of silicon oxide. Then, anisotropic dry etching is performed on the silicon oxide hard mask, removing the silicon oxide from the SiC surface and retaining the silicon oxide hard masks on both sides of the hard mask 621. Figure 10b As shown. The silicon oxide hard masks 111 on both sides of the hard mask 621 mask the channel, and ion implantation forms an N-type heavily doped region 510, as shown. Figure 10c As shown.

[0069] In step S400, a junction field-effect transistor region 210 extending into the N-type drift region 120 is formed under the first mask 112 by an ion implantation process, and then a P-type heavily doped region 410 is formed under the second mask 113 by an ion implantation process.

[0070] In this embodiment, combined with Figure 11 As shown, N-type doping of the JFET region can be performed under the cover of the first mask 112 to improve conductivity.

[0071] In some embodiments, in step S400, the implantation depth of the ion implantation process is approximately 1.0-1.4 μm.

[0072] In some embodiments, in step S400, the ion implantation process is performed 4-6 times, the implantation energy decreases sequentially, and the doping concentration of the junction field-effect transistor region 210 is 2E16-2E17 cm⁻¹. -3 The overall distribution is in the shape of a box.

[0073] In this embodiment, combined with Figure 12 As shown, after removing the first mask, a second mask is formed. Under the cover of the second mask, a P-type heavily doped region 410 is formed by ion implantation. The P-type heavily doped region 410 and the junction field-effect transistor region 210 are isolated by a P-type well region 310.

[0074] In some embodiments, in step S400, P-type ion implantation forms a heavily doped P-type region 410. The implantation depth of the P-type ions is approximately 1.0-1.5 μm, the number of P-type ion implantations is 3-5 times, the P-type ion implantation energy decreases sequentially, and the doping concentration of the heavily doped P-type region 410 is greater than 1E19 cm⁻¹. -3 The P-type heavily doped region 410 is distributed in a box pattern. After P-type ion implantation, the device is annealed at 1600-1800℃.

[0075] In step S500, the second mask is removed, and a gate dielectric layer 610 covering the P-type well region 310 and the junction field-effect transistor region 210 and a gate layer 620 included by the gate dielectric layer 610 are formed.

[0076] In this embodiment, see Figure 13 As shown, the implantation process ends with annealing and activation at 1600-1800℃, sacrificial oxidation to form the gate dielectric layer 610, and deposition of polysilicon material to form the gate layer 620.

[0077] In step S600, a first electrode 710 is formed covering the gate dielectric layer 610 and the P-type heavily doped region 410, and a second electrode 720 is formed on the back side of the silicon carbide substrate 110.

[0078] In this embodiment, see Figure 14 As shown, the first electrode 710 and the second electrode 720 are formed by depositing metallic materials.

[0079] In some embodiments, the silicon carbide substrate 110 in step S100 can be N-type doped, and the silicon carbide device structure can be a MOS structure.

[0080] In some embodiments, the silicon carbide substrate 110 in step S100 can be P-type doped, and the silicon carbide device structure can be an IGBT structure.

[0081] This application also provides a chip including a silicon carbide device structure as described in any of the above embodiments.

[0082] Combination Figure 15 As shown, the depth and concentration of the P-type well region 310 and the JFET region are precisely adjusted through process techniques to achieve an optimal combination, forming a superjunction-like structure. Therefore, under the same mask, the on-resistance (Ron) of the silicon carbide device structure (rectangular + P-type blocking region) using the new process is approximately 10% lower than that of the conventional process, while maintaining the same breakdown voltage (BV). Figure 16 As shown, for the same active region size, different designs exhibit BVDSS and Ron performance in actual fabrication. It can be seen that the BVDSS of the structure in this application (rectangular + P-type blocking region) is 1675V, exceeding several other conventional designs by more than 200V. Simultaneously, its on-resistance (Ron) is 44-54% lower than that of the strip structure, 10-15% lower than that of the square structure, and 6% lower than that of the hexagonal structure, exhibiting the optimal BV-Ron trade-off. Combined with... Figure 16 As shown, under a voltage of 1200V, except for the hexagonal structure which has a more discrete IDSS, the IDSS of other structures is less than 400nA. The IDSS of the silicon carbide device structure (rectangular + P-type blocking region) and the strip structure in this application is even less than 10nA. By (the P-type well region and the P-type blocking region surround the JFET region, reducing leakage current), this is far superior to the IDSS (<50μA) of commercially available SiC MOSFETs of the same specifications.

[0083] In some embodiments, the chip includes a chip substrate on which one or more silicon carbide device structures are disposed, the silicon carbide device structures including the silicon carbide device structures of any of the above embodiments.

[0084] In one specific application embodiment, when the silicon carbide substrate 110 is N-type doped, the silicon carbide device structure can be a MOS structure, with the first electrode 710 as the source and the second electrode 720 as the drain. When the silicon carbide substrate 110 is P-type doped, the silicon carbide device structure can be an IGBT structure, with the first electrode 710 as the emitter and the second electrode 720 as the collector.

[0085] Other related semiconductor devices, as well as MOSFETs, can be integrated on the chip substrate to form an integrated circuit.

[0086] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0087] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0088] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0089] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0090] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0091] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A silicon carbide device structure, characterized in that, The silicon carbide device structure includes: silicon carbide substrate; An N-type drift region is formed on the front side of the silicon carbide substrate; A P-type well region is formed on the N-type drift region; Multiple junction field-effect transistor regions are formed on the N-type drift region, and adjacent junction field-effect transistor regions are isolated by the P-type well region; Multiple P-type heavily doped regions are formed on the N-type drift region; wherein the P-type heavily doped regions are isolated from the adjacent junction field-effect transistor regions by the P-type well regions; Multiple N-type heavily doped regions are formed on the P-type well region; wherein the N-type heavily doped regions are isolated from the adjacent junction field-effect transistor regions by the P-type well region, and the thickness of the N-type heavily doped regions is less than the thickness of the P-type well region; A gate dielectric layer is formed on the junction field-effect transistor region and the P-type well region, and the gate dielectric layer covers the P-type well region; A gate layer enclosed by the gate dielectric layer; A first electrode covering the gate dielectric layer and the P-type heavily doped region; A second electrode is formed on the back side of the silicon carbide substrate.

2. The silicon carbide device structure as described in claim 1, characterized in that, The multiple junction field-effect transistor regions are arranged sequentially according to a first direction and a second direction, and the angle between the first direction and the second direction is greater than 30°.

3. The silicon carbide device structure as described in claim 2, characterized in that, Each junction field-effect transistor region has a P-type heavily doped region on both sides, and each P-type heavily doped region has an N-type heavily doped region on both sides; wherein, the first direction is perpendicular to the second direction.

4. The silicon carbide device structure as described in claim 2, characterized in that, The N-type heavily doped region and the P-type heavily doped region are located on both sides of the junction field-effect transistor region, and the intersection point of the line connecting two adjacent N-type heavily doped regions and the line connecting two adjacent P-type heavily doped regions is located in the region between adjacent junction field-effect transistor regions; wherein, the first direction is perpendicular to the second direction.

5. The silicon carbide device structure as described in claim 1, characterized in that, The plurality of junction field-effect transistor regions are arranged sequentially in a first direction, a second direction and a third direction on a horizontal cross section, wherein the angle between the first direction and the second direction is 120° and the angle between the first direction and the third direction is 120°.

6. The silicon carbide device structure as described in claim 5, characterized in that, The N-type heavily doped region is arranged around the P-type heavily doped region in a horizontal cross section.

7. The silicon carbide device structure as described in claim 1, characterized in that, The multiple junction field-effect transistor regions are arranged in multiple directions, and P-type blocking regions are provided at the intersection of the multiple directions.

8. The silicon carbide device structure as described in claim 7, characterized in that, The central region of the P-type blocking area is also provided with a JFET area.

9. A method for fabricating a silicon carbide device structure, characterized in that, The preparation method includes: An N-type drift region and a top epitaxial region are sequentially formed on the front side of a silicon carbide substrate; After depositing polycrystalline silicon material, the polycrystalline silicon material is etched to form a preset pattern, and a P-type well region is formed in the top epitaxial region by ion implantation process; A thermal oxide layer is formed, and an N-type heavily doped region is formed by ion implantation under the protection of the thermal oxide layer. A junction field-effect transistor region extending into the N-type drift region is formed by ion implantation under the first mask coverage, and then a heavily doped P-type region is formed by ion implantation under the second mask coverage; the heavily doped P-type region and the junction field-effect transistor region are isolated by the P-type well region. Remove the second mask and form a gate dielectric layer covering the P-type well region and the junction field-effect transistor region, as well as a gate layer included by the gate dielectric layer; A first electrode is formed covering the gate dielectric layer and the P-type heavily doped region, and a second electrode is formed on the back side of the silicon carbide substrate.

10. A chip, characterized in that, Including the silicon carbide device structure as described in any one of claims 1-8.

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