Inductor Current Shunt for Mitigating Load Dump Transients in DC-DC Regulators

Abstract

The present disclosure relates to an inductor current shunt for mitigating load dump transients in a DC-DC regulator. A voltage regulator circuit includes: a switch circuit configured to adjust a switch duty cycle to regulate an output voltage using an error signal representing a difference between a target voltage value and an output voltage at an output node of the voltage regulator circuit; an inductor coupled to the switch circuit and configured to provide an inductor current to the output node; and a shunt circuit coupled in parallel to the inductor and configured to shunt the inductor current from the output node when the output voltage exceeds a specified maximum output voltage.

Description

Technical Field

[0001] This document relates to regulator circuits, and in particular to mitigating output transients in direct current to direct current (DC-DC) regulator circuits. Background Art

[0002] Regulator circuits can be used to generate a regulated output from a circuit input. For example, a buck regulator circuit uses an input voltage to generate a regulated output voltage that is less than the input voltage, while a boost regulator circuit generates a regulated output voltage that is greater than the input voltage. Switches are used to charge and discharge an inductor of the circuit to produce a regulated output. In these types of circuits, as well as in non-inductor based regulator circuits, output load current transients can cause undesirable voltage transients on the regulated output voltage. Summary of the invention

[0003] This document relates generally to electronic circuits for voltage regulation and, more particularly, to improvements in mitigating the effects of load dump transients on regulator circuits.

[0004] In some aspects, a voltage regulator circuit includes: a switching circuit configured to adjust a switching duty cycle to regulate the output voltage using an error signal representing a difference between a target voltage value and an output voltage at an output node of the voltage regulator circuit; an inductor coupled to the switching circuit and configured to provide an inductor current to the output node; and a shunt circuit coupled in parallel to the inductor and configured to shunt the inductor current away from the output node when the output voltage exceeds a specified maximum output voltage.

[0005] In some aspects, a method of operating a voltage converter circuit includes: activating and deactivating a switching circuit to charge and discharge an inductor to generate an output voltage, and providing an inductor current to an output node of the voltage regulator circuit; adjusting a switching duty cycle of the switching circuit to regulate the output voltage using an error signal representing a difference between a target voltage value and the output voltage; comparing the output voltage to a specified maximum output voltage; and shunting the inductor current away from the output node when the output voltage exceeds the specified maximum output voltage.

[0006] In some aspects, a voltage regulator includes: a switching circuit configured to adjust a switching duty cycle to regulate the output voltage using an error signal representing a difference between a target voltage value and an output voltage at an output node of the voltage regulator circuit; an inductor coupled to the switching circuit and configured to provide an inductor current to the output node; and a shunt circuit loop coupled to the inductor and configured to circulate the inductor current away from the output node when the output voltage exceeds a specified maximum output voltage, and to restore the inductor current to the output node when the output voltage decreases to a target voltage that is less than the specified maximum output voltage.

[0007] This section is intended to provide an overview of the subject matter of this patent application. It is not intended to provide an exclusive or exhaustive explanation of the present invention. The detailed description is included to provide further information about this patent application. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the drawings, which are not necessarily drawn to scale, like numbers may describe similar components in different views. Like numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0009] Figure 1 is a schematic diagram of an example of a voltage regulator circuit.

[0010] Figure 2 Shown are current and voltage waveforms for a conventional regulator circuit experiencing load dump.

[0011] Figure 3 is a flow chart of a method of operating a voltage regulator circuit.

[0012] Figure 4 Shown for Figure 1 Current and voltage waveforms of the voltage regulator circuit.

[0013] Figure 5 is a schematic diagram of another example of a voltage regulator circuit.

[0014] Figure 6 Shown for Figure 5 Current and voltage waveforms of the voltage regulator circuit.

[0015] Figure 7 is a schematic diagram of an example of a boost regulator circuit.

[0016] Figure 8 is a schematic diagram of an example of a buck-boost regulator circuit. DETAILED DESCRIPTION

[0017] Figure 1 is a schematic diagram of an example of a voltage regulator circuit 100. The circuit includes a top gate transistor M1, a bottom gate transistor M2, and an inductor 102 (L). In this example, M1 and M2 are field effect transistors (FETs). The voltage regulator circuit 100 may include an output capacitor 104 electrically coupled to an output node and may provide an output voltage V to an output load. OUT The voltage regulator circuit 100 includes a switch circuit 110 having a gate driver 114 and including M1 and M2. The gate driver 114 is configured (e.g., via logic circuitry) to use a clock signal to provide a switch duty cycle including a charging portion and a discharging portion. The voltage regulator circuit 100 receives power during the charging portion of the switch duty cycle.

[0018] Inductor 102 may be coupled between output capacitor 104 and switch circuit node 108. Bottom gate transistor M2 may be electrically coupled between switch circuit node 108 and circuit ground, while top gate transistor M1 may be electrically coupled between switch circuit node 108 and an input node that is electrically coupled to an input voltage V IN .

[0019] During the charging portion of the continuous cycle, transistor M1 is turned on or activated to raise the voltage of the switching circuit node 108 to almost the input voltage V IN This initial activation drives a gradually increasing current through the inductor 102 and to the output capacitor 104 and the load. During the discharge portion of the switch duty cycle, M2 conducts to pull the switch circuit node 108 nearly to circuit ground. This second activation provides a gradually decreasing current from the energy stored in the inductor 102 to the output capacitor 104 and the load.

[0020] The duration of the charging portion of the switch duty cycle is automatically adjusted to minimize the output voltage V OUT The regulation can be accomplished using a circuit feedback loop including an error amplifier circuit 112. The error amplifier circuit 112 generates a voltage V at the output node of the voltage regulator circuit 100 that represents the target voltage value and OUT The output voltage may be scaled (eg, using a resistor divider) to provide a scaled representation of the output voltage to the error amplifier circuit 112, rather than using the actual output voltage as the feedback voltage. The error amplifier circuit 112 uses the feedback voltage (V FB ) and the reference voltage (V REG ) is compared to generate an error signal. REG This can be the desired regulated output voltage or a scaled voltage derived from the desired regulated output voltage.

[0021] The switch circuit 110 may include logic circuitry for implementing pulse width modulation (PWM) switch control. The switch circuit 110 sets the duration of the charging portion and the discharging portion of the switch duty cycle according to the output voltage. For example, the switch circuit 110 may turn on the top gate transistor M1 for a certain duration based on a comparison of the error signal with the reference waveform signal, and then activate the bottom gate transistor M2 for the remainder of each cycle of the clock signal.

[0022] During each switching duty cycle, activating the M1 transistor generates a gradually increasing current in the inductor, while activating the M2 transistor generates a gradually decreasing current in the inductor. The increasing and then decreasing current keeps the feedback voltage substantially equal to the reference voltage, V REF This activation sequence will increase the output voltage V OUT Maintained at the desired level regardless of the current demand at the load.

[0023] exist Figure 1 In the example shown, the circuit topology and target voltage value are V OUT Generates a regulated voltage that is less than the input V of a voltage regulator circuit (e.g., a buck regulator circuit) IN Other examples may include: for generating a voltage greater than V IN The regulated V OUT A voltage regulator circuit topology (e.g., a boost regulator circuit) and a circuit for generating a voltage that can be less than or greater than V IN The regulated V OUT circuit topology (e.g., buck-boost regulator circuit), etc.

[0024] The output load transient of the DC-DC voltage regulator in the negative direction (e.g., load shedding, where the load is removed and the load current I LOAD decreases to zero) will usually be in the regulated output voltage V OUT This is due to: a) the finite response time of the voltage regulator to correct the amount of current delivered to the load, and b) the nearly instantaneous effect of the combination of the series resistance (ESR) and series inductance (ESL) in the output capacitor. This problem is exacerbated for inductor-based DC-DC regulators, where the inductor current I Lcannot change immediately, and the inductor current will typically continue to be delivered to the output capacitor for additional cycles until the current can be reduced to zero. This continued delivery of inductor current to the reduced load can cause the regulated output voltage to increase further, which risks violating the output voltage specification; especially if the application requires tight control of the output voltage. This positive voltage transient may cause the system to shut down due to tripping of the overvoltage monitoring circuit, or worse, may damage the circuits connected to the output node due to overvoltage stress.

[0025] Figure 2 1 shows current and voltage waveforms for a conventional buck regulator circuit experiencing a load dump (e.g., as shown in the top graph, I LOAD At time t1, from value I MAX Just before the load dump event, the inductor current waveform I L The DC-DC switching frequency shows normal ripple, while the output voltage V OUT At the same frequency, the corresponding voltage ripple is shown. This is because C OUT Experience I L The AC component (because I COUT =I L -I LOAD After t1, all inductor current 205 (including the DC component I MAX ) is delivered to the output capacitor until the inductor current 205 can drop to zero. This is true regardless of whether the buck regulator control scheme disconnects both M1 and M2 or only turns on M2. Figure 2 As shown in the bottom graph, the output voltage response to this additional current is a voltage overshoot 210. The amount of the overshoot depends on C OUT value, and the higher the C OUT The value of C will result in a reduction in voltage overshoot 215. However, the cost of bill of materials (BOM) and board space associated with increasing the output capacitance increases. In addition, because the inductor current continues to be delivered to the output node, increasing C OUT The added capacitance does not eliminate the additional overshoot, it only reduces it.

[0026] To eliminate or limit voltage overshoot, the inductor current can be diverted from the output capacitor C OUT and output node V OUT This causes the inductor current to drop to zero and the output voltage to not increase further.

[0027] Figure 3 is to operate a voltage regulator circuit (such as Figure 1Flowchart of a method for a voltage regulator circuit of a device. At 305, a switching circuit is activated and deactivated to charge and discharge an inductor to generate an output voltage, and an inductor current is provided to an output node of the voltage regulator circuit. At 310, an error signal representing a difference between a target voltage value and an output voltage is used to adjust a switching duty cycle of the switching circuit to adjust the output voltage. In some examples, PWM is used to adjust the output voltage.

[0028] At 315, the output voltage is compared to a specified maximum output voltage. The specified maximum voltage may be greater than the desired regulation voltage. At 320, the inductor current is shunted from the output node when the output voltage exceeds the specified maximum output voltage.

[0029] Return to Figure 1 In order to shunt the inductor current, the voltage regulator circuit includes a shunt circuit that shunts the inductor current from the output node and the output capacitor when the output voltage exceeds the specified maximum output voltage. The shunt circuit includes a transistor M3 connected in parallel to the inductor L. The transistor M3 is used as a shunt switch controlled by the hysteresis comparator 120. When the output voltage rises to the specified maximum output voltage value (V HI ), the output of comparator 120 is active or high. Due to its hysteresis, it will not be until the output voltage drops below V HI (For example, the desired regulation voltage level V REG ), the output of comparator 120 returns to invalid or low level.

[0030] Figure 4 Shown for Figure 1 Current and voltage waveforms of the voltage regulator circuit. Figure 4 The top graph in the figure shows the experience occurring at time t1 and Figure 2 The same voltage regulator circuit for load dump transients. Figure 4 In the I before t1 L and V OUT The waveform is also Figure 2 Immediately after t1, all inductor currents 405 (including the DC component I MAX ) is initially delivered to the output capacitor, causing V OUT However, when V OUT Rising to V HI When (in Figure 4 As shown in the bottom graph of FIG. 1 at time t2, comparator 120 trips and turns on transistor M3. M3As shown in the waveform of , the inductor current 405 is then shunted from the output capacitor and instead circulates in M3 acting as a "load dump shunt". Although M3 is on, the main control loop transistors M1 and M2 are both off. With M3 on, the inductor current can drop to zero without the output voltage 410 increasing further.

[0031] Because the circulating inductor current does not flow to the output capacitor C OUT , so it does not have to reach zero "quickly". The speed at which the circulating inductor current decays to zero depends on the size of transistor M3. A smaller M3 (i.e., a higher on-resistance R DS(ON) ) accelerates the decay to zero and is less costly in terms of silicon die area, but the size of M3 should not be too small because it must dissipate the energy E stored in the inductor (E = 1 / 2LI MAX 2 ). In addition, if the voltage drop across M3 exceeds V OUT If the diode voltage drop is added, the body diode of M2 will conduct, thus limiting the voltage drop across M3 and possibly OUT Back into the current loop. Since the changing current is multiplied by the resistor (IR) drop in M3, the decay follows an exponential curve. An example of a good performance tradeoff between cost and energy consumption is to design the size of M3 to be around 5% to 10% of the size of M2. The low hysteresis voltage level of comparator 120 should be set so that if the output voltage subsequently drops to the target voltage value V REG If a load is turned on (either due to leakage or due to a new load being turned on), M3 opens and normal control loop operation is resumed.

[0032] Figure 5 is a schematic diagram of another example of a voltage regulator circuit 500. The circuit is as Figure 1 The buck regulator circuit in Figure 1 The circuit includes an inductor 502, a top switch transistor (M1), a bottom switch transistor (M2), a comparator 520 with hysteresis, and an error amplifier 512. Figure 1 The difference is that the shunt circuit includes a current matching amplifier 522 and a shunt switch from V OUT Transistor M4 is connected to ground. The input of current matching amplifier 522 is connected to bottom switch transistor M2 and shunt switch transistor M4. The output of current matching amplifier 522 is coupled to the control gate of M4, and the current amplifier includes an enable input connected to the output of comparator 520.

[0033] Figure 6 Shown for Figure 5 The current and voltage waveforms of the voltage regulator circuit. Function and Figure 1The circuit of the voltage regulator is the same as that of the voltage regulator circuit until time t2. In the top graph, the voltage regulator circuit experiences the same Figure 4 The same load shedding transient in Figure 1 and before the load shedding transient, Figure 6 The inductor current waveform I L The normal ripple is shown at the DC-DC switching frequency. After time t1, all inductor current 605 (including the DC component I MAX ) is initially delivered to the output capacitor C OUT At time t2, when V OUT Rising to V HI , comparator 520 trips (eg, the output goes high).

[0034] At this time, the top switch transistor M1 is turned off, and the shunt switch transistor M4 is turned on, and the current matching amplifier 522 is enabled by the output of the comparator 520. The current matching amplifier 522 controls M4 to generate a positive drain current in M4 to match the negative drain current of M2. Figure 6 middle, I M4 The waveform shows the inductor current flowing through M4. To the extent that these drain currents of M2 and M4 “match”, they are delivered to the output capacitor C OUT The resulting portion of the inductor current is zero, and the output voltage 610 is proportional to V HI Compared to will not increase further, such as Figure 6 As shown in the bottom graph of . The size of transistor M4 can be the same as or proportional to M2 (for example, size (M4) = size (M2 / k), where k is a positive integer). As shown in Figure 1 In the example of OUT , and does not have to reach zero quickly. When V OUT When V drops below the low hysteresis voltage level of comparator 520, the shunt switch connection is removed and the circuit resumes normal operation.

[0035] Figure 1 and Figure 5 The circuit in the example is a buck regulator circuit. The example method of mitigating a load dump transient at the output of the circuit may be used for other types of regulator circuits.

[0036] Figure 7 is a schematic diagram of an example of a boost regulator circuit 700. In this example, an inductor 702 is coupled to an input node V of the voltage regulator circuit. INThe switch circuit includes: a first switch transistor M1, which is coupled to the switch circuit node 708 and the circuit ground node; and a second switch transistor M2, which is coupled to the output node and the switch circuit node. The gate driver of the switch circuit is not shown. The shunt switch transistor M3 is coupled in parallel to the inductor 702 and is coupled to the switch circuit node 708 and the input node V IN When the output voltage V OUT When the trip voltage of the hysteresis comparator 720 is exceeded, the shunt switch transistor M3 is turned on to circulate the inductor current and divert the inductor current from the output capacitor C OUT The output node is shunted to limit output voltage transients.

[0037] Figure 8 8 is a schematic diagram of an example of a buck-boost regulator circuit 800. In this example, an inductor 802 is coupled to a first switching circuit node 808 and a second switching circuit node 809. The switching circuit includes a first switching transistor MA coupled to an input node V IN and a first switch circuit node 808; and a second switch transistor MB, the second switch transistor coupled to the first switch circuit node 808 and the circuit ground node. The switch circuit further includes: a third switch transistor MC, the third switch transistor coupled to the second switch circuit node 809 and the circuit ground node; and a fourth switch circuit MD, the fourth switch circuit coupled to the second switch circuit node 809 and the output node V OUT The shunt switch transistor M3 is coupled to the first switch circuit node 808 and the second switch circuit node 809. As in other examples, when the output voltage V OUT When the trip voltage of the hysteresis comparator 820 is exceeded, the shunt switch transistor M3 is turned on to make the inductor current I L During a load dump transient, this shunts the inductor current away from the output capacitor and the output node to limit the output voltage.

[0038] The methods, circuits, and systems described herein provide a DC-DC regulator circuit that shunts inductor current away from the output capacitor in an accurate and safe manner to limit output voltage transients and avoid system shutdown or damage to the circuit.

[0039] Additional Description and Methods

[0040] Aspect 1 may include subject matter, such as a voltage regulator circuit, comprising: a switching circuit configured to adjust a switching duty cycle to regulate the output voltage using an error signal representing a difference between a target voltage value and an output voltage at an output node of the voltage regulator circuit; an inductor coupled to the switching circuit and configured to provide an inductor current to the output node; and a shunt circuit coupled in parallel to the inductor and configured to shunt the inductor current away from the output node when the output voltage exceeds a specified maximum output voltage.

[0041] In aspect 2, the subject matter of aspect 1 optionally includes: an output capacitor coupled to the output node; and a comparator circuit coupled to the output node and configured to compare the output voltage with the specified maximum output voltage, and to enable the shunt circuit to shunt the inductor current from the output capacitor when the output voltage exceeds the specified maximum output voltage.

[0042] In aspect 3, the subject matter of aspect 2 optionally includes a comparator circuit coupled to the output node. The shunt circuit includes a shunt switch coupled in parallel to the inductor; and the shunt switch includes a control gate coupled to the output of the comparator circuit. The comparator is optionally configured to compare the output voltage with the specified maximum output voltage and a target voltage less than the specified maximum output voltage, enable the shunt switch when the output voltage exceeds the specified maximum output voltage, and disable the shunt switch when the output voltage decreases to the target voltage after enabling the shunt switch.

[0043] In aspect 4, the subject matter of aspect 3 optionally includes the inductor being coupled to the output node, and the switch circuit comprising: a top switch circuit coupled to a switch circuit node and an input node of the voltage regulator circuit; and a bottom switch circuit coupled to the switch circuit node and a circuit ground node. The shunt switch is coupled to the inductor in parallel and to the switch circuit node and the output node.

[0044] In aspect 5, the subject matter of aspect 3 optionally includes the inductor coupled to an input node of the voltage regulator circuit. The switch circuit includes: a first switch circuit coupled to a switch circuit node and a circuit ground node; and a second switch circuit coupled to the output node and the switch circuit node. The shunt circuit is coupled to the inductor in parallel and to the switch circuit node and the input node.

[0045] In aspect 6, the subject matter of aspect 3 optionally includes a switch circuit comprising: a first switch circuit coupled to an input node of the voltage regulator circuit and a first switch circuit node; a second switch circuit coupled to the first switch circuit node and a circuit ground node; a third switch circuit coupled to a second switch circuit node and the circuit ground node; and a fourth switch circuit coupled to the second switch circuit node and the output node. The inductor and the shunt switch are coupled to the first switch circuit node and the second switch circuit node.

[0046] In aspect 7, the subject matter of aspect 1 optionally includes an output capacitor coupled to the output node; and a comparator circuit coupled to the output node. The switch circuit includes: a top switch circuit coupled to a switch circuit node and an input node of the voltage regulator circuit; and a bottom switch circuit coupled to the switch circuit node and a circuit ground node. The shunt circuit includes: a shunt switch coupled to the output node and circuit ground; and a current matching amplifier including an input coupled to the bottom switch circuit and the shunt switch, an output coupled to a control gate of the shunt switch, and an enable input. The comparator circuit is configured to compare the output voltage to the specified maximum output voltage, and to provide an enable signal to the current matching amplifier to shunt the inductor current from the output capacitor.

[0047] Aspect 8 includes subject matter such as a method of operating a voltage regulator circuit or may be optionally combined with one or any combination of Aspects 1 to 7 to include such subject matter, comprising: activating and deactivating a switching circuit to charge and discharge an inductor to generate an output voltage, and providing an inductor current to an output node of the voltage regulator circuit; adjusting a switching duty cycle of the switching circuit to regulate the output voltage using an error signal representing a difference between a target voltage value and the output voltage; comparing the output voltage to a specified maximum output voltage; and shunting the inductor current from the output node when the output voltage exceeds the specified maximum output voltage.

[0048] In aspect 9, the subject matter of aspect 8 optionally includes charging an output capacitor to generate the output voltage, and shunting the inductor current away from the output capacitor when the output voltage exceeds the specified maximum output voltage.

[0049] In aspect 10, the subject matter of aspect 9 optionally includes enabling a circuit shunt connection to shunt the current from the output capacitor when the output voltage exceeds the specified maximum output voltage, and disabling the circuit shunt connection when the output voltage decreases to a target voltage less than the specified maximum output voltage.

[0050] In aspect 11, the subject matter of one or any combination of aspects 8 to 10 optionally includes pulse width modulating the switching circuit to charge the inductor to generate an output voltage that is less than an input voltage of the voltage regulator circuit.

[0051] In aspect 12, the subject matter of one or any combination of aspects 8 to 10 optionally includes pulse width modulating the switching circuit to charge the inductor to generate an output voltage greater than an input voltage of the voltage regulator circuit.

[0052] In aspect 13, the subject matter of one or any combination of aspects 8 to 10 optionally includes forming a matching current to match the inductor current, and shunting the matching current from an output capacitor at the output node.

[0053] In aspect 14, the subject matter of aspect 13 optionally includes pulse width modulating the switching circuit to charge the inductor to generate an output voltage that is less than an input voltage of the voltage regulator circuit.

[0054] Aspect 15 includes subject matter (such as a voltage regulator circuit) or can be optionally combined with one or any combination of Aspects 1 to 14 to include such subject matter, comprising: a switching circuit, the switching circuit being configured to adjust a switching duty cycle to regulate the output voltage using an error signal representing a difference between a target voltage value and an output voltage at an output node of the voltage regulator circuit; an inductor, the inductor coupled to the switching circuit and configured to provide an inductor current to the output node; and a shunt circuit loop, the shunt circuit loop coupled to the inductor and configured to circulate the inductor current away from the output node when the output voltage exceeds a specified maximum output voltage, and to restore the inductor current to the output node when the output voltage decreases to a target voltage less than the specified maximum output voltage.

[0055] In aspect 16, the subject matter of aspect 15 optionally includes: an output capacitor coupled to the output node; and a comparator circuit coupled to the output node and configured to compare the output voltage with the specified maximum output voltage, and to enable the shunt circuit loop to shunt the inductor current from the output capacitor when the output voltage exceeds the specified maximum output voltage.

[0056] In aspect 17, the subject matter of one or both of aspects 15 and 16 optionally includes: the inductor, the inductor is coupled to the output node; the switching circuit, the switching circuit comprising: a top switching circuit, the top switching circuit is coupled to the switching circuit node and the input node of the voltage regulator circuit; and a bottom switching circuit, the bottom switching circuit is coupled to the switching circuit node and the circuit ground node; and a shunt circuit loop, the shunt circuit loop comprising a shunt switch, the shunt switch is coupled in parallel to the inductor and coupled to the switching circuit node and the output node.

[0057] In aspect 18, the subject matter of one or both of aspects 15 and 16 optionally includes: the inductor, the inductor is coupled to the input node of the voltage regulator circuit; the switching circuit, the switching circuit comprising: a first switching circuit, the first switching circuit is coupled to a switching circuit node and a circuit ground node; and a second switching circuit, the second switching circuit is coupled to the output node and the switching circuit node; and a shunt circuit loop, the shunt circuit loop comprising a shunt switch, the shunt switch is coupled in parallel to the inductor and coupled to the switching circuit node and the input node.

[0058] In aspect 19, the subject matter of one or both of aspects 15 and 16 optionally includes a switch circuit comprising: a first switch circuit coupled to an input node of the voltage regulator circuit and a first switch circuit node; a second switch circuit coupled to the first switch circuit node and a circuit ground node; a third switch circuit coupled to a second switch circuit node and the circuit ground node; and a fourth switch circuit coupled to the second switch circuit node and the output node. The inductor is coupled to the first switch circuit node and the second switch circuit node, and the shunt circuit loop includes a shunt switch coupled in parallel to the inductor and in turn coupled in parallel to the first switch circuit node and the second switch circuit node.

[0059] In aspect 20, the subject matter of aspect 15 optionally includes: an output capacitor coupled to the output node; and a switch circuit, the switch circuit including: a top switch circuit coupled to a switch circuit node and an input node of the voltage regulator circuit; and a bottom switch circuit coupled to the switch circuit node and a circuit ground node. The shunt circuit loop includes the bottom switch circuit and a shunt switch coupled to the output node and circuit ground. The subject matter further optionally includes: a current matching amplifier including an input coupled to the bottom switch circuit and the shunt switch, an output coupled to a control gate of the shunt switch, and an enable input; and a comparator circuit coupled to the output node, wherein the comparator circuit is configured to compare the output voltage to the specified maximum output voltage, and to provide an enable signal to the current matching amplifier to cause the inductor current to circulate in the shunt circuit loop and away from the output capacitor.

[0060] These non-limiting aspects may be combined in any arrangement or combination. The above detailed description includes references to the accompanying drawings that form a part of the detailed description. The accompanying drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". All publications, patents, and patent documents mentioned in this document are incorporated herein by reference in their entirety, as if individually incorporated by reference. If there is an inconsistency in usage between this document and the documents incorporated herein by reference, the usage in the incorporated references shall be considered to supplement this document; for irreconcilable inconsistencies, the usage in this document shall prevail.

[0061] In this document, as is common in patent documents, the term "a" or "an" is used to include one or more than one, independent of any other instance or usage of "at least one" or "one or more". In this document, unless otherwise indicated, the term "or" is used to represent a non-exclusive or, such that "A or B" includes: "A but not B", "B but not A", and "A and B". In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein". Moreover, in the following claims, the terms "including" and "comprising" are open-ended, i.e., systems, devices, articles, or processes that include elements other than those listed after such terms in the claims are still deemed to fall within the scope of the claims. Furthermore, in the appended claims, the terms "first", "second", and "third", etc., are used merely as labels and are not intended to impose numerical requirements on their objects. The method examples described herein may be machine or computer-implemented, at least in part.

[0062] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used when the above description is reviewed by a person of ordinary skill in the art. The abstract of the specification is provided to comply with 37 CFR § 1.72 (b) to allow readers to quickly determine the nature of the technical disclosure. It should be understood at the time of submission that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the above specific embodiments, various features may be combined together to simplify the present disclosure. This should not be interpreted as intending that the disclosed features that are not claimed for protection are essential to any claim. On the contrary, the subject matter of the invention may be less than all the features of a specific disclosed embodiment. Therefore, the following claims are thus incorporated into the specific embodiments, wherein each claim itself is a separate embodiment. The scope of this subject matter should be determined with reference to the full scope of the attached claims together with the equivalent rights enjoyed by such claims.

Claims

1. A voltage regulator circuit, comprising: a switching circuit configured to adjust a switching duty cycle to regulate the output voltage using an error signal representing a difference between a target voltage value and an output voltage at an output node of the voltage regulator circuit; an inductor coupled to the switching circuit and configured to provide an inductor current to the output node; a shunt circuit coupled in parallel to the inductor and configured to shunt the inductor current away from the output node when the output voltage exceeds a specified maximum output voltage; an output capacitor coupled to the output node; as well as a comparator circuit coupled to the output node; wherein the switch circuit comprises: a top switch circuit coupled to a switch circuit node and an input node of the voltage regulator circuit; and a bottom switch circuit coupled to the switch circuit node and a circuit ground node; The shunt circuit comprises: a shunt switch coupled to the output node and circuit ground; and a current matching amplifier comprising an input coupled to the bottom switch circuit and the shunt switch, an output coupled to a control gate of the shunt switch, and an enable input; and The comparator circuit is configured to compare the output voltage with the specified maximum output voltage and provide an enable signal to the current matching amplifier to shunt the inductor current away from the output capacitor.

2. The voltage regulator circuit according to claim 1, The comparator circuit is configured to compare the output voltage with the specified maximum output voltage and enable the shunt circuit to shunt the inductor current from the output capacitor when the output voltage exceeds the specified maximum output voltage.

3. The voltage regulator circuit according to claim 1, The comparator is configured to compare the output voltage with the specified maximum output voltage and a target voltage less than the specified maximum output voltage, enable the shunt switch when the output voltage exceeds the specified maximum output voltage, and disable the shunt switch when the output voltage decreases to the target voltage after enabling the shunt switch.

4. The voltage regulator circuit according to claim 3, Wherein the inductor is coupled to the output node.

5. The voltage regulator circuit of claim 1, wherein the comparator circuit comprises a hysteresis comparator.

6. A method of operating a voltage regulator circuit, the method comprising: activating and deactivating a switching circuit to charge and discharge an inductor to generate an output voltage and to provide an inductor current to an output node of the voltage regulator circuit; adjusting a switching duty cycle of the switching circuit to regulate the output voltage using an error signal representing a difference between a target voltage value and the output voltage; comparing the output voltage to a specified maximum output voltage; as well as shunting the inductor current from the output node through a shunt circuit when the output voltage exceeds a specified maximum output voltage; wherein the switch circuit comprises: a top switch circuit coupled to a switch circuit node and an input node of the voltage regulator circuit; and a bottom switch circuit coupled to the switch circuit node and a circuit ground node; The shunt circuit comprises: a shunt switch coupled to the output node and circuit ground; and a current matching amplifier comprising an input coupled to the bottom switch circuit and the shunt switch, an output coupled to a control gate of the shunt switch, and an enable input; and The comparator circuit is configured to compare the output voltage with the specified maximum output voltage and provide an enable signal to the current matching amplifier to shunt the inductor current away from the output capacitor.

7. The method according to claim 6, comprising: charging an output capacitor to generate the output voltage; and Wherein shunting the inductor current includes shunting the inductor current away from the output capacitor when the output voltage exceeds the specified maximum output voltage.

8. The method of claim 7 , wherein shunting the inductor current further comprises enabling a circuit shunt connection to shunt current from the output capacitor when the output voltage exceeds the specified maximum output voltage, and disabling the circuit shunt connection when the output voltage decreases to a target voltage less than the specified maximum output voltage.

9. The method of claim 6, wherein activating and deactivating the switching circuit comprises pulse width modulating the switching circuit to charge the inductor to generate an output voltage that is less than an input voltage of the voltage regulator circuit.

10. The method of claim 6, wherein activating and deactivating the switching circuit comprises pulse width modulating the switching circuit to charge the inductor to generate an output voltage greater than an input voltage of the voltage regulator circuit.

11. The method of claim 6, wherein shunting the inductor current comprises forming a matching current to match the inductor current, and shunting the matching current from an output capacitor at the output node. 12 . The method of claim 11 , wherein activating and deactivating the switching circuit comprises pulse width modulating the switching circuit to charge the inductor to generate an output voltage that is less than an input voltage of the voltage regulator circuit.

13. A voltage regulator circuit comprising: a switching circuit configured to adjust a switching duty cycle to regulate the output voltage using an error signal representing a difference between a target voltage value and an output voltage at an output node of the voltage regulator circuit; an inductor coupled to the switching circuit and configured to provide an inductor current to the output node; a shunt circuit loop coupled to the inductor and configured to circulate the inductor current away from the output node when the output voltage exceeds a specified maximum output voltage and to restore the inductor current to the output node when the output voltage decreases to a target voltage less than the specified maximum output voltage; as well as an output capacitor coupled to the output node; wherein the switch circuit comprises: a top switch circuit coupled to a switch circuit node and an input node of the voltage regulator circuit; and a bottom switch circuit coupled to the switch circuit node and a circuit ground node; wherein the shunt circuit loop includes the bottom switch circuit and a shunt switch coupled to the output node and circuit ground; The voltage regulator circuit further comprises: a current matching amplifier including an input coupled to the bottom switch circuit and the shunt switch, an output coupled to a control gate of the shunt switch, and an enable input; and a comparator circuit coupled to the output node, wherein the comparator circuit is configured to compare the output voltage to the specified maximum output voltage and to provide an enable signal to the current matching amplifier to cause the inductor current to circulate in the shunt circuit loop and away from the output capacitor.

14. The voltage regulator circuit according to claim 13, The comparator circuit is configured to compare the output voltage with the specified maximum output voltage and enable the shunt circuit loop to shunt the inductor current away from the output capacitor when the output voltage exceeds the specified maximum output voltage.

15. The voltage regulator circuit according to claim 14, Wherein the inductor is coupled to the output node.

16. The voltage regulator circuit of claim 13, wherein the comparator circuit comprises a hysteresis comparator.

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