A circuit for DC synchronous boosting

Abstract

A circuit for DC synchronous boosting comprises a boost control chip, an input power supply, an input capacitor, an energy storage inductor, an output capacitor, a load and an external programming resistor; the boost control chip comprises an overcurrent protection module and a current limiting protection module; a port LX end is connected to one end of the energy storage inductor, and the other end of the energy storage inductor is connected to a power port VCC end of the boost control chip, a positive electrode of the input capacitor and a positive electrode of the input power supply; an output port output end VOUT of the boost control chip is connected to the positive electrode of the output capacitor, and a load is connected in series between the output port output end VOUT and a ground terminal GND; an external programming resistor is connected in series between a current limiting setting end VSET of the boost control chip and a ground terminal GND; the negative electrode of the input power supply, the negative electrode of the input capacitor and the negative electrode of the output capacitor are all connected to the ground terminal GND; wherein the current limiting protection module controls the overcurrent protection module to limit the current of the load to a predetermined threshold value after the load is overcurrented, and the predetermined threshold value is related to the resistance value of the external programming resistor.

Description

Technical Field

[0001] The invention belongs to the technical field of circuits and relates to a circuit for direct current synchronous boosting. Background Art

[0002] In recent years, DC synchronous boost has been widely developed and applied as a power management product, achieving high-efficiency DC to DC power conversion and is used in various environments and occasions.

[0003] See also Figure 1 , Figure 1 The figure shows a schematic diagram of a DC synchronous boost protection circuit in the prior art. Figure 1 As shown, the LX terminal of the control chip 101 is connected to the inductor 14, and the other end of the inductor 14 is connected to the power supply terminal VCC of the chip 101, the positive electrode of the input capacitor 13 and the positive electrode of the input power supply 12; the output terminal VOUT of the chip 101 is connected to the positive electrode of the output capacitor 15, and the load 16 is connected in series between the output terminal VOUT and the ground; the negative electrode of the input power supply 12, the negative electrode of the input capacitor 13, and the negative electrode of the output capacitor 15 are all connected to the ground.

[0004] In the prior art, an operational amplifier 111 is used to perform error amplification on the output terminal VOUT, the voltage sampling signal of the output signal, and the reference voltage VREF to output a signal COMP. When FB is lower than VREF, the COMP signal rises, and when FB is higher than the reference voltage VREF, the COMP signal drops. The COMP signal is clamped at COMPMAX by a module 112 so that it cannot rise indefinitely.

[0005] The error comparator 113 compares the voltage of LX and the voltage of COMP. When the voltage of LX is higher than the voltage of COMP, PWM outputs a high level signal, and when the voltage of LX is lower than the voltage of COMP, it outputs a low level signal. When NCH is low, the output of the error comparator 113 is low.

[0006] PWM is controlled in each cycle to achieve: when COMP is lower than COMPMAX, the synchronous boost circuit is in a constant voltage output working state, and the output terminal VOUT = VREF*(1+R71 / R72); when COMP is clamped at COMPMAX, it is in current limiting mode, the output voltage drop will decrease, and the output peak current limiting point is IPK = COMP / R204.

[0007] See also Figure 2 , Figure 2 FIG. 1 is a waveform diagram of some signals of a DC synchronous boost protection circuit in the prior art during short circuit protection. Figure 2As shown, in the logic control of the logic selection module 114, the output OSC signal of the oscillator 61 is the setting signal, the output signal PWM of the error comparator 113 is the reset signal, the falling edge of OSC turns on the power N-tube 204, that is, NCH is a high-level signal, and the rising edge of PWM turns on the power N-tube 204, that is, NCH is a low-level signal; PCH is the logic inverse signal of NCH, and when the current flowing through the freewheeling P-tube 205 is lower than zero, the freewheeling P-tube is turned off, that is, PCH is a high level, and at this time, PCH has nothing to do with the logic of NCH.

[0008] However, since the prior art realizes output overcurrent protection by comparing the clamping of the error amplifier output signal COMP with the on-state voltage drop generated by the current on the power NMOS, the overcurrent protection point is affected by the on-state impedance and temperature characteristics of the power NMOS tube, so the consistency is poor, and the current limiting protection point is fixed and lacks flexibility, which has become one of the problems that technical personnel in this field need to solve urgently. Summary of the invention

[0009] In order to solve the above technical problems, the present invention proposes a new circuit for DC synchronous boosting, which can improve the consistency of current limiting protection points and short-circuit current triggering points, and can flexibly set different values ​​externally.

[0010] To achieve the above object, the technical solution of the present invention is as follows:

[0011] A circuit for DC synchronous boosting, comprising: a boost control chip, an input power supply, an input capacitor, an energy storage inductor, an output capacitor, a load and an external programming resistor; the boost control chip comprises an overcurrent protection module, a current limiting protection module, a power port VCC, a port LX, an output port output terminal VOUT, a current limiting setting terminal VSET and a ground terminal GND; the port LX terminal is connected to one end of the energy storage inductor, and the other end of the energy storage inductor is connected to the power port VCC terminal of the boost control chip, the positive electrode of the input capacitor and the positive electrode of the input power supply; the output port of the boost control chip is connected to ... The output terminal VOUT is connected to the positive electrode of the output capacitor, and a load is connected in series between the output port output terminal VOUT and the ground terminal GND; the external programming resistor is connected in series between the current limiting setting terminal VSET of the boost control chip and the ground terminal GND; the negative electrode of the input power supply, the negative electrode of the input capacitor, and the negative electrode of the output capacitor are all connected to the ground terminal GND; wherein, the current limiting protection module controls the overcurrent protection module to limit the current of the load to a predetermined threshold after the load is overcurrent, and the external programming resistor is an adjustable resistor, and the resistance value of the external programming resistor is related to the predetermined threshold.

[0012] Furthermore, the overcurrent protection module is a short-circuit comparator, and the current limiting protection module is a current limiting comparator; the boost control chip also includes a reference voltage module, a current source module, an active resistance module, a power N tube, a freewheeling P tube, a constant voltage control module, a counting module, a logic and drive module, and a feedback resistance network; wherein the reference voltage module is used to provide a reference voltage signal inside the chip, and its input signal is VCC, and its output signal is VREF; the current source module is used to provide different current source modules according to different external programming resistors, and its working power supply is VCC, The output signal is HVCL; the active resistor module generates a voltage drop through the current of the current source module, which is used as the input voltage comparison value of current limiting and short-circuit protection, and its input signal is HVCL, and the output signal is VCL; the power N tube is the main current loop of the inductor to the ground. When the current flows through this path, due to the on-resistance of the power N tube, a voltage drop is generated at the drain of the power N tube. The gate of the power N tube is connected to the output signal NCH of the N tube driving module, its source is connected to the ground terminal GND, and its drain is connected to the port LX; the freewheeling P tube is the inductor The main current path of the output terminal VOUT; the current limiting comparator is used to compare the voltage LX sampled by the power N tube with the set predetermined value VCL, and its output signal is LIM; the short-circuit comparator is used to compare the voltage LX sampled by the power N tube with the set predetermined value HVCL, and its output signal is OC; the enabling signal of the current limiting comparator and the short-circuit protection comparator is NCH, and the two comparators only work when NCH is at a high level, and their output signals are all at a low level when NCH is at a low level; the constant voltage control module is used to realize the control of output constant voltage The control module has input signals VREF and FB, and output signal PWM; the counting module is used for short-circuit triggering and output reset timing, the input signal OC, and the output signal OSP; the logic and driving module is used for logic selection of constant voltage control, current limiting and short-circuit protection, the input signals are PWM, ILIM and OSP, and the output signals are NCH and PCH; the feedback network is used to sample the voltage of the output voltage output terminal VOUT and send the signal to the constant voltage control module, the input signal is the output terminal VOUT, and the output signal is FB.

[0013] Further, the current source module includes an operational amplifier, an N driving tube, a current source generating tube and a current source mirror tube; the input of the operational amplifier is connected to the output signal VREF of the reference voltage module and the current limit setting terminal VSET, and the output of the operational amplifier is connected to the gate of the N driving tube; the drain of the N driving tube is connected to the drain of the current source generating tube, and its source is connected to the current limit setting terminal VSET; the gate and drain of the current source generating tube are connected, and its source is connected to the power supply VCC; the gate of the current source mirror tube is connected to the gate of the current source generating tube, its drain is connected to the signal HVCL, and its source is connected to the power supply terminal VCC.

[0014] Furthermore, the active resistance module is composed of a plurality of NMOS tubes connected in series between the HVCL signal and the ground terminal GND, and the gates of the plurality of NMOS tubes are all connected to the power supply terminal VCC.

[0015] Further, the counting module includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a clock generator: the input D terminal of the first D flip-flop is connected to its output QN terminal, its CLK input terminal is connected to OC, and its output signal Q1 is connected to the CLK input terminal of the second D flip-flop; the input D terminal of the second D flip-flop is connected to its output QN terminal, and its output signal Q2 is connected to the CLK input terminal of the third D flip-flop; the input D terminal of the third D flip-flop is connected to the VCC terminal of the boost control chip, and its Q terminal output signal is OSP; the output signal RB of the clock generator is connected to the RB input terminal of the three D flip-flops.

[0016] Furthermore, the logic and driving module includes an oscillator, three OR gates, an RS trigger, an N driving module, two OR gates and a P driving module; the output signal of the oscillator is OSC; the input end of the three OR gates is connected to OSP, ILIM and PWM signals, and the output end is connected to the OFF signal; the input end SET of the RS trigger is connected to the OSC signal, the input end RESET is connected to the OFF signal, the output Q end is connected to the input end of the N driving module, and the output QN end is connected to one input end of the two OR gates; the other input end of the two OR gates is connected to the signal OSP, and the output signal is connected to the input end of the P driving module; the output signal of the N driving module is NCH, and the output signal of the P driving module is PCH. The N driving module and the P driving module are used to improve the driving capability of the logic output signal so as to realize the fast switching of the power N tube and the freewheeling P tube.

[0017] Furthermore, the feedback resistor network is composed of an upper feedback resistor and a lower feedback resistor connected in series between the output terminal VOUT and the ground terminal GND of the boost control chip, and is used to proportionally sample the voltage of the output terminal VOUT, and the output signal FB is connected to the input terminal of the constant voltage control module.

[0018] It can be seen from the above technical solution that the circuit for DC synchronous boosting of the present invention can be externally programmed with a current limiting protection circuit, which has the following beneficial effects:

[0019] ①. Support the use of external resistor programming to achieve current limiting protection with different current limiting values;

[0020] ② The circuit of the present invention limits the current in each switching cycle, thereby improving the consistency of the overcurrent protection point;

[0021] ③. The circuit of the present invention can realize short-circuit monitoring and protection of the output end. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The structure diagram of the DC synchronous boost circuit in the prior art embodiment is shown as follows

[0023] Figure 2 The figure shows the waveform diagram of the signal of the prior art DC synchronous boost circuit during short circuit protection.

[0024] Figure 3 The structure diagram of the DC synchronous boost circuit in the embodiment of the present invention is shown as follows

[0025] Figure 4 The waveform diagram of some signals in the circuit during current limiting protection in the embodiment of the present invention is shown as follows

[0026] Figure 5 FIG. 1 is a schematic diagram showing waveforms of some signals of a circuit for DC synchronous boosting during short circuit protection in an embodiment of the present invention.

[0027] Component number description

[0028] 11. Control chip

[0029] 12 DC voltage source

[0030] 13 Input Capacitance

[0031] 14 Inductor

[0032] 15 Output Capacitor

[0033] 16 Load

[0034] 17 External resistor

[0035] 101 Prior Art Control Chip

[0036] 111 Error Operational Amplifier

[0037] 112 Clamp Module

[0038] 113 Error Comparator

[0039] 114 Logic selection module

[0040] 201 Reference Voltage Module

[0041] 202 Current Source Module

[0042] 203 Active resistor module

[0043] 204 Power N tube

[0044] 205 Freewheeling P tube

[0045] 206 Current Limit Protection Comparator

[0046] 207 Short-circuit protection comparator

[0047] 208 Constant pressure control module

[0048] 209 Counting module

[0049] 210 Logic and driver module

[0050] 211 Feedback Resistor Network

[0051] 31 Operational Amplifier

[0052] 32 N drive tube

[0053] 33 Current source module generates tube

[0054] 34 Current source module mirror tube

[0055] 41 to 44 Active resistor NMOS tube

[0056] 51 The first D flip-flop

[0057] 52 Second D flip-flop

[0058] 53 The third D flip-flop

[0059] 54 Clock Generator

[0060] 61 Oscillator

[0061] 62 Triple OR Gate

[0062] 63 RS flip-flop

[0063] 64 N drive module

[0064] 65 Binary OR Gate

[0065] 66 P driver module

[0066] 71 Upper feedback resistor

[0067] 72 Lower feedback resistor DETAILED DESCRIPTION

[0068] The following is combined with Figure 3-5 , the specific implementation modes of the present invention are further described in detail.

[0069] See also Figure 3 , Figure 3 FIG. 1 is a schematic diagram of a DC synchronous boost circuit according to an embodiment of the present invention. Figure 3 As shown, the DC synchronous boost circuit of the present invention includes a boost control chip 11, an input power supply 12, an input capacitor 13, an energy storage inductor 14, an output capacitor 15, a load 16 and an external programming resistor 17.

[0070] The boost control chip 11 includes an overcurrent protection module 207, a current limiting protection module 206, a power port VCC, a port LX, an output port output terminal VOUT, a current limiting setting terminal VSET and a ground terminal GND; the port LX terminal is connected to one end of the energy storage inductor, and the other end of the energy storage inductor 14 is connected to the power port VCC terminal of the boost control chip 11, the positive electrode of the input capacitor 13 and the positive electrode of the input power supply; the output port output terminal VOUT of the boost control chip 11 is connected to the positive electrode of the output capacitor 15, and the output port output terminal VOUT is connected to the positive electrode of the output capacitor 15. A load is connected in series between T and the ground terminal GND; the external programming resistor is connected in series between the current limiting setting terminal VSET of the boost control chip 11 and the ground terminal GND; the negative electrode of the input power supply, the negative electrode of the input capacitor 13, and the negative electrode of the output capacitor 15 are all connected to the ground terminal GND; wherein, the current limiting protection module 206 controls the overcurrent protection module 207 to limit the current of the load 16 to a predetermined threshold after the load 16 overcurrents, and the external programming resistor 17 is an adjustable resistor, and the resistance value of the external programming resistor 17 is related to the predetermined threshold.

[0071] The overcurrent protection module is a short-circuit comparator 207, and the current limiting protection module is a current limiting comparator 206; the boost control chip 11 also includes a reference voltage module 201, a current source module 202, an active resistance module 203, a power N tube 204, a freewheeling P tube 205, a constant voltage control module 208, a counting module 209, a logic and drive module 210, and a feedback resistance network 211.

[0072] The reference voltage module 201 is used to provide a reference voltage signal inside the chip, and its input signal is VCC and its output signal is VREF; the current source module 202 is used to provide different current sources according to different external programming resistors 17, and its working power supply is VCC and its output signal is HVCL; the active resistance module 203, through the current of the current source 202, generates a voltage drop, and is used for the input voltage comparison value of current limiting and short-circuit protection, and its input signal is HVCL and its output signal is VCL; the power N tube 204 is an inductor 14 is the main current loop from the inductor 14 to the ground. When the current flows through this path, due to the on-resistance of the power N-tube 204, a voltage drop is generated at the drain of the power N-tube 204. The gate of the power N-tube 204 is connected to the output signal NCH of the N-tube driving module 64, its source is connected to the ground terminal GND of the boost control chip 11, and its drain is connected to the LX terminal of the boost control chip 11; the freewheeling P-tube 205 is the main current path from the inductor 14 to the output terminal VOUT output terminal; the current limiting comparator 206 is used to sample the voltage L X is compared with the set predetermined value VCL, and its output signal is LIM; the short-circuit comparator 207 is used to compare the voltage LX sampled by the power N tube 204 with the set predetermined value HVCL, and its output signal is OC; the enabling signal of the current limiting comparator 206 and the short-circuit protection comparator 207 is NCH, and these two comparators only work when NCH is at a high level, and their output signals are all at a low level when NCH is at a low level; the constant voltage control module 208 is used to realize the control of output constant voltage, and its input signals are VREF and FB, The output signal is PWM; the counting module 209 is used for short-circuit triggering and output reset timing, its input signal is OC, and its output signal is OSP; the logic and driving module 210 is used for the logic selection of constant voltage control, current limiting and short-circuit protection, its input signals are PWM, ILIM and OSP, and its output signals are NCH and PCH; the feedback network 211 is used to sample the voltage of the output voltage output terminal VOUT and send the signal to the constant voltage control module 208, its input signal is the output terminal VOUT, and the output signal is FB.

[0073] In an embodiment of the present invention, the current source module 202 includes: an operational amplifier 31, an N driver tube 32, a current source generating tube 33 and a current source mirror tube 34; the input of the operational amplifier 31 is connected to the output signal VREF of the reference voltage module 201 and the current limit setting terminal VSET of the boost control chip 11, and the output of the operational amplifier 31 is connected to the gate of the N driver tube 32; the drain of the N driver tube 32 is connected to the drain of the current source generating tube 33, and its source is connected to the VSET terminal of the boost control chip 11; the gate of the current source generating tube 33 is connected to the drain, and its source is connected to the power supply terminal VCC of the boost control chip 11; the gate of the current source mirror tube 34 is connected to the gate of the current source generating tube 33, its drain is connected to the signal HVCL, and its source is connected to the power supply terminal VCC of the boost control chip 11.

[0074] In an embodiment of the present invention, the active resistance module 203 is composed of a plurality of N-tubes (for example, 4, 41, 42, 43 and 44) ​​connected in series between the HVCL signal and the ground terminal GND, and the gates of the 4 N-tubes are all connected to the power terminal VCC. In the layout design of the chip, these series-connected N-tubes are close to the power N-tube 204 and form a proportional match.

[0075] In an embodiment of the present invention, the counting module 209 includes a first D flip-flop 51, a second D flip-flop 52, a third D flip-flop 53 and a clock generator 54: the input D terminal of the first D flip-flop 51 is connected to its output QN terminal, its CLK input terminal is connected to OC, and its output signal Q1 is connected to the CLK input terminal of the second D flip-flop 52; the input D terminal of the second D flip-flop 52 is connected to its output QN terminal, and its output signal Q2 is connected to the CLK input terminal of the third D flip-flop 53; the input D terminal of the third D flip-flop 53 is connected to the VCC terminal of the boost control chip 11, and its Q terminal output signal is OSP; the output signal RB of the clock generator 54 is connected to the RB input terminals of the three D flip-flops.

[0076] In the embodiment of the present invention, the logic and driving module 210 includes an oscillator 61, a triple OR gate 62, an RS trigger 63, an N driving module 64, a double OR gate 65 and a P driving module 66; the output signal of the oscillator 61 is OSC; the input end of the triple OR gate 62 is connected to the OSP, ILIM and PWM signals, and the output end thereof is connected to the OFF signal; the input end SET of the RS trigger 63 is connected to the OSC signal, the input end RESET of the RS trigger 63 is connected to the OFF signal, the output Q end thereof is connected to the input end of the N driving module 64, and the output QN end thereof is connected to one input end of the double OR gate 65; the other input end of the double OR gate 65 is connected to the signal OSP, and the output signal thereof is connected to the input end of the P driving module 66; the output signal of the N driving module 64 is NCH, and the output signal of the P driving module 66 is PCH. The N driving module 64 and the P driving module 66 are used to improve the driving capability of the logic output signal so as to realize the fast switching of the power N tube 204 and the freewheeling P tube 205.

[0077] In an embodiment of the present invention, the feedback resistor network 211 is composed of an upper feedback resistor 71 and a lower feedback resistor 72 connected in series between the output terminal VOUT and the ground terminal GND of the boost control chip 11, and is used to proportionally sample the voltage of the output terminal VOUT, and the output signal FB is connected to the input terminal of the constant voltage control module 208.

[0078] The series resistor 17 between the VSET terminal of the boost control chip 11 and the ground is R17, the output voltage of the reference voltage module 201 is VREF, the two inputs of the operational amplifier 31 are virtually shorted, so the voltage value of VSET is equal to VREF, the current flowing through the current source generating tube 33 is IM33=VREF / R17, the current source mirror tube 34 is m times the current source generating tube, then the current flowing through the current source mirror tube 34 is IM34=m*VREF / R17; the active resistors formed by the series MOS tubes 41, 42, 43 and 44 are R41, R42, R43, R44 respectively, when the current of the current mirror 202 flows through the active resistor 203, the generated voltage output signal is:

[0079] VCL=(R43+R44)*m*VREF / R17

[0080] HVCL=(R41+R42+R43+R44)*m*VREF / R17.

[0081] See also Figure 4 and Figure 5 , Figure 4 FIG. 1 is a schematic diagram showing waveforms of some signals of the circuit during current limiting protection in an embodiment of the present invention. Figure 5The waveform diagram of some signals of the circuit for DC synchronous boosting in the embodiment of the present invention during short circuit protection is shown. As shown in the figure, when the LX voltage of the current limiting comparator 206 increases and the LX voltage is higher than VCL, the output signal ILIM changes from low level to high level, triggering the logic and driving module 210, so that its output signal NCH changes from high level to low level, and PCH changes from high level to low level, that is, the power N tube 204 is open, and the freewheeling P tube 205 is turned on, so that the current on the inductor 14 changes from rising to falling, and the on-resistance of the power N tube 204 is R204, then the peak current limit point of the inductor 14 is ILX_PK=VCL / R204, that is:

[0082] ILX_PK=(R43+R44)*m*VREF / (R17*R204);

[0083] When the LX voltage of the short-circuit comparator 207 rises and is higher than HVCL, the output signal OC changes from a low level to a high level, triggering the counting module 209. After 4 cycles of continuous triggering of OSC, the output signal OSP of the counting module 209 jumps from a low level to a high level and is maintained, then NCH is locked at a low level, and PCH is locked at a high level, that is, the power N tube 204 and the freewheeling P tube 205 are both open circuits, and the current of the inductor 14 will drop to zero, realizing output short-circuit protection. The current point that triggers the short-circuit counting protection is:

[0084] ILX_SHORT=(R41+R42+R43+R44)*m*VREF / (R17*R204)

[0085] When the short-circuit protection is triggered, it can be reset according to different clock reset signals RB to re-detect whether the output is short-circuited; since R41~R44 and R204 are the same type of resistors, and are laid out close and matched in the layout, their deviation characteristics can be offset, VREF is a high-precision voltage signal after adjustment, and R17 is an external resistor 17 with high precision and good temperature characteristics, so the consistency of the current limiting protection point and the short-circuit current trigger point is very high.

[0086] In summary, the DC synchronous boost circuit of the present invention can improve the consistency of the current limiting protection point and the short-circuit current triggering point through an externally programmable current limiting protection circuit, and can flexibly set different values ​​externally.

[0087] The above-described embodiments are only preferred embodiments of the present invention, and the embodiments are not intended to limit the patent protection scope of the present invention. Therefore, any equivalent structural changes made using the description and drawings of the present invention should also be included in the protection scope of the present invention.

Claims

1. A circuit for DC synchronous boosting, characterized in that: include: A boost control chip, an input power supply, an input capacitor, an energy storage inductor, an output capacitor, a load and an external programming resistor; the boost control chip includes an overcurrent protection module, a current limiting protection module, a power supply terminal VCC, a port LX, an output terminal VOUT, a current limiting setting terminal VSET and a ground terminal GND; the port LX terminal is connected to one end of the energy storage inductor, and the other end of the energy storage inductor is connected to the power supply terminal VCC of the boost control chip, the positive electrode of the input capacitor and the positive electrode of the input power supply; the output terminal VOUT of the boost control chip is connected to the positive electrode of the output capacitor, and the load is connected in series between the output terminal VOUT and the ground terminal GND; the external programming resistor is connected in series between the current limiting setting terminal VSET of the boost control chip and the ground terminal GND; the negative electrode of the input power supply, the negative electrode of the input capacitor and the negative electrode of the output capacitor are all connected to the ground terminal GND; Wherein, the current limiting protection module controls the overcurrent protection module to limit the current of the load to a predetermined threshold value after the load is overcurrent, the external programming resistor is an adjustable resistor, and the resistance value of the external programming resistor is related to the predetermined threshold value; The overcurrent protection module is a short-circuit comparator, and the current limiting protection module is a current limiting comparator; the boost control chip also includes a reference voltage module, a current source module, an active resistance module, a power N tube, a freewheeling P tube, a constant voltage control module, a counting module, a logic and drive module, and a feedback resistance network; the current source module is used to provide different current source modules according to different external programming resistors, and its working power supply is VCC and its output signal is HVCL; the reference voltage module is used to provide a reference voltage signal inside the chip, and its input signal is VCC and its output signal is V REF; the active resistor module generates a voltage drop through the current of the current source module, which is used as the input voltage comparison value for current limiting and short-circuit protection, and its input signal is HVCL, and its output signal is VCL; the power N tube is the main current loop from the inductor to the ground. When the current flows through this path, due to the on-resistance of the power N tube, a voltage drop is generated at the drain of the power N tube. The gate of the power N tube is connected to the output signal NCH of the N tube driving module, its source is connected to the ground terminal GND, and its drain is connected to the port LX; the freewheeling P tube is an inductor to the output terminal VO The main current path of the UT; the current limiting comparator is used to compare the voltage LX sampled by the power N tube with the set predetermined value VCL, and its output signal is ILIM; the short-circuit comparator is used to compare the voltage LX sampled by the power N tube with the set predetermined value HVCL, and its output signal is OC; the enabling signal of the current limiting comparator and the short-circuit comparator is NCH, and the two comparators only work when NCH is at a high level, and their output signals are all at a low level when NCH is at a low level; the constant voltage control module is used to realize the control of the output constant voltage, and its output The input signals are VREF and FB, and the output signal is PWM; the counting module is used for short-circuit triggering and output reset timing, and its input signal is OC, and its output signal is OSP; the logic and driving module is used for the logic selection of constant voltage control, current limiting and short-circuit protection, and its input signals are PWM, ILIM and OSP, and its output signals are NCH and PCH; the feedback resistor network is used to sample the voltage of the output voltage output terminal VOUT and send the signal to the constant voltage control module, and its input signal is the output terminal VOUT, and the output signal is FB; The current source module includes an operational amplifier, an N-type driving tube, a current source generating tube and a current source mirror tube; the input of the operational amplifier is connected to the output signal VREF of the reference voltage module and the current limit setting terminal VSET, and the output of the operational amplifier is connected to the gate of the N-type driving tube; the drain of the N-type driving tube is connected to the drain of the current source generating tube, and its source is connected to the current limit setting terminal VSET; the gate and drain of the current source generating tube are connected, and its source is connected to the power supply terminal VCC; the gate of the current source mirror tube is connected to the gate of the current source generating tube, its drain is connected to the signal HVCL, and its source is connected to the power supply terminal VCC; The active resistance module is composed of a plurality of NMOS tubes connected in series between the HVCL signal and the ground terminal GND, and the gates of the plurality of NMOS tubes are all connected to the power supply terminal VCC.

2. The circuit for DC synchronous boosting according to claim 1, characterized in that: The counting module includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a clock generator: the input D terminal of the first D flip-flop is connected to its output QN terminal, its CLK input terminal is connected to OC, and its output signal Q1 is connected to the CLK input terminal of the second D flip-flop; the input D terminal of the second D flip-flop is connected to its output QN terminal, and its output signal Q2 is connected to the CLK input terminal of the third D flip-flop; the input D terminal of the third D flip-flop is connected to the power supply terminal VCC of the boost control chip, and its Q terminal output signal is OSP; the output signal RB of the clock generator is connected to the RB input terminal of the three D flip-flops.

3. The circuit for DC synchronous boosting according to claim 1, characterized in that: The logic and driving module includes an oscillator, a triple OR gate, an RS trigger, an N driving module, a dual OR gate and a P driving module; the output signal of the oscillator is OSC; the input end of the triple OR gate is connected to OSP, ILIM and PWM signals, and the output end is connected to the OFF signal; the input end SET of the RS trigger is connected to the OSC signal, the input end RESET is connected to the OFF signal, the output Q end is connected to the input end of the N driving module, and the output QN end is connected to one input end of the dual OR gate; the other input end of the dual OR gate is connected to the signal OSP, and the output signal is connected to the input end of the P driving module; the output signal of the N driving module is NCH, and the output signal of the P driving module is PCH. The N driving module and the P driving module are used to improve the driving capability of the logic output signal so as to realize the fast switching of the power N tube and the freewheeling P tube.

4. The circuit for DC synchronous boosting according to claim 1, characterized in that: The feedback resistor network is composed of an upper feedback resistor and a lower feedback resistor connected in series between the output terminal VOUT and the ground terminal GND of the boost control chip, and is used to proportionally sample the voltage of the output terminal VOUT. The output signal FB is connected to the input terminal of the constant voltage control module.

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