Systems that provide bidirectional power flow and power regulation for low-voltage to high-voltage applications

Abstract

A system providing bidirectional power flow and power regulation for high-voltage applications. The system includes a normally-off four-quadrant power electronic switch having two gates and two normally-on junction field-effect transistors (JFETs). The normally-off 4Q switch and two normally-off JFETs are coupled to each other in a double-cascaded configuration.

Description

Technical Field

[0001] This invention relates to a system for providing bidirectional power flow and power regulation for high-voltage applications. Background Technology

[0002] It is known to use power semiconductor switching devices, such as four-quadrant switches, to conduct current in both directions and block voltage for both positive and negative polarities.

[0003] No single device possesses these characteristics, so four-quadrant switches are typically constructed by combining available power electronics in an appropriate manner. For example, an anti-series connection of two MOSFETs (and their body diode) can form a four-quadrant switch.

[0004] However, it is known to control the cascading on and off using a more advanced cascaded structure of bipolar normally-off semiconductors or high-voltage normally-on JFETs and low-voltage normally-off MOSFETs.

[0005] Document EP2707959A1 describes a fully controlled bidirectional power switch that can be used in devices such as AC-AC matrix converters to provide higher operating efficiency for the converter compared to conventional DC-linked AC-AC converters.

[0006] However, these solutions are not entirely satisfactory.

[0007] This configuration results in high conduction losses for the entire switch.

[0008] The present invention aims to solve the problem of conduction loss. Summary of the Invention

[0009] For this purpose, the present invention relates to a system for providing bidirectional power flow and power regulation for low-voltage to high-voltage applications, the system comprising:

[0010] • A normally-off four-quadrant (4Q) power electronic switch with two gates; and

[0011] • Two normally-on junction field-effect transistors (JFETs);

[0012] The normally open 4Q switch and the two normally open JFETs are coupled to each other in a cascaded configuration.

[0013] Within the meaning of this invention, low voltage refers to a voltage below 1500V.

[0014] Within the meaning of this invention, high voltage refers to a voltage higher than 1500V.

[0015] This configuration, particularly the normally-off 4Q switch coupled with JFETs, allows for low on-state and switching losses. Indeed, an advantage of the 4Q switch is that this structure enables the sharing of the active region, for example, between different applications.

[0016] This configuration, especially the normally-off 4Q switch coupled with JFETS, allows for high semiconductor utilization.

[0017] This configuration, especially the normally-off 4Q switch coupled with JFETS, allows for high power density.

[0018] In this embodiment, the normally off 4Q switch is used as the control switch for the cascade.

[0019] This configuration, more specifically, using a normally off 4Q switch as the cascaded control switch, allows for low power loss even in high-voltage applications.

[0020] According to an embodiment, each of two normally-on JFETs coupled to each other via a normally-off 4Q switch is connected to at least one other normally-on JFET in a cascaded manner.

[0021] This configuration allows for very low on-state and switching losses in high-voltage applications.

[0022] According to an embodiment, the normally-on JFET is made of silicon carbide (SiC).

[0023] According to an embodiment, the normally-through JFET is made of diamond (C).

[0024] According to an embodiment, the normally-on JFET is made of silicon (Si).

[0025] According to an embodiment, the normally open 4Q switch is a monolithic bidirectional power electronic switch.

[0026] According to an embodiment, the normally off 4Q switch comprises a wide bandgap semiconductor material.

[0027] Such an embodiment allows the system to be used at high temperatures such as 300°C.

[0028] Such an implementation allows the system to be used at high voltages.

[0029] Such an implementation allows the system to be used at high frequencies.

[0030] According to an embodiment, the wide bandgap semiconductor material is aluminum gallium nitride / gallium nitride (AIGaN / GaN).

[0031] According to an embodiment, the wide-bandgap semiconductor material is silicon carbide (SiC).

[0032] According to an embodiment, the wide-bandgap semiconductor material is diamond (C).

[0033] According to an embodiment, each of the two normally-on JFETs is coupled to each other by a normally-off 4Q switch across the bias circuit (20), for example, the bias circuit (20) is configured to ensure that the voltage across the system is within a safe range.

[0034] This configuration allows for the establishment of appropriate operating conditions within the electronic components.

[0035] According to an embodiment, each bias circuit includes a Zener diode (22) mounted in parallel with a capacitor (24) and a resistor (26).

[0036] According to an embodiment, the breakdown voltage of the Zener diode is selected to be equal to each of the two normally-on JFET threshold voltages, thereby allowing the first gate-source junction to have a voltage equal to zero. Therefore, when the system is gated on, as the second gate-source junction discharges toward zero volts through the system parallel resistor and capacitor, the voltage across the system drops to zero, thereby allowing connected devices to be switched on.

[0037] According to an embodiment, the parallel resistor and capacitor have capacitance that allows a low-impedance path during switching, thereby enabling the connected device to be switched on more quickly.

[0038] This configuration allows for a smaller current requirement compared to during switching, thus allowing resistors on the order of several thousand ohms.

[0039] According to the embodiment, the higher the resistance value of the resistor, the more it ensures that the leakage current remains within acceptable limits.

[0040] According to an embodiment, each bias circuit includes a Zener diode mounted in series with a capacitor, the capacitor itself being mounted in parallel with a resistor.

[0041] According to an embodiment, the resistor and capacitor have capacitance that allows a low-impedance path during switching transitions, thereby enabling faster switching on of the connected devices.

[0042] According to an embodiment, a Zener diode is connected across the gate-source junction, thus allowing the cutoff voltage to be clamped to a threshold and limiting the gate-source voltage of the two normally off JFETs in the on state to the forward voltage drop of the Zener diode.

[0043] According to the embodiment, even though a capacitor across the resistor helps accelerate switching, a high resistor value negatively impacts switching speed and leakage current in the off-state. Furthermore, since the capacitor is active during switching, it reduces control over the switching speed.

[0044] According to an embodiment, each bias circuit includes N-type metal-oxide-semiconductor logic (NMOS).

[0045] Such an embodiment allows electrons to be conducted between n-type "source" and "drain" terminals.

[0046] According to an embodiment, each bias circuit includes a Zener diode mounted in parallel with the NMOS and a resistor mounted in series with the NMOS.

[0047] According to the embodiment, when the system is turned off, the first NMOS is gated off, thereby blocking the voltage across each parallel Zener diode. Therefore, there is no bias current requirement for each series resistor.

[0048] Therefore, the resistance values ​​of each series resistor can be kept low, or they can be completely removed to achieve maximum switching speed. Such an embodiment ensures a very low impedance discharge path to the gate-source capacitance during turn-on transitions, without limitation on turn-on speed.

[0049] According to an embodiment, the capacitor and resistor across the Zener diode can also be removed.

[0050] According to the embodiment, the gate of the NMOS device can be connected to the corresponding gate of the system. This means that no auxiliary circuitry is required due to the active NMOS switching device. Therefore, it can be used like other four-quadrant device configurations, offering the advantages of reduced losses and better utilization of semiconductors, as previously described.

[0051] According to the embodiments, the resistance of each resistor allows the switching to be controlled based on application requirements. For example, for high-speed applications, a resistance value of less than 10 ohms can be selected.

[0052] For example, in electrical equipment applications where it is desirable to slow down switching to minimize stress on system components, a resistance value greater than 100 ohms can be selected.

[0053] According to the embodiments, NMOS devices are low-voltage, low-current devices, and their installation and use are very simple.

[0054] According to embodiments, the system can be used in a variety of applications, such as photovoltaic inverters, motor drives, and uninterruptible power supplies for data centers.

[0055] It can combine the different incompatible aspects defined above. Attached Figure Description

[0056] The invention will be better understood from the following detailed description with reference to the accompanying drawings, in which:

[0057] [ Figure 1An embodiment of a four-quadrant power electronic switch according to the present invention is shown;

[0058] [ Figure 2 The system shown is a cascaded configuration according to the present invention;

[0059] [ Figure 3 The system in a super-cascade configuration according to the present invention is shown;

[0060] [ Figure 4 The diagram illustrates a system according to the invention, including a bias circuit having components mounted in parallel;

[0061] [ Figure 5 The diagram illustrates a system according to the invention including a bias circuit having components mounted in series and parallel;

[0062] [ Figure 6 A system according to the invention includes a bias circuit having components mounted in series and parallel; and

[0063] [ Figure 7 The simulation results of the system according to the present invention are shown. Detailed Implementation

[0064] Figure 2 The invention relates to a system for providing bidirectional power flow and power regulation for low-voltage to high-voltage applications, the system comprising a normally off four-quadrant (4Q) power electronic switch with two gates.

[0065] Within the meaning of this invention, low voltage refers to a voltage below 1500V.

[0066] Within the meaning of this invention, high voltage refers to a voltage higher than 1500V.

[0067] Figure 1 Some examples of possible embodiments of the 4Q switch are shown.

[0068] According to an embodiment, the normally open 4Q switch is a monolithic bidirectional power electronic switch. This configuration reduces system losses.

[0069] According to an embodiment, the normally off 4Q switch comprises a wide bandgap semiconductor material.

[0070] Such an embodiment allows the system to be used at high temperatures such as 300°C.

[0071] Such an implementation allows the system to be used at high voltages.

[0072] Such an implementation allows the system to be used at high frequencies.

[0073] According to embodiments, the wide bandgap semiconductor material is, for example, aluminum gallium nitride / gallium nitride (AIGaN / GaN), silicon carbide (SiC), or diamond (C).

[0074] The system also includes two normally-on junction field-effect transistors (JFETs), wherein the normally-off 4Q switch and the two normally-off JFETs are coupled to each other in a double-cascaded configuration. The normally-off 4Q switch is used as the control switch for the cascade.

[0075] This configuration, more specifically, using a normally off 4Q switch as the cascaded control switch, allows for low power loss even in high-voltage applications.

[0076] This configuration, particularly the normally-off 4Q switch coupled with a JFET, allows for low on-state and switching losses. Indeed, one advantage of the 4Q switch is that this structure enables the sharing of the active region, for example, between different applications.

[0077] Due to the low on-resistance of the JFET, the resistance of the normally off 4Q switch can increase or even dominate the overall resistance of the system.

[0078] This configuration, especially the normally-off 4Q switch coupled with a JFET, allows for high semiconductor utilization.

[0079] This configuration, especially the normally-off 4Q switch coupled with a JFET, allows for high power density.

[0080] In another embodiment, such as Figure 3 As shown, each of the two normally-on JFETs coupled to each other by a normally-off 4Q switch is connected to at least one other normally-on JFET in a cascaded manner.

[0081] This configuration allows for very low on-state and switching losses in high-voltage applications.

[0082] According to embodiments, for example, the normally-on JFET is made of silicon carbide (SiC), or the normally-on JFET is made of diamond (C), or the normally-on JFET is made of silicon (Si).

[0083] like Figure 4 , Figure 5 and Figure 6 As shown, according to an embodiment, each of the two normally-on JFETs in the system is coupled to each other via a normally-off 4Q switch across a bias circuit 20, which is configured to ensure that the voltage across the system is within a safe range. This configuration ensures reliable operation. This configuration allows for the establishment of appropriate operating conditions in the electronic components.

[0084] Figure 4A first example of a bias circuit is shown, which includes a Zener diode 22 mounted in parallel with a capacitor 24 and a resistor 26.

[0085] According to an embodiment, the breakdown voltage of Zener diode 22 is selected to be equal to each of the two normally-on JFET threshold voltages, thereby allowing the first gate-source junction to have a voltage equal to zero.

[0086] Therefore, when the system is turned on, as the second gate-source junction discharges toward zero volts through the system and the parallel resistor 26 and capacitor 24, the voltage across the system drops to zero, thereby allowing the connected devices to be turned on.

[0087] According to an embodiment, the parallel resistor 26 and capacitor 24 have capacitance that allows a low-impedance path during switching, thereby enabling faster switching on of the connected devices. This configuration allows for a smaller current requirement compared to during switching, and therefore allows the resistor 26 to be on the order of several thousand ohms.

[0088] According to the embodiment, the higher the resistance value of resistor 26, the more it ensures that the leakage current remains within acceptable limits.

[0089] Figure 5 A second example of a bias circuit 20 is shown, which includes a Zener diode 22 mounted in series with a capacitor 24, the capacitor 24 itself being mounted in parallel with a resistor 26. According to an embodiment, the resistor 26 and the capacitor 24 have capacitance that allows a low-impedance path during switching transitions, thereby enabling faster switching of connected devices.

[0090] According to the embodiment, the Zener diode 22 is connected across the gate-source junction, thus allowing the cutoff voltage to be clamped to a threshold and limiting the gate-source voltage of the two normally off JFETs in the on state to the forward voltage drop of the Zener diode 22.

[0091] According to the embodiment, even though the capacitor across resistor 26 helps accelerate switching, the high resistance of resistor 26 negatively impacts switching speed and leakage current in the off-state. Furthermore, since capacitor 24 is active during switching, control over the switching speed is reduced.

[0092] Figure 6 A second example of the bias circuit 20 is shown, which includes a Zener diode 22 mounted in parallel with an N-type metal-oxide-semiconductor logic NMOS 28 and a resistor 26 mounted in series with the NMOS 28. The use of the NMOS allows electrons to be conducted between the n-type "source" and "drain" terminals.

[0093] According to the embodiment, when the system is turned off, the first NMOS 28 is turned off, thereby blocking the voltage across each of the parallel Zener diodes 22. Therefore, there is no bias current requirement for each series resistor 26.

[0094] Therefore, the resistance values ​​of each series resistor 26 can be kept low, or they can be completely removed to achieve maximum switching speed. This embodiment ensures a very low impedance discharge path to the gate-source capacitance during turn-on transitions, without limitation on turn-on speed. Therefore, according to this embodiment, the capacitor and resistors across the Zener diode can also be removed.

[0095] According to the embodiment, the gate of the NMOS 28 device can be connected to the corresponding gate of the system. This means that no auxiliary circuitry is required due to the active NMOS 28 switching device. Therefore, it can be used like other four-quadrant device configurations, offering the advantages of reduced losses and better utilization of semiconductors, as previously described.

[0096] According to an embodiment, the resistance of each resistor 26 allows for control of switching transitions based on application requirements. For example, for high-speed applications, a resistance value of less than 10 ohms can be selected. For example, for electrical applications where it is desirable to slow down switching transitions to minimize stress on system components, a resistance value of more than 100 ohms can be selected.

[0097] According to the embodiments, the NMOS 28 device is low-voltage, low-current, and its installation and use are very simple.

[0098] Figure 7 Shown according to Figure 6 The switching simulation results of the system in the illustrated embodiment, wherein the bias circuit 20 includes a Zener diode 22 mounted in parallel with an N-type metal-oxide-semiconductor logic NMOS 28 and a resistor 26 mounted in series with the NMOS 28.

[0099] The simulation shows the switching waveform, and more specifically, it shows the connection to and from the switch according to... Figure 6 How fast can the devices in the system of the illustrated embodiment be?

[0100] Of course, the present invention is not limited to the embodiments shown and described above, but covers all variations.

Claims

1. A system for providing bidirectional power flow and power regulation for low-voltage to high-voltage applications, the system comprising: • A normally off four-quadrant 4Q power semiconductor switch with two gate terminals and a first conductive terminal and a second conductive terminal; as well as • A first normally-on junction field-effect transistor (JFET) and a second normally-on junction field-effect transistor (JFET), each having a gate terminal and a first conductive terminal and a second conductive terminal; The 4Q switch is coupled to each of the first JFET and the second JFET in a cascaded configuration. The first conductive terminal of the 4Q switch is coupled to the first conductive terminal of the first JFET and to the gate terminal of the second JFET. The second conductive terminal of the 4Q switch is coupled to the first conductive terminal of the second JFET and to the gate terminal of the first JFET.

2. The system according to claim 1, wherein, Each of the first JFET and the second JFET is connected in series with at least another corresponding normally-on JFET, the series-connected JFETs having interconnected gate terminals, and a second conductive terminal of each of the first JFET and the second JFET is connected to a conductive terminal of the other corresponding JFET.

3. The system according to claim 1 or 2, wherein, The JFET is made of silicon carbide (SiC).

4. The system according to claim 1 or 2, wherein, The JFET is made of diamond (C).

5. The system according to claim 1 or 2, wherein, The JFET is made of silicon (Si).

6. The system according to claim 1 or 2, wherein, The 4Q switch is a monolithic bidirectional power semiconductor switch.

7. The system according to claim 1 or 2, wherein, The 4Q switch comprises a wide-bandgap semiconductor material.

8. The system according to claim 7, wherein, The wide bandgap semiconductor material is aluminum gallium nitride / gallium nitride (AIGaN / GaN).

9. The system according to claim 7, wherein, The wide-bandgap semiconductor material is silicon carbide (SiC).

10. The system according to claim 7, wherein, The wide-bandgap semiconductor material is diamond (C).

11. The system according to claim 1 or 2, wherein, The gate terminals of the first JFET and the second JFET are coupled to the first conductive terminal and the second conductive terminal of the 4Q switch respectively through corresponding bias circuits.

12. The system according to claim 11, wherein, Each bias circuit includes: A Zener diode includes an anode connected to the gate terminal of one of a first JFET and a second JFET, and a cathode connected to a first conductive terminal of the other of the first JFET and the second JFET. A capacitor and a resistor are both connected between the anode and cathode of the Zener diode.

13. The system according to claim 11, wherein, Each bias circuit includes: A Zener diode includes an anode connected to the gate terminal of one of the first and second JFETs, and a cathode connected to a first conductive terminal of said JFET. A capacitor, which is connected in parallel with a resistor, is mounted between the anode of the Zener diode and the first conductive terminal of another of the first and second JFETs.

14. The system according to claim 11, wherein, Each bias circuit includes an N-type metal-oxide-semiconductor logic NMOS connected between the gate terminal of one of the first JFET and the second JFET and a first conductive terminal of the other of the first JFET and the second JFET.

15. The system according to claim 14, wherein, Each bias circuit includes: a Zener diode having an anode connected to a gate terminal of one of the first JFETs and the second JFET, and a cathode connected to a first conductive terminal of the other of the first JFETs and the second JFETs; and a resistor connected in series with the NMOS between the gate terminal of one of the first JFETs and the first conductive terminal of the other of the first JFETs and the second JFETs.

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