Semiconductor device with electroplated die attach

Abstract

A packaged semiconductor device (200) includes a metal substrate (120) having a central opening with a plurality of raised traces (125) surrounding the central opening, the plurality of raised traces comprising a metal layer (125b) on a dielectric base layer (125a). A semiconductor die (180) having a backside metal (BSM) layer (181) is mounted topside up in the top of the central opening. A single metal layer (121) located directly between the BSM layer and the walls of the metal substrate defining the central opening provides a die attach that fills the bottom of the central opening. Leads (126) having at least one bend contacting the metal layer are located on the plurality of traces and include distal portions extending beyond the metal substrate. Wirebonds are located between the traces and pads (180a) on the semiconductor die. A mold compound (175) provides encapsulation.

Description

Technical Field

[0001] This description relates to semiconductor device assembly, and more particularly to die attach of substrates. Background Art

[0002] Packaged semiconductor devices can include an integrated circuit (IC) die (such as a silicon die) mounted on a die pad of a workpiece (such as a lead frame) using a die attach adhesive. Other workpieces include interposers, printed circuit boards (PCBs), and other IC dies. For IC dies assembled with the top (active) side up and the back side down, the die attach adhesive provides mechanical attachment and can also provide an electrical and / or thermal path to the die pad. The die attach adhesive can include a polymer (such as a polyimide or epoxy-based adhesive). Silver can be added as a filler in the form of particulate flakes to increase the electrical and thermal conductivity of the polymer material. Summary of the Invention

[0003] This summary is provided to introduce a brief selection of concepts in a simplified form that are further described below in the detailed description, including the provided figures. This summary does not limit the scope of the claimed subject matter.

[0004] The described aspects recognize that some die attach solutions comprising metal particle filled polymers have considerable thermal resistance and electrical resistance. As thermal management becomes more important with the trend towards more compact and highly integrated electronic systems with smaller features and running at higher operating currents, a need exists for higher thermal conductivity die attach arrangements that also provide low electrical resistance when backside electrical contacts are used. It has been recognized that while solder die attach, such as eutectic gold and tin (AuSn), can provide backside electrical contacts with relatively good thermal resistance and electrical resistance compared to metal filled polymers, solder die attach is relatively expensive, limited to solderable die surfaces, and the solder die attach process involves inert reflow at temperatures that can result in temperature induced stresses on the metal interconnects of the semiconductor die.

[0005] The packaged semiconductor device described includes a metal substrate having a central opening, the central opening including an outer ring having a plurality of raised traces surrounding the central opening, the plurality of raised traces comprising a metal layer on a dielectric base layer. A semiconductor die having a backside metal (BSM) layer is mounted topside up on top of the central opening. A single metal layer is directly located between the BSM layer and the substrate wall defining the central opening to provide a die attachment that fills the bottom of the opening. Leads having at least one bend contacting the metal layer are located on the plurality of traces and include distal portions that extend beyond the metal substrate. Bond wires are located between the traces and bond pads on the semiconductor die. A molding compound provides encapsulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0007] Figures 1A to 1J Components used and an assembly process progression are shown for forming the disclosed packaged semiconductor device having a semiconductor die with a BSM layer attached directly to a metal substrate via an electroplated metal die attach layer, according to example aspects.

[0008] Figure 2 is a cross-sectional view of an example packaged semiconductor device having a semiconductor die with a BSM layer attached directly to a metal substrate by an electroplated metal die attach layer, having leads with 90 degree bends according to an example aspect.

[0009] Figure 3 is a cross-sectional view of an example packaged semiconductor device according to an example aspect, the example packaged semiconductor device having a semiconductor die with a BSM layer directly attached to a metal substrate by a plated metal die attach layer, and gull-wing leads having non-90-degree bends as example lead bends. DETAILED DESCRIPTION

[0010] Example embodiments are described with reference to the accompanying drawings, in which like reference numerals are used to identify similar or equivalent elements. The illustrated order of actions or events should not be considered limiting, as some actions or events can occur in a different order and / or can occur simultaneously with other actions or events. Furthermore, some illustrated actions or events may not be required to implement the methods according to this specification.

[0011] Figures 1A to 1IComponents and assembly process progressions used to form the described packaged semiconductor device having a backside metal plated semiconductor die attached directly to a metal substrate via an electroplated metal die attach layer are shown according to example aspects. Figure 1A The described stack, comprising a dielectric cap 130 on a metal substrate 120 with a die therein, is shown immersed in a plating vessel 150 that provides an electroplating bath. The components are immersed in a solution called an electrolyte, which contains one or more dissolved metal salts and other ions that allow electricity to flow.

[0012] The cover 130 comprises a dielectric (e.g., plastic) material that covers the top of the metal substrate 120. The metal substrate 120 is in the form of a substrate sheet / plate having a plurality of die locations (e.g., 4 die locations are shown), wherein the dies (not shown) in the rectangular die locations are positioned top side up within the openings in the metal substrate 120. The substrate sheet / plate may have between about 50 and 1000 die locations. A plating solution 145 is present in the plating vessel 150. There is also a seal, such as a strip resistant to the plating solution, between the dielectric cover 130 and the metal substrate 120 to avoid plating metal on the top side of the semiconductor die. For electroplating, the metal substrate 120 is connected to the negative terminal (cathode) of the power supply 190 and a conductive structure (such as in the case of a substrate 120) having an opening spaced apart from the metal substrate 120. Figure 1A The metal block (shown as anode 135 spaced apart from the metal substrate 120) is connected to the positive terminal (anode) of the power supply 190. The electroplating can be performed at a temperature of 15°C to 30°C to avoid introducing temperature-induced stresses such as to the semiconductor die interconnects. At the cathode, the metal ions (e.g., Cu 2+ ions) dissolved in the electrolyte solution are +2 ) are reduced at the interface between the solution and the cathode, causing them to plate out zero-valent metal (e.g., Cu metal) onto the cathode. Electroplating can be performed using direct current (DC), but can also be performed as pulse plating.

[0013] Figure 1B An example dielectric cap 130 is shown. The dielectric cap 130 may comprise plastic. The dielectric cap 130 has a first repeating pattern of recesses 130 a, which are shown as being sized and shaped to match the rectangular shape of the semiconductor die to be covered, but slightly larger in area than the semiconductor die to accommodate the semiconductor die.

[0014] Figure 1CAn example metal substrate 120 is shown with an insert having a portion thereof enlarged to illustrate corresponding features of raised traces 125 on the metal substrate 120. The metal substrate 120 may comprise copper, such as a copper alloy. Other example metals include Ni, Co, Sn, or alloys thereof. The metal substrate 120 includes a second repeating pattern having a matching Figure 1B , the position of the first repeating pattern on the dielectric cap 130 is shown in FIG. , including a central via opening 120a positioned to match the recess 130a. The via opening 120a has an outer ring 120a1 for die seating and a plurality of raised traces 125 surrounding the via opening 120a, wherein the raised traces 125 include a metal layer 125b on a dielectric base layer 125a (e.g., polyimide) on the metal substrate 120. The metal layer 125b can be printed on the dielectric base layer 125a.

[0015] Figure 1D Semiconductor die 180 is shown seated top (active) side up, back side down on outer ring 120a1 (not shown) within through-via opening 120a of example metal substrate 120. Pad 180a is shown on the active top side of semiconductor die 180. Figure 1E The dielectric cap 130 is shown just before being placed on the metal substrate 120 over the semiconductor die 180 . Figure 1F The dielectric cap 130 is shown looking down upon the dielectric cap 130 after being placed on the metal substrate 120 over the semiconductor die 180 . Figure 1G yes Figure 1F Inverted to look down at the bottom of metal substrate 120 , this view shows the portion of opening 120 a not occupied by semiconductor die 180 .

[0016] Figure 1H A backside view of a stack including a dielectric cap 130 on a metal substrate 120 above a semiconductor die 180 is shown after electroplating for depositing a single layer of plated metal (such as copper) to fill the volume between the BSM layer on the semiconductor die 180 and the walls of the metal substrate 120 defining the opening, thereby providing die attach. The time for the electroplating process can be calculated by dividing the desired thickness by the deposition rate. The thickness of the metal die attach layer 121 is designed to fill the opening, such as 10 to 250 μm thick, for example 20 to 100 μm thick. Figure 1H The portions of the openings not occupied by the semiconductor die 180 (beneath the die) are shown now filled with an electroplated metal die attach layer 121 deposited as a sheet across the bottom surface of the metal substrate 120. Although the metal die attach layer 121 is shown as planar, there may be a slight recess when positioned over the corresponding through-via opening 120a.

[0017] The metal die attach layer 121, being an electroplated metal layer, is different from other layers of the same metal material deposited by other methods, such as sputtered metal layers. Unlike sputtered layers, electrodeposited layers are known to fill non-line-of-sight areas. Electrodeposited layers are also known to have a unique microstructure, including an initially deposited Nernst diffusion layer that has a different density and microstructure than the bulk of the electrodeposited layer.

[0018] Figure 1I A single packaged semiconductor device precursor is shown after removing the stack from the plating solution, removing the dielectric cap 130, singulating the metal substrate 120 to form a plurality of packaged semiconductor device precursors including a first packaged semiconductor device precursor, and then adding leads 126. Leads 126 include strips of metal (e.g., the same metal as the lead frame) such as copper, copper alloy, or tin-coated leads that can be commercially available or generated in-house. For example, a metal sheet can be cut into the metal strips.

[0019] Lead 126 contacts metal layer 125b on the plurality of raised traces 125, has at least one bend, and includes a distal portion that extends beyond metal substrate 120. Lead 126 can be soldered to metal layer 125b, but can also be attached via fusion soldering or a conductive adhesive material. Wirebonds 133 are shown added before dicing and are located between the plurality of raised traces 125 and pads 180a on semiconductor die 180. Figure 1J A single packaged semiconductor device 190 is shown after being molded to form a mold compound 175 for encapsulation, thereby completing the packaged semiconductor device. A Sn (tin) layer may optionally be added to the leads 126.

[0020] Figure 2 is a cross-sectional view of an example packaged semiconductor device 200 according to an example aspect, the example packaged semiconductor device having a semiconductor die 180 with a BSM layer 181 attached directly to a metal substrate 120 via an electroplated metal die attach layer 121, and having leads 126 with 90-degree bends. As described above, the metal substrate 120 can include copper (such as a copper alloy), Ni, Co, Sn, or alloys thereof. The metal substrate 120 can be approximately 0.1 mm (3.94 mils) to 0.3 mm (11.81 mils) thick. Furthermore, as described above, the metal die attach layer 121 can be 10 to 250 μm thick, such as 20 to 100 μm thick. Figure 3is a cross-sectional view of an example packaged semiconductor device 300 according to an example aspect, the example packaged semiconductor device having a semiconductor die 180 with a BSM layer 181 directly attached to a metal substrate via a plated metal die attach layer 121, and gull-wing leads 126a having non-90 degree bends as examples of lead bends.

[0021] Advantages of the described aspects include the ability to perform die attach at room temperature, high heat dissipation from the semiconductor die to the metal substrate, and strong mechanical die support due to the high ductility of the electroplated metal die attach layer (such as when copper is included). In addition, a lower cost die attach solution is provided compared to silver-filled epoxies.

[0022] The described embodiments can be integrated into multiple assembly processes to form a variety of different packaged semiconductor integrated circuit (IC) devices and related products. The assembly can include a single semiconductor die or multiple semiconductor dies, such as a PoP configuration including multiple stacked semiconductor dies. A variety of packaging substrates can be used. The semiconductor die can include various components therein and / or layers thereon, including barrier layers, dielectric layers, device structures, active components and passive components, including source regions, drain regions, bit lines, bases, emitters, collectors, wires, conductive vias, etc. In addition, the semiconductor die can be formed by a variety of processes, including bipolar transistors, insulated gate bipolar transistors (IGBTs), CMOS, BiCMOS, and MEMS.

[0023] Those skilled in the art to which this description relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and that further additions, deletions, substitutions, and modifications may be made to the described embodiments without departing from the scope of this description.

Claims

1. A method for attaching a semiconductor die, comprising: providing a dielectric cover and a metal substrate, the dielectric cover having a first repeating pattern of grooves, the metal substrate including a second repeating pattern having positions matching the first repeating pattern and including a central via opening, the central via opening having an outer ring having positions matching the grooves and a plurality of raised traces surrounding the via opening, the plurality of raised traces comprising a metal layer on a dielectric base layer on the metal substrate; inserting a semiconductor die top side up into corresponding openings of the plurality of openings to be seated on the outer ring, the semiconductor die having a backside metal layer (BSM layer); placing the dielectric cap over the semiconductor die to form a plurality of stacks; sealing between the dielectric cover and the metal substrate along a periphery; immersing the stack in a metal plating solution within a solution container, wherein the metal substrate is connected to a negative terminal of a power source and a conductive structure spaced apart from the metal substrate is connected to a positive terminal of the power source; as well as Electroplating is performed to deposit a single layer of plated metal to fill a volume between the BSM layer and walls of the metal substrate defining the opening to provide die attach.

2. The method of claim 1, wherein the metal electroplating solution comprises a copper electroplating solution. The method of claim 1 , wherein the dielectric base layer comprises polyimide. The method of claim 1 , wherein the BSM layer, the metal substrate, and the single metal layer all comprise copper.

5. The method of claim 1 , wherein the metal substrate is part of a substrate sheet, the substrate sheet comprising a plurality of the metal substrates, the method further comprising: placing bond wires between the plurality of raised traces and bond pads on the semiconductor die; After said placing, cutting said substrate sheet to form a plurality of packaged semiconductor device precursors, said plurality of packaged semiconductor device precursors including a first packaged semiconductor device precursor; adding a lead having at least one bend that contacts the metal layer on the plurality of raised traces and includes a distal portion that extends beyond the metal substrate, and Molding to form a molding compound, thereby adding an encapsulation to form a first packaged semiconductor device. The method of claim 1 , wherein the electroplated single metal layer is 20 μm to 100 μm thick. The method of claim 1 , wherein the dielectric cap comprises plastic.

8. The method of claim 1, wherein the electroplating is performed at a temperature of from 15°C to 30°C.

9. The method of claim 1, wherein the sealing comprises placing a tape between the dielectric cover and the metal substrate along the periphery.

10. The method of claim 1, wherein the electroplating comprises direct current plating. The method of claim 1 , wherein the electroplating comprises pulse plating.

12. A packaged semiconductor device comprising: a metal substrate having a central opening with a plurality of raised traces surrounding the central opening, the plurality of raised traces comprising a metal layer on a dielectric base layer; a semiconductor die having a backside metal layer (BSM layer), the semiconductor die being mounted topside up on top of the opening; a single metal layer positioned directly between the BSM layer and the walls of the metal substrate to provide a die attach, the walls defining the central opening, the die attach filling a bottom of the opening; a lead having at least one bend contacting the metal layer on the plurality of traces and including a distal portion extending beyond the metal substrate; bond wires between the plurality of traces and bond pads on the semiconductor die, and A molding compound provides the encapsulation.

13. The packaged semiconductor device of claim 12, wherein the dielectric base layer comprises polyimide. 14 . The packaged semiconductor device of claim 12 , wherein the BSM layer, the metal substrate, and the single metal layer all comprise copper. 15 . The packaged semiconductor device of claim 12 , wherein the single metal layer is 20 μm to 100 μm thick.

16. The packaged semiconductor device of claim 12, wherein the metal substrate is 0.1 mm to 0.3 mm thick.

17. The packaged semiconductor device of claim 12, wherein the single metal layer is an electroplated metal layer.

18. A packaged semiconductor device comprising: a substrate comprising copper, the substrate having a central opening with a plurality of raised traces surrounding the central opening, the plurality of raised traces comprising a metal layer on a dielectric base layer; a semiconductor die having a backside metal layer (BSM layer), the semiconductor die being mounted topside up on top of the opening; a single copper layer positioned directly between the BSM layer and walls of the copper-containing substrate to provide a die attach, the walls defining the central opening, the die attach filling a bottom of the opening; a lead having at least one bend contacting the metal layer on the plurality of traces and including a distal portion extending beyond the copper-containing substrate; bond wires between the plurality of traces and bond pads on the semiconductor die, and A molding compound provides the encapsulation. The packaged semiconductor device of claim 18 , wherein the BSM layer comprises copper.

20. The packaged semiconductor device of claim 18, wherein the single copper layer is 20 μm to 100 μm thick.

21. A method for manufacturing a packaged semiconductor device, comprising: providing a metal substrate having a central opening with a plurality of raised traces surrounding the central opening, the plurality of raised traces comprising a metal layer on a dielectric base layer; Mounting a semiconductor die having a backside metal layer (BSM layer), the semiconductor die being mounted top side up on top of the opening; forming a single metal layer positioned directly between the BSM layer and walls of the metal substrate to provide a die attach, the walls defining the central opening, the die attach filling a bottom of the opening; forming a lead having at least one bend contacting the metal layer on the plurality of traces and including a distal portion extending beyond the metal substrate; attaching wire bonds between the plurality of traces and pads on the semiconductor die, and The semiconductor device is covered with a molding compound.

22. The method of claim 21, wherein the dielectric base layer comprises polyimide.

23. The method of claim 21, wherein the BSM layer, the metal substrate, and the single metal layer all comprise copper.

24. The method of claim 21, wherein the single metal layer is 20 μm to 100 μm thick.

25. The method of claim 21, wherein the metal substrate is 0.1 mm to 0.3 mm thick.

26. The method of claim 21, wherein the single metal layer is an electroplated metal layer.

27. A method of manufacturing a packaged semiconductor device, comprising: providing a substrate comprising copper, the substrate having a central opening with a plurality of raised traces surrounding the central opening, the plurality of raised traces comprising a metal layer on a dielectric base layer; Mounting a semiconductor die having a backside metal layer (BSM layer), the semiconductor die being mounted top side up on top of the opening; forming a single copper layer directly between the BSM layer and walls of the copper-containing substrate to provide a die attach, the walls defining the central opening, the die attach filling a bottom of the opening; forming a lead having at least one bend contacting the metal layer on the plurality of traces and including a distal portion extending beyond the copper-containing substrate; attaching wire bonds between the plurality of traces and pads on the semiconductor die, and The semiconductor device is covered with a molding compound. The method of claim 27 , wherein the BSM layer comprises copper.

29. The method of claim 27, wherein the single copper layer is 20 μm to 100 μm thick.

30. A method of semiconductor die attach, comprising: providing a dielectric cover and a metal substrate, the dielectric cover having a recess, the metal substrate including a central through-hole opening having an outer ring positionally matching the recess of the dielectric cover and a plurality of raised traces surrounding the through-hole opening, the plurality of raised traces comprising a metal layer on a dielectric base layer on the metal substrate; inserting a semiconductor die top side up into the opening to sit on the outer ring, the semiconductor die having a backside metal layer (BSM layer); placing the dielectric cap over the semiconductor die to form a stack; sealing between the dielectric cover and the metal substrate along a periphery; immersing the stack in a metal plating solution within a solution container, wherein the metal substrate is connected to a negative terminal of a power source and a conductive structure spaced apart from the metal substrate is connected to a positive terminal of the power source; as well as Electroplating is performed to deposit a single layer of plated metal to fill a volume between the BSM layer and walls of the metal substrate defining the opening to provide die attach.

31. The method of claim 30, wherein the metal electroplating solution comprises a copper electroplating solution.

32. The method of claim 30, wherein the dielectric base layer comprises polyimide.

33. The method of claim 30, wherein the BSM layer, the metal substrate, and the single metal layer all comprise copper.

34. The method of claim 30, wherein the metal substrate is part of a substrate sheet, the substrate sheet comprising a plurality of the metal substrates, the method further comprising: placing bond wires between the plurality of raised traces and bond pads on the semiconductor die; After said placing, cutting said substrate sheet to form a plurality of packaged semiconductor device precursors, said plurality of packaged semiconductor device precursors including a first packaged semiconductor device precursor; adding a lead having at least one bend that contacts the metal layer on the plurality of raised traces and includes a distal portion that extends beyond the metal substrate, and Molding to form a molding compound, thereby adding an encapsulation to form a first packaged semiconductor device.

35. The method of claim 30, wherein the electroplated single metal layer is 20 μm to 100 μm thick.

36. The method of claim 30, wherein the dielectric cap comprises plastic.

37. The method of claim 30, wherein the electroplating is performed at a temperature of from 15°C to 30°C.

38. The method of claim 30, wherein the sealing comprises placing a tape between the dielectric cover and the metal substrate along the periphery.

39. The method of claim 30, wherein the electroplating comprises direct current plating.

40. The method of claim 30, wherein the electroplating comprises pulse plating.

41. A method of semiconductor die attach, comprising: providing a dielectric cover and a metal substrate, the dielectric cover having a first repeating pattern of grooves, the metal substrate including a second repeating pattern having positions matching the first repeating pattern and including a central via opening, the central via opening having an outer ring having positions matching the grooves and a plurality of raised traces surrounding the via opening, the plurality of raised traces comprising a metal layer on a dielectric base layer on the metal substrate; inserting a semiconductor die top side up into corresponding openings of the plurality of openings to be seated on the outer ring, the semiconductor die having a backside metal layer (BSM layer); placing the dielectric cap over the semiconductor die to form a plurality of stacks; as well as Electroplating is performed to deposit a single layer of plated metal to fill a volume between the BSM layer and walls of the metal substrate defining the opening to provide die attach.

42. A method of semiconductor die attach, comprising: providing a metal substrate having a central via opening, the central via opening having an outer ring and a plurality of raised traces surrounding the via opening, the plurality of raised traces comprising a metal layer on a dielectric base layer on the metal substrate; inserting a semiconductor die top side up into corresponding openings of the plurality of openings to be seated on the outer ring, the semiconductor die having a backside metal layer (BSM layer); as well as Electroplating is performed to deposit a single layer of plated metal to fill a volume between the BSM layer and walls of the metal substrate defining the opening to provide die attach.

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