Promoting high-side control of a switching power converter

Abstract

In an example apparatus, a latch (108) includes a first node (128) coupled to a source of a first switch (110) and an output (130) coupled to a gate of the first switch (110). A first diode (218) is coupled to the first node (128) and a second node (224). A second diode (220) is coupled to the second node (224) and ground (132). A second switch (206) is coupled to a voltage source (200) and the second node (224). A third switch (212) includes a gate coupled to the second switch (206), a third source coupled to the second node (224), and a third drain coupled to the latch (108).

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to power converters, and more particularly to methods, apparatuses, and systems that facilitate high-side control of a switching power converter. BACKGROUND

[0002] Power converters are circuits that can be used in a variety of devices to convert an input voltage to a desired output voltage. For example, a buck converter converts an input voltage to a lower output voltage by controlling transistors and / or switches to charge and / or discharge an inductor and / or a capacitor to maintain a desired output voltage. Some power converters can include one or more power switches that can be turned on and off synchronously (e.g., when one switch is on, the other switch is off) to change a current path in the power converter. In some examples, such as in high voltage power converters, wide bandgap devices can be used to implement power switches for high voltage and / or high temperature power switch applications. SUMMARY

[0003] Examples described herein facilitate high-side control of a switching power converter. An example apparatus includes a latch including a first node coupled to a first source of a first switch and an output coupled to a first gate of the first switch, a first diode coupled to the first node and a second node, a second diode coupled to the second node and ground, a second switch coupled to a voltage source and a resistor, and a third switch including a third gate coupled to the resistor and the second switch, a third source coupled to the second node, and a third drain coupled to the latch. BRIEF DESCRIPTION OF DRAWINGS

[0004] Figure 1 An example switching power converter is shown.

[0005] Figure 2 An example circuit implementation of a high-side level shifter of Figure 1 is shown.

[0006] Figure 3 An alternative circuit implementation of a high-side level shifter of Figure 1 is shown.

[0007] Figure 4 A timing diagram corresponding to a low-side to high-side transition using a high-side level shifter of Figure 2 and / or 3 is shown.

[0008] Figure 5 An alternative example high-side level shifter trigger of Figure 1 is shown.

[0009] Figure 6 A timing diagram corresponding to a low-side to high-side transition using a high-side level shifter of Figure 5Timing diagram of the low-side to high-side transition of the alternative high-side level shift trigger.

[0010] Figure 7 shows Figure 1 An alternative example is the high-side level shifter latch.

[0011] Figure 8 It shows the corresponding use Figure 8 Timing diagram of the low-side to high-side transition of the alternative high-side level shifter latch.

[0012] Figure 9 It shows Figure 1 Example bonding pads.

[0013] Figure 10 To represent the purpose of achieving Figure 1 A flowchart of example machine-readable instructions and / or hardware configurations that can be executed for the power converter.

[0014] Figure 11 To represent the purpose of achieving Figure 1 A flowchart of example machine-readable instructions and / or hardware configurations that can be executed for the power converter.

[0015] Figure 12 To construct execution Figures 10-11 Machine-readable instructions to implement Figures 1-3 , Figure 5 And / or a block diagram of the processor platform for the high-side level shifter in Figure 7. Detailed Implementation

[0016] The accompanying drawings are not to scale. Where possible, the same reference numerals are used throughout the drawings and this specification to refer to the same or similar parts.

[0017] Power converters (e.g., buck converters, boost converters, alternating current (AC)-AC converters, direct current (DC)-DC converters, AC-DC converters, etc.) can include power switches (e.g., relays, metal oxide silicon field effect transistors (MOSFETs), etc.) in a half-bridge power stage that switches current from one path (e.g., from a voltage source (Vdd) to an output) to another path (e.g., from the output to ground). In such half-bridge switching converters, a microcontroller outputs control signals to a low-side level shifter and / or a high-side level shifter. The low-side level shifter enables a low-side switch to decrease an output voltage of the power converter based on the control signals. The high-side level shifter enables a high-side level shifter to enable a high-side switch / transistor to increase the output voltage of the power converter. The microcontroller can output the control signal(s) to the level shifters to switch between high-side control (e.g., by enabling the high-side switch and disabling the low-side switch) and low-side control (e.g., by disabling the high-side switch and enabling the low-side switch) at a frequency and / or pulse width modulation to produce a desired output voltage.

[0018] A level shifter in a power converter converts a received digital control signal at a first logic standard (e.g., 3.3 volts (V) or 5V output of a microcontroller represents a logic value of “1”) to a second logic standard (e.g., another voltage (e.g., 400V) represents a logic value of “1”) that corresponds to a voltage high enough to control a high-side switch. In certain half-bridge converters, the high-side level shifter includes one or more latches that are used to hold state information (e.g., a logic “1” or a logic “0”) to trigger an output voltage that is high enough to enable the high-side switch or an output voltage that is low enough to disable the high-side switch. For example, when the output of the microcontroller corresponds to a logic value of “1” (e.g., 3.3V or 5V, etc.), the one or more latches output a voltage to a gate of the high-side switch that rises to a bootstrap node potential to enable the high-side switch. In such an example, when the output of the microcontroller corresponds to a logic value of “0” (e.g., 0V or ground), the one or more latches output a voltage to the gate of the high-side switch that is the same as a voltage at a switch node, thereby disabling the low-side switch. The bootstrap node corresponds to a bootstrap capacitor coupled to the switch node, a voltage across the bootstrap capacitor corresponds to the voltage at the bootstrap node, which is higher than the voltage at the switch node. The switch node corresponds to a node coupled to a source of the high-side switch, a drain of the low-side switch, and an output stage of the power converter.

[0019] Gallium nitride (GaN) switches are wide bandgap transistors that can be used to implement switching devices for power converters. GaN switches (e.g., transistors) have very high breakdown voltage (e.g., a reverse bias breakdown voltage that can be greater than [minimum breakdown] V), high electron mobility, and saturation velocity. As a result, GaN switches are used in high power and / or high frequency power converters or other high voltage switching devices. Such systems have parasitic inductance and parasitic capacitance. GaN transistors include a thick, high resistance GaN layer between the silicon layer and the source, gate, and drain of the transistor.

[0020] Some wide bandgap devices, such as GaN transistors, lack an intrinsic body diode. As a result, when a GaN transistor is implemented in a half-bridge switching converter, a switching node (e.g., a node connecting the half-bridge to an output stage) can become negative. For example, when the amount of current drawn from ground during low-side control and / or during a dead time (e.g., a duration of time between low-side control and high-side control when both the high-side transistor and the low-side transistor are disabled) is high enough (e.g., 4 amps (A) or more), the voltage at the switching node can become negative as the inductor of the power converter draws negative current through the low-side transistor / switch. If the voltage at the switching node becomes too negative (e.g., -4 V, -5 V, etc.), the level shifter will not be able to trigger one or more latches. As a result, the power converter can fail to trigger high-side control. The examples described herein include a circuit that provides a mobile level shift ground that tracks the voltage at the switching node when the switching voltage is negative, by a preset voltage higher than the switching voltage. In this way, the voltage at the mobile level shift ground will always be low enough to ensure that the latches can be triggered based on the voltage difference corresponding to the mobile level shift ground. When the voltage at the switching node is positive, the voltage at the mobile level shift ground tracks ground when the switching voltage is positive, by a preset voltage higher than ground. In this way, the level shifter can control the high-side switch when the switching voltage is negative.

[0021] Moreover, some switching converters include bond wires and / or bond pads to couple components of the power converter together. Bond wires and / or bond pads have inherent parasitic capacitance. Such capacitance can pull down or up one or more nodes in and / or coupled to one or more level shifters of the power converter (e.g., pull a node of a latch up above a bootstrap node and / or pull a node of a latch down below a switch node), causing an undesirable voltage shift at the nodes in the level shifters. This undesirable voltage shift can cause one or more latches in the level shifters to not flip state information when it should or to flip state information when it should not. Furthermore, certain power converters can have device mismatches. Device mismatches correspond to differences between devices in a circuit that, ideally, should be identical and have identical operating parameters to function accurately. Mismatches in GaN-based circuits can be higher than in silicon-based circuits due to voltage threshold movement under high voltage reverse bias stress. Examples described herein include circuits that provide two separate hysteresis paths in a latch of a level shifter. The hysteresis paths add resistance to one side of the latch that, after a high conversion rate transition (e.g., when state information in the level shifter is corrected and / or lost), pulls an internal node of the latch to a previous state. In this way, undesirable voltage shifts caused by parasitic capacitance of bond wires, bond pads, and / or devices (e.g., drain-source capacitance of transistors) will not cause undesirable state information flips in the latch(s).

[0022] Some examples described herein apply shielding to bond pads and / or bond wires to reduce parasitic capacitance. For example, a shield can be added where a two-dimensional electron gas layer (2-DEG) or a lower level metal connected to a switch node at the level shifter can be used to shield high voltages on the pads. Using such examples described herein, parasitic capacitance is reduced to reduce the effects of parasitic capacitance.

[0023] Figure 1An example power converter 100 (e.g., a switching power converter) is shown to convert an input voltage (Vin) to a desired output voltage. The power converter 100 includes an example controller 102, an example input buffer 104, example high-side level shifters 105a, 105b (including example high-side level shift flip-flops 106a, 106b and an example high-side level shifter latch 108), an example high-side switch 110, an example low-side level shifter (including an example low-side level shift flip-flop 112 and an example low-side level shifter latch 114), an example low-side switch 116, an example diode 120, an example inter-die bond pad 122, an example output stage 124, an example bootstrap node 126, an example switch node 128, an example high-side gate node 130, and an example ground node 132. In some examples, the power converter 100 is a gallium nitride (GaN) die for implementing the input buffer 104, the high-side level shifter 105b, the high-side switch 110, the low-side level shift flip-flop 112, the low-side switch 116, and / or the diode 120.

[0024] Figure 2 The controller 102 is a controller that outputs a control signal(s) corresponding to a logic value(s) (e.g., “1” or “0”). For example, the controller 102 can output a first logic value “1” on an input high-side node (INH) and a second logic value “0” on an input low-side node (INL) to trigger high-side control (e.g., by enabling the switch 110 and disabling the switch 116 to charge the input voltage to the output stage 124). Also, the controller 102 can output the second logic value “0” on the input high-side node (INH) and the first logic value “1” on the input low-side node (INL) to trigger low-side control (e.g., by disabling the switch 110 and enabling the switch 116 to discharge the output stage 124 to ground). In some examples, the controller 102 outputs the second logic value “0” at both the low-side node and the input high-side node for a short duration between high-side control and low-side control (e.g., and vice versa) to trigger a dead time (e.g., where both the high-side switch 110 and the low-side switch 116 are disabled) to prevent shoot-through (e.g., a short from Vin to ground). The controller 102 switches the logic values output on the input nodes at a frequency or pulse width modulation such that the voltage at the output stage 124 corresponds to the desired output voltage. The controller 102 outputs the logic signals to the input buffer 104 via the input nodes to initiate control of the switches 110, 116. The input buffer 104 stores the output of the controller 102 before the output of the controller 102 is processed by the high-side level shift flip-flops 106a, 106b and / or the low-side level shift flip-flop 112.

[0025] Once the controller 102 has initiated control of the switches 110, 116, the input buffer 104 outputs the logic values to the high-side level shift flip-flops 106a, 106b and the low-side level shift flip-flop 112. The high-side level shift flip-flops 106a, 106b and the low-side level shift flip-flop 112 output the logic values to the high-side level shifter latch 108 and the low-side level shifter latch 114, respectively. The high-side level shifter latch 108 and the low-side level shifter latch 114 output the logic values to the high-side switch 110 and the low-side switch 116, respectively. Figure 1The input buffer 104 buffers control signals from the controller 102 that are then transmitted to the (high-side) HS level shift flip-flops 106a, 106b and low-side level shift flip-flop 112 to trigger high-side control or low-side control. For example, if the control signal on the input high-side node is logic high (e.g., “1”) and the control signal on the input low-side node is logic low (e.g., “0”), the high-level shift flip-flops 106a, 106b trigger the high-side level shifter latch 108 to output a high logic value (e.g., a voltage high enough to enable the high-side switch 110) at the high-side gate node 130 to enable the high-side switch 110 and the low-side level shift flip-flop 112 triggers the low-side level shifter latch 114 to output a low logic value (e.g., a voltage low enough to disable the low-side switch 116) at the gate of the low-side switch 116 to disable the low-side switch 116. Additionally, if the control signal on the input high-side node is logic low and the control signal on the input low-side node is logic high, the high-side level shift flip-flops 106a, 106b trigger the high-side level shifter latch 108 to output a low logic value at the high-side gate node 130 to disable the high-side switch 110 and the low-side level shift flip-flop 112 triggers the low-side level shifter latch 114 to output a high logic value at the gate of the low-side switch 116 to enable the low-side switch 116. During deadband time (e.g., when the controller 102 outputs a low logic value on both the high-side input and the input low-side to prevent shoot-through), the high-side level shift flip-flops 106a, 106b and the low-side shift flip-flop 112 both trigger the respective level shifter latches 108, 114 to output a voltage at the gates of the switches 110, 116 to disable the switches 110, 116. In some examples, the level shifter latches 108, 114 can include two latches. An example of a two-latch level shifter implementation is further described below in connection with FIG. 7.

[0026] Figure 1 The switches 110, 116 are transistors (e.g., the high-side switch 110 is a high-side transistor and the low-side switch 116 is a low-side transistor). For example, as Figure 1As shown, switches 110, 116 are gallium nitride high electron mobility transistors (GaN HEMTs). However, switches 110, 116 can be any type of switch (e.g., field effect transistors, metal oxide field effect transistors, etc.). When high-side switch 110 is enabled and low-side switch 116 is disabled (e.g., during high-side control), the input voltage is coupled to output stage 124, causing the output voltage corresponding to output stage 124 to increase toward the input voltage. When high-side switch 110 is disabled and low-side switch 116 is enabled (e.g., during low-side control), output stage 124 is grounded, causing the output voltage corresponding to output stage 124 to decrease. When both switches 110, 116 are disabled (e.g., during dead-time), output stage 124 is isolated from the ground connection at the source of switch 116 and the input voltage at the drain of switch 110 to prevent the input voltage from being shorted to ground. As described above, controller 102 switches between high and low logic values on the input nodes (e.g., INH and INL) to switch the direction of current to / from output stage 124 (e.g., from the input voltage to output stage 124 or from output stage 124 to ground) at a predetermined frequency and / or pulse width modulation to achieve the desired output voltage. In some examples, controller 102 outputs a control signal(s) corresponding to the dead-time before switching from low-side control to high-side control and / or from high-side control to low-side control to prevent shoot-through. In some examples, such as using the HS level shift trigger 106b of FIG. 1, the maximum load current that can flow through switch node 128 without causing issues in high-side level shifter latch 108 depends on Vt and Rdson. Thus, the maximum load current (I_load) = 0.6 Vt / Rdson LS, where Vt is the threshold voltage of switches 300, 302 of FIG. 1, and Rdson LS is the drain-source resistance of low-side switch 116 when enabled (e.g., turned on). Based on the above equation, the maximum current can be increased by selecting low-side switch 116 to have a lower Rdson than high-side switch 110. Figure 3 Figure 3

[0027] Figure 1 ​​Capacitor 118 is a bootstrap capacitor that boosts the voltage at the switch node 128 to a higher voltage at the bootstrap node 126. For example, the bootstrap capacitor 118 provides a bias voltage that exceeds the input voltage by storing a charge corresponding to the GVDD voltage (e.g., a voltage source / input voltage). In this way, the voltage at the bootstrap node 126 is GVDD higher than the voltage at the switch node 128. For example, if the high-side switch 110 is enabled and the input voltage is 400V, the voltage at the switch node 128 is approximately 400V. In this example, if the voltage provided by GVDD and stored in the capacitor 118 is 6V, the voltage at the bootstrap node 126 is 406V. In this way, the high-side level shifter latch 108 can output the voltage at the bootstrap node 126 at the high-side gate node 130 to enable the high-side switch 110 or can output the voltage at the switch node 128 at the high-side gate node 130 to disable the high-side switch 110.

[0028] Figure 1 Diode 120 (e.g., a bootstrap diode) helps to charge the bootstrap capacitor 118. For example, when the voltage at the switch node 128 drops to a low voltage (e.g., during low-side control), the diode 120 allows GVDD to charge the bootstrap capacitor 118. When the voltage at the switch node 128 rises to a high voltage (e.g., during high-side control), the diode 120 isolates GVDD from the bootstrap node 126, thereby creating a voltage at the bootstrap node 126 that is GVDD higher than the switch node. In this way, the bootstrap node 126 is always at a higher voltage than the switch node 128. Figure 1 In the example shown, the diode 120 is a GaN transistor with its gate coupled to its source. Thus, the GaN transistor operates like a diode, where the source of the GaN transistor is the anode of the diode and the drain of the GaN transistor is the cathode of the diode. Alternatively, any type of circuit that behaves or functions as a diode can alternatively be used.

[0029] Figure 1Bond pads 122, 123 are interconnect pads that connect components in power converter 100. In some examples, bond pads 122, 123 connect to components implemented in different dies (e.g., low-side die and high-side die). For example, input buffer 104, HS level shift flip-flops 106a, 106b, low-side level shift flip-flops 112, low-side level shifter latches 114, switch 116, and diode 120 can be implemented in a low-side die, while HS level shifter latches 108 and switch 110 can be implemented in a high-side die. In such examples, any components that are connected to components implemented in different dies require one or more bond pads 122, 123 to make the connection between the different dies. Bond pads 122, 123 correspond to some parasitic capacitance, which can create an undesirable ground path, which can cause displacement current and / or can cause the gates of the two switches in HS level shifter latch 108 to be pulled higher than the voltage at bootstrap node 126 or to be pulled lower than the voltage at switch node 128, which will cause the latch to fail to latch to a state (e.g., high output state or low output state). In some examples, the parasitic capacitance of certain bond pads 122 is negligible compared to the impedance / resistance of the devices connected to the bond pads 122. In some examples, the amount of charge caused by the parasitic capacitance of some bond pads 122 can be small. However, the bond pad 123 voltage swing applied to bond pad 123 is large (e.g., 0V to 400V). Thus, the parasitic capacitance of bond pad 123 can provide a large amount of unwanted charge to the devices connected to the bond pad. As further described below, bond pad 123 reduces the effect of parasitic capacitance by including a 2-DEG layer on the backside of bond pad 122, where the contact is connected to the 2-DEG layer. The contact can be coupled to switch node 128 to reduce the amount of parasitic capacitance in power converter 100. Figure 9

[0030] During a low-side to high-side transition and / or during a dead-time between low-side and high-side transitions, Figure 1 ​The voltage at the switch node 128 can go significantly negative (e.g., -4.3V). For example, during the dead time, since both gates of the two switches 110, 116 are grounded, the inductor in the output stage 124 will try to force current from ground to the output stage 124. Thus, the voltage at the switch node 128 goes significantly negative to allow the current forced by the inductor to flow to the output stage 124. When the switch node 128 reaches such a negative voltage, some high-side level shifters can fail to flip state based on the INH signal flip-flop to trigger the high-side control due to the negative voltage at the switch node 128. However, as further described below, the HS level shifter 105a, 105b includes circuitry to provide a mobile level shift ground to allow the level shifter 105a, 105b to enable the high-side control even when the switch node 128 is significantly negative.

[0031] Figure 2 To Figure 1 implementations of the level shifter 105a. Figure 2 The level shifter 105a includes Figure 1 the high-side level shift flip-flop 106a, the high-side level shifter latch 108, the bootstrap node 126, the switch node 128, and the ground node 132. Figure 2 The level shifter 105a further includes a first example input voltage 200 (e.g., representative of the GVDD from the Figure 1 controller 102) and a second example input voltage 202 (e.g., representative of the voltage at the input low-side node (INL) from the Figure 1 controller 102) and a third example input voltage 204 (e.g., representative of the voltage at the input high-side node (INH) from the Figure 1 controller 102). Figure 2 The level shifter 105a further includes example switches 206, 208, 212, 216, 230, 232, example resistors 210, 214, 226, 228, example diodes 218, 220, and an example capacitor 222. Although Figure 1 The level shift latch 108 is implemented with one latch, the level shift latch 108 can be implemented with any number of latches, as further described below in connection with FIG. 7.

[0032] Figure 2 The input voltage 200 (e.g., voltage source) representative of the GVDD voltage applied in the Figure 1 controller 102. The first input voltage 204 is representative of the control signal output by the Figure 1 controller 102 on the input high-side node (INH), and the second input voltage 202 is representative of the voltage at the input low-side node (INL) from the Figure 1The controller 102 outputs a control signal on an input low-side node (INL). As described above, a high logic value at the INH node corresponds to enabling the HS switch 110, and a high logic value at the INL node corresponds to disabling the HS switch 110. The input voltages 202, 204 are coupled to ground (e.g., an analog ground node 132).

[0033] Figure 2 The switches 206, 208 are transistors that, when enabled (e.g., based on a logic signal from a respective input voltage 202, 204 applied to a gate of the respective switch 206, 208), allow current to flow from the input voltage 200 to ground via a respective resistor 210, 214 to create a voltage at a gate of a respective switch 212, 216. In Figure 2 In the example of FIG. 2, the switches 206, 208 are p-channel metal-oxide-semiconductor transistors. Alternatively, the switches 206, 208 can be n-channel metal-oxide-semiconductor transistors (e.g., with connections adjusted to ensure that a logic signal corresponding to high-side control enables the high-side switch 110), GaN transistors (e.g., as further described below in connection with FIG. 3), and / or any other type of switch. Figure 3 Further description of the switches 206, 208 is provided below in connection with FIG. 3.

[0034] Figure 2 The switches 212, 216 are transistors that, when enabled, allow current to flow from the bootstrap node 126 to the mobile-level-shift ground node 224 via a respective resistor 226, 228. The switches 212, 216 are enabled when a voltage higher than a threshold voltage is applied to a gate of the respective switch 212, 216. As shown in Figure 2 FIG. 2, the switches 212, 216 are GaN switches. Alternatively, any type of switch can be used.

[0035] Figure 2The diodes 218, 220 are implemented by GaN transistors. Alternatively, the diodes 218, 220 can be any device that implements the function of a diode (e.g., to allow current to flow in one direction and prevent current from flowing in a second direction). For example, the source of the GaN implementation corresponds to the anode of the diode 218 (e.g., coupled to the mobile level shift ground node 224), and the drain of the GaN implementation corresponds to the cathode of the diode 218 (e.g., coupled to the switch node 128). Also, the source of the GaN implementation corresponds to the anode of the diode 220 (e.g., coupled to the mobile level shift ground node 224), and the drain of the GaN implementation corresponds to the cathode of the diode 220 (e.g., coupled to the analog ground node 132). The diodes 218, 220 produce a voltage drop corresponding to the threshold voltage. The diode 218 allows current to flow from the mobile level shift ground node 224 to the switch (SW) node 128, and prevents current from flowing from the SW node 128 to the mobile level shift ground node 224. Also, the diode 220 allows current to flow from the mobile level shift ground node 224 to the analog ground (AGND) node 132. In this way, when the voltage at the SW node 128 is positive, the mobile level shift ground node 224 is isolated from the SW node 128, and the voltage at the mobile level shift ground node 224 is higher than the voltage at the AGND node (e.g., 0V) by a threshold voltage (e.g., 2V). Also, when the voltage at the SW node 128 is negative, the mobile level shift ground node 224 is isolated from the AGND node 132, and the voltage at the mobile level shift ground node is higher than the voltage at the SW node 128 by a threshold voltage (e.g., 2V). Thus, the diodes 218, 220 are implemented to produce a mobile level shift ground node 224 that tracks the SW node 128 when the voltage at the SW node 128 is negative (e.g., is higher than the voltage at the SW node 128 by a threshold voltage), and tracks the AGND 132 when the voltage at the SW node 128 is positive (e.g., is higher than the voltage at the AGND node 132 by a threshold voltage / corresponds to the voltage difference across the diode 220 from the switch node 224 to the AGND 132).

[0036] When the voltage at the switch node 128 rises to the high voltage, Figure 2 The capacitor 222 absorbs the charging current of the blocking diode 218. In this way, the capacitor 222 holds the voltage drop from the AGND 132 to the mobile level shift ground node 224 low until the level shifting action is complete (e.g., after the voltage at the switch node 128 settles to the high voltage level).

[0037] Figure 2The resistors 226, 228 provide a path for current to flow to ground (e.g., based on the enabling of the switches 212, 216) to create a voltage at the gates of the respective switches 230, 232 to store state information (e.g., a high state output or a low state output) corresponding to a voltage on the high-side gate node 130 that is either high enough to enable the switch 110 or low enough to disable the switch 110. In some examples, the resistors 226, 228 can be replaced with p-channel transistors and / or p-channel GaN transistors.

[0038] Figure 2 The switches 230, 232 are transistors that latch to state information based on the voltage applied to the gates of the respective switches 230, 232. The switches 230, 232 are implemented such that when the switch 230 is on, the switch 232 is off, and when the switch 230 is off, the switch 232 is on. When the switch 230 is off and the switch 232 is on, the voltage at the high-side gate node 130 (e.g., the latch output) corresponds to a low logic state (e.g., a voltage that is low enough to disable the switch 110). When the switch 230 is on and the switch 232 is off, the voltage at the high-side gate node 130 corresponds to a high logic state (e.g., a voltage that is high enough to enable the switch 110).

[0039] In operation, when the first input voltage 200 is high and the second input voltage 202 is low (e.g., corresponding to high-side control), the switch 206 is enabled and the switch 208 is disabled. Thus, the input voltage 200 (e.g., GVDD) is applied to the resistor 210 to create a voltage drop across the resistor 210 (e.g., because the voltage at the mobile level shift ground node 224 is low or negative during low-side / dead-time control). This voltage drop corresponds to a voltage applied to the gate of the switch 212 that is high enough to enable the switch 212, thereby providing a path from the bootstrap node 126 to ground via the resistor 226. Because the voltage at the mobile level shift ground node 224 tracks the SW node voltage, the voltage at the mobile level shift ground node 224 will always be low enough to cause a voltage drop across the resistor 226, which corresponds to a flip of the switches 230, 232, even when the voltage at the bootstrap node 126 is 0. In this way, the voltage applied to the gate of the switch 212 is high enough to enable the switch 212 (e.g., flip the state of the latch). Thus, the voltage at the high-side gate node 130 is approximately the same as the voltage at the bootstrap node 126 (e.g., a voltage high enough to enable the switch 110 for high-side control).

[0040] In systems that do not include a mobile level shift ground node 224 (e.g., systems without diodes 218, 220), the AGND node 132 is used to trigger the latch. However, such systems cannot flip the latch because the voltage at the bootstrap node 126 can be very small or zero during the deadband time. For example, if the voltage at the SW node 128 is -6V during the deadband time, the voltage at the bootstrap node 126 will be 0V. Since the voltage at the AGND node 132 is also 0V, there will be no voltage drop across either of the resistors 226, 228. Thus, such systems will not be able to flip the latch to enable the high-side control. However, since the diode 218 creates a voltage drop corresponding to the voltage at the mobile level shift ground node 224, which is higher than the voltage at the SW node 128 by the threshold voltage, the voltage at the mobile level shift ground node 224 will be some voltage less than the voltage at the bootstrap node 126. For example, if the voltage at the bootstrap node 126 is 0V, the voltage at the SW node 128 is -6V, and the voltage at the mobile level shift ground node 224 is -4V. Thus, there will still be a voltage drop across the resistor 226 (e.g., 0V to -4V) to facilitate the state switching (e.g., flipping) of the switches 230, 232 during the deadband time.

[0041] Figure 3 For Figure 1 a replacement circuit implementation of the level shifter 105b. Figure 3 Including Figure 1 and / or Figure 2 a high-side level shift flip-flop 106b, a high-side level shifter latch 108, a bootstrap node 126, a switch node 128, and a ground node 132, a first example input voltage 200 and a second example input voltage 202, a third example input voltage 204, switches 212, 216, 230, 232, resistors 210, 214, 226, 228, diodes 218, 220, and a capacitor 222. Figure 3 Further including GaN-based switches (e.g., transistors) 300, 302.

[0042] Figure 3 The GaN transistor 300 operates in substantially the same manner as the switches 206, 208 of Figure 1 However, because the GaN transistor 300 is implemented as an n-channel GaN transistor, the input voltages 202, 204 are flipped so that the voltage at the INH input corresponds to the high-side control, and the voltage at the INL input corresponds to the low-side control. Alternatively, an inverter gate / circuit can be used, and the input voltages 202, 204 can remain the same as in Figure 2 However, the operation of the circuit of Figure 3 is substantially the same as the circuit of Figure 2They are essentially similar, wherein enabling GaN transistor 300 corresponds to outputting a high logic value at high-side gate node 130 (e.g., for low-side control and / or dead time), and enabling transistor 302 corresponds to outputting a low logic value at high-side gate node 130 (e.g., for high-side control).

[0043] Figure 4 For corresponding Figure 1 An example timing diagram 400 for the low-side to high-side control transition of the power converter 100. Timing diagram 400 includes an example high-side input voltage 402 and an example gate voltage 404 (e.g., corresponding to...). Figure 2 The voltage at the gate of switch 212), example shift level ground voltage 406, and example switch node voltage 408. Figure 4 Timing diagram 400 corresponds to a power converter whose load draws -4 amperes (A) during the dead time.

[0044] Before time t0, power converter 100 operates in low-side control (e.g., low-side switch 116 is enabled and high-side switch 110 is disabled, causing the voltage at switching node 128 to discharge toward ground). After time t0, power converter 100 operates in dead time (e.g., low-side switch 116 is disabled and high-side switch 110 is disabled) to prevent shoot-through. As described above, the inductor of output stage 124 draws current from ground during the dead time. Therefore, during the dead time, switching node voltage 408 becomes negative (e.g., -4.5V). Because diode 218 generates a voltage drop from shift level shift ground node 224 to switching node 128, shift level shift ground voltage 406 is higher than switching node voltage 408 by a diode threshold voltage (e.g., -2.7V). Moreover, when the voltage at shift level shift ground node 224 is negative, gate voltage 404 also becomes negative due to the voltage difference across resistor 210. At time t1, the high-side input voltage increases to trigger high-side control. Therefore, switches 206 and 300 are enabled to create a voltage difference across resistor 210, corresponding to an increase in gate voltage 404. As described above, based on gate voltage 404, enabling switch 212 causes level shifter latch 108 to toggle its output state by disabling switch 232 and enabling switch 230 to increase switch node voltage 408 sufficiently to enable the voltage of high-side switch 110. At time t1 (e.g., during high-side control), the shifted level-shift ground voltage 406 begins to track the voltage at analog ground (e.g., AGND node 132).

[0045] Figure 5 for Figure 1alternative circuit implementation of the high-side level-shifted flip-flops 106a, 106b that can be implemented to draw greater amounts of current to ground (e.g., -4A to -6A or higher) during low-side control. Figure 5 The high-side level-shifted flip-flops 106a, 106b include Figure 1 , Figure 2 and / or Figure 3 the switch node 128, the switches 212, 216, 300, 302, the diodes 218, 220, the capacitor 222, and the mobile level-shifted ground node 224. Figure 5 The high-side level-shifted flip-flops 106a, 106b further include example diodes 500, 504, 506, 508, 510, 514, 516, 518 and resistors 502, 512.

[0046] Figure 5 The high-side level-shifted flip-flops 106a, 106b include diodes 500, 504, 506, 508, 510, 514 and resistors 502, 512 to handle the greater amount of current drawn by the inductor of the output stage 124 during low-side control / dead time corresponding to more negative switch node voltage 128. For example, using Ohm’s law, Figure 1 I = V / R, where I is the current, V is the voltage, and R is the resistance. For example, using Ohm’s law, Figure 2 or Figure 3 The maximum load current that the level-shifted flip-flops 106a, 106b can handle is 0.6VT / Rdson LS, where VT is the threshold voltage and Rdson LS is the drain-source resistance of the switch 116. As described above, one way to increase the maximum load current is to make Rdson LS lower than Rdson HS (e.g., the drain-source resistance of the switch 110). Alternatively, a third diode 500, 510 can be added to the high-side level-shifted flip-flops 106a, 106b to adjust the formula using Ohm’s law corresponding to a higher maximum load current. For example, for the third diode, I load = 0.9VT / Rdson LS, which corresponds to a higher load current. In some examples, one or more charge pumps can be added to the gates of the switches 300, 302 to inject enough current to create a voltage drop across the respective resistors 210, 214 to create a voltage at the gates of the switches 212, 216 sufficient to enable the switches 212, 216.

[0047] Figure 6 is an example timing diagram 600 for a low-side control to high-side control transition of the power converter 100 of the high-side level-shifted flip-flops 106a, 106b using Figure 5 Figure 5 ​voltage at the gate of switch 300), an example drain voltage 604 (e.g., corresponding to the voltage at the drain of diode 500), an example gate voltage 605 (e.g., corresponding to the voltage at the gate of switch 212), an example mobile level shift ground voltage 606, and an example switch node voltage 608. Timing diagram 600 corresponds to a case where the load current reaches -6A during the dead time. Figure 5 Figure 5 voltage at the gate of switch 212), an example mobile level shift ground voltage 606, and an example switch node voltage 608. Timing diagram 600 corresponds to a case where the load current reaches -6A during the dead time.

[0048] Initially, timing diagram 600 begins with power converter 100 operating in dead time (e.g., at which time low side switch 116 is disabled and high side switch 110 is disabled) to prevent shoot through. As described above, the inductor of output stage 124 draws current from ground during the dead time. Thus, during the dead time, switch node voltage 608 becomes negative (e.g., -6V). Because diode 218 creates a voltage drop from mobile level shift ground node 224 to switch node 128, mobile level shift ground voltage 606 is higher than switch node voltage 608 by a diode threshold voltage (e.g., -4V). Also, when mobile level shift ground node 224 is negative, gate voltage 605 and drain voltage 604 also become negative due to the voltage difference across resistor 210. At tl, high side input voltage increases to trigger high side control. Thus, switches 206, 300 are enabled to create a voltage difference across resistor 210 through diode 500, which corresponds to an increase in drain voltage 604 and gate voltage 605. As described above, enabling switch 212 based on gate voltage 605 causes level shifter latch 108 to flip the output state by disabling switch 232 and enabling switch 230 to increase switch node voltage 608 to be high enough to enable high side switch 110. At time tl (e.g., during high side control), mobile level shift ground voltage 606 begins to track the voltage at analog ground (e.g., AGND node 132).

[0049] FIG. 7 illustrates an alternative circuit implementation of high side level shifter latch 108 including bidirectional hysteresis. Figure 1 High side level shifter latch 108 of FIG. 7 includes an example first hysteresis circuit 700, example switches 701, 703, 708, 710, example resistors 702, 704, an example second hysteresis circuit 706, a first example latch 712, a second example latch 714, an example circuit 715, an example driver 716, an example circuit 718, and example nodes 720, 721, 723, 722, 724, 726, 728, 730, 732, 734.

[0050] ​During the transition from low-side control to high-side control, a displacement current can flow due to the parasitic capacitance of the bond pad 123. In some examples, the displacement current can cause the voltage at the gates of both switches 230, 232 to be driven to ground, resulting in an error in the high-side level shifter latch 108 and losing the stored state information. When this error occurs, the first hysteresis circuit 700 and the second hysteresis circuit 706 restore the previous state of the high-side level shifter latch 108. The first hysteresis circuit 700 provides another parallel resistance (e.g., one or more resistors in parallel) to one of the resistors 226, 228 according to the previously stored state, and the second hysteresis circuit 706 provides a stronger path toward the switch node 128 via one of the switches 230, 232 according to the previously stored state (e.g., a higher resistance and path to the side of the latch that was previously high, and a lower resistance and path to the side of the latch that was previously low). In this way, if the voltage applied to the gates of the switches 230, 232 due to the parasitic capacitance are both zero, the stronger side will pull up in the correct direction to maintain the stored state information (e.g., the latch maintains its previous state).

[0051] The first hysteresis circuit 700 of FIG. 7 includes switches 701, 703 and resistors 702, 704. When the first switch 701 is enabled (e.g., based on the output of the rail-to-rail driver node 730), the resistor 702 provides additional resistance to the resistor 226 (e.g., by connecting in parallel, thereby lowering the total resistance to the bootstrap node 126), thereby providing a stronger pull-up path to the bootstrap node 126. Having a stronger path corresponds to the voltage at the bootstrap node 126 being pulled up faster, thereby returning the latch to the previous state by providing the correct voltage to the gate of the switch 232. When the second switch 703 is enabled, the resistor 704 provides additional resistance to the resistor 228 (e.g., by connecting in parallel), thereby providing a stronger pull-up path to the bootstrap node 126 through the resistor 228.

[0052] The second hysteresis circuit 706 of FIG. 7 includes switches 708, 710 to provide a strong path to the switch node 128. For example, when the first switch 708 is enabled, the switch 708 provides a stronger ground path on the side of the latch corresponding to the resistor 226, thereby causing a slower pull-up to the voltage at the bootstrap node 126, thereby returning the latch to the previous state by providing the correct voltage to the gate of the switch 232.

[0053] The first latch 712 of FIG. 7 corresponds to the latch described in Figure 2 and Figure 3 For example, the first latch 712 includes Figure 2 and Figure 3resistors 226, 228 and switches 230, 232. Also, latch 712 includes additional components (e.g., diode clamps, switches, resistors, capacitors, etc.) to handle common mode current. For example, the additional components clamp the voltage at different nodes to the bootstrap rate potential or the switch node rate potential.

[0054] Second latch 714 of FIG. 7 operates in a substantially similar manner as first latch 712. Second latch 714 receives the voltage on each side of first latch 712 (e.g., the voltage at first latch output nodes 721, 723) and adjusts the state based on the received voltage to produce a second latch output logic signal on second latch output nodes 724, 726. The voltage on second latch output nodes 724, 726 is coupled to rail-rail driver output nodes 728, 730, 732, 734, which are coupled to the gates of switches 701, 703, 708, 710. Buffer output nodes 730, 728 are designed to output a voltage higher than the voltage on the bootstrap node potential to effectively drive n-channel devices. For example, rail-rail driver output nodes 730, 732 are coupled to switches 701, 708, and rail-rail driver output nodes 728, 734 are coupled to switches 703, 710. In this manner, the switches 701, 703, 708, 710 of hysteresis circuits 700, 706 use previously stored state information to ensure that parasitic capacitance that causes errors in first latch 712 (e.g., by setting first latch 712 to the previously stored state information based on the additional resistance / path, 0V at both nodes 720, 722 does not cause errors in second latch 714).

[0055] Circuit 715 of FIG. 7 forces a predefined current state during startup. In this manner, the predefined state information will be set by first latch 712 and second latch 714 at startup. Circuit 716 corresponds to a rail-rail driver that outputs the voltage at bootstrap node 126 or a switch node 128 corresponding to the output(s) of second latch 714 on high-side gate node 130. Circuit 716 can be used to ensure that sufficient current is used to drive the gate of switch 110 at a predefined speed. Circuit 718 provides under-voltage protection and startup clamping to define the state of the latches during power up.

[0056] Figure 8 is an example timing diagram 800 corresponding to a low-side control to high-side control transition for power converter 100 using high-side level shifter latch 108 of FIG. 7. Timing diagram 800 includes a first example control voltage 802 (e.g., corresponding to Figure 2 and / or Figure 3The voltage at the drain of switch 212, which corresponds to the first latch 712 on the first side, and the second example control voltage 804 (e.g., corresponding to...) Figure 2 and / or Figure 3 The voltages at the drain of switch 216 correspond to the voltages of the first latch 712 on the second first side, example first latch output voltage 806 corresponding to the voltage at node 720, example first latch output voltage 808 corresponding to the voltage at node 722, example second latch output voltage 810 corresponding to the voltage at node 724, example second latch output voltage 812 corresponding to the voltage at node 726, and example voltage 814 corresponding to switch node 128. Voltages 802-812 are relative to voltage 814 at switch node 128. For example, when voltage 810 is 6V, it is 6V higher than voltage 814 at switch node 128.

[0057] Before time t0, the power converter 100 operates in low-side control or dead-time. At time t0, the first low-side control voltage 802 goes low and the second low-side control voltage 804 goes high, indicating a transition from low-side control to high-side control. Therefore, between times t0 and t1, the first latch output voltage 806 and the second latch output voltage 810 drop to low voltages, while the first latch output voltage 808 and the second latch output voltage 812 rise to high voltages. Between times t1 and t2, parasitic capacitances on components of the power converter 100 cause the control voltages 802, 804 and similarly cause the first latch output voltages 806, 808 to drop to low voltages. However, hysteresis circuits 700, 706 cause the level shifter latch 108 to maintain its previously stored state (e.g., corresponding to the high-side state that occurs between times t0 and t1). In this way, the second latch outputs 810, 812 maintain their voltage levels, and the switching node voltage 814 increases to a high voltage without any error corresponding to parasitic capacitance.

[0058] Figure 9 It shows Figure 1 An example of a bonding pad 122. The bonding pad includes an example bonding pad connection terminal 900, an example 2-DEG layer 902, and an example contact 904 connected to the switch node 128.

[0059] As mentioned above, the bonding pads correspond to the amount of parasitic capacitance. Parasitic capacitance can lead to undesirable ground paths. Therefore, shielding can be used to redirect the ground paths caused by parasitic capacitance to the path to SW node 128, thereby limiting the impact of parasitic induced currents on nodes 720 and 722 of Figure 7.

[0060] Figure 9The bond pad 123 includes a bond pad terminal 900 that connects one component to another using a bond wire. On the back side of the bond pad terminal 900, the bond pad 123 includes a 2-DEG layer 902 (e.g., a 2-DEG sheet) that corresponds to some resistance and a contact 904 connected to the 2-DEG layer 902. The 2-DEG layer 902 is a conductive layer, which is a way to achieve shielding. The contact 904 is connected to the SW node 128. In this way, the parasitic capacitance is tied to the SW node 128 as opposed to ground. In this way, the parasitic current on the nodes 720, 722 is minimized and the effect of the parasitic capacitance is reduced.

[0061] Although the example ways of implementing the high-side level shifters 105a, 105b are shown in Figure 2 , Figure 3 , Figure 5 and FIG. 7, one or more elements, processes, and / or devices shown in Figure 1 , Figure 2 , Figure 3 , Figure 5 and FIG. 7 can be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Further, the HS level shift flip-flops 106a, 106b, the HS level shifter latches 108, and / or more generally the high-side level shifters 105a, 105b of Figures 1-3 , Figure 5 and FIG. 7 can be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, the HS level shift flip-flops 106a, 106b, the HS level shifter latches 108, and / or more generally the high-side level shifters 105a, 105b of Figures 1-3 , Figure 5 and FIG. 7 can be implemented with any one or more analog or digital circuits, logic circuits, programmable processor(s), programmable controller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)) and / or field programmable logic device(s) (FPLD(s)). When reading any claims into the application that append "circuitry" to any element thereof, it is submitted that the element is specifically designed to perform the recited function s) and therefore the claim is not addressed to an article of manufacture including a software and / or firmware component. When reading any claims into the application that append "circuitry" to any element thereof, it is submitted that the element is specifically designed to perform the recited function s) and therefore the claim is not addressed to an article of manufacture including a software and / or firmware component. Figures 1-3 , Figure 5At least one of the high-side level shifters 105a and 105b in Figure 7 is hereby explicitly defined as including non-transitory computer-readable storage devices or storage disks, such as memory, digital versatile discs (DVDs), compact discs (CDs), Blu-ray discs, etc., including software and / or firmware. Furthermore, Figure 1 The HS level shifters 105a and 105b may include additions to or replacements of Figures 1-4 , Figure 5 And one or more of the elements, processes and / or devices shown in Figure 7, and / or may include more than one or all of the elements, processes and devices shown. As used herein, the phrase “communication” (including variations thereof) covers direct communication and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but additionally includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals and / or one-off events.

[0062] exist Figure 10 and Figure 11 The diagram shows the representation used for implementation. Figure 1 The power converter 100 is illustrated with example hardware logic, machine-readable instructions, a hardware-implemented state machine, and / or any combination thereof flowcharts. Machine-readable instructions can be generated by a computer processor (such as, in conjunction with, below) Figure 12 The processor 1212 shown in the processor platform 1200 discussed executes an executable program or a portion thereof. This program may be embodied in software stored on a non-transitory computer-readable storage medium (such as a CD-ROM, floppy disk, hard disk drive, DVD, Blu-ray disc, or memory associated with the processor 1212), but the entire program and / or portions thereof may alternatively be executed by a device other than the processor 1212 and / or embodied in firmware or dedicated hardware. Furthermore, although references... Figures 10-11 The flowchart shown illustrates the procedure, but many other methods of implementing the power converter 100 can be used alternatively. For example, the execution order of the blocks can be changed, and / or some of the blocks described can be changed, eliminated, or combined. Additionally or alternatively, any or all blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, comparators, operational amplifiers, logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware.

[0063] As mentioned above, Figures 10-11The process can be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on non-transitory computer and / or machine-readable media (such as hard disk drives, flash memory, read-only memory, compact disks, digital universal disks, caches, random access memory, and / or any other storage device or disk that stores information for any duration (e.g., extended time periods, permanently, for transient instances, for temporary buffering, and / or for caching information)). As used herein, the term "non-transitory computer-readable media" is explicitly defined to include any type of computer-readable storage device and / or disk, excluding propagation signals and transmission media.

[0064] In this specification, the term "and / or" (when used in the form of A, B, and / or C) means any combination or subset of A, B, and C, such as: (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; (g) A, B, and C. Furthermore, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") means an implementation that includes any of the following: (a) at least one A; (b) at least one B; (c) at least one A and at least one B.

[0065] Figure 10 As a representative, it can be made by Figure 1 The power converter 100 executes example machine-readable instructions and / or hardware configurations of example flowchart 1000 to control the high-side switch 110 based on control signals from the controller 102. Although combined with... Figure 1 The power converter 100 is described Figure 10 The flowchart 1000 is the same as the flowchart 1000, but it can be described in conjunction with any type of switching power supply converter.

[0066] At block 1002, HS-level shift triggers 106a and 106b receive a disable high-side signal. For example, switch 208 can receive a low logic value at its gate, and switch 206 can receive a high logic value at its gate (e.g., corresponding to enabling switch 208 and disabling switch 206). In another example, Figure 3 Switch 300 can receive a low logic value at its gate, and switch 302 can receive a high logic value at its gate (e.g., corresponding to disabling switch 300 and enabling switch 302). At block 1004, power converter 100 disables high-side switch 110, as described below. Figure 11Further described. During low-side control, the voltage at the switch node 128 reaches zero volts and / or a negative voltage. Accordingly, during low-side control, the bootstrap capacitor 118 charges based on the voltage difference between GVDD and the SW node 128 (e.g., via the diode 120). As described above in connection with Figure 1 Further described, because the bootstrap capacitor 118 is charged during low-side control, the voltage at the bootstrap node 126 is GVDD higher than the switch node 128 of the bootstrap capacitor 118 during high-side control.

[0067] At block 1005, the low-side level shifter latch 114 enables the low-side switch 116 by applying a high voltage to the gate of the low-side switch 116. After the low-side level shifter latch 114 enables the low-side switch 116, the power converter 100 remains in low-side mode until a high-side switch signal is received from the controller 102. In some examples, the controller 102 outputs a control signal to disable both the high-side switch 110 and the low-side switch 116 for a duration of time between low-side / high-side transitions to prevent shoot-through. At block 1006, the HS level shift flip-flops 106a, 106b determine whether a high-side switch signal has been received. For example, when the voltage at the gate of the switch 206 is a low logic value and the voltage at the gate of the switch 208 is a high logic value, the HS level shift flip-flops 106a, 106b determine that a high-side switch signal is received. In another example, when the voltage at the gate of the switch 300 is a high logic value and the voltage at the gate of the switch 302 is a low logic value, the HS level shift flip-flops 106a, 106b determine that a high-side switch signal is received.

[0068] If the HS level shift flip-flops 106a, 106b determine that the high-side switch signal is not received (block 1006: NO), the process continues with the high-side switch 110 disabled. If the HS level shift flip-flops 106a, 106b determine that the high-side switch signal is received (block 1006: YES), the LS level shift flip-flops 112 and the LS level shifter latch 114 disable the low-side switch 116 (block 1007) (e.g., by applying a low voltage to the gate of the low-side switch 116). At block 1008, the diode 218 creates a voltage drop from the mobile level shift ground node 224 to the switch node 128. For example, during a transition from low to high or during a dead time to high-side transition, the voltage at the switch node 128 can be negative. Accordingly, the diode 218 creates a voltage drop such that the voltage at the mobile level shift ground node 224 is higher than the voltage at the switch node 128 by a threshold voltage (e.g., 0.7V, 1.5V, 2V, etc.). Because the mobile level shift ground node 224 can be negative, the diode 220 prevents current from flowing from the mobile level shift ground node 224 to the AGND node 132 due to the large degree of negative voltage at the switch node 128. Accordingly, the voltage at the mobile level shift ground node 224 tracks the voltage at the switch node 128 when the voltage at the switch node 128 is negative.

[0069] At block 1010, the voltage applied to the gate of the switch 206, 300 enables the switch 206, 300 to draw current from the input voltage 200 (e.g., GVDD) to the mobile level shift ground node 224 via the first resistor 210, creating a voltage drop across the first resistor 210. At block 1012, the voltage across the resistor 210 (e.g., the voltage at the gate of the switch 212) enables the switch 212. At block 1014, because the enabling of the switch 212 creates a path from the bootstrap node 126 to the mobile level shift ground node 224 via the resistor 226, the resistor 226 creates a low voltage at the gate of the switch 232 to disable the switch 232. At block 1016, in response to the enabling of the switch 212, the latch of the high-side level shifter latch 108 toggles the high logic latch state because there is no path to ground via the resistor 228, resulting in the voltage at the bootstrap node 126 (e.g., a voltage high enough to enable the switch 110) being output to the gate of the switch 110 to enable the high-side control.

[0070] At block 1018, the HS level shift flip-flops 106a, 106b determine whether a low-side switch signal has been received. For example, the HS level shift flip-flops 106a, 106b determine whether a low-side switch signal is received when the voltage at the gate of the switch 206 is high and the voltage at the gate of the switch 208 is low or if the voltage at the gate of the switch 300 is low and the voltage at the gate of the switch 302 is high. If the HS level shift flip-flops 106a, 106b determine that a low-side switch signal has not been received (block 1018: NO), the process continues in high-side control. If the HS level shift flip-flops 106a, 106b determine that a low-side switch signal has been received (block 1018: YES), the process returns to block 1004 to disable the high-side switch 110.

[0071] Figure 11 An example flowchart 1004 of example machine-readable instructions and / or hardware configurations that can be executed by the power converter 100 to disable the high-side switch 110, as described above in connection with block 1004 of the power converter 100, is shown in FIG. 10B. Although the flowchart 1004 is described in connection with the power converter 100, the flowchart 1004 can be described in connection with any type of switching power converter. Figure 1 Figure 10 Figure 1 Figure 11

[0072] At block 1102, the diode 220 generates a voltage drop from the mobile level shift ground node 224 to the analog ground (AGND) node 132. As described above in connection with block 1102 of the power converter 100, during high-side control, the voltage at the switch node 128 is positive. Thus, the diode 218 prevents current from flowing from the switch node 128 to the mobile level shift ground node 224. In this way, the voltage at the mobile level shift ground node 224 tracks the voltage of 0V at the AGND node 132. Thus, when the voltage at the SW node 128 is positive, the voltage at the mobile level shift ground node 224 is higher than the ground voltage at the AGND node 132 by a threshold voltage (e.g., corresponding to the threshold voltage of the diode 220). Figure 2

[0073] ​​​​​At block 1104, the voltage applied to the gate of switch 208, 302 enables switch 208, 302 to draw current from input voltage 200 to mobile level shift ground node 224 via resistor 214, creating a voltage drop across resistor 214. At block 1106, the voltage across resistor 214 (e.g., the voltage at the gate of switch 216) enables switch 216. At block 1108, because enabling switch 216 creates a path from bootstrap node 126 to mobile level shift ground node 224 via resistor 228, resistor 228 creates a low voltage at the gate of switch 230 to disable switch 230. At block 1110, the latch of high-side level shifter latch 108 triggers to a low logic latch state in response to enabling switch 216 because high-side gate node 130 is tied to switch node 128, causing the voltage at switch node 128 (e.g., a voltage corresponding to being low enough to disable switch 110) to be output to the gate of switch 110 to enable low-side control. After block 1110, the process returns to block 1102. Figure 10 of block 1006.

[0074] Figure 12 A block diagram of an example processor platform 1200 is shown, which is structured to execute instructions of Figures 10-11 to implement the HS level shifter 105a, 105b and / or controller 102 of FIGS. Figures 1-3 , Figure 5 and / or FIG. 7. Processor platform 1200 can be, for example, a server, a self-learning machine (e.g., a neural network), an internet appliance, a microcontroller, or any other type of computing device.

[0075] Processor platform 1200 of the illustrated example includes a processor 1212. Processor 1212 of the illustrated example is hardware. For example, processor 1212 can be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. A hardware processor can be a semiconductor-based (e.g., silicon-based) device. In this example, processor implements high-side level shift flip-flops 106a, 106b and / or HS level shifter latch 108.

[0076] Processor 1212 of the illustrated example includes local memory 1213 (e.g., cache). Processor 1212 of the illustrated example communicates via a bus 1218 with main memory including a volatile memory 1214 and a non-volatile memory 1216. Volatile memory 1214 can be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), and / or the like. Non-volatile memory 1216 can be implemented by read only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, and / or the like. dynamic random access memory and / or any other type of random access memory device. The non-volatile memory 1216 can be implemented by flash memory and / or any other desired type of memory device. Access to both the main memory 1214, 1216 is controlled by a memory controller.

[0077] The processor platform 1200 of the illustrated example also includes an interface circuit 1220. The interface circuit 1220 can be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), a Bluetooth® interface, a near field communication (NFC) interface, and / or a PCI Express interface.

[0078] In the illustrated example, one or more input devices 1222 are connected to the interface circuit 1220. The input device(s) 1222 permit a user to enter data and / or commands into the processor 1212. The input device(s) can be implemented by, for example, a sensor, a microphone, a camera (still or video), a keyboard, or a button.

[0079] One or more output devices 1224 are also connected to the interface circuit 1220 of the illustrated example. The output devices 1224 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube display (CRT), an in-place switching (IPS) display, a touchscreen, etc.), haptic output devices, and / or speakers. Thus, the interface circuit 1220 of the illustrated example, in one

[0080] The interface circuit 1220 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and / or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) via a network 1226. The communication can be via, for example, an Ethernet connection, a digital subscriber line (DSL), a telephone line, a coaxial cable, a satellite system, a line-of-site wireless system, a cellular telephone system, etc.

[0081] The processor platform 1200 of the illustrated example also includes one or more mass storage devices 1228 for storing software and / or data. Examples of such mass storage devices 1228 include floppy

[0082] Figures 10-11 ​The machine executable instructions 1232 can be stored in the mass storage device 1228, in the volatile memory 1214, in the non-volatile memory 1216, and / or on a removable non-transitory computer readable storage medium such as a CD or DVD.

[0083] Example 1 includes an apparatus comprising: a latch including a first node coupled to a first source of a first switch and an output coupled to a first gate of the first switch; a first diode coupled to the first node and a second node; a second diode coupled to the second node and ground; a second switch coupled to a voltage source and the second node; and a third switch including a third gate coupled to the second switch, a third source coupled to the second node, and a third drain coupled to the latch.

[0084] Example 2 includes the apparatus of example 1, wherein the voltage source is coupled to ground.

[0085] Example 3 includes the apparatus of example 1, wherein the first switch is a high side switch coupled to an output stage of a power converter.

[0086] Example 4 includes the apparatus of example 3, further comprising a low side switch coupled to the output stage of the power converter, the low side switch including a first drain-source resistance lower than a second drain-source resistance of the high side switch.

[0087] Example 5 includes the apparatus of example 1, further comprising: a fourth switch coupled to the voltage source; and a fifth switch including a fifth gate coupled to the fourth switch, a fifth source coupled to the second node, and a fifth drain coupled to the latch.

[0088] Example 6 includes the apparatus of example 5, wherein the second switch is coupled to the second node via a first resistor, and the fifth switch is coupled to the second node via a second resistor.

[0089] Example 7 includes the apparatus of example 1, wherein the first diode includes a first anode and a first cathode, wherein the first anode is coupled to the second node and the first cathode is coupled to the first node.

[0090] Example 8 includes the apparatus of example 7, wherein the second diode includes a second anode and a second cathode, wherein the second anode is coupled to the second node and the second cathode is coupled to ground.

[0091] Example 9 includes the apparatus of example 1, further comprising a bond pad to couple the second switch to the latch, the bond pad including a two-dimensional electron gas layer coupled to a contact coupled to the first node.

[0092] Example 10 includes the apparatus of Example 9, wherein the two-dimensional electron gas layer and the contact coupled to the first node reduce parasitic capacitance.

[0093] Example 11 includes an apparatus comprising: a latch that outputs a first voltage corresponding to a first node or a second voltage corresponding to a second node to a transistor of a power converter based on a first state or a second state of the latch, the second node coupled to a source of the transistor; a first diode that creates a first voltage drop from a third node to the second node when the second voltage corresponding to the second node is negative and prevents a first current from flowing from the second node to the third node when the second voltage corresponding to the second node is positive; and a second diode that creates a second voltage drop from the third node to ground when a third voltage at the third node is positive and prevents a second current from flowing from ground to the third node when the third voltage at the third node is negative.

[0094] Example 12 includes the apparatus of Example 11, further comprising: a first transistor that allows a third current to flow from a voltage source through a first resistor to the third node based on a first control signal; and a second transistor that is enabled when the first transistor allows the third current to flow through the first resistor, the enablement of the second transistor creating a first path from the first node of the latch to the third node, the latch triggering the first state of the latch in response to the enablement of the second transistor.

[0095] Example 13 includes the apparatus of Example 12, further comprising: a third transistor that allows a fourth current to flow from the voltage source through a second resistor to the third node based on a second control signal; and a fourth transistor that is enabled when the third transistor allows the fourth current to flow through the second resistor, the enablement of the fourth transistor creating a second path from the first node of the latch to the third node, the latch triggering the second state of the latch in response to the enablement of the fourth transistor.

[0096] Example 14 includes the apparatus of Example 11, wherein the transistor is a high-side transistor that includes a first drain-source resistance, the apparatus further comprising a low-side transistor that includes a second drain-source resistance that is lower than the first drain-source resistance.

[0097] Example 15 includes the apparatus of Example 11, further comprising a hysteresis circuit that adds resistance to the first side of the latch or the second side of the latch based on a previous state of the latch.

[0098] Example 16 includes the apparatus of Example 15, wherein the hysteresis circuit is to add the resistance to prevent errors of the latch caused by parasitic capacitance.

[0099] Example 17 includes the apparatus of Example 11, wherein the third voltage at the third node corresponds to the second voltage at the second node when the second voltage is negative, and the third voltage at the third node corresponds to a voltage difference between the third node and ground when the second voltage is positive.

[0100] Example 18 includes the apparatus of Example 11, further comprising a bond pad to couple the first diode to the latch, the bond pad comprising a two-dimensional electron gas layer coupled to the second node to reduce parasitic capacitance.

[0101] Example 19 includes a method comprising: at a latch, outputting a first voltage corresponding to a first node or a second voltage corresponding to a second node to a high-side transistor of a power converter based on a control signal, the second node coupled to a source of the high-side transistor; when the second voltage corresponding to the second node is negative, causing a first voltage drop from a third node to the second node, and when the second voltage corresponding to the second node is positive, preventing a first current from flowing from the second node to the third node; when a third voltage at the third node is positive, causing a second voltage drop from the third node to ground, and when the third voltage at the third node is negative, preventing a second current from flowing from ground to the third node.

[0102] Example 20 includes the method of Example 19, further comprising adding a resistance to a first side of the latch or a second side of the latch based on a previous state of the latch to add the resistance to prevent errors of the latch caused by parasitic capacitance.

[0103] Example 21 includes the method of Example 19, wherein the third voltage at the third node corresponds to the second voltage at the second node when the second voltage is negative, and the third voltage at the third node corresponds to a voltage difference between the third node and ground when the second voltage is positive. From the foregoing, it will be appreciated that example methods, apparatus and articles of manufacture have been described that facilitate high-side control of a switching power converter. The described methods, apparatus and articles of manufacture improve efficiency of using a power converter by facilitating low-side control to high-side control transitions, even when a switching node of the power converter is negative. The described methods, apparatus and articles of manufacture accordingly address one or more improvements in functionality of a power converter.

[0104] Within the scope of the claims, modifications in the described embodiments can be made, and other embodiments can be utilized.

Claims

1. A power converter comprising: a latch having a latch input node, a boost node, a switch node, and a latch output node; a first diode having an anode coupled to an intermediate ground node, and a cathode coupled to the switch node; a second diode having an anode coupled to the intermediate ground node, and a cathode coupled to an analog ground terminal; a first switch coupled between the latch input node and the intermediate ground node; and a second switch coupled between a voltage supply node and a control terminal of the first switch.

2. The power converter of claim 1, wherein the second switch has a first current terminal coupled to the voltage supply node, and a second current terminal coupled to the control terminal of the second switch.

3. The power converter of claim 2, further comprising: a resistor having a first end coupled to the second current terminal of the second switch, and a second end coupled to the intermediate ground node.

4. The power converter of claim 1, wherein the first switch is configured to enable a conductive path between the latch input node and the intermediate ground node.

5. The power converter of claim 1, wherein the second switch is configured to enable a conductive path between the voltage supply node and the control terminal of the first switch.

6. The power converter of claim 1, wherein the first diode comprises a diode-connected gallium nitride transistor.

7. The power converter of claim 1, wherein the second diode comprises a diode-connected gallium nitride transistor.

8. The power converter of claim 1, further comprising: a bootstrap capacitor having a first plate coupled to the boost node, and a second plate coupled to the switch node; and a third diode having an anode coupled to the voltage supply node, and a cathode coupled to the boost node.

9. The power converter of claim 1, further comprising: a high-side power switch having a first current terminal configured to receive an input voltage; a second current terminal coupled to the switch node configured to deliver an output voltage; and a control terminal coupled to the latch output node, wherein the switch node is isolated from the intermediate ground node by the first diode.

10. The power converter of claim 9, further comprising: a low-side power switch having a first current terminal coupled to the switch node configured to deliver the output voltage; a second current terminal coupled to a power supply ground terminal; a control terminal decoupled from the latch output node, wherein the power supply ground terminal is isolated from the intermediate ground node and the analog ground terminal.

11. A power converter comprising: ​ ​ a latch having a latch upper supply node, a latch lower supply node, a latch input node, and a latch output node; a first diode having an anode coupled to an intermediate ground node, and a cathode coupled to the latch lower supply node; a second diode having an anode coupled to the intermediate ground node, and a cathode coupled to an analog ground terminal; a first switch configured to establish a conductive path between the latch input node and the intermediate ground node; and a second switch configured to enable the first switch based on a gate driver input signal.

12. The power converter of claim 11, further comprising: a resistor having a first end, and a second end coupled to the intermediate ground node, wherein the second switch has: a control terminal configured to receive the gate driver input signal; a first current terminal coupled to a voltage supply node; and a second current terminal coupled to the control terminal of the second switch and the first end of the resistor.

13. The power converter of claim 11, wherein: the first diode comprises a first diode junction gallium nitride transistor; and the second diode comprises a second diode junction gallium nitride transistor.

14. The power converter of claim 11, further comprising: a bootstrap capacitor having a first plate coupled to the latch upper supply node, and a second plate coupled to the latch lower supply node; and a third diode having an anode coupled to a voltage supply node, and a cathode coupled to the latch upper supply node.

15. The power converter of claim 11, further comprising: a high-side power switch having: a first current terminal configured to receive an input voltage; a second current terminal coupled to a switch node configured to deliver an output voltage; and a control terminal coupled to the latch output node, wherein the switch node is coupled to the latch lower supply node and isolated from the intermediate ground node by the first diode.

16. The power converter of claim 15, further comprising: a low-side power switch having: a first current terminal coupled to the switch node configured to deliver the output voltage; a second current terminal coupled to a power supply ground terminal; and a control terminal decoupled from the latch output node, wherein the power supply ground terminal is isolated from the intermediate ground node and the analog ground terminal.

17. A power converter, comprising: a latch having a latch upper supply node, a latch lower supply node, a latch input node, and a latch output node; a first diode junction gallium nitride (GaN) transistor having an anode coupled to an intermediate ground node, and a cathode coupled to the latch lower supply node; a second diode junction GaN transistor having an anode coupled to the intermediate ground node, and a cathode coupled to an analog ground terminal. a second diode-connected GaN transistor having an anode coupled to the intermediate ground node, and a cathode coupled to an analog ground terminal; a first switch configured to establish a conductive path between the latch input node and the intermediate ground node; and a second switch configured to enable the first switch based on a high-side gate driver input signal.

18. The power converter of claim 17, further comprising: a high-side power switch having a first current terminal configured to receive an input voltage; a second current terminal coupled to a switching node configured to deliver an output voltage; and a control terminal coupled to the latch output node, wherein the switching node is coupled to the latch lower supply node and isolated from the intermediate ground node by the first diode.

19. The power converter of claim 18, further comprising: a low-side power switch having a first current terminal coupled to the switching node configured to deliver the output voltage; a second current terminal coupled to a power supply ground terminal; and a control terminal decoupled from the latch output node, wherein the power supply ground terminal is isolated from the intermediate ground node and the analog ground terminal.

20. The power converter of claim 17, further comprising: a bootstrap capacitor having a first plate coupled to the latch upper supply node, and a second plate coupled to the latch lower supply node; and a third diode having an anode coupled to a voltage supply node, and a cathode coupled to the latch upper supply node.

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