Voltage controller and memory device including the same

Abstract

The present disclosure relates to a voltage controller and a memory device including the voltage controller. A memory device of the present disclosure includes: a memory cell array including a plurality of memory cells storing data; a sense amplifier connected to the memory cell array; and a voltage controller. The voltage controller includes a voltage driver that generates a control signal and an overdrive controller that generates an overdrive control signal, the overdrive control signal regulating the generation of the control signal in response to a comparison result between the control signal and a reference voltage and at least one of process, voltage, and temperature (PVT) information. The voltage driver adjusts the control signal in response to the overdrive control signal to generate an overdrive control signal, and outputs the overdrive control signal to the sense amplifier.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0126400 filed on October 11, 2019, in the Korean Intellectual Property Office, the subject matter of which is incorporated herein by reference. Technical Field

[0003] The inventive concept generally relates to a voltage controller and a memory device including the same. Background Art

[0004] Memory devices perform various operations, including write operations, read operations, erase operations, and trim operations. These operations are performed and controlled, at least in part, using multiple control voltages. There are many different types of control signals, and some control signals differ in nature depending on the mode or other operating characteristics of the memory device. For example, some memory devices may overdrive one or more control voltages before applying the overdrive control voltage to the memory cell array to maintain a desired level of the control voltage. In this way, the control voltage can be maintained within a target range or above a target level.

[0005] In this regard, the control voltage may be affected (or may unexpectedly change) in response to changes in process and temperature conditions and in response to changes in the level of one or more externally provided supply voltages. Therefore, in order to stably operate the memory device, the control voltage must be controlled taking into account process, voltage, and temperature (PVT) conditions. Summary of the Invention

[0006] One aspect of the inventive concept provides a memory device that operates more stably by controlling a specific control voltage in consideration of PVT conditions. Another aspect of the inventive concept controls a specific control voltage using PVT information during operation of the memory device.

[0007] In one aspect, the present inventive concept provides a memory device comprising: a memory cell array including a plurality of memory cells storing data; a sense amplifier connected to the memory cell array; and a voltage controller. The voltage controller includes: a voltage driver generating a control signal; and an overdrive controller generating an overdrive control signal, the overdrive control signal regulating generation of the control signal in response to a comparison result between the control signal and a reference voltage and at least one of process, voltage, and temperature (PVT) information. The voltage driver adjusts the control signal in response to the overdrive control signal to generate an overdrive control signal, and outputs the overdrive control signal to the sense amplifier.

[0008] In another aspect, the present invention provides a memory device comprising: a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; a sense amplifier connected to the plurality of bit lines and sensing amplified data stored in the plurality of memory cells; an input and output circuit for exchanging data via the plurality of data lines using a data signal (DQ) and a data strobe signal (DQS); and a voltage controller for providing a control voltage to at least one of the plurality of memory cells and the sense amplifier. The voltage controller includes: a voltage driver for generating the control voltage; a first overdrive controller for generating a first overdrive control signal applied to the voltage controller in response to a change in an externally provided power supply voltage to adjust the generation of the control voltage; and a second overdrive controller for generating a second overdrive control signal applied to the voltage driver in response to at least one of a ZQ code for matching an on-resistance of the input and output circuit to a reference ZQ resistance and a phase difference between the data signal (DQ) and the data strobe signal (DQS) to adjust the generation of the control voltage.

[0009] In another aspect, the present inventive concept provides a voltage controller including: a voltage driver configured to generate a control signal for performing a bit line sensing operation of a memory device; a first overdrive controller configured to generate a first overdrive control signal in response to a result of comparing the control signal with a reference voltage, the first overdrive control signal regulating generation of the control signal; and a second overdrive controller configured to generate a second overdrive control signal in response to process, voltage, and temperature (PVT) information, the second overdrive control signal regulating generation of the control signal. The PVT information includes at least one of a ZQ code for matching on-resistances of input and output circuits of the memory device with reference ZQ resistances and a phase difference between a data signal (DQ) and a data strobe signal (DQS) applied to the input and output circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and other advantages of the present invention will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a memory device according to an example embodiment of the inventive concept;

[0012] Figure 2 is a block diagram further illustrating, in one example, a voltage controller of a memory device according to an example embodiment of the inventive concept;

[0013] Figure 3A and Figure 3B are corresponding signal waveform diagrams illustrating specific timing considerations for a memory device according to example embodiments of the inventive concepts;

[0014] Figure 4 is a block diagram further illustrating, in another example, a voltage controller of a memory device according to an example embodiment of the inventive concept;

[0015] Figure 5A and Figure 5B is to list the Figure 4 a corresponding chart of exemplary mapping tables stored by a voltage controller;

[0016] Figure 6A 、 Figure 6B and Figure 6C is a corresponding signal diagram of a method for adjusting a control voltage in response to PVT information;

[0017] Figure 7 is a block diagram further illustrating, in one example, an overdrive controller according to an example embodiment of the present inventive concept;

[0018] Figure 8A is a block diagram further illustrating an overdriving controller according to an example embodiment of the present inventive concept in another example;

[0019] Figure 8B and Figure 8C It shows the operation Figure 8A A corresponding conceptual diagram of the overdrive controller method;

[0020] Figure 9 is a block diagram illustrating a memory device according to an example embodiment of the inventive concept in an example control logic;

[0021] Figure 10 and Figure 11 is a flowchart summarizing a method of generating a control voltage in response to PVT information in a memory device according to an example embodiment of the inventive concept; and

[0022] Figure 12 is a block diagram illustrating a computing device including a memory device according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0023] Hereinafter, exemplary embodiments of the inventive concept will be described with additional reference to the accompanying drawings. Like reference numerals and signs indicate like (or similar) elements.

[0024] Figure 1 is a block diagram illustrating a memory device 10 according to an example embodiment.

[0025] Reference Figure 1The memory device 10 may output data via a plurality of data lines DQ in response to a specific command CMD, an address ADDR, and a control signal. At least one of the command CMD, the address ADDR, and the control signal may be provided externally from, for example, a central processing unit (CPU) or a memory controller.

[0026] like Figure 1 As shown, the memory device 10 may include a memory cell array 110 , an address buffer 112 , a command buffer 114 , control logic 116 , a row decoder 118 , a column decoder 119 , a sense amplifier 120 , input and output circuits 122 , and a voltage controller 130 .

[0027] The memory cell array 110 may include a plurality of word lines, a plurality of column lines, and a plurality of memory cells, each capable of storing data. The plurality of memory cells may be arranged at points where the plurality of word lines and the plurality of bit lines intersect (or intersect) each other. The plurality of memory cells may be provided in a matrix arrangement of rows and columns, wherein the plurality of word lines may be connected to the rows of the plurality of memory cells, and the plurality of bit lines may be connected to the columns of the plurality of memory cells.

[0028] The address buffer 112 may receive an address ADDR from a CPU or a memory controller. The address ADDR may include a row address RA for addressing one or more rows of the memory cell array 110 and a column address CA for addressing one or more columns of the memory cell array 110. The address buffer 112 may send the row address RA to a row decoder 118 and may send the column address CA to a column decoder 119.

[0029] The command buffer 114 may receive a command CMD from the CPU or the memory controller. The command CMD may take many different forms, including, for example, an activate command, a read command, a write command, a precharge command, etc. The command buffer 114 may send the command CMD to the control logic 116 .

[0030] The control logic 116 may be used to control the overall operation of the memory device 10. For example, the control logic 116 may decode a row address strobe signal ( / RAS), a column address strobe signal ( / CAS), a chip select signal ( / CS), and a write enable signal ( / WE) received from a CPU or a memory controller to generate a control signal corresponding to a command CMD.

[0031] In response to the row address RA received from the address buffer 116, the row decoder 118 may be used to select at least one word line among a plurality of word lines connected to the memory cell array 110. For example, the row decoder 130 may decode the row address RA received from the address buffer 120 and select at least one word line corresponding to the decoded row address RA.

[0032] The column decoder 119 may decode the column address CA received from the address buffer 116 and transmit the decoded column address to the sense amplifier 120 .

[0033] The sense amplifier 120 may be connected to a plurality of bit lines of the memory cell array 110. The sense amplifier 120 may be used to select at least one bit line among the plurality of bit lines connected to the memory cell array 110 in response to a decoded column address CA received from the column decoder 119. For example, the sense amplifier 120 may select at least one of the bit lines corresponding to the decoded column address CA received from the column decoder 119. In addition, the sense amplifier 120 may sense a voltage change of the selected bit line and may amplify and output the sensed voltage change.

[0034] The input and output circuit 122 can be used to exchange data with a CPU or memory controller via a plurality of data lines DQ. For example, during a write operation performed by the memory device 10, the input and output circuit 122 can receive data from the CPU or memory controller via the plurality of data lines DQ and transmit the received data to the sense amplifier 120. In addition, during a read operation performed by the memory device 10, the input and output circuit 122 can output data corresponding to a voltage change of a bit line received from the sense amplifier 120 to the CPU or memory controller via the data lines DQ.

[0035] The voltage controller 130 can be used to use at least one externally provided power supply voltage V EXT Generate control voltages that are variably associated with corresponding operations of the memory device 10. The control voltages may include, for example, a write voltage for a bit line sensing operation, a read voltage, and an array voltage V INT The voltage controller 130 may provide one or more control voltages to the memory cell array 110 through the signal line SL. In addition, the voltage controller 130 may provide one or more control voltages to the sense amplifier 120.

[0036] The respective levels of the control voltages provided to the memory cell array 110 and the sense amplifier 120 may typically decrease during operation of the memory device 10. For example, during the initial stages of a bit line sensing operation performed by the sense amplifier 120, the array voltage V INT Unfortunately, when the array voltage V INTWhen the level of the bit line drops, the bit line sensing time increases to the point where the operation fails. To avoid this result, during various operations performed by the memory device 10, the voltage controller 130 can overdrive the control voltage to ensure that the control voltage provided (or applied) to the memory cell array 110 and / or the sense amplifier 120 remains at a target level. The term "overdrive" refers to applying a regulated voltage generation process or voltage generation control process that can compensate for the effects that would otherwise adversely change the characteristics of one or more control voltages.

[0037] However, it should be noted that the characteristics of the control voltage (e.g., level, timing, etc.) may be affected by process and temperature variations as well as by one or more externally provided supply voltages V EXT Therefore, in order to prevent the overshoot of the control voltage, it is necessary to control the control voltage in consideration of process, voltage, and temperature (PVT) conditions. In this regard, the voltage controller 130 according to an exemplary embodiment of the present inventive concept defines and appropriately controls the overdrive level for the control voltage and / or the timing of the control voltage in response to PVT information, so that the memory device 10 operates stably.

[0038] Figure 2 is a block diagram of another voltage controller 200 of a memory device further illustrating example embodiments of the inventive concepts in one example. Figure 3A and Figure 3B is a corresponding signal timing diagram illustrating exemplary DQS timing considerations.

[0039] Reference Figure 1 and Figure 2 , the voltage controller 200 includes a voltage driver 210 and an over-driving controller 230 .

[0040] The voltage driver 210 may be used to generate a control voltage V required for the operation of the memory device 10 under the control of the control logic 116. CONT The generated control voltage V CONT may be provided to the memory cell array 110 and / or the sense amplifier 120. In example embodiments, the control voltage V CONT The array voltage V may be included for use during the bit line sensing operation performed by the sense amplifier 120. INTA The control voltage V generated by the voltage driver 210 CONT It can also be fed back to the overdrive controller 230 as a feedback control voltage.

[0041] The overdrive controller 230 can be used to adjust the voltage driver 210 so that the voltage driver 210 provides the overdrive control voltage V CONT For example, the overdrive controller 230 may generate an overdrive control signal S ODC, the overdrive control signal S ODC Can be used to adjust the control voltage V generated by the voltage driver 210 CONT That is, the voltage driver 210 may respond to the control signal S received from the over-driving controller 230. ODC Adjust the control voltage V CONT As a result, the control voltage V provided by the voltage controller 200 is CONT It can be a control voltage V provided to the memory cell array 110 and / or the sense amplifier 120 for overdriving (or overdriving adjustment). CONT Here, the control voltage V CONT The timing (eg, output timing) may refer to the control voltage V CONT Timing applied to the memory cell array 110 and / or the sense amplifier 120 .

[0042] In example embodiments, the overdriving controller 230 may respond to the feedback control voltage V received from the voltage driver 210 by CONT The comparison result is compared with the reference voltage to generate the control voltage V CONT The level of the overdrive control signal S ODC For example, the overdrive controller 230 may generate a voltage for regulating the control voltage V CONT The level of the overdrive control signal S ODC , so that the feedback control voltage V received from the voltage driver 210 CONT The level is equal to the reference voltage level.

[0043] In example embodiments, the overdrive controller 230 may generate a voltage for adjusting the control voltage V in response to process, voltage, and / or temperature information (hereinafter generally referred to as “PVT information”). CONT The level and / or control voltage V CONT At least one of the overdrive control signals S ODC For example, when the operating temperature of the memory device 10 increases, the overdriving controller 230 may generate the overdriving control signal S ODC , the overdrive control signal S ODC Make the control voltage V CONT level increases by a predetermined value and / or advances the control voltage V CONT Output timing.

[0044] In some examples, the PVT information may include a ZQ code and DQS timing information. Here, the ZQ code may be a binary correction value used to match the on-resistance Ron of the input and output circuit 122 with the ZQ resistor connected to the ZQ pad. The DQS timing information may be a phase difference between the data signal DQ and the data strobe signal DQS. For example, when the memory device 10 performs a read operation, the data signal DQ and the data strobe signal DQS may be output from the input and output circuit 122 with the same phase, as shown in FIG. Figure 3A shown.

[0045] However, when the memory device 10 performs a write operation, the data strobe signal DQS may be applied through the buffer. Figure 3B As shown, the data strobe signal DQS may be delayed relative to the data signal DQ applied to the input and output circuit 122. In addition, the phase difference between the data signal DQ and the data strobe signal DQS may change according to changes in PVT conditions. Therefore, the overdrive controller 230 may be used to adjust the control voltage V in response to changes in the phase difference between the data signal DQ and the data strobe signal DQS. CONT In this way, the memory device 10 can operate more stably.

[0046] According to the data stored in the memory cell, the data signal DQ can be output at a high level voltage V OH (hereinafter referred to as "high") and output low level voltage V OL (hereinafter referred to as "low"), a signal having an alternating (or AC) swing between Figure 3A and Figure 3B are shown in comparison.

[0047] Since the data signal DQ is used, V OH and V OL Determines the reference voltage used to determine the state (e.g., "1" or "0") of the data stored in the memory cell, so it is important to maintain V OH and V OL However, according to PVT conditions, the on-resistance Ron of the input and output circuit 122 may change, and therefore, the V OH To prevent this effect using the ZQ code, a ZQ calibration operation may be performed to match the on-resistance Ron of the input and output circuit 122 with the ZQ resistance.

[0048] Figure 4 is a block diagram further illustrating another voltage controller 300 of a memory device according to example embodiments of the inventive concepts in one example. Figure 5A and Figure 5Bis to list the Figure 4 1 and 2 are corresponding graphs of examples of mapping tables (MAP1 and MAP2) stored in the voltage controller 300.

[0049] Reference Figure 1 、 Figure 2 and Figure 4 , the voltage controller 300 may include a voltage driver 310 , an overdriving controller 330 and a PVT information mapping unit 350 .

[0050] Here again, the voltage driver 310 can be used to generate the control voltage V required for the operation of the memory device 10 under the control of the control logic 116. CONT For example, the generated control voltage V CONT Can be applied to the memory cell array 110 and / or the sense amplifier 120. The control voltage V CONT It can also be fed back to the overdrive controller 330.

[0051] The over-driving controller 330 can control the voltage driver 310 so that the voltage driver 310 can generate an over-driving control voltage V CONT For example, as previously mentioned Figure 2 As described, the overdrive controller 330 may generate an overdrive control signal S ODC , the overdrive control signal S ODC The control voltage V generated by the voltage driver 310 is regulated CONT That is, the voltage driver 310 may respond to the over-driving control signal S received from the over-driving controller 330. ODC Adjust the control voltage V CONT Then, the adjusted (or overdriven) control voltage V CONT Applied to the memory cell array 110 and / or the sense amplifier 120 .

[0052] In the example embodiment of FIG. 3 , the overdrive controller 330 may respond by feeding back the control voltage V CONT The overdrive control signal S is generated by comparing at least one of the comparison results obtained by comparing with the reference voltage and the PVT information. ODC In some examples, the PVT information may include ZQ code and / or DQS timing information.

[0053] The PVT information mapping unit 350 can map the PVT information to the control voltage V CONTThe mapping information between one or more characteristics (e.g., level and / or timing) of the PVT condition is provided to the overdrive controller 330. For example, the PVT information mapping unit 350 can map one or more changes in one or more PVT conditions to one or more control voltages V CONT The obtained control values ​​can be provided to the overdrive controller 330. In an example embodiment, the PVT information mapping unit 350 can be provided in the form of a mapping table, such as Figure 5A and Figure 5B shown.

[0054] Reference Figure 5A , Figure 4 The PVT information mapping unit 350 may include a first mapping table MAP1, which stores the ZQ code and the control voltage V CONT The first mapping table MAP1 may store the first reference value REF obtained using a design tool (eg, P-SPICE), and may store the control voltage V CONT Various levels and output timing control values ​​related to different ZQ codes.

[0055] exist Figure 5A In the embodiment of the present invention, different ZQ codes may be determined relative to a first reference value REF1 (e.g., the first reference value plus or minus a defined number of increments "n" or REF1+ / -n). The level control value may be determined according to a linear incremental (or step) scale from a reference level "0" to "n" increments, and may be determined according to the applied reference clock signal T. CLK The timing change multiplier determines the output timing control value.

[0056] Reference Figure 5B , Figure 4 The PVT information mapping unit 350 is configured to include a second mapping table MAP2, which stores DQS timing information and control voltage V CONT The various levels of the control voltage V CONT The second mapping table MAP2 may store a second reference value REF2 obtained using a design tool (eg, P-SPICE), and may store a second reference value for controlling the voltage V CONT Various level control values ​​and output timing control values ​​according to the phase difference between the data signal DQ and the data select signal DQS.

[0057] In the following, in some additional details, the award reference Figure 1 、 Figure 2 Figure 3 Figure 4 、 Figure 5A and Figure 5BDescribes the use of voltage controllers (similar to Figure 2 and Figure 4 The controller described herein adjusts the control voltage V in response to PVT information. CONT method.

[0058] Figure 6A 、 Figure 6B and Figure 6C It is shown in various examples that Figure 4 The voltage controller 300 adjusts the control voltage V in response to the PVT information CONT The corresponding signal plot of the method. Figure 6A The array voltage V is adjusted in response to DQS timing information. INT The level method. Figure 6B Schematic diagram showing how the memory cell array voltage V is adjusted in response to DQS timing information. INT Output timing method. Figure 6C The array voltage V is adjusted in response to DQS timing information. INT The level and array voltage V INT Output timing method.

[0059] Reference Figure 1 、 Figure 4 and Figure 6A , when the phase difference between the data signal DQ and the data strobe signal DQS increases, in the initial stage of the bit line sensing operation performed by the sense amplifier 120, the array voltage V INTA To avoid such an undesirable result (e.g., to compensate for such an effect), the voltage controller 300 may reduce the array voltage V compared to a reference level “h” that is proportional to the phase difference between the phase of the data signal DQ and the phase of the data strobe signal DQS. INTA Increase the level by the level increment.

[0060] Reference Figure 1 、 Figure 4 and Figure 6B , when the phase difference between the data signal DQ and the data strobe signal DQS increases, the array voltage V INTA The duration that the level "h" must be maintained (i.e., the array voltage V INTA The pulse width of the bit line sense operation performed by the sense amplifier 120 may also increase. To compensate for this effect, the voltage controller 300 may adjust the output timing (eg, the array voltage V INTA The time when the sense amplifier 120 is applied to the sense amplifier 120) is advanced by a timing increment (e.g., t1, t2) proportional to the phase difference between the data signal DQ and the data strobe signal DQS. As a result, when the sense amplifier 120 performs the actual bit line sensing operation, the array voltage VINTA The timing duration “t” (or “t” plus one or more timing increments, such as t1 and t2 ) of maintaining the level “h” is uniform, and such a time can stably perform the bit line sensing operation.

[0061] Reference Figure 1 、 Figure 4 and 6C , the voltage controller 300 can adjust the array voltage V compared to the reference level “h” INTA The level of the array voltage V compared with the reference timing "t INT Here, as before, Figure 6A and Figure 6B In the embodiment, the array voltage V may be increased in response to a change in the phase difference (Δp) between the phase of the data signal DQ and the phase of the data strobe signal DQS. INTA The level "h" can be maintained, and the duration "t" for maintaining the level can be increased in one or more timing increments, such as t1 and t2.

[0062] As mentioned above, Figure 4 The voltage controller 300 can be used to adjust the array voltage V in response to PVT information. INTA At least one of the level and / or output timing of the bit line sensing operation is stabilized.

[0063] Figure 7 is a block diagram further illustrating, in one example, an overdriving controller 400 according to an example embodiment of the inventive concept.

[0064] Reference Figure 1 and Figure 7 , the overdriving controller 400 may include a first control unit 410 and a second control unit 430 .

[0065] The first control unit 410 may be configured to generate a first overdriving control signal S ODC1 , the first overdrive control signal S ODC1 For regulating the control voltage V provided by the voltage controller 130 CONT In one method, the first overdrive control signal S ODC1 Can be controlled by feedback voltage V CONT Used in conjunction to ensure that the control voltage V CONT Maintains a level equal to the reference value.

[0066] The second control unit 430 may be configured to generate a second overdriving control signal S in response to the PVT information. ODC2 , the second overdrive control signal S ODC2 Used to adjust the control voltage V CONTThe level and control voltage V CONT In example embodiments, the PVT information may include a ZQ code and / or DQS timing information. The ZQ code may include a binarization correction value for a ZQS calibration operation. In addition, the DQS timing information may include a phase difference between a data signal DQ and a data strobe signal DQS generated during a write operation of the memory device 10, as previously described with reference to FIG. Figure 3A and Figure 3B As stated.

[0067] The voltage driver (200 or 300) can be controlled by using the first overdriving control signal S provided by the overdriving controller 400. ODC1 and / or the second overdrive control signal S ODC2 At least one of the voltage level and / or output timing is used to adjust at least one of the voltage levels and / or output timings to generate a control voltage V CONT Here, the voltage driver (200 or 300) can set the second control voltage V CONT2 (not shown) are output to the memory cell array 110 and / or the sense amplifier 120 .

[0068] Figure 8A is a block diagram illustrating an overdriving controller 500 according to an example embodiment of the inventive concept in one example. Figure 8B and Figure 8C It shows the operation Figure 7 Corresponding conceptual diagram of the method of overdriving controller 400.

[0069] First, refer to Figure 1 、 Figure 2 、 Figure 4 and Figure 8A The overdrive controller 500 may include a first control unit 510, a second control unit 530, and a selector 550, wherein the first control unit 510 generates a first overdrive control signal S ODC1 , the first overdrive control signal S ODC1 For regulating the control voltage V that can be fed back from the voltage driver (210, 310) of the overdrive controller (230, 330) CONT level so that the level remains equal to the reference value.

[0070] The second control unit 530 generates a second overdriving control signal S in response to the PVT information. ODC2 , the second overdrive control signal S ODC2 Used to adjust the control voltage V CONT At least one of the level and / or output timing.

[0071] The selector 550 may be configured to generate a first overdrive control signal S ODC1and the second overdrive control signal S ODC2 Then the selected first overdrive control signal S ODC1 and the second overdrive control signal S ODC2 One of the voltages is applied to the voltage driver (210, 310). The selector 550 may be implemented as a multiplexer, but example embodiments of the inventive concept are not limited thereto.

[0072] In example embodiments, the selector 550 may select and output the first overdriving control signal S in response to a result of comparing the DQS timing information with the first threshold TH1. ODC1 and the second overdrive control signal S ODC2 For example, Figure 8B As shown, when the phase difference between the data signal DQ and the data strobe signal DQS is less than the first threshold TH1 as DQS timing information, it can be determined that the PVT condition or the change in the PVT condition is not obvious. In this case, the first overdrive control signal S ODC1 .

[0073] On the contrary, when the phase difference between the data signal DQ and the data strobe signal DQS is greater than or equal to the first threshold TH1, it can be determined that the PVT condition or the change in the PVT condition is significant. In this case, the second overdrive control signal S ODC2 .

[0074] In an example embodiment, in response to outputting a high level voltage V OH As a result of the comparison with the second threshold TH2, the selector 550 may select and output the first over-driving control signal S ODC1 and the second overdrive control signal S ODC2 one of the.

[0075] For example, Figure 8C As shown, when the output high level voltage V OH When the level of is lower than the second threshold TH2, the PVT condition may be determined to be insignificant. In this case, the first overdrive control signal S may be selected and output. ODC1 On the other hand, when the output high level voltage V OH When the level of is greater than or equal to the second threshold TH2, the PVT condition may be determined to be important. In this case, the second overdrive control signal S may be selected and output. ODC2 .

[0076] In some examples, the first threshold TH1 and the second threshold TH2 may be preset in consideration of various system requirements and data reliability constraints.

[0077] As a result of the comparison between the DQS timing information and the first threshold TH1, or as an output high level voltage V OH The result of the comparison with the second threshold TH2 is used to select the control signal S SC can be applied to the selector 550. In some examples, when the selection control signal S SC When the signal is high, the selector 550 can select and output the first over-driving control signal S ODC1 In addition, when the control signal S SC When the signal is low, the selector 550 can select and output the second over-driving control signal S ODC2 .

[0078] Figure 9 is a block diagram further illustrating, in one example, control logic 600 of a memory device according to example embodiments of the inventive concepts.

[0079] Reference Figure 9 , the control logic 600 may be used to generate PVT information and may further include a ZQ code generator 610 and / or a DQS timer 630 .

[0080] The ZQ code generator 610 can be used to generate a binary correction value for matching the on-resistance of the input and output circuits with the ZQ resistor connected to the ZQ pin as a ZQ code. The control logic 600 can use the ZQ code to perform a ZQ calibration operation to maintain the output high-level voltage V OH Meanwhile, since the ZQ code varies according to the PVT conditions, PVT information can be obtained from the ZQ code through a matching process provided by, for example, running a simulation.

[0081] The DQS timer 630 can be used to generate a phase difference between the data signal DQ and the data strobe signal DQS as DQS timing information. For example, the DQS timer 630 can operate an internal oscillator within a specific count time to count the number of clocks of the oscillation signal. The DQS timer 630 can use the count time and the number of clocks during the count time to calculate the clock period of the oscillation signal, and can obtain 1 / 2 of the calculated clock period as the phase difference between the data signal DQ and the data strobe signal DQS. At the same time, since the DQS timing information varies according to PVT conditions, PVT information can be obtained from the DQS timing information through a matching process provided by (for example) running a simulation.

[0082] Figure 10 and Figure 11 is a flowchart summarizing a method of generating a control voltage in response to PVT information using a voltage controller of a memory device according to an example embodiment of the inventive concept.

[0083] Reference Figure 2 and Figure 10 The voltage driver 210 can be used to generate a first control voltage V required for the operation of the memory device under the control of the control logic. CONT1 (S710). The first control voltage V generated by the voltage driver 210 CONT1 The voltage can be fed back to the overdriving controller 230 as a first feedback control voltage.

[0084] Then, the overdrive controller 230 can compare the first feedback control voltage with the reference voltage and generate an adjusted first control voltage V CONT1 The first overdrive control signal S ODC1 (S720).

[0085] The overdrive controller 230 can also be used to generate and adjust the first control voltage V in response to the PVT information. CONT1 A second overdrive control signal S of at least one of the level and output timing ODC2 (S730). In example embodiments, the PVT information may include a ZQ code for matching the on-resistance Ron of the input and output circuit 122 with the ZQ resistance. In addition, the PVT information may include DQS timing information indicating a phase difference between the data signal DQ and the data strobe signal DQS.

[0086] The voltage driver 210 may be configured to respond to a first overdriving control signal S received from the overdriving controller 230. ODC1 and the second overdrive control signal S ODC2 To adjust the first control voltage V CONT1 , to generate the second control voltage V CONT2 (S740).

[0087] In addition, the voltage driver 210 can generate the second control voltage V CONT2 is output to the memory cell array 110 and / or the sense amplifier 120 (S750). In an example embodiment, the first control voltage V CONT1 and the second control voltage V CONT2 It can be the array voltage V used to perform the bit line sensing operation through the sense amplifier 120. INTA .

[0088] Refer to above Figure 10 The control voltage generation method described may be performed during an electronic die sort (EDS) test, which is typically used to test / check the electrical characteristics of memory devices before packaging the memory devices, such as Figure 11 shown.

[0089] Reference Figure 11, a specific semiconductor process integrated with the manufacture of memory devices may be performed on the wafer (S810). The wafer may include a plurality of chip regions formed with a plurality of memory devices, a scribe line region for separating the plurality of chip regions, and the like.

[0090] Once semiconductor processing is completed and wafer production is underway, the memory controller can be used to store data in the fuse cell. Then, an electronic die sort (EDS) test (S820) of the wafer can be performed. The EDS test can be performed multiple times at different temperatures. When performing the EDS test, the custom data used to ensure the performance of the memory device can be changed. The memory controller can change the data stored in the fuse cell to change the custom data during the execution of the EDS test.

[0091] When performing EDS testing, a voltage controller similar to the voltage controller described above may be used to generate one or more control voltages required for various operations of the memory device. The generation of these control voltages (S830) may be performed in response to PVT information. For example, the generation of the control voltages may be performed using a reference voltage. Figure 10 A method for generating a control voltage using a voltage controller is described.

[0092] Once the EDS test is completed, the memory controller may migrate the data stored in the fuse cell to other cells. Then, a packaging process may be performed (S840).

[0093] Figure 12 is an overall block diagram illustrating a computing device 1000 including a memory device according to an example embodiment of the inventive concept.

[0094] Figure 12 The computing device 1000 may include a display 1010, a memory device 1020, a port 1030, and a processor 1040. The computing device 1000 may further include wired / wireless communication devices, a power supply, etc. Figure 12 Among the components shown, the computing device 1000 may be provided with a port 1030 for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, etc. The computing device 1000 may include concepts such as a smartphone, a tablet PC, a smart wearable device, etc., as well as a desktop computer and a laptop computer according to the prior art.

[0095] The processor 1040 may execute specific operations, commands, tasks, etc. The processor 1040 may be a central processing unit (CPU), a microprocessor unit (MCU), a system on a chip (SoC), etc., and may communicate with the display 1010 , the memory device 1020 , and other devices connected to the port 1030 through a bus 1050 .

[0096] The memory device 1020 may be a storage medium for storing data or multimedia data required for the operation of the computing device 1000. The memory device 1020 may include a semiconductor-based storage device. For example, the memory device 1020 may include a dynamic random access memory device (such as DRAM, synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), low power double data rate SDRAM (LPDDR SDRAM), graphics double data rate SDRAM (GDDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, etc.), or a resistive memory device (such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.).

[0097] In addition, the memory device 1020 may include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical disk drive (ODD) as a storage device.

[0098] In an example embodiment, the memory device 1020 may include the memory device 1020 according to the previous reference Figures 1 to 11 The memory devices described may include various example embodiments and do not exclude any one party.

[0099] As described above, according to example embodiments of the inventive concepts, a memory device may adjust one or more control voltages required for an operation of the memory device according to PVT information to perform the operation more stably.

[0100] Furthermore, memory devices according to example embodiments of the inventive concepts may use PVT information to more accurately control one or more control voltages, thereby preventing overshoot or undershoot of control voltage levels.

[0101] Furthermore, memory devices according to example embodiments of the inventive concepts may use PVT information to more accurately control an overdriving operation of an internal array voltage, thereby maintaining a constant bit line sensing condition.

[0102] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device comprising: a memory cell array comprising a plurality of memory cells for storing data; a sense amplifier connected to the memory cell array; as well as voltage controller, Wherein, the voltage controller comprises: a voltage driver that generates a control signal; and an overdrive controller that generates an overdrive control signal, wherein the overdrive control signal adjusts the generation of the control signal in response to a comparison result between the control signal and a reference voltage and at least one of process, voltage, and temperature (PVT) information, The voltage driver adjusts the control signal in response to the over-driving control signal to generate an over-driving control signal, and outputs the over-driving control signal to the sense amplifier.

2. The memory device according to claim 1, wherein The control signal is an array voltage, and the voltage driver adjusts the level of the array voltage to generate an overdriven array voltage.

3. The memory device according to claim 1, wherein The voltage driver adjusts the timing of the array voltage as an output to the sense amplifier to generate an overdriven array voltage.

4. The memory device according to claim 1, wherein The PVT information is obtained during an electronic die sort (EDS) testing process that tests the electrical characteristics of the memory devices before packaging them.

5. The memory device of claim 1 , further comprising: An input and output circuit, wherein the PVT information includes a ZQ code for matching an on-resistance of the input and output circuit with a predetermined ZQ resistance.

6. The memory device of claim 1 , further comprising: An input and output circuit, wherein the PVT information includes a phase difference between a data signal DQ and a data strobe signal DQS applied to the input and output circuit.

7. The memory device according to any one of claims 1 to 6, wherein: The voltage controller further includes a PVT information mapping unit that stores mapping information between the PVT information and at least one control value of the array voltage.

8. A memory device comprising: a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines; a sense amplifier connected to the plurality of bit lines and sensing amplified data stored in the plurality of memory cells; Input and output circuits that exchange data through a plurality of data lines using a data signal DQ and a data strobe signal DQS; as well as a voltage controller that provides a control voltage to at least one of the plurality of memory cells and the sense amplifier, Wherein, the voltage controller comprises: a voltage driver, generating a control voltage; a first overdriving controller that generates a first overdriving control signal applied to the voltage controller in response to a change in an externally provided power supply voltage to adjust generation of a control voltage; and A second overdrive controller generates a second overdrive control signal applied to the voltage driver in response to at least one of a ZQ code that matches the on-resistance of the input and output circuits with a reference ZQ resistance and a phase difference between the data signal DQ and the data select signal DQS to adjust generation of a control voltage.

9. The memory device of claim 8, further comprising: A ZQ code generator is used to generate a ZQ code.

10. The memory device of claim 8, further comprising: The DQS timer is used to determine the phase difference between the data signal DQ and the data strobe signal DQS.

11. The memory device according to claim 8, wherein The voltage controller further includes a selector configured to selectively output one of the first overdriving control signal and the second overdriving control signal.

12. The memory device of claim 11, wherein: The selector is further configured to select and output one of the first overdriving control signal and the second overdriving control signal in response to a result of comparing a phase difference between the data signal DQ and the data strobe signal DQS with a first threshold.

13. The memory device of claim 12, wherein: The selector is configured to select and output the first overdriving control signal when a phase difference between the data signal DQ and the data strobe signal DQS is less than a first threshold.

14. The memory device of claim 12, wherein: The selector is configured to select and output the second overdriving control signal when a phase difference between the data signal DQ and the data strobe signal DQS is greater than or equal to a first threshold.

15. The memory device of claim 11, wherein: The voltage driver is configured to adjust a level of the control voltage in response to the first overdriving control signal.

16. The memory device of claim 11, wherein: The voltage driver is configured to adjust at least one of a level and a timing of the control voltage in response to the second overdriving control signal.

17. A voltage controller comprising: a voltage driver configured to generate a control signal for performing a bit line sensing operation of the memory device; a first overdrive controller configured to generate a first overdrive control signal in response to a result of comparing the control signal with a reference voltage, the first overdrive control signal regulating generation of the control signal by the voltage driver; as well as A second overdrive controller is configured to generate a second overdrive control signal in response to process, voltage, and temperature (PVT) information, wherein the second overdrive control signal regulates the generation of the control signal by the voltage driver. The PVT information includes at least one of the following: a ZQ code for matching the on-resistance of the input and output circuits of the memory device with a reference ZQ resistance, and a phase difference between a data signal DQ and a data selection signal DQS applied to the input and output circuits.

18. The voltage controller according to claim 17, wherein: The control voltage is an array voltage, and the voltage driver is configured to adjust a level of the array voltage in response to a first overdrive control signal.

19. The voltage controller according to claim 17, wherein: The control voltage is an array voltage, and the voltage driver is configured to adjust at least one of a level and an output timing of the array voltage in response to a second overdriving control signal.

20. The voltage controller according to claim 17, wherein The control voltage is the array voltage, and The voltage control device further includes a PVT information mapping unit that stores mapping information between the PVT information and at least one control value of the array voltage.

Images