A method for forming a semiconductor device

Abstract

An embodiment of the present invention provides a method for forming a semiconductor device. In the embodiment of the present invention, before the annealing treatment, a protective layer covering the active region is formed, which can protect the active region during the annealing process. The protective layer can isolate the active region from oxygen, preventing the silicon and oxygen in the active region from contacting and forming gaseous silicon oxide at high temperatures, which may cause holes to appear in the active region. Therefore, the method for forming a semiconductor device according to the embodiment of the present invention can ensure the integrity of the gate oxide layer, improve the breakdown voltage of the semiconductor device, and further improve the reliability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor device. Background Art

[0002] With the continuous development of semiconductor manufacturing processes, the integration of semiconductor devices is getting higher and higher, and the feature size of semiconductor devices is gradually shrinking. However, the performance of semiconductor devices still needs to be improved. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a method for forming a semiconductor device to improve the performance of the semiconductor device.

[0004] The method according to the embodiments of the present invention includes:

[0005] Providing a front-end device layer, the front-end device layer including an active region and a shallow trench isolation structure;

[0006] Forming a protective layer covering at least the active region to isolate the active region from external gases;

[0007] Performing an annealing treatment on the active region.

[0008] Further, the material of the protective layer is a material with a dense structure.

[0009] Further, the material of the protective layer is dense silicon dioxide.

[0010] Further, the thickness of the protective layer is 10 nanometers to 20 nanometers.

[0011] Further, the forming of the protective layer covering at least the active region specifically includes:

[0012] Using a chemical vapor deposition process, with tetraethyl orthosilicate as a reaction gas, to form the protective layer on the active region.

[0013] Further, the annealing treatment of the active region is specifically:

[0014] At a temperature of 500°C - 800°C, for 3 hours - 8 hours of heat preservation.

[0015] Further, the semiconductor device is a metal oxide semiconductor.

[0016] Further, the operating voltage of the semiconductor device is 18V.

[0017] Further, after providing the front-end device layer and before forming the protective layer covering at least the active region, the method further includes:

[0018] Ion implantation is performed in a predetermined region of the active region to form a well region.

[0019] Further, before the ion implantation, the method further includes:

[0020] Forming a gate and source / drain regions in the active region.

[0021] In an embodiment of the present invention, before the annealing treatment, a protective layer covering the active region is formed, which can protect the active region during the annealing process. The protective layer can isolate the active region from oxygen, preventing silicon and oxygen in the active region from contacting to form gaseous silicon oxide at high temperatures, which may cause holes in the active region. Therefore, the method for forming a semiconductor device according to the embodiment of the present invention can ensure the integrity of the gate oxide layer, improve the breakdown voltage of the semiconductor device, and further improve the reliability of the semiconductor device. Description of the Drawings

[0022] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0023] Figure 1 is a schematic diagram of the structure formed by the method for forming a semiconductor device of the comparative example;

[0024] Figure 2 is a flowchart of the method for forming a semiconductor device according to an embodiment of the present invention;

[0025] Figures 3 - 4 is a schematic diagram of the structure formed by each step of the method for forming a semiconductor device according to an embodiment of the present invention;

[0026] Figures 5 - 6 is a schematic diagram of the detection result of the gate oxide layer integrity of the semiconductor device according to an embodiment of the present invention. Detailed Embodiments

[0027] The following describes the present invention based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. Those skilled in the art can fully understand the present invention without the description of these details. To avoid obscuring the essence of the present invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0028] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0029] Meanwhile, it should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one component or sub-circuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or when an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0030] Unless the context clearly requires otherwise, the words such as "comprising", "including" and the like in the specification shall be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".

[0031] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0032] In the description of the present invention, it should be understood that the term "layer" is used in its broadest sense, thus including films, capping layers or the like, and a layer may include a plurality of sub-layers.

[0033] In the description of the present invention, it should be understood that the conventional etching techniques known in the semiconductor manufacturing field for selectively removing polysilicon, silicon nitride, silicon dioxide, metal, photoresist, polyimide or similar materials mentioned throughout the specification include, for example, wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical polishing process (CMP) and similar processes. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to specific deposition techniques should not be limited to those described. In some examples, two such techniques may be interchangeable. For example, stripping photoresist may include immersing the sample in a wet chemical bath or alternatively spraying the wet chemical directly onto the sample.

[0034] A semiconductor device is an electronic device with conductivity between that of a good conductor and an insulator, which utilizes the special electrical properties of semiconductor materials to perform specific functions, and can be used to generate, control, receive, transform, amplify signals and perform energy conversion. Commonly used existing semiconductor devices include field-effect transistors (FETs). Field-effect transistors include high-voltage field-effect transistors.

[0035] Typically, during the manufacturing process of semiconductor devices, a shallow trench isolation (STI) structure is formed in the semiconductor devices. The role of the shallow trench isolation structure is to isolate each semiconductor device to prevent leakage current from occurring between the devices.

[0036] An active area (AA) is formed in the region between the shallow trench isolation structures. The active area includes various semiconductor devices such as N-Metal-Oxide-Semiconductor (NMOS) or P-Metal-Oxide-Semiconductor (PMOS).

[0037] When forming a high-voltage field-effect transistor, a well region is formed in the field-effect transistor by ion implantation to increase the breakdown voltage of the semiconductor device. To meet the device's withstand voltage, usually the ion implantation region is relatively deep. After ion implantation, high-temperature and long-time annealing are required to reduce the stress concentration caused by ion implantation.

[0038] However, during the annealing process, since silicon and oxygen in the gate oxide layer in the active area react to form gaseous silicon dioxide (SiO2), defects such as holes appear in the active area. These defects are prone to form at the junction of the active area and the shallow trench isolation area. These defects will cause the failure of the High Voltage Gate Oxide Integrity Voltage Ramp (HV GOI Vramp) test.

[0039] Reference Figure 1 , in the formation method of the comparative semiconductor device, the active area 1 and the shallow trench isolation structure 2 are annealed, resulting in the formation of gaseous silicon dioxide by silicon and oxygen at high temperature, thereby forming holes 3.

[0040] In other comparative examples, the annealing temperature is reduced to avoid forming holes. However, after reducing the annealing temperature, only the number of holes is reduced to a certain extent, and the formation of holes cannot be completely avoided.

[0041] In view of this, in order to improve the performance of semiconductor devices, embodiments of the present invention provide a method for forming a semiconductor device. In the embodiments of the present invention, taking the formation of a field effect transistor as an example for illustration, further, the method of the embodiments of the present invention can be used to form a high-voltage field effect transistor. For example, it is used to form a field effect transistor with an operating voltage of 18V. Further, the method for forming a field effect transistor formed by the method of the embodiments of the present invention can also be used to form other semiconductor devices such as Metal Oxide Semiconductor (CMOS), NAND Flash Memory, and Static Random Access Memory (SRAM).

[0042] Figure 2 is a flowchart of the method for forming a semiconductor device according to an embodiment of the present invention. As Figure 2 shown, the method for forming a semiconductor device according to an embodiment of the present invention includes the following steps:

[0043] Step S100: Provide a front-end device layer, where the front-end device layer includes an active region and a shallow trench isolation structure.

[0044] Step S200: Form a protective layer covering at least the active region to isolate the active region from external gases.

[0045] Step S300: Anneal the active region.

[0046] In an alternative implementation, before step S200 and after step S100, the method for forming a semiconductor device further includes:

[0047] Step S100a: Form a gate and source / drain regions in the active region.

[0048] Step S100b: Perform ion implantation in a predetermined region of the active region to form a well region.

[0049] Figures 3 - 4 is a cross-sectional view of the structure formed by each step of the method for forming a semiconductor device according to an embodiment of the present invention.

[0050] Refer to Figure 3 , in step S100, provide a front-end device layer 10. The front-end device layer includes an active region 11 and a shallow trench isolation structure 12.

[0051] Specifically, the front-end device layer 10 provided in step S100 may include a single-crystalline silicon substrate, a single-crystalline germanium substrate, or a silicon-germanium single-crystalline substrate. Alternatively, the front-end device layer 10 may further include a silicon-on-insulator (SOI) substrate, a stacked silicon-on-insulator (SSOI), a stacked silicon-germanide-on-insulator (S-SiGeOI), a silicon-germanide-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a substrate with an epitaxial layer structure on silicon, a compound substrate, or an alloy substrate. The compound substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysproside, and the alloy substrate includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. The SOI substrate includes a semiconductor layer (such as a silicon layer, a silicon-germanium layer, a silicon-carbon layer, or a germanium layer) disposed on an insulating material layer, and source devices and passive devices are provided in the semiconductor layer. The insulating material layer protects the active devices and passive devices disposed on the semiconductor layer. On the surface of the front-end device layer, several epitaxial interface layers or strain layers and other structures may also be formed to improve the electrical performance of the semiconductor devices.

[0052] The shallow trench isolation structure 12 is located between the active regions 11. The function of the shallow trench isolation structure 12 is to isolate each semiconductor device to prevent leakage current from occurring between the devices. The shallow trench isolation structure 12 can avoid doping ions from being implanted into the substrate material during subsequent ion implantation processes. The material of the shallow trench isolation structure 12 may be silicon dioxide (SiO2), silicon oxynitride (SiON), or silicon oxycarbide (SiOC). The material of the shallow trench may also be a low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or an ultra-low-K dielectric material (dielectric constant less than 2.5). In this embodiment, the material of the shallow trench isolation structure 12 is silicon dioxide.

[0053] In step S100a, a gate and source-drain regions are formed in the active region 11.

[0054] Specifically, the source-drain regions are on both sides of the gate, and the source-drain regions can be formed by the method of source-drain ion implantation. In an alternative implementation, when the formed semiconductor device is a P-type transistor, P-type impurity ions are doped in the source-drain regions. In another alternative implementation, when the formed semiconductor device is an N-type transistor, N-type impurity ions are doped in the source-drain regions. The N-type impurity ions are one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Te) ions; the P-type impurity ions are one or more of boron (B) ions, indium (In) ions, and gallium (Ga) ions.

[0055] The gate is in the middle of the source-drain regions, and by connecting the control potential, it controls whether the source-drain regions conduct with each other.

[0056] Optionally, a buried layer, a reverse ion implantation layer, etc. are also formed at the bottom of the active region.

[0057] The material of the buried layer is usually silicon oxide, with a thickness of about 100 nm to 1 μm. Therefore, the buried layer is also called the buried oxide layer. The buried layer can prevent excess electrons from leaking to the underlying semiconductor substrate.

[0058] The reverse ion implantation layer is located above the buried layer. The doping type of the reverse ion implantation layer is opposite to that of the source / drain regions, which can play a role in suppressing leakage current.

[0059] In step S100b, ion implantation is performed in a predetermined region of the active region to form a well region.

[0060] The well region is located outside the source / drain regions, surrounding the gate and the source / drain regions. The doping type of the well region is opposite to that of the source / drain regions to prevent the formation of leakage current.

[0061] In other alternative implementation manners, the well region may include a plurality of unconnected doped regions to improve the isolation effect.

[0062] In an alternative implementation manner, when the implanted impurity ions for ion implantation are one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Te) ions, the implantation angle of ion implantation is 0 - 5 degrees, and the implantation dose is 5E15 atom / cm 2 - 5E20 atom / cm 2 , and the implantation energy is 6 Kev - 50 Kev. In another alternative implementation manner, when the implanted impurity ions for ion implantation are one or more of boron (B) ions, indium (In) ions, and gallium (Ga) ions, the implantation angle of ion implantation is 0 - 5 degrees, and the implantation dose is 5E15 atom / cm 2 - 5E20 atom / cm 2 , and the implantation energy is 12 Kev - 50 Kev.

[0063] Reference Figure 3 , in step S200, a protective layer 20 covering at least the active region 11 is formed to isolate the active region 11 from the external gas.

[0064] Specifically, the protective layer 20 covers the active region 11 and the shallow trench isolation structure 12, ensuring that the entire active region 11 is covered by the protective layer 20.

[0065] Specifically, the material of the protective layer 20 is a material with a dense structure. Further, the material of the protective layer 20 is dense silicon dioxide. At the same time, the material of the protective layer 20 also needs to have good stability and is not easily decomposed at high temperatures.

[0066] Materials with a dense structure can have a better isolation effect, effectively isolating silicon and oxygen, and preventing silicon from reacting with oxygen to form gaseous silicon dioxide during subsequent annealing processes, thereby avoiding the formation of holes in the active region.

[0067] The protective layer 20 has good stability and can ensure that it still plays a role in protecting the underlying active region under subsequent high-temperature conditions.

[0068] The thickness of the protective layer 20 is 10 nanometers to 20 nanometers. The thicker the protective layer 20, the better the isolation effect. However, if the protective layer 20 is too thick, it will cause excessive stress, prone to cracks, and also prolong the time required for the process, reducing the formation efficiency of semiconductor devices. Therefore, in the embodiments of the present invention, considering reliability and efficiency comprehensively, the thickness of the protective layer 20 is in the range of 10 nanometers to 20 nanometers. In an optional implementation manner, the thickness of the protective layer 20 is 15 nanometers.

[0069] Specifically, the protective layer 20 can be formed by chemical vapor deposition (CVD), such as low-temperature chemical vapor deposition (LTCVD), plasma chemical vapor deposition process (PCVD), low-pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), plasma-enhanced chemical vapor deposition (PECVD), fluid chemical vapor deposition process (FCVD).

[0070] In an optional implementation manner, the formation of the protective layer 20 that at least covers the active region specifically includes:

[0071] Using a chemical vapor deposition process, with tetraethyl orthosilicate as the reaction gas, the protective layer 20 is formed on the active region.

[0072] In step S300, the active region 11 is annealed.

[0073] Specifically, the annealing treatment is: maintaining the temperature at 500°C - 800°C for 3 hours - 8 hours.

[0074] The Gate Oxide Integrity (GOI) test is a test process for verifying the quality of the gate oxide layer. During the manufacturing process of semiconductor devices, a dedicated test structure is generally formed for the GOI test to detect whether there are defects in the gate oxide layer and prevent the reliability of the device from decreasing due to gate oxide layer defects. Prevent the breakdown voltage of the dielectric layer from decreasing due to defects such as ion diffusion, resulting in a decrease in the reliability of the device.

[0075] When performing the GOI test, the semiconductor device under test includes an active region in which a metal oxide transistor is formed. The metal oxide transistor mainly includes a substrate, a gate oxide layer, a gate electrode, and a source electrode and a drain electrode. A voltage is applied between the substrate and the gate electrode to measure the breakdown voltage (Vbd) of the gate oxide layer. If the breakdown voltage is higher than the specified voltage, it indicates that there are no defects in the gate oxide layer and the test passes; on the contrary, if the breakdown voltage is lower than the specified voltage, it indicates that there are defects in the gate oxide layer and the test fails.

[0076] Figure 5 and Figure 6 are respectively the test result diagrams of the GOI of the embodiment and the comparative example of the present invention. Among them, the abscissa represents the breakdown voltage, and the ordinate represents the probability value of the detection result. The detection result curve starts from Figure 6 It can be seen that the convergence of the detection of the semiconductor device formed by the method of the comparative example is poor, and the range of the detection result is large, indicating that the consistency of the gate oxide layer is poor and the gate oxide layer detection fails. From Figure 5 It can be seen that the detection results of the semiconductor device formed by the method of the embodiment of the present invention converge, indicating that the consistency of the gate oxide layer is very good. Comparing Figure 5 and Figure 6 it can be known that the method for forming a semiconductor device according to the embodiment of the present invention can improve the integrity of the gate oxide layer formed by the method of the comparative example, thereby improving the breakdown voltage resistance of the semiconductor device and ensuring the reliability of the semiconductor device.

[0077] In the embodiment of the present invention, before the annealing treatment, a protective layer covering the active region is formed, which can protect the active region during the annealing process. The protective layer can isolate the active region and oxygen, avoiding the silicon and oxygen in the active region from contacting to form gaseous silicon oxide at high temperature, resulting in holes in the active region. Therefore, the method for forming a semiconductor device according to the embodiment of the present invention can ensure the integrity of the gate oxide layer, improve the breakdown voltage resistance of the semiconductor device, and thus improve the reliability of the semiconductor device.

[0078] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, The method is used for preparing a high-temperature resistant high-voltage field effect transistor, and the method includes: Providing a front-end device layer, where the front-end device layer includes an active region and a shallow trench isolation structure; Performing ion implantation in a predetermined region of the active region to form a well region; Forming a protective layer covering at least the active region, where the material of the protective layer is dense silicon dioxide, to isolate the active region from external gases and prevent silicon in the active region from reacting with oxygen during subsequent annealing treatment to form gaseous silicon dioxide and cause holes to appear in the active region; Performing annealing treatment on the active region.

2. The method for forming a semiconductor device according to claim 1, wherein The thickness of the protective layer is 10 nanometers to 20 nanometers.

3. The method for forming a semiconductor device according to claim 1, wherein The forming of the protective layer covering at least the active region specifically includes: Using a chemical vapor deposition process and taking tetraethyl orthosilicate as a reaction gas to form the protective layer on the active region.

4. The method for forming a semiconductor device according to claim 1, wherein The performing of the annealing treatment on the active region specifically is: Maintaining the temperature at 500°C - 800°C for 3 hours - 8 hours.

5. The method for forming a semiconductor device according to claim 1, wherein, The semiconductor device is a metal oxide semiconductor.

6. The method for forming a semiconductor device according to claim 1, wherein, The operating voltage of the semiconductor device is 18V.

7. According to the method for forming the semiconductor device as claimed in claim 1, wherein Before the ion implantation, the method further includes: Forming a gate and source-drain regions in the active region.

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