Symmetrical two-dimensional fin structure for vertical field effect transistor and method of manufacturing the same

Abstract

The present invention is conceived to provide a method for manufacturing a fin structure of a vertical field effect transistor (VFET) and a fin structure manufactured by the method. The method includes: (a) patterning a lower layer and an upper layer deposited on the lower layer to form two patterns extending in two directions perpendicular to each other; (b) forming a first spacer and a second spacer side by side in the two patterns along the sidewalls of the lower layer and the upper layer exposed by patterning; (c) removing the first spacer, the second spacer and the upper layer above the level of the top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed by the two patterns in a top view; (d) removing the lower layer, the upper layer and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except for a portion of the substrate located below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby obtaining a fin structure.

Description

Technical Field

[0001] Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to a fin structure for a vertical field effect transistor (VFET) having a two-dimensional (2D) shape in a top view, and more particularly, to a method of manufacturing the fin structure and a fin structure manufactured by the method. Background Art

[0002] In VFET, unlike the planar FET or finFET of the related art, current flows in a vertical direction through a channel formed at a fin structure protruding from a substrate. The vertically protruding fin structure is wrapped by a gate structure, and a bottom source / drain (S / D) region and a top S / D region are formed around the bottom portion and the top portion of the fin structure, respectively.

[0003] Although known VFET devices including VFETs have various advantages, including high density structures with reduced size compared to related art planar FET devices or finFET devices, there is still a need for more improved VFET structures (especially the structure of the fins of the VFET) and improved methods of manufacturing such VFET structures. Summary of the invention

[0004] Various embodiments of the inventive concept provide methods of manufacturing a fin structure for a VFET, the fin structure having a 2D shape in a top view, and the fin structure for a VFET manufactured by the methods.

[0005] According to one aspect of an exemplary embodiment, a method for manufacturing at least one fin structure for a VFET is provided, the method may include the following operations: (a) forming a first layer on a substrate, the first layer having at least one first pattern, the pattern extending in a first direction with a constant first width (CD2) and penetrating the first layer, such that a top surface of the substrate is exposed in the first direction through the first pattern; (b) forming a second layer on the first layer, such that the second layer is formed on a top surface of the first layer and fills the first pattern; (c) forming a third layer on a top surface of the second layer, the third layer having at least one mask pattern, the at least one mask pattern traversing the first pattern, extending in a second direction different from the first direction with a constant second width (CD3), and penetrating the third layer, such that a top surface of the second layer is exposed in the second direction through the mask pattern; (d) patterning the second layer along the mask pattern using the third layer as a mask, such that the mask pattern penetrates the second layer to form a mask pattern having the same shape as the mask pattern. (e) removing the third layer; (f) forming a first spacer along the sidewalls of the first layer and the second layer exposed by the first pattern and the second pattern; (g) forming a second spacer along the sidewalls of the first spacer; (h) removing the first spacer formed above the top surface of the first layer and between the second layer and the second spacer, and the first spacer below the top surface of the first layer and exposed by the first pattern and the second pattern in a top view; (i) removing the second layer and the second spacer formed above the level of the top surface of the first layer; (j) removing the first layer, the second layer and the second spacer above the level of the top surface of the substrate; and (k) etching the substrate downward except for a portion of the substrate below the first spacer remaining from operation (j), and removing the first spacer remaining from operation (j), thereby obtaining a fin structure.

[0006] According to another aspect of an exemplary embodiment, a method for manufacturing at least one fin structure for a VFET is provided, which may include the following operations: (a) stacking a plurality of layers including a lower layer and an upper layer on a substrate, the lower layer and the upper layer respectively having at least one first pattern and at least one second pattern extending in different directions across each other to expose the substrate therethrough; (b) forming a first spacer on the sidewalls of the plurality of layers exposed by the first pattern and the second pattern; (c) forming a second spacer on the sidewalls of the first spacer; (d) removing the first spacer, the second spacer and the upper layer above the level of the top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed by the first pattern and the second pattern in a top view; (e) removing the plurality of layers and the second spacer remaining on the substrate after operation (d); and (f) etching downward the substrate except for a portion of the substrate located below the first spacer remaining on the substrate after operation (e), and removing the remaining first spacer, thereby obtaining a fin structure.

[0007] According to another aspect of an exemplary embodiment, a fin structure for a VFET is provided, the fin structure may include a first sub-fin structure and a second sub-fin structure protruding from a substrate, wherein in a top view, the first sub-fin structure and the second sub-fin structure are symmetrical to each other on the substrate. The first sub-fin structure and the second sub-fin structure may be separated from each other or connected to each other on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects of the inventive concept will become more apparent to those skilled in the art by describing in detail example embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0009] Figures 1A to 1E A method of manufacturing a fin structure for a VFET in a top view according to an embodiment is shown;

[0010] Figure 2 shows a top view of a 2D fin structure to be fabricated for a VFET according to an embodiment; and

[0011] Figure 3A and FIG. 3B to FIG. 13A and Fig. 13B A method of fabricating a fin structure for a VFET according to an embodiment is shown. DETAILED DESCRIPTION

[0012] Various embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. These embodiments are exemplary and may be embodied in many different forms and should not be construed as limiting the inventive concept. Rather, these embodiments are provided only so that the present disclosure will be thorough and complete and will fully convey the inventive concept to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of various layers and regions may be exaggerated for clarity, and therefore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show the details of specific parts or elements. Therefore, the specific structural and functional details disclosed herein will not be construed as limiting, but merely as a representative basis for teaching those skilled in the art to adopt the methods and structures of the embodiments in various ways.

[0013] It is not excluded that the embodiments provided herein are associated with one or more features of another example or another embodiment that is also provided herein or not provided herein but is consistent with the inventive concept. For example, even if the content described in a specific embodiment is not described in a different embodiment, the content can also be understood to be associated with or combined with the different embodiments, unless otherwise mentioned in its description.

[0014] For the purposes of the following description, the terms "upper", "lower", "top", "bottom", "left", and "right" and their derivatives may be related to the disclosed structures as they are oriented in the drawings based on the context. The same reference numerals in different drawings may refer to the same structural components or elements thereof.

[0015] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0016] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when following a list of elements, modify the entire list of elements and do not modify the individual elements in the list. Thus, for example, "at least one of A, B, or C" and "any of A, B, and / or C" both mean A, B, C, or any combination thereof. Expressions such as "at least one of," when following a list of elements, modify the entire list of elements and do not modify the individual elements in the list.

[0017] The terms used herein are for the purpose of describing specific example embodiments only and are not intended to limit the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "include" and / or "comprise" when used in this specification specify the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof.

[0018] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the embodiments belong. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0019] Compared to planar devices such as planar FETs, the performance of multidimensional semiconductor devices such as FinFETs and VFETs can be improved by increasing the Z-direction length of the device. For example, the gate controllability of a VFET can be improved by increasing the height of the fin structure measured from the substrate. However, due to the limitation of the overall size of the VFET, the height of the fin structure may be limited. Therefore, a fin structure having a two-dimensional (2D) shape such as the letter "H", the letter "E", or the "+" symbol in a top view of the substrate (i.e., when viewed from the top) is introduced because its x-direction length and y-direction length can increase the size of the fin structure to have a larger current path between the bottom S / D region and the top S / D region of the VFET.

[0020] Figures 1A to 1E A method of manufacturing a fin structure of a VFET protruding from a substrate and having a two-dimensional (2D) shape such as an “H” letter in a top view of the substrate according to an embodiment is shown.

[0021] Reference Figure 1A , the substrate 100 is provided with a pair of rectangular cores 110 - 1 and 110 - 2 having a critical dimension gap (hereinafter referred to as “gap CD”) that may define a critical dimension of a fin structure to be formed according to the present embodiment.

[0022] The cores 110-1 and 110-2 may be formed on the substrate 100 through photolithography and etching processes so that the cores 110-1 and 110-2 may have a protrusion shape protruding from the substrate 100, although a cross-sectional view of the substrate 100 having the cores 110-1 and 110-2 thereon is omitted here. Figures 1A to 1EAlthough not shown, one or more hard mask layers (not shown) may be provided between the substrate 100 and the mandrels 110 - 1 and 110 - 2 .

[0023] The substrate 100 may be formed of a single element semiconductor material such as silicon (Si), germanium (Ge), etc. (not limited thereto), or a compound thereof (SiGe). The substrate 100 may be a doped or undoped layer. The cores 110-1 and 110-2 may be formed of a spin-on hard mask (SOH) material including a silicon-based organic material (not limited thereto). A variety of different amorphous silicon materials may be used to form the cores 110-1 and 110-2, as long as the cores 110-1 and 110-2 have an etching selectivity relative to the spacers to be formed on the side surfaces (i.e., sidewalls) of the cores 110-1 and 110-2 and on the fin structure in the following steps of the method according to the present embodiment.

[0024] Figure 1B It is shown that spacers 120 are formed on the side surfaces of the cores 110-1 and 110-2, and the spacers 120 fill the gap between the cores 110-1 and 110-2 having a gap CD. The spacers 120 may be formed by depositing a spacer material such as silicon oxide (SiO) on the cores 110-1 and 110-2 to cover the top and side surfaces thereof; and etching away the spacer material deposited on the top surface to expose the top surface to the outside and leaving the spacer material on the side surfaces of the cores 110-1 and 110-2.

[0025] The process of depositing the spacer material may be performed by a thin film deposition technique such as atomic layer deposition (ALD) (not limited thereto), so that the spacer 120 may have the same width along the side surfaces of the cores 110-1 and 110-2, which may be the size required for the desired fin structure to be formed according to the present embodiment. According to the inventive concept, the etching process used in this step may be anisotropic etching or plasma etching (not limited thereto). The spacer material forming the spacer 120 may also not be limited to SiO, as long as the spacer material has etching selectivity relative to the material forming the cores 110-1 and 110-2.

[0026] Figure 1C It is shown that the mandrels 110 - 1 and 110 - 2 surrounded by the spacers 120 are removed by another etching process such as dry etching (not limited thereto) to leave the spacers 120 formed at the side surfaces of the mandrels 110 - 1 and 110 - 2 on the substrate 100 .

[0027] Figure 1DThe spacer 120 is shown having two opposite sides in the length direction cut or etched away to form an H-shaped spacer 130, i.e., a spacer having the shape of the letter "H" in a top view, the shape of the letter "H" having the desired dimensions. Figures 1A to 1C The lithography, deposition and etching processes shown, Figure 1A The gap CD shown is transferred to the critical dimension (hereinafter referred to as “spacer CD”) of the H-shaped spacer 130. The spacer CD of the H-shaped spacer 130 represents the width of the horizontal portion 130H of the H-shaped spacer 130 and may be equal to the gap CD, which will define the critical dimension of the fin structure to be formed in the next step in the top view. In addition, the width of the horizontal portion 130H of the H-shaped spacer 130 may be equal to the width of the vertical portion 130V of the H-shaped spacer 130.

[0028] Figure 1E , the substrate 100 is etched downward using the H-shaped spacer 130 as a hard mask layer, and the H-shaped spacer 130 is also removed by etching, thereby forming an H-shaped fin structure 140 which is perpendicular to the substrate 100 and also has the shape of the letter "H". Then, a bottom source / drain region is formed in the substrate 100 below the H-shaped fin structure 140. Here, the spacer CD is transferred to the critical dimension (hereinafter referred to as "fin CD") of the H-shaped fin structure 140. Therefore, Figure 1A The gap CD shown is eventually transferred to the fin CD and defines the fin CD. According to the inventive concept, the etching process for obtaining the H-shaped fin structure 140 here may be dry etching, but is not limited thereto.

[0029] According to the above embodiments, a 2D-shaped fin structure such as the H-shaped fin structure 140 can be obtained, thereby providing better performance for the VFET. However, there are limitations in scaling the fin CD through the above process, and due to the process distribution during the manufacture of the 2D-shaped fin structure, the two symmetrical parts 141 and 142 of the H-shaped fin structure 140 may not have equal lengths. That is, after the H-shaped fin structure 140 is formed on the substrate 100, the length L1 and the length L2 may not be the same, and thus the parts 141 and 142 may not provide a consistent current path for the VFET.

[0030] Therefore, a method of manufacturing a fin structure of a VFET having two symmetrical portions having the same length is described below.

[0031] Figure 2 A top view of a 2D-shaped fin structure to be fabricated for a VFET is shown according to an embodiment.

[0032] Reference Figure 2 , the first fin structure 210 and the second fin structure 220 protrude on the substrate 200 .

[0033] The first fin structure 210 has two sub-fin structures 210-1 and 210-2, which are separated from each other and symmetrical to each other on the substrate 200 relative to the Y-direction center line (not shown). The sub-fin structure 210-1 includes two horizontal portions having the same length L3 and connected by a vertical portion, which is defined by a critical dimension 5 (CD5) in the Y direction and a critical dimension 4 (CD4) in the X direction. Here, CD4 represents the width of the vertical portion of the sub-fin structure 210-1 in the X direction. CD4 is shorter than the length L3. CD4 also represents the width of the horizontal portion of the sub-fin structure 210-1. The sub-fin structure 210-1 is also defined by a critical dimension (CD2), which is its Y-direction length.

[0034] The sub-fin structure 210-2 also includes two horizontal portions having the same length L4 and connected by a vertical portion, which is also defined by the same critical dimensions CD4 and CD5. Note that the length L3 of each horizontal portion of the sub-fin structure 210-1 is equal to the length L4 of each horizontal portion of the sub-fin structure 210-2. Therefore, the first fin structure 210 is divided into two symmetrical portions at least about the Y-direction center line. Specifically, Figure 2 Two “C” letter-shaped fin structures, ie, a sub-fin structure 210 - 1 and a sub-fin structure 210 - 2 symmetrically facing each other in a top view, are shown formed on a substrate 200 .

[0035] As described later, the first fin structure 210 is also defined by critical dimensions CD6 , CD7 , and CD8 .

[0036] The second fin structure 220 is formed in the same shape as the first fin structure 210 except that upper horizontal portions of the second fin structure 220 are connected to each other, and thus the second fin structure 220 presents an open loop shape in a top view of the substrate 200. However, the fin structure 220 may still be referred to as having two symmetrical portions at least about its Y-direction center line (not shown).

[0037] Hereinafter, a method of manufacturing the first fin structure 210 and the second fin structure 220 is provided.

[0038] Figure 3A and FIG. 3B to FIG. 12A and Fig. 12B A method of fabricating a fin structure for a VFET according to an embodiment is shown. FIG. 3A to FIG. 13A is a perspective view of a substrate on which a fin forming operation is applied, FIG. 3B to FIG. 13B is the corresponding top view of the substrate.

[0039] Reference Figure 3A and Figure 3BThe first layer 300 is deposited on the top surface of the substrate 200 and then patterned in a first direction to form a first pattern 310 that penetrates the first layer 300 with a constant width, the constant width defining Figure 2 CD2 shown. The first pattern 310 is opened at both ends 310-1 and 310-2 at the first layer 300. However, the inventive concept is not limited thereto. According to an embodiment, at least one of the two ends 310-1 and 310-2 may not be opened in the first pattern 310, and in the first pattern 310, only the end 310-1 or 310-2 may be closed while the other is opened. The first pattern 310 thus formed may expose the top surface of the substrate through it in a top view of the substrate 200.

[0040] although Figure 3A and Figure 3B It is shown that the first layer 300 is first deposited on the substrate 200 and then the first pattern 310 is formed thereon, but according to one embodiment, the first layer 300 can be formed so that two parts thereof are deposited on the substrate with a gap of CD2 to expose the top surface of the substrate 200 along the gap of CD2 corresponding to the first pattern 310.

[0041] According to an embodiment, the first layer 300 may have a flat top surface, and may be formed of an amorphous silicon material, polysilicon, silicon oxide (SiO), and / or silicon nitride (not limited thereto).

[0042] Figure 4A and Figure 4B It is shown that the second layer 400 is formed on the first layer 300 according to one embodiment.

[0043] Reference Figure 4A and Figure 4B , a second layer 400 having an etching selectivity with respect to the first layer 300 is deposited on the first layer 300, such that the second layer 400 covers the first layer 300 and fills the first pattern 310. According to an embodiment, the second layer 400 may cover only a sufficient portion of the first layer 300 and completely fill a sufficient portion of the first pattern 310 in which the first fin structure 210 and the second fin structure 220 are to be formed.

[0044] After depositing the second layer 400, the second layer 400 may be planarized to be flat on the top surface thereof. According to an embodiment, chemical mechanical polishing (CMP) may be applied to the second layer 400 to flatten the top surface thereof, but is not limited thereto.

[0045] According to an embodiment, the second layer 400 may be formed of polysilicon having an etching selectivity with respect to the first layer 300 , but is not limited thereto.

[0046] Figure 5A and Figure 5B The formation of a third layer on the second layer 400 that was planarized in a previous operation is shown according to one embodiment.

[0047] Reference Figure 5A and Figure 5B , a third layer is deposited on the top surface of the second layer 400, wherein the third layer is patterned to form two mask patterns 510 and 520, which cross the first pattern 310 and extend in a second direction perpendicular to the first direction in which the first pattern 310 extends. The mask patterns 510 and 520 have a constant width defining CD3, and penetrate the third layer so that the top surface of the second layer 400 is exposed in the second direction through the mask patterns 510 and 520.

[0048] Figure 5A and Figure 5B It is also shown that the mask pattern 510 and the mask pattern 520 have different shapes in the top view. The mask pattern 510 is opened at the two ends 510-1 and 510-2 at the third layer, and the mask pattern 520 is closed at the two ends 520-1 and 520-2 in the third layer, so that the two mask patterns 510 and 520 have different shapes in the top view. However, the inventive concept is not limited to this. According to an embodiment, at least one of the two ends 510-1 and 510-2 may not be opened in the mask pattern 510, and in the mask pattern 520, only the end 520-1 or 510-2 may be closed and the other open.

[0049] although Figure 5A and Figure 5B It is shown that the third layer is first deposited on the second layer 400 and then the mask patterns 510 and 520 are formed thereon, but according to an embodiment, the third layer having the mask patterns 510 and 520 may be formed to expose the top surface of the second layer 400 therethrough.

[0050] Fig. 6A and 6B It is shown that according to one embodiment, the second layer 400 is patterned along the mask patterns 510 and 520 using the third layer as a mask, so that the mask patterns 510 and 520 penetrate the second layer 400 to form second patterns 410 and 420 corresponding to the mask patterns 510 and 520 on the second layer 400 and expose the top surface of the first layer 300.

[0051] Reference Fig. 6A and Figure 6B, since the second patterns 410 and 420 cross the first pattern 310, the top surface of the substrate 200 is exposed at the position where the second patterns 410 and 420 cross the first pattern 310. Note that since the mask pattern 510 is open at both ends 510-1 and 510-2 at the third layer and the mask pattern 520 is closed within the third layer, as shown in FIG. Figure 5A and 5B As shown, patterning the second layer 400 using the mask patterns 510 and 520 results in the second pattern 410 being open at both ends 410-1 and 410-2 at the second layer 400 and the second pattern 420 being closed within the second layer 400. Therefore, the top surface area of ​​the first layer 300 exposed by the second pattern 410 and the top surface area of ​​the first layer 300 exposed by the second pattern 420 are different from each other. In particular, the top surface area 301 of the first layer 300 exposed by one closed end 420-1 of the second pattern 420 can be small enough to accommodate only the top surface area 302 of the first layer 300 to be referred to later. Fig. 7A and Figure 7B A portion of the first spacer 710 is depicted.

[0052] Next, the third layer is removed to expose the top surface of the second layer 400 where the second patterns 410 and 420 are formed.

[0053] Fig. 7A and Figure 7B It is shown that a first spacer 710 is formed on the substrate 200 along the sidewalls of the first layer 300 and the second layer 400 according to an embodiment.

[0054] Specifically, refer to Fig. 7A and Figure 7B , the first portion 710-1 of the first spacer 710 is deposited on the substrate 200 exposed by the first pattern 310 and the second patterns 410 and 420 along the sidewalls of the first layer 300 and the second layer 400 exposed by the first pattern 310 and the second patterns 410 and 420. After depositing the first portion 710-1 of the first spacer 710 in this manner, the substrate 200 is exposed by the first pattern 310 and the second patterns 410 and 420 with a gap of CD5 between the first portions 710-1 in the first pattern 310 facing each other in the second direction and a gap of CD6 between the first portions 710-1 in the first pattern 310 facing each other in the first direction.

[0055] Note that the top surface of the first portion 710-1 of the first spacer 710 may be at the same level as the top surface of the first layer 300. Also note that when the final Figure 2When the first fin structure 210 and the second fin structure 220 are formed as shown, some of the first portions 710-1 of the first spacer 710 facing each other in the second direction under the second pattern 410 in the first pattern 310 form the first fin structure 210, because other portions of the first portions 710-1 are located under the second pattern 410. Fig. 9A and Fig. 9B The first spacers 710 are etched away in the operation of , and all first portions 710 - 1 of the first spacers 710 facing each other in the first direction in the first pattern 310 under the second patterns 410 and 420 form the second fin structure 220 .

[0056] However, in Fig. 7A and Figure 7B , first portions 710 - 1 of the first spacer 710 facing each other in the first direction in the first pattern 310 are not shown because they are formed under second portions 710 - 2 of the first spacer 710 to be described below.

[0057] Refer again Fig. 7A and Figure 7B , the second portion 710-2 of the first spacer 710 is deposited on the top surface of the first layer 300 exposed by the second patterns 410 and 420 and the first portion 710-1 of the first spacer 710 facing each other in the first direction in the first pattern 310 along the inner wall of the second layer 400 exposed by the second patterns 410 and 420. Here, the second portion 710-2 of the first spacer 710 deposited on the first layer 300 along the sidewall of the second layer 400 exposed at the closed end 420-1 may cover the first layer 300 formed by Fig. 6A and Figure 6B The closed end 420 - 1 is shown with the top surface area 301 exposed.

[0058] After the second portions 710-2 of the first spacer 710 are deposited in this manner, the substrate 200 is still exposed through the gaps of CD5 and CD6 described above because the width of each of the second portions 710-2 is the same as the width of each of the first portions 710-1 facing each other in the first direction in the first pattern 310 under the second portions 710-2. In addition, it is noted that the second portions 710-2 of the first spacer 710 deposited on the first layer 300 along the sidewalls of the second layer 400 in the second pattern 420 present a closed shape in a top view.

[0059] Although according to the present embodiment, the first portion 710-1 and the second portion 710-2 of the first spacer 710 are formed in this order, according to one embodiment, this order may be changed, and further, the first portion 710-1 of the first spacer 710 and the second portion 710-2 of the first spacer 710 facing each other along the first direction in the first pattern 310 may be formed by one deposition.

[0060] According to an embodiment, the first portion 710 - 1 and the second portion 710 - 2 of the first spacer 710 may be formed to have a constant width defining CD4 , which will be the width of the first fin structure 210 and the second fin structure 220 .

[0061] According to one embodiment, the first spacer 710 may be made of SiO x and SiN x (not limited to this) is formed by at least one of the following.

[0062] Fig. 8A and Figure 8B It is shown that the second spacer 810 is formed on the sidewall of the first spacer 710 according to one embodiment.

[0063] Specifically, refer to Fig. 8A and Figure 8B , the first portion 810 - 1 of the second spacer 810 is deposited on the substrate exposed by the gaps of CD5 and CD6 defined by the first spacer 710 along sidewalls of the first spacer 710 facing each other in the first direction and the second direction in the first pattern 310 .

[0064] Note here that the top surface of the first portion 810 - 1 of the second spacer 810 may be at the same level as the top surface of the first portion 710 - 1 of the first spacer 710 and the top surface of the first layer 300 .

[0065] However, in Fig. 8A and Figure 8B , first portions 810 - 1 of the second spacer 810 facing each other in the first direction in the first pattern 310 are not shown because they are formed under second portions 810 - 2 of the second spacer 810 to be described below.

[0066] Refer again Fig. 8A and Figure 8B The second portion 810 - 2 of the second spacer 810 is deposited on the first layer 300 exposed by the second patterns 410 and 420 in which the second portion 710 - 2 of the first spacer 700 is deposited, along the sidewalls of the second layer 400 exposed by the second patterns 410 and 420 .

[0067] Although the first portion 810-1 and the second portion 810-2 of the second spacer 810 are formed in this order according to the present embodiment, this order may be changed according to an embodiment. For example, the first portion 810-1 of the second spacer 810 deposited on the substrate 200 along the sidewalls of the first spacer 710 in the first pattern 310 and facing each other in the first direction, and the second portion 810-2 of the second spacer 810 facing each other in the first direction may be formed by one deposition.

[0068] Note that the width of the second portion 810 - 2 of the second spacer 810 may define Figure 2 CD8 as shown.

[0069] According to one embodiment, the second spacer 810 may be made of SiO x and SiN x However, the second spacer 810 may have an etching selectivity relative to the first spacer 710, so that when the first spacer 710 includes SiO x When the second spacer 810 may include SiN x .

[0070] Now refer to Figure 8B , after the second spacer 810 is deposited in the above-described manner, the top view of the substrate 200 on which the first layer 300, the second layer 400, the first spacer 710, and the second spacer 810 are formed still shows the two portions 201 and 202 of the substrate 200 exposed through the gaps of CD7 in the first pattern 310 and the second patterns 410 and 420. However, according to an embodiment, by depositing the first portion 810-1 of the second spacer 810 on the two portions 201 and 202, the two portions 201 and 202 may not be exposed. This is because even according to this embodiment, Figure 2 A first fin structure 210 and a second fin structure 220 are shown.

[0071] Fig. 9A and Fig. 9B It is shown that the second portion 710-2 of the first spacer 710 above the level of the top surface of the first layer 300 is removed, and further, the first portion 710-1 of the first spacer 710 facing each other in the second direction in the first pattern 310 and exposed by the first pattern 310 and the second patterns 410 and 420 is removed. Fig. 9B It is shown that first portions 710 - 1 of the first spacers 710 facing each other in the first direction in the first pattern 310 , formed under the removed second portions 710 - 2 of the first spacers 710 , are exposed through the first pattern 310 and the second patterns 410 and 420 .

[0072] Fig. 10A and Fig. 10B The second layer 400 and the second spacer 810 are removed above the level of the first layer 300 to expose the top surface of the first layer 300 and the first spacer 710. Fig. 9A and Fig. 9B After the removal operation in , the top surface of the first portion 710-1 in the first pattern 310 remains. Fig. 10A and Fig. 10B In the removal operation, Fig. 9A and Fig. 9B The first portion 810-1 of the second spacer 810 and the second layer 400 remaining in the first pattern 310 after the removal operation are also exposed. Fig. 10A and Fig. 10B In this removal operation, the second patterns 410 and 420 no longer exist. According to one embodiment, in Fig. 10A and Fig. 10B The removal operation used in the process may be CMP (but not limited to this).

[0073] Fig.11A and 11B The first layer 300, the second layer 400 filled in the first pattern 310, and the first portion 810-1 of the second spacer 810 are removed together with the first pattern 310, thereby leaving only the first spacer 710. Fig. 9A and Fig. 9B A first portion 710 - 1 remains on the substrate 200 after the removal operation in FIG.

[0074] According to one embodiment, Fig.11A and Fig. 11B The removal operation used in may be dry etching and / or wet etching (without limitation).

[0075] Fig. 12A and Fig. 12B The first spacer 710 is now used. Fig. 9A and 9B The first portion 710-1 remaining on the substrate 200 after the removal operation in the above step is used as a mask to etch the substrate 200 downward to a predetermined depth. Here, the predetermined depth may define the height of the first fin structure 210 and the second fin structure 220 on the substrate 200. According to one embodiment, the etching operation used here may be dry etching (not limited thereto). After the etching operation, the first fin structure 210 and the second fin structure 220 are formed on the substrate 200 with the first spacer 710 thereon. Fig. 9A and Fig. 9B The first portion 710 - 1 remains on the substrate 200 after the removal operation.

[0076] Fig.13A and 13B The first spacer 710 is now removed by etching. Fig. 9A and Fig. 9B The first portion 710-1 remains after the removal operation in order to expose the Figure 2 A first fin structure 210 and a second fin structure 220 are shown on an etched substrate 200 .

[0077] In the aforementioned embodiment, the first fin structure 210 and the second fin structure 220 are simultaneously formed on the substrate 200 using the first spacer 710 and the second spacer 810 based on the first pattern 310 and the second patterns 410 and 420. However, the inventive concept is not limited thereto. According to one embodiment, each of the first fin structure 210 and the second fin structure 220 may be formed independently of the other using the first spacer 710 and the second spacer 810 based on only one of the second patterns 410 and 420 and the first pattern 310.

[0078] Furthermore, in the aforementioned embodiment, the first fin structure 210 and the second fin structure 220 are formed on the substrate 200 using the first spacer 710 and the second spacer 810 based on three patterns, namely, the first pattern 310 and the second patterns 410 and 420. However, the inventive concept is not limited thereto, as more fin structures may be formed on the substrate 200 using two or more first patterns at the first layer 300 and three or more second patterns at the second layer 400.

[0079] According to the aforementioned embodiments, a multi-dimensional semiconductor device such as a FinFET and a VFET may have a fin structure having no length deviation between substructures, thereby enabling the manufacture of an ultra-fine fin structure.

[0080] The foregoing is illustrative of exemplary embodiments and is not to be construed as limiting thereof. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the above embodiments without substantially departing from the inventive concept.

[0081] This application claims priority to U.S. Provisional Application No. 62 / 913,408, entitled “Semiconductor Process for Uniformly Cut 2D Structures,” filed in the USPTO on October 10, 2019, and U.S. Application No. 16 / 824,196, entitled “Symmetrical Two-Dimensional Fin Structure for Vertical Field Effect Transistor and Method for Fabricating the Same,” filed in the USPTO on March 19, 2020, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A method for manufacturing at least one fin structure of a vertical field effect transistor, the method comprising the following operations: (a) forming a first layer on a substrate, the first layer having at least one first pattern, the first pattern extending in a first direction with a constant first width and penetrating the first layer, so that a top surface of the substrate is exposed through the first pattern in the first direction; (b) forming a second layer on the first layer, such that the second layer is formed on a top surface of the first layer and fills the first pattern; (c) forming a third layer on the top surface of the second layer, the third layer having at least one mask pattern, the at least one mask pattern crossing the first pattern, extending in a second direction different from the first direction with a constant second width, and penetrating the third layer so that the top surface of the second layer is exposed through the mask pattern in the second direction; (d) patterning the second layer along the mask pattern using the third layer as a mask, so that the mask pattern penetrates the second layer to form at least one second pattern corresponding to the mask pattern, the top surface of the first layer is exposed through the second pattern, and the top surface of the substrate is exposed through the first pattern and the second pattern; (e) removing the third layer; (f) forming a first spacer along a sidewall of the first layer exposed by the first pattern and a sidewall of the second layer exposed by the second pattern; (g) forming a second spacer along a sidewall of the first spacer; (h) removing the first spacer formed on the top surface of the first layer and between the second layer and the second spacer, and the first spacer under the top surface of the first layer and exposed by the first pattern and the second pattern in a top view; (i) removing the second layer and the second spacer formed above the level of the top surface of the first layer; (j) removing the first layer, the second layer and the second spacer above the level of the top surface of the substrate; as well as (k) Etching down the substrate except for a portion of the substrate under the first spacer remaining from operation (j), and removing the first spacer remaining from operation (j), thereby obtaining the fin structure. The method of claim 1 , wherein the first direction and the second direction are substantially perpendicular to each other.

3. The method according to claim 1, wherein operation (a) include: forming the first layer on the top surface of the substrate; as well as patterning the first layer to form the first pattern, and The operation (c) includes: forming the third layer on the top surface of the second layer; as well as The third layer is patterned to form the mask pattern.

4. The method according to claim 1, in, In operation (d), the second layer filled in the first pattern and exposed by the second pattern is removed so that the top surface of the substrate is exposed through the first pattern and the second pattern.

5. The method according to claim 1, in, In operation (f), the first spacer is formed on all sidewalls of the first layer and the second layer exposed by at least one of the first pattern and the second pattern, and Wherein, in operation (g), the second spacer is formed on all sidewalls of the first spacer exposed by the second pattern.

6. The method according to claim 1, wherein the first spacer formed in operation (f) include: a first portion formed on the substrate exposed by the first pattern and the second pattern along the sidewalls of the first layer facing each other in the second direction in the first pattern; as well as A second portion is formed on the substrate exposed by the first pattern and the second pattern along the side walls of the second layer facing each other in the first direction in the first pattern, The second spacer formed in operation (g) includes: a first portion formed along the sidewall of the first spacer in the first pattern on the substrate exposed by the first pattern and the second pattern; as well as A second portion along the sidewall of the second layer exposed by the second pattern is formed on the first layer exposed by the second pattern of the second portion of the first spacer deposited therein. 7 . The method of claim 1 , wherein the first spacer remaining after operation (h) exhibits the same shape as the fin structure in a top view. The method of claim 1 , wherein the first layer and the second layer have an etch selectivity with respect to each other.

9. The method of claim 1, further comprising planarizing the second layer by chemical mechanical polishing after operation (b) and before operation (c).

10. A method for manufacturing at least one fin structure of a vertical field effect transistor, the method include: (a) stacking a plurality of layers including a lower layer and an upper layer on a substrate, the lower layer and the upper layer respectively having at least one first pattern and at least one second pattern extending in different directions across each other to expose the substrate therethrough; (b) forming first spacers on sidewalls of the plurality of layers exposed by the first pattern and the second pattern; (c) forming a second spacer on a sidewall of the first spacer; (d) removing the first spacer, the second spacer, and the upper layer above the level of the top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed by the first pattern and the second pattern in a top view; (e) removing the plurality of layers and the second spacer remaining on the substrate after operation (d); as well as (f) Etching down the substrate except for a portion of the substrate located below the first spacer remaining on the substrate after operation (e), and removing the remaining first spacer, thereby obtaining the fin structure.

11. The method according to claim 10, wherein operation (a) include: depositing the lower layer on the substrate and patterning the lower layer to form the first pattern; depositing the upper layer on the lower layer; depositing a mask layer on the upper layer and patterning the mask layer to form at least one mask pattern corresponding to the second pattern; as well as The upper layer is patterned to form the second pattern using the patterned mask layer as a mask.

12. The method according to claim 10, wherein the second pattern comprises a second first pattern and a second second pattern different from each other, and The fin structure include: a first fin structure obtained from the first pattern and the second first pattern and having two symmetrical parts separated from each other in a top view; as well as The second fin structure is obtained from the first pattern and the second second pattern and has two symmetrical parts connected to each other in a top view. 13 . The method of claim 12 , wherein an area of ​​the lower layer exposed by the second first pattern is larger than an area of ​​the lower layer exposed by the second second pattern.

14. The method according to claim 13, wherein at least one end of the second pattern is closed within the upper layer, The area of ​​the lower layer exposed by the closed end of the second pattern is completely covered by the first spacer formed thereon through operation (b).

15. The method according to claim 10, wherein operation (d) include: etching away the first spacer formed between the upper layer and the second spacer above the level of the top surface of the lower layer; etching away the first spacer located in the first pattern and formed between the first pattern and the second spacer in the first pattern; as well as The second spacer and the upper layer are removed above the level of the top surface of the lower layer.

16. The method according to claim 10, in, In a plan view, the width of the first spacer formed on each of the sidewalls in the first pattern of the lower layer is the same as the width of the fin structure.

17. The method according to claim 10, in, In operation (f), etching down the substrate is performed to a predetermined depth, the predetermined depth defining a height of the fin structure.

18. A fin structure for a vertical field effect transistor, the fin structure comprising a first sub-fin structure and a second sub-fin structure protruding from a substrate, in, In a top view, the first sub-fin structure and the second sub-fin structure are symmetrical to each other on the substrate, and The fin structure is formed by: (a) patterning a lower layer and an upper layer deposited on the lower layer to form two patterns extending in two directions perpendicular to each other; (b) forming a first spacer and a second spacer side by side in the two patterns along the sidewalls of the lower layer and the upper layer exposed by the patterning; (c) removing the first spacer, the second spacer, and the upper layer above the level of the top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed by the two patterns in a top view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); as well as (e) Etching down the substrate except for a portion of the substrate located below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby obtaining the fin structure. The fin structure of claim 18 , wherein the first sub-fin structure and the second sub-fin structure are separated from each other on the substrate. 20 . The fin structure of claim 18 , wherein the first sub-fin structure and the second sub-fin structure are connected to each other on the substrate.

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