A closed-loop RFID carrier automatic cancellation system

Abstract

The present invention provides a closed-loop RFID carrier automatic cancellation system, which includes a reader transmitter, a reader receiver, a frequency discriminator and phase detector module, a low-pass filter, a first-stage signal amplitude processing module, a second-stage signal amplitude processing module and a frequency divider. The reader transmitter is connected to the first input end of the frequency discriminator and phase detector module. The output end of the frequency discriminator and phase detector module is connected to the input end of the low-pass filter. The low-pass filter, the first-stage signal amplitude processing module, the second-stage signal amplitude processing module and the frequency divider are connected in sequence. The output end of the first-stage signal amplitude processing module is coupled to the reader receiver. The output end of the frequency divider is connected to the second input end of the frequency discriminator and phase detector module. The carrier signals generated inside the RFID reader are respectively connected to the reference ends of the first-stage signal amplitude processing module and the second-stage signal amplitude processing module. The present invention realizes the self-cancellation of the interference signals leaked from the transmitting link to the receiving link, thereby greatly improving the sensitivity of the receiver.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency identification, and in particular to a closed-loop RFID carrier automatic cancellation system. Background Art

[0002] With the gradual popularization of the Internet of Things, the ultra-high frequency radio frequency identification technology faces unprecedented historical opportunities, which promotes the rapid development and improvement of related technologies. RFID can identify the information carried on the label of the target object without contact, and this technology has been widely applied to warehouse management systems, file management systems, logistics warehousing systems, and Industry 4.0, etc.

[0003] The current main technical problem is that the effective distance for the RFID reader to read the label is limited by its own sensitivity. This is mainly because the isolation degree of the antenna circulator is limited, resulting in easy leakage of the transmit link power to the receive link. When the receiver demodulates the label signal, it is interfered by the strong carrier signal, resulting in a decrease in the receiver sensitivity.

[0004] Therefore, achieving the elimination of the interference signal leaked from the transmit link to the receive link, so as to greatly improve the sensitivity of the receiver, is the key to improving the effective distance for the RFID reader to read the label. Summary of the Invention

[0005] In order to solve the above problems, the present invention proposes a closed-loop RFID carrier automatic cancellation system, which realizes the isolation between the transmit link and the receive link, and has a relatively high stability of the carrier suppression result.

[0006] The present invention is achieved through the following technical solutions:

[0007] The present invention proposes a closed-loop RFID carrier automatic cancellation system, including a reader transmitter, a reader receiver, a frequency discriminator and phase detector module, a low-pass filter, a first-stage signal amplitude processing module, a second-stage signal amplitude processing module, and a frequency divider. The reader transmitter is the radio frequency signal transmitting end of the RFID reader, and the reader receiver is the radio frequency signal receiving end of the RFID reader. The reader transmitter is connected to the first input end of the frequency discriminator and phase detector module. The output end of the frequency discriminator and phase detector module is connected to the input end of the low-pass filter. The output end of the low-pass filter is connected to the input end of the first-stage signal amplitude processing module. The output end of the first-stage signal amplitude processing module is connected to the input end of the second-stage signal amplitude processing module. The output end of the first-stage signal amplitude processing module is coupled to the reader receiver. The output end of the second-stage signal amplitude processing module is connected to the input end of the frequency divider. The output end of the frequency divider is connected to the second input end of the frequency discriminator and phase detector module. The carrier signals generated inside the RFID reader are respectively connected to the reference end of the first-stage signal amplitude processing module and the reference end of the second-stage signal amplitude processing module.

[0008] Further, in a closed-loop RFID carrier automatic cancellation system proposed by the present invention, the frequency discriminator and phase discriminator module includes a first D flip-flop, a second D flip-flop, an exclusive-OR gate, a third D flip-flop, a fourth D flip-flop, a first NAND gate, and a second NAND gate. The clock input terminal of the first D flip-flop is connected to the clock input terminal of the third D flip-flop and serves as the first input terminal of the frequency discriminator and phase discriminator module. The clock input terminal of the second D flip-flop is connected to the clock input terminal of the fourth D flip-flop and serves as the second input terminal of the frequency discriminator and phase discriminator module. The data input terminal of the first D flip-flop is connected to its inverted output terminal. The data input terminal of the second D flip-flop is connected to its inverted output terminal. The output terminal of the first D flip-flop is connected to the first input terminal of the exclusive-OR gate. The output terminal of the second D flip-flop is connected to the second input terminal of the exclusive-OR gate. The output terminal of the exclusive-OR gate is respectively connected to the data input terminal of the third D flip-flop, the data input terminal of the fourth D flip-flop, and the first input terminal of the first NAND gate. The inverted output terminal of the third D flip-flop is respectively connected to the set terminal of the fourth D flip-flop and the first input terminal of the second NAND gate. The output terminal of the fourth D flip-flop is respectively connected to the reset terminal of the third D flip-flop and the second input terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the second input terminal of the second NAND gate. The output terminal of the second NAND gate serves as the output terminal of the frequency discriminator and phase discriminator module.

[0009] Further, in a closed-loop RFID carrier automatic cancellation system proposed by the present invention, the first-stage signal amplitude processing module and the second-stage signal amplitude processing module have the same structure, and both include a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, and an amplifier. The first end of the first resistor is connected to the first end of the first capacitor and the first end of the second capacitor and serves as the input terminal of the first-stage signal amplitude processing module or the second-stage signal amplitude processing module. The second end of the first resistor is connected to the first end of the third capacitor and the negative input terminal of the amplifier. The positive input terminal of the amplifier serves as the reference terminal of the first-stage signal amplitude processing module or the second-stage signal amplitude processing module. The second end of the first capacitor is grounded. The second end of the second capacitor is connected to the first end of the second resistor. The second end of the second resistor is connected to the second end of the third capacitor and the output terminal of the amplifier and serves as the output terminal of the first-stage signal amplitude processing module or the second-stage signal amplitude processing module.

[0010] Further, in a closed-loop RFID carrier automatic cancellation system proposed by the present invention, it further includes a power detector connected to the output terminal of the first-stage signal amplitude processing module for detecting the effect of carrier automatic cancellation.

[0011] Further, in a closed-loop RFID carrier automatic cancellation system proposed by the present invention, the power detector includes an AD8312 chip.

[0012] Further, in a closed-loop RFID carrier automatic cancellation system proposed by the present invention, the frequency divider includes a fifth D flip-flop. The clock input terminal of the fifth D flip-flop serves as the input terminal of the frequency divider. The inverted output terminal of the fifth D flip-flop is connected to its data input terminal, and the output terminal of the fifth D flip-flop serves as the output terminal of the frequency divider.

[0013] Further, in a closed-loop RFID carrier automatic cancellation system proposed by the present invention, it further includes a directional coupler and an antenna. The input terminal of the directional coupler is connected to the transmitting end of the reader / writer, the output terminal of the directional coupler is connected to the receiving end of the reader / writer, and the coupled terminal of the directional coupler is connected to the antenna.

[0014] Further, in a closed-loop RFID carrier automatic cancellation system proposed by the present invention, the output signal of the directional coupler and the output signal of the first-stage signal amplitude processing module are superimposed and then input into the receiving end of the reader / writer.

[0015] Advantages of the present invention:

[0016] The present invention proposes a new carrier loop suppression scheme to eliminate the influence of the transmitted power on the receiving circuit. It has been verified that the carrier suppression result of the present invention has high stability, a simple structure, realizes the self-cancellation of the interference signal leaked from the transmitting link to the receiving link, thereby greatly improving the sensitivity of the receiver. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of the overall structure of an embodiment of the present invention;

[0018] Figure 2 It is a schematic diagram of the structure of the frequency discriminator and phase discriminator module of an embodiment of the present invention;

[0019] Figure 3 It is a schematic diagram of the structure of the first-stage signal amplitude processing module or the second-stage signal amplitude processing module of an embodiment of the present invention;

[0020] Figure 4 It is a schematic diagram of the structure of the frequency divider of an embodiment of the present invention. Detailed Embodiments

[0021] In order to more clearly and completely illustrate the technical solution of the present invention, the present invention will be further described below with reference to the drawings.

[0022] Please refer to Figure 1, an embodiment of a closed-loop RFID carrier automatic cancellation system proposed by the present invention includes a reader transmitter 101, a reader receiver 102, a frequency discriminator and phase detector module 103, a low-pass filter 104, a first-stage signal amplitude processing module 105, a second-stage signal amplitude processing module 106, and a frequency divider 107. The reader transmitter 101 is the radio frequency signal transmitting end of the RFID reader, and the reader receiver 102 is the radio frequency signal receiving end of the RFID reader. The reader transmitter 101 is connected to the first input end of the frequency discriminator and phase detector module 103. The output end of the frequency discriminator and phase detector module 103 is connected to the input end of the low-pass filter 104. The output end of the low-pass filter 104 is connected to the input end of the first-stage signal amplitude processing module 105. The output end of the first-stage signal amplitude processing module 105 is connected to the input end of the second-stage signal amplitude processing module 106. The output end of the first-stage signal amplitude processing module 105 is coupled to the reader receiver 102. The output end of the second-stage signal amplitude processing module 106 is connected to the input end of the frequency divider 107. The output end of the frequency divider 107 is connected to the second input end of the frequency discriminator and phase detector module 103. The carrier signals generated inside the RFID reader are respectively connected to the reference end of the first-stage signal amplitude processing module 105 and the reference end of the second-stage signal amplitude processing module 106.

[0023] In this embodiment, after the reader transmitter 101 of the RFID reader finishes sending instructions, it will continuously transmit a carrier to provide energy for the tag. A part of this carrier will leak to the reader receiver 102 through the circulator, and at the same time, a part will enter the frequency discriminator and phase detector module 103 of this embodiment through coupling. The frequency discriminator and phase detector module 103 performs detection and phase comparison on the carrier signal fed back by the frequency divider 107 and the carrier signal leaked by the circulator and then outputs. The low-pass filter 104 is used to convert the phase comparison signal into a DC voltage signal. The DC voltage signal controls the first-stage signal amplitude processing module 105 to invert the input carrier generated by the carrier input module, and then the signal is restored again through the second-stage signal amplitude processing module 106. The frequency divider 107 feeds back the output carrier signal to the frequency discriminator and phase detector module 103. At this time, the carrier signal output by the first-stage signal amplitude processing module 105 after loop processing and the carrier signal that leaks a part to the reader receiver 102 through the circulator have the same amplitude and opposite phases, and then they are superimposed on the reader receiver 102 to achieve the purpose of automatic cancellation of the RFID carrier in the closed-loop.

[0024] The carrier automatic cancellation system solution of the embodiment of the present invention is different from the traditional phase shift solution. First, the present invention realizes the phase synchronization self-alignment of the receiving link and the transmitting link through phase discrimination, loop filtering, the intrinsic carrier and the frequency division circuit, then performs amplitude deflection and attenuation and feeds them into the receiving link, and further realizes the phase self-alignment cancellation of the carrier leakage of the receiving link, so that the sensitivity of the receiver is greatly improved. When the transmission power of the reader / writer transmitter increases, the carrier power leaked to the reader / writer receiver gradually increases. Generally, the carrier signal is suppressed by about 45 dB. The sensitivity of the receiver using the cancellation solution of the present invention is about 35 dB higher than that of the receiver using the traditional cancellation solution. At the same time, the present invention solves the problem of poor stability of the traditional cancellation and realizes the isolation between the transmitting link and the receiving link.

[0025] Further, referring to Figure 2 , in an embodiment of a closed-loop RFID carrier automatic cancellation system, the frequency discriminator and phase discriminator module 103 includes a first D flip-flop 1031, a second D flip-flop 1032, an exclusive-OR gate 1033, a third D flip-flop 1034, a fourth D flip-flop 1035, a first NAND gate 1036 and a second NAND gate 1037. The clock input terminal of the first D flip-flop 1031 is connected to the clock input terminal of the third D flip-flop 1034 and serves as the first input terminal of the frequency discriminator and phase discriminator module 103. The clock input terminal of the second D flip-flop 1032 is connected to the clock input terminal of the fourth D flip-flop 1035 and serves as the second input terminal of the frequency discriminator and phase discriminator module 103. The data input terminal of the first D flip-flop 1031 is connected to its inverted output terminal. The data input terminal of the second D flip-flop 1032 is connected to its inverted output terminal. The output terminal of the first D flip-flop 1031 is connected to the first input terminal of the exclusive-OR gate 1033. The output terminal of the second D flip-flop 1032 is connected to the second input terminal of the exclusive-OR gate 1033. The output terminal of the exclusive-OR gate 1033 is respectively connected to the data input terminal of the third D flip-flop 1034, the data input terminal of the fourth D flip-flop 1035 and the first input terminal of the first NAND gate 1036. The inverted output terminal of the third D flip-flop 1034 is respectively connected to the set terminal of the fourth D flip-flop 1035 and the first input terminal of the second NAND gate 1037. The output terminal of the fourth D flip-flop 1035 is respectively connected to the reset terminal of the third D flip-flop 1034 and the second input terminal of the first NAND gate 1036. The output terminal of the first NAND gate 1036 is connected to the second input terminal of the second NAND gate 1037. The output terminal of the second NAND gate 1037 serves as the output terminal of the frequency discriminator and phase discriminator module 103.

[0026] In this embodiment, the two input signals of the frequency discriminator and phase discriminator module 103 are pulse sequences, and their leading edges or trailing edges respectively represent their respective phases. By comparing the frequencies and phases of these two pulse sequences, an output related to the phase difference can be obtained. This module uses multi-stage cascading and synchronous processing to meet the requirements of the cancellation system.

[0027] Further, referring to Figure 3 In an embodiment of a closed-loop RFID carrier automatic cancellation system, the first-stage signal amplitude processing module 105 and the second-stage signal amplitude processing module 106 have the same structure, and both include a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a third capacitor C3, and an amplifier. The first end of the first resistor R1 is connected to the first ends of the first capacitor C1 and the second capacitor C2 and serves as the input terminal Vin of the first-stage signal amplitude processing module 105 or the second-stage signal amplitude processing module 106. The second end of the first resistor R1 is connected to the first end of the third capacitor C3 and the negative input terminal of the amplifier. The positive input terminal of the amplifier serves as the reference terminal Vref of the first-stage signal amplitude processing module 105 or the second-stage signal amplitude processing module 106. The second end of the first capacitor C1 is grounded. The second end of the second capacitor is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to the second end of the third capacitor C3 and the output terminal of the amplifier and serves as the output terminal Vout of the first-stage signal amplitude processing module 105 or the second-stage signal amplitude processing module 106.

[0028] In this embodiment, for the amplitude processing module, first of all, the output of the charge pump should always be directly fed into a high-Q capacitor, that is, the capacitor with the smallest series resistance, to attenuate its high-frequency content before feeding it into the loop filter operational amplifier. The reason for this is that the operational amplifier has a limited bandwidth, and if directly driven by high frequencies, it may exhibit non-linear behavior such as those present in the charge pump output. In addition, the feedback of the operational amplifier should be configured to achieve unity gain from the operational amplifier terminals to its output. In this way, the reference noise input to the operational amplifier does not affect the loop filter output and thus will not be amplified.

[0029] Further, in an embodiment of a closed-loop RFID carrier automatic cancellation system, it further includes a power detector connected to the output terminal of the first-stage signal amplitude processing module 105 for detecting the effect of carrier automatic cancellation. By detecting the output signal of the first-stage signal amplitude processing module 105 through the power detector, the effect of automatic cancellation of the carrier signal in the embodiment of the present invention can be reflected.

[0030] Further, in an embodiment of a closed-loop RFID carrier automatic cancellation system, the power detector includes an AD8312 chip. The first pin of the AD8312 chip is connected to the power supply. The second and third pins serve as the detection result output terminals. The fourth and fifth pins are grounded. The sixth pin serves as the detection signal input terminal.

[0031] Further, referring to Figure 4, in an embodiment of a closed-loop RFID carrier automatic cancellation system, the frequency divider 107 includes a fifth D flip-flop. The clock input terminal of the fifth D flip-flop serves as the input terminal of the frequency divider 107. The inverted output terminal of the fifth D flip-flop is connected to its data input terminal, and the output terminal of the fifth D flip-flop serves as the output terminal of the frequency divider 107.

[0032] In this embodiment, the frequency divider 107 uses D flip-flops in the chain to divide the frequency for two counters. One D flip-flop divides the clock frequency by half. If two flip-flops are used, the clock frequency is divided by a quarter. One advantage of using bistable flip-flops for frequency division is that the output at any point has an exact 50% duty cycle. According to the change of the frequency in the link, the frequency division equal parts of the loop are changed, thereby realizing the phase synchronization of the loop.

[0033] Further, referring to Figure 1 , in an embodiment of a closed-loop RFID carrier automatic cancellation system, it further includes a directional coupler 108 and an antenna 109. The input terminal of the directional coupler 108 is connected to the transmitter 101 of the reader / writer, the output terminal of the directional coupler 108 is connected to the receiver 102 of the reader / writer, and the coupled terminal of the directional coupler 108 is connected to the antenna 109.

[0034] Further, referring to Figure 1 , in an embodiment of a closed-loop RFID carrier automatic cancellation system, the output signal of the directional coupler 108 and the output signal of the first-stage signal amplitude processing module 105 are superimposed and then input into the receiver 102 of the reader / writer.

[0035] In summary, the present invention proposes a new carrier loop suppression scheme to eliminate the influence of the transmitted power on the receiving circuit. It has been verified that the carrier suppression result of the present invention has high stability, a simple structure, realizes the self-cancellation of the interference signal leaked from the transmitting link to the receiving link, thereby greatly improving the sensitivity of the receiver.

[0036] Of course, the present invention may have other various implementation manners. Based on this implementation manner, other implementation manners obtained by those of ordinary skill in the art without any creative labor belong to the scope protected by the present invention.

Claims

1. A closed-loop RFID carrier automatic cancellation system, characterized in that, It includes a reader transmitter (101), a reader receiver (102), a frequency discriminator and phase detector module (103), a low-pass filter (104), a first-stage signal amplitude processing module (105), a second-stage signal amplitude processing module (106), and a frequency divider (107). The reader transmitter (101) is the RF signal transmitter of the RFID reader. The reader receiver (102) is the RF signal receiver of the RFID reader. The reader transmitter (101) is connected to the first input end of the frequency discriminator and phase detector module (103). The output end of the frequency discriminator and phase detector module (103) is connected to the input end of the low-pass filter (104). The output end of the low-pass filter (104) is connected to the input end of the first-stage signal amplitude processing module (105). The output end of the first-stage signal amplitude processing module (105) is connected to the input end of the second-stage signal amplitude processing module (106). The output end of the first-stage signal amplitude processing module (105) is coupled to the reader receiver (102). The output end of the second-stage signal amplitude processing module (106) is connected to the input end of the frequency divider (107). The output end of the frequency divider (107) is connected to the second input end of the frequency discriminator and phase detector module (103). The carrier signal generated inside the RFID reader is respectively connected to the reference end of the first-stage signal amplitude processing module (105) and the reference end of the second-stage signal amplitude processing module (106); The first-stage signal amplitude processing module (105) and the second-stage signal amplitude processing module (106) have the same structure, and both include a first resistor (R1), a second resistor (R2), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), and an amplifier. The first end of the first resistor (R1) is connected to the first end of the first capacitor (C1) and the first end of the second capacitor (C2) and serves as the input end (Vin) of the first-stage signal amplitude processing module (105) or the second-stage signal amplitude processing module (106). The second end of the first resistor (R1) is connected to the first end of the third capacitor (C3) and the negative input end of the amplifier. The positive input end of the amplifier serves as the reference end (Vref) of the first-stage signal amplitude processing module (105) or the second-stage signal amplitude processing module (106). The second end of the first capacitor (C1) is grounded. The second end of the second capacitor is connected to the first end of the second resistor (R2). The second end of the second resistor (R2) is connected to the second end of the third capacitor (C3) and the output end of the amplifier and serves as the output end (Vout) of the first-stage signal amplitude processing module (105) or the second-stage signal amplitude processing module (106); After the reader transmitter (101) sends out an instruction, it continuously transmits a carrier wave to provide energy for the tag. A part of this carrier wave leaks to the reader receiver (102) through the circulator, and at the same time, a part of it enters the frequency discriminator and phase comparator module (103) through coupling. The frequency discriminator and phase comparator module (103) outputs after detecting and comparing the phase of the carrier wave signal fed back by the frequency divider (107) with the carrier wave signal leaked by the circulator. The low-pass filter (104) is used to convert the phase comparison signal into a DC voltage signal. The DC voltage signal flips the input carrier wave generated by the carrier input module through the control of the first signal amplitude processing module (105), and then the signal is restored through the second signal amplitude processing module (106). The frequency divider (107) feeds back the output carrier wave signal to the frequency discriminator and phase comparator module (103). The carrier wave signal output by the first signal amplitude processing module (105) after loop processing and the carrier wave signal that leaks from the circulator to the reader receiver (102) have the same amplitude but opposite phases, and then they are superimposed on the reader receiver (102) to achieve closed-loop RFID carrier automatic cancellation.

2. The closed-loop RFID carrier automatic cancellation system according to claim 1, characterized in that The frequency discriminator and phase comparator module (103) includes a first D flip-flop (1031), a second D flip-flop (1032), an exclusive-OR gate (1033), a third D flip-flop (1034), a fourth D flip-flop (1035), a first NAND gate (1036), and a second NAND gate (1037). The clock input terminal of the first D flip-flop (1031) is connected to the clock input terminal of the third D flip-flop (1034) and serves as the first input terminal of the frequency discriminator and phase comparator module (103). The clock input terminal of the second D flip-flop (1032) is connected to the clock input terminal of the fourth D flip-flop (1035) and serves as the second input terminal of the frequency discriminator and phase comparator module (103). The data input terminal of the first D flip-flop (1031) is connected to its inverted output terminal. The data input terminal of the second D flip-flop (1032) is connected to its inverted output terminal. The output terminal of the first D flip-flop (1031) is connected to the first input terminal of the exclusive-OR gate (1033). The output terminal of the second D flip-flop (1032) is connected to the second input terminal of the exclusive-OR gate (1033). The output terminal of the exclusive-OR gate (1033) is respectively connected to the data input terminal of the third D flip-flop (1034), the data input terminal of the fourth D flip-flop (1035), and the first input terminal of the first NAND gate (1036). The inverted output terminal of the third D flip-flop (1034) is respectively connected to the set terminal of the fourth D flip-flop (1035) and the first input terminal of the second NAND gate (1037). The output terminal of the fourth D flip-flop (1035) is respectively connected to the reset terminal of the third D flip-flop (1034) and the second input terminal of the first NAND gate (1036). The output terminal of the first NAND gate (1036) is connected to the second input terminal of the second NAND gate (1037). The output terminal of the second NAND gate (1037) serves as the output terminal of the frequency discriminator and phase comparator module (103).

3. The closed-loop RFID carrier automatic cancellation system according to claim 1, characterized in that It further includes a power detector, which is connected to the output end of the first-stage signal amplitude processing module (105) and is used to detect the carrier auto-cancellation effect.

4. The closed-loop RFID carrier automatic cancellation system according to claim 3, characterized in that, The power detector includes an AD8312 chip.

5. The closed-loop RFID carrier automatic cancellation system according to claim 1, characterized in that, The frequency divider (107) includes a fifth D flip-flop. The clock input end of the fifth D flip-flop serves as the input end of the frequency divider (107). The inverted output end of the fifth D flip-flop is connected to its data input end. The output end of the fifth D flip-flop serves as the output end of the frequency divider (107).

6. The closed-loop RFID carrier automatic cancellation system according to claim 1, characterized in that It further includes a directional coupler (108) and an antenna (109). The input end of the directional coupler (108) is connected to the transmitter end (101) of the reader-writer. The output end of the directional coupler (108) is coupled to the receiver end (102) of the reader-writer. The coupling end of the directional coupler (108) is connected to the antenna (109).

7. A closed-loop RFID carrier auto-cancellation system according to claim 6, wherein The output signal of the directional coupler (108) and the output signal of the first-stage signal amplitude processing module (105) are superimposed and then input into the receiver end (102) of the reader-writer.

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