Method of manufacturing a semiconductor device and semiconductor device

Abstract

In a method for manufacturing a semiconductor device, a fin structure is formed over a substrate, an isolation insulating layer is formed over the substrate so that an upper portion of the fin structure protrudes from the isolation insulating layer, a first dielectric layer is formed on the upper portion of the fin structure, a cap layer is formed on the first dielectric layer, the cap layer is removed from an upper portion of the upper portion of the fin structure having the first dielectric layer, the first dielectric layer is removed from the upper portion of the upper portion of the fin structure, a second dielectric layer is formed on the upper portion of the upper portion of the fin structure, and a gate electrode is formed on the second dielectric layer and the first dielectric layer disposed on a lower portion of the upper portion of the fin structure. Embodiments of the invention also relate to a semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to a method of manufacturing a semiconductor device and a semiconductor device. BACKGROUND

[0002] The present invention relates to a method of manufacturing a semiconductor integrated circuit, and more particularly, to a method of manufacturing a semiconductor device including a fin field effect transistor (FinFET). As the scaling of integrated circuits increases and the demand for integrated circuit speed becomes more and more high, transistors need to have greater drive current and smaller and smaller size. Therefore, a fin field effect transistor (FinFET) has been developed. The FinFET includes a vertical semiconductor fin located over a substrate. The semiconductor fin is used to form source and drain regions and a channel region between the source and drain regions. A shallow trench isolation (STI) region is formed to define the semiconductor fin. The FinFET also includes a gate stack formed on sidewalls and a top surface of the semiconductor fin. Since the FinFET has a three-dimensional channel structure, extra care is needed for ion implantation processes to the channel to reduce any geometric effects. SUMMARY

[0003] Some embodiments of the present invention provide a method of manufacturing a semiconductor device, comprising: forming a fin structure over a substrate; forming an isolation insulating layer over the substrate such that an upper portion of the fin structure protrudes from the isolation insulating layer; forming a first dielectric layer on the upper portion of the fin structure; forming a capping layer on the first dielectric layer; removing the capping layer from an upper portion of the upper portion of the fin structure having the first dielectric layer; removing the first dielectric layer from the upper portion of the fin structure; forming a second dielectric layer on the upper portion of the upper portion of the fin structure; and forming a gate electrode on the second dielectric layer and the first dielectric layer disposed on a lower portion of the upper portion of the fin structure.

[0004] Some embodiments of the present invention provide a method of manufacturing a semiconductor device, comprising: forming a first pair of fin structures over a substrate; forming an isolation insulating layer over the substrate such that upper portions of the first pair of fin structures protrude from the isolation insulating layer; forming a first dielectric layer on the upper portions of the first pair of fin structures; forming a capping layer on the first dielectric layer; partially removing the capping layer from upper portions of the upper portions of the first pair of fin structures having the first dielectric layer; removing the first dielectric layer from the upper portions of the first pair of fin structures; forming a second dielectric layer on the upper portions of the upper portions of the first pair of fin structures; and forming a gate electrode on the second dielectric layer and the first dielectric layer disposed on lower portions of the upper portions of the first pair of fin structures.

[0005] Yet another embodiment of the present invention provides a semiconductor device including: a fin structure disposed above a substrate; an isolation insulating layer from which an upper portion of the fin structure protrudes; a first dielectric layer disposed on a lower portion of the upper portion of the fin structure; a second dielectric layer disposed on an upper portion of the upper portion of the fin structure; and a gate electrode disposed above the first dielectric layer and the second dielectric layer, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the present invention can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various components can be arbitrarily increased or decreased for the sake of a discussion of clarity.

[0007] Figure 1 One of the various stages of a semiconductor device manufacturing process according to an embodiment of the present invention is shown.

[0008] Figure 2A And Figure 2B One of the various stages of a semiconductor device manufacturing process according to an embodiment of the present invention is shown.

[0009] Figure 3 One of the various stages of a semiconductor device manufacturing process according to an embodiment of the present invention is shown.

[0010] Figure 4A And Figure 4B One of the various stages of a semiconductor device manufacturing process according to an embodiment of the present invention is shown.

[0011] Figure 5A , Figure 5B And Figure 5C One of the various stages of a semiconductor device manufacturing process according to an embodiment of the present invention is shown.

[0012] Figure 6 One of the various stages of a semiconductor device manufacturing process according to an embodiment of the present invention is shown.

[0013] Figure 7 One of the various stages of a semiconductor device manufacturing process according to an embodiment of the present invention is shown.

[0014] Figure 8 One of the various stages of a semiconductor device manufacturing process according to an embodiment of the present invention is shown.

[0015] Figure 9 One of the various stages of a semiconductor device manufacturing process according to an embodiment of the present invention is shown.

[0016] Figure 10 One of the stages in a semiconductor device manufacturing process according to an embodiment of the application is shown.

[0017] Figure 11 One of the stages in a semiconductor device manufacturing process according to an embodiment of the application is shown.

[0018] Figure 12 One of the stages in a semiconductor device manufacturing process according to an embodiment of the application is shown.

[0019] Figure 13 One of the stages in a semiconductor device manufacturing process according to another embodiment of the application is shown.

[0020] Figure 14 One of the stages in a semiconductor device manufacturing process according to another embodiment of the application is shown.

[0021] Figure 15 One of the stages in a semiconductor device manufacturing process according to another embodiment of the application is shown.

[0022] Figure 16 One of the stages in a semiconductor device manufacturing process according to another embodiment of the application is shown.

[0023] Figure 17 One of the stages in a semiconductor device manufacturing process according to another embodiment of the application is shown.

[0024] Figure 18 One of the stages in a semiconductor device manufacturing process according to another embodiment of the application is shown.

[0025] Figure 19 One of the stages in a semiconductor device manufacturing process according to another embodiment of the application is shown.

[0026] Figure 20 One of the stages in a semiconductor device manufacturing process according to another embodiment of the application is shown.

[0027] Figure 21 One of the stages in a semiconductor device manufacturing process according to another embodiment of the application is shown.

[0028] Figure 22 One of the stages in a semiconductor device manufacturing process according to another embodiment of the application is shown. DETAILED DESCRIPTION

[0029] The following disclosure provides a number of different embodiments or examples for implementing different features of the present application. Specific examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, the dimensions of the elements can depend on the process conditions and / or desired characteristics of the device. Furthermore, in the following description, forming a first component over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components can be formed between the first component and the second component, such that the first component and the second component can not be in direct contact. For simplicity and clarity, various components can be shown in different proportions to one another in the drawings. In the following drawings, some layers / components can be omitted for simplicity.

[0030] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's or portion's relationship to another element, component or portion as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, the term "from" can mean "comprising" or "consisting of". Moreover, in the following description, one or more additional operations can be included in the process and the order of the operations can be changed. In the present application, the phrase "at least one of A, B and C" means any one of A, B, C, A+B, A+C, B+C or A+B+C, unless otherwise specified.

[0031] The disclosed embodiments relate to semiconductor devices, and in particular, to field effect transistors (FETs) and methods of manufacturing the same. Embodiments such as those disclosed herein are generally applicable not only to FinFETs, but also to other FETs.

[0032] In semiconductor devices, various transistors such as high current / power transistors and low power transistors are provided. For example, a FinFET with two (or more) fins provides higher drain current and power, but can sacrifice switching power and leakage current. On the other hand, a FinFET with one fin provides low power and low leakage, but it can require additional manufacturing processes, including one or more additional photolithography operations. The present application provides manufacturing operations for low power semiconductor devices.

[0033] Figures 1-12Various stages of a semiconductor device manufacturing process according to an embodiment of the present invention are illustrated. It should be understood that... Figures 1-12 Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated.

[0034] First, such as Figure 1 As shown, a fin structure 20 is formed over a substrate 10 using, for example, a patterning process. Depending on design requirements, the substrate 10 may include various doped regions (e.g., a p-type substrate or an n-type substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants such as boron or BF2; n-type dopants such as phosphorus or arsenic; and / or combinations thereof. The doped regions may be configured for n-type FinFETs, or optionally configured for p-type FinFETs.

[0035] In some embodiments, the substrate 10 is made of a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as group IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon carbide germanium (SiGeC), GeSn, SiSn, SiGeSn), group III-V compound semiconductors (e.g., gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GaInP)), etc. Furthermore, the substrate 10 may include an epitaxial layer (epi layer) which may be strained to improve performance, and / or may include a silicon-on-insulator (SOI) structure.

[0036] The fin structure 20 can be patterned using any suitable method. For example, the fin structure can be patterned using one or more photolithography processes, including dual patterning or multi-patterning processes. Typically, dual patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure. Multi-patterning processes combining photolithography and self-alignment processes typically enable the formation of fin structure pairs. Figure 1 The diagram shows three fin structures 20. However, the number of fin structures is not limited to three. In some embodiments, the fin structures 20 adjacent to the active FinFET form one or more pseudo-fin structures.

[0037] In some embodiments, the entire fin structure 20 is formed of crystalline silicon. In other embodiments, at least the channel region of the fin structure 20 includes SiGe, where the content of Ge is in the range of about 20 atomic % to 50 atomic %. When SiGe channels are employed, a SiGe epitaxial layer is formed on the substrate 10, and a patterning operation is performed. In some embodiments, one or more buffer semiconductor layers having a lower Ge concentration than the channel region are formed above the substrate 10.

[0038] After the fin structure is formed, an isolation insulating layer 30 (e.g., shallow trench isolation (STI)) is disposed above the fin structure 20 and the substrate 10. In some embodiments, one or more liner layers (not shown) are formed above the substrate 10 and the sidewalls of the bottom portion of the fin structure 20 prior to forming the isolation insulating region 30. In some embodiments, the liner layers include a first fin liner layer formed on the substrate 10 and the sidewalls of the bottom portion of the fin structure 20, and a second fin liner layer formed on the first fin liner layer. In some embodiments, each of the liner layers has a thickness between about 1 nm and about 20 nm. In some embodiments, the first fin liner layer includes silicon oxide and has a thickness between about 0.5 nm and about 5 nm, and the second fin liner layer includes silicon nitride and has a thickness between about 0.5 nm and about 5 nm. The liner layers can be deposited by one or more processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), although any acceptable process can be utilized.

[0039] The isolation insulating layer 30 includes one or more layers of insulating material, such as silicon dioxide, silicon oxynitride, and / or silicon nitride formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. In flowable CVD, a flowable dielectric material is deposited rather than silicon oxide. As the name implies, the flowable dielectric material can "flow" during deposition to fill gaps or spaces having a high aspect ratio. Typically, various chemicals are added to a silicon-containing precursor to allow the deposited film to flow. In some embodiments, a nitrogen-hydrogen bond is added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include silicates, siloxanes, methylsilsesquioxane (MSQ), hydrosilsesquioxane (HSQ), MSQ / HSQ, perhydrosilazane (TCPS), perhydro-polysilazane (PSZ), tetraethyl orthosilicate (TEOS), or silyl amines such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a number of operational processes. After the flowable film is deposited, the flowable film is cured and then annealed to remove undesirable elements to form silicon oxide. When the undesirable elements are removed, the flowable film densifies and shrinks. In some embodiments, multiple annealing processes are performed. The flowable film is cured and annealed more than once. The flowable film can be doped with boron and / or phosphorous. In some embodiments, the isolation insulating layer 130 is formed from one or more layers of SOG, SiO, SiON, SiOCN, and / or fluorine-doped silicate glass (FSG).

[0040] After the isolation insulating layer 30 is formed on the fin structures 20, a planarization operation is performed to remove a portion of the isolation insulating layer 30 and the mask layer (e.g., the pad oxide layer and the silicon nitride mask layer) used to pattern the fin structures. The planarization operation can include chemical mechanical polishing (CMP) and / or a etch-back process. Subsequently, portions of the isolation insulating layer 30 extending above the top surfaces of the fin structures 20 and portions of the pad layer located above the top surfaces of the fin structures 20 are removed using, for example, an etching process, chemical mechanical polishing (CMP), or the like. In addition, the isolation insulating layer 30 is recessed to expose the upper portions of the fin structures 20. In some embodiments, the isolation insulating layer 30 is recessed using a single etching process or multiple etching processes. In some embodiments where the isolation insulating layer 30 is made of silicon oxide, the etching process can be, for example, a dry etching, a chemical etching, or a wet cleaning process. In certain embodiments, a wet etching process can be used to perform the partial removal of the isolation insulating layer 30, for example, by immersing the substrate in hydrofluoric acid (HF). In another embodiment, a dry etching process can be used to perform the partial removal of the isolation insulating layer 30. For example, a dry etching process using CHF3or BF3as the etching gas can be used.

[0041] After the formation of the isolation insulating layer 30, a thermal process, such as an annealing process, can be implemented to improve the quality of the isolation insulating layer 30. In certain embodiments, the thermal process is implemented by using rapid thermal annealing (RTA) at a temperature of about 900 °C to about 1050 °C for about 1.5 seconds to about 10 seconds in an inert gas environment, such as N2, Ar, or He environment.

[0042] As shown in Figure 1 , the fin structures 20 extend in the X direction and are arranged at equal spacing P1 in the Y direction. In some embodiments, the width W1 of the fin structures 20 at this stage is in the range of about 5 nm to about 40 nm. In certain embodiments, the width W1 of the fin structures 20 is in the range of about 7 nm to about 15 nm. In some embodiments, the height H1 of the fin structures 20 measured from the upper surface of the isolation insulating layer 30 at this stage is in the range of about 50 nm to about 300 nm. In certain embodiments, the height H1 of the fin structures 20 is in the range of about 50 nm to about 100 nm. In some embodiments, the spacing P1 of the fin structures 20 is in the range of about 10 nm to about 90 nm. In certain embodiments, the width of the fin structures 20 is in the range of about 14 nm to about 45 nm. The spacing between the fin structures 20 is in some embodiments in the range of about 5 nm to about 80 nm, and in other embodiments can be in the range of about 7 nm to about 15 nm.

[0043] After the formation of the fin structures 20 and the isolation insulating layer 30, a sacrificial gate structure 40 including a sacrificial gate dielectric layer 41 and a sacrificial gate electrode layer 45 is formed over the exposed fin structures 20, which are to be subsequently used as channel layers, as shown in Figure 2A and Figure 2B . Figure 2A is a perspective view, and Figure 2B is a cross-sectional view corresponding to line a-a of Figure 2A along the Y direction.

[0044] The sacrificial gate dielectric layer 41 and the sacrificial gate electrode layer 45 are to be subsequently used to define and form source / drain regions. In some embodiments, the sacrificial gate dielectric layer 41 and the sacrificial gate electrode layer 45 are formed by deposition and patterning of a sacrificial gate dielectric layer and a dummy electrode layer formed over the exposed fin structures 20. The sacrificial gate dielectric layer 41 can be formed by thermal oxidation, CVD, sputtering, or any other method of forming a sacrificial gate dielectric layer known and used in the art. In some embodiments, the sacrificial gate dielectric layer 41 can be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, SiCN, SiON, and SiN, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, polymers such as polyimides, etc., or combinations thereof. In one embodiment, SiO2 is used.

[0045] Subsequently, a sacrificial gate electrode layer 45 is formed over the sacrificial gate dielectric layer. In some embodiments, the sacrificial gate electrode layer is an electrically conductive material and is selected from the group including amorphous silicon, polysilicon, amorphous germanium, polysilicon germanium, amorphous silicon germanium, polysilicon germanium, metal nitride, metal silicide, metal oxide, and metal. The sacrificial gate electrode layer can be deposited by PVD, CVD, sputter deposition, or other techniques known and used in the art for depositing electrically conductive materials. Other materials, both electrically conductive and non-conductive, can be used. In one embodiment, polysilicon is used.

[0046] A mask pattern can be formed over the sacrificial gate electrode layer 45 to assist in patterning. The mask pattern includes a first mask layer and a second mask layer disposed on the first mask layer. The mask pattern includes one or more layers of SiO2, SiCN, SiON, aluminum oxide, silicon nitride, or other suitable materials. In some embodiments, the first mask layer includes silicon nitride or SiON and the second mask layer includes silicon oxide. The dummy electrode layer is patterned into the sacrificial gate electrode 45 by using the mask pattern as an etch mask. In some embodiments, the dielectric layer is also patterned to define the sacrificial gate dielectric layer. The fin structure 20 extends in an X-direction and the sacrificial gate structure 40 extends in a Y-direction substantially perpendicular to the X-direction. In Figure 2A and Figure 2B In

[0047] In addition, as shown in Figure 2A spacers 47 are formed on the opposing sidewalls of the sacrificial gate structure 40. The sidewall spacers 47 include one or more dielectric layers. In one embodiment, the sidewall spacers 47 are made of one or more of silicon oxide, silicon nitride, SiOCN, SiCN, aluminum oxide, AlCO, or AlCN, or any other suitable dielectric material. A blanket layer of sidewall insulating material can be formed by CVD, PVD, ALD, or other suitable techniques. An anisotropic etch is then performed on the sidewall insulating material to form a pair of sidewall insulating layers (spacers) 47 on the two major sides of the gate structure. In some embodiments, the thickness of the sidewall insulating layers 47 is in the range of about 5 nm to about 30 nm, while in other embodiments, in the range of about 10 nm to about 20 nm.

[0048] Subsequently, the source / drain regions of the fin structure 20 are recessed down below the upper surface of the isolation insulating layer 30. A source / drain epitaxial layer 60 is then formed over the recessed source / drain regions of the fin structure 20, as shown in Figure 3 In some embodiments, the source / drain epitaxial layer 60 is a p-type or n-type doped epitaxial layer. In one embodiment, the source / drain epitaxial layer 60 is a p-type doped epitaxial layer of silicon germanium. In another embodiment, the source / drain epitaxial layer 60 is an n-type doped epitaxial layer of silicon germanium. Figure 3The merged epitaxial layer is shown. In other embodiments, the source / drain epitaxial layer 60 is formed separately over the recessed fin structures 20 without merging adjacent source / drain epitaxial layers.

[0049] For n-type and p-type FinFETs, the material used for the source / drain epitaxial layer 60 can vary such that one type of material is used for n-type FinFETs to impart tensile stress in the channel region and another material is used for p-type FinFETs to impart compressive stress. For example, SiP or SiC can be used to form n-type FinFETs and SiGe or Ge can be used to form p-type FinFETs. In some embodiments, boron (B) is doped in the source / drain epitaxial layer for p-type FinFETs. Other materials can be used. In some embodiments, the source / drain epitaxial layer 60 includes two or more epitaxial layers with different compositions and / or different dopant concentrations. The source / drain epitaxial layer 60 can be formed by CVD, ALD, molecular beam epitaxy (MBE), or any other suitable method.

[0050] After forming the source / drain epitaxial layer 60, an interlayer dielectric (ILD) layer 50 is formed. In some embodiments, prior to forming the ILD layer, an etch stop layer (ESL) is formed over the source / drain epitaxial layer 60 and the sidewall spacers 47. The ESL is made of silicon nitride or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). The material used for the ILD layer 50 includes Si, O, C, and / or H containing compounds such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 50.

[0051] After forming the ILD layer 50, a planarization operation such as an etch-back process and / or a chemical mechanical polishing (CMP) process is implemented to expose the upper surface of the sacrificial gate electrode layer 45, as shown in Figure 4A and Figure 4B . Figure 4A is a cross-sectional view along the X-direction, and Figure 4B is a cross-sectional view along the Y-direction. In Figure 4B and Figure 5B , only two fin structures 20 are shown for simplicity.

[0052] Then, the sacrificial gate electrode layer 45 is removed, as shown in Figure 5A and Figure 5B , thereby forming gate spacers 49. When the sacrificial gate electrode layer 45 is polysilicon and the ILD layer 50 is silicon oxide, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode.

[0053] Figure 5CThe structure after removal of the sacrificial gate electrode layer 45 is shown. In some embodiments, the semiconductor device includes a first circuit (e.g., core circuit) and a second circuit (e.g., I / O circuit or peripheral circuit) formed on the same substrate 10. The first circuit requires different power consumption and / or current driving capability compared to the second circuit. In some embodiments, the first circuit requires lower power consumption and / or current driving capability compared to the second circuit. In some embodiments, the size of the fin structure 20 for the first circuit and the second circuit is the same, and in other embodiments, the size of the fin structure 20 for the first circuit is smaller than the size of the fin structure for the second circuit. In some embodiments, the thickness T1 of the sacrificial gate dielectric layer 41 is in a range from about 0.2 nm to about 4 nm, and in other embodiments, in a range from about 0.3 nm to about 3 nm.

[0054] Figure 6 One of the various stages of a semiconductor device manufacturing process according to an embodiment of the present application is shown. After removal of the sacrificial gate electrode layer 45, a capping layer 100 is formed over the sacrificial gate dielectric layer 41. In some embodiments, the capping layer 100 is formed by applying hexamethyldisilazane (HMDS) vapor. In some embodiments, the HMDS reacts with Si-OH groups on the surface of the sacrificial gate dielectric layer 41 to convert Si-OH to Si-OCH3. Thus, in some embodiments, a monolayer of Si-OCH3 is formed as the capping layer 100.

[0055] In some embodiments, the HMDS coating operation includes a series of vacuum and inert gas flushing operations. For example, in some embodiments, a vacuum is applied to the deposition chamber. In some embodiments, the pressure in the chamber is reduced to about 10 Torr or less over a period of about 30 seconds to about 5 minutes. An inert gas, such as nitrogen, is then introduced into the deposition chamber, thereby increasing the pressure to about 760 Torr. In some embodiments, the pressure of the inert gas is maintained at about 760 Torr for about 1 minute to about 10 minutes. The vacuum is then again applied for a period of about 30 seconds to about 5 minutes to a pressure of about 10 Torr or less, followed by the introduction of the inert gas to increase the pressure to about 760 Torr. In some embodiments, the operations of applying a vacuum and flushing with an inert gas are repeated multiple times. The application of the vacuum and the flushing operations remove moisture and oxygen from the chamber. Prior to the introduction of the HMDS, a vacuum of about 1 Torr or less is applied for a period of about 30 seconds to about 5 minutes. The HMDS is then introduced into the chamber to a pressure of about 2 Torr to about 20 Torr. In some embodiments, the pressure of the HMDS in the chamber is about 5 Torr to about 10 Torr. In some embodiments, the HMDS is applied for a period of about 1 minute to about 20 minutes. In some embodiments, the chamber is heated to a temperature of about 125 °C to about 200 °C during the application of the HMDS to the sacrificial gate dielectric layer 41. In some embodiments, the substrate 10 is heated to a temperature of about 125 °C to about 200 °C during the application of the HMDS by placing the substrate 10 on a heated platen. In some embodiments, the substrate 10 is heated to about 150 °C. In some embodiments, after the application of the HMDS, the chamber is purged by additional alternating vacuum application and inert gas flushing operations. When the deposition operation is complete, the chamber is backfilled with inert gas, and the substrate 10 can be removed from the chamber. The application of the HMDS is not limited to the operations described above and other methods. In some embodiments, the HMDS is applied to the surface of the sacrificial dielectric layer 41 under atmospheric pressure in an inert gas filled chamber.

[0056] In some embodiments, the HMDS undergoes an alkylation reaction with the wafer surface in the chamber. For example, in some embodiments, when the sacrificial gate dielectric layer 41 is silicon oxide, the HMDS reacts with the hydroxyl groups (Si-OH) on the surface of the sacrificial gate dielectric layer 41 and introduces alkyl (methyl) groups (Si-O-CH3) on the surface of the sacrificial gate dielectric layer 41. In other embodiments, the monolayer includes a polymer containing C, H, O, and N. After the application of the HMDS, the substrate 10 is cooled.

[0057] In some embodiments, the thickness T2 of the capping layer 100 is in a range of about 0.05 nm to about 2 nm, and in other embodiments in a range of about 0.1 nm to about 0.5 nm.

[0058] In some embodiments, the capping layer 100 is made of another organic material including a polymer. In other embodiments, the capping layer 100 is made of a dielectric material different from the sacrificial gate dielectric layer 41. In certain embodiments, the capping layer 100 is made of silicon nitride formed by ALD.

[0059] Figure 7 One of the various stages of a semiconductor device manufacturing process according to embodiments of the present application is shown. A photoresist is coated on the capping layer 100 and the photoresist is patterned by using one or more photolithography operations to form the protective layer 110. In some embodiments, the substrate 10 coated with the photoresist is soft-baked at a temperature of about 40 °C to about 150 °C for about 10 seconds to about 10 minutes to remove the photoresist solvent prior to the actinic radiation exposure. In other embodiments, the capping layer 100 is formed prior to forming the protective layer 110.

[0060] Figure 8 One of the various stages of a semiconductor device manufacturing process according to embodiments of the present application is shown. A portion of the capping layer 100 disposed at the upper portion of the fin structure 20 covered with the sacrificial dielectric layer 41 is removed by using one or more etching operations. In some embodiments, an oxygen plasma or other plasma generated from an oxygen-containing gas (oxygen-based plasma) is used. The capping layer 100 is removed from the top of the fin structure when the input power and the flow rate of the oxygen or oxygen-containing gas are low. In some embodiments, in the etching, the input power is in the range of about 100 W to about 800 W, the pressure is in the range of about 5 mTorr to about 60 mTorr, and the substrate temperature is in the range of 25 °C to about 60 °C.

[0061] In some embodiments, the remaining height H3 of the capping layer 100 is about 30% to about 70% of the height H2 of the top of the sacrificial gate dielectric layer 41 above the fin structure 20 measured from the upper surface of the isolation insulating layer 30.

[0062] In other embodiments, the gate spacing is filled with a material different from the sacrificial gate dielectric layer 41 and the interlayer dielectric layer 50, and an etch-back operation is performed to reduce the thickness of the fill material to expose the upper portion of the fin structure 20 covered with the sacrificial dielectric layer 41. Then, the capping layer 100 is removed, and the fill material is removed.

[0063] Figure 9 One of the various stages of a semiconductor device manufacturing process according to embodiments of the present application is shown. After the capping layer 100 is partially removed, the exposed sacrificial gate dielectric layer 41 is removed to expose the upper portion of the fin structure 20, as Figure 9The height H5 of the exposed upper portion (upper portion of the upper portion) of the fin structure is about 30% to about 70% of the height H4 of the fin structure 20 (upper portion) measured from the upper surface of the isolation insulating layer 30. In other embodiments, the height H5 is about 40% to about 60% of the height H4.

[0064] Figure 10 One of the various stages of a semiconductor device manufacturing process according to embodiments of the present application is shown. Subsequently, the remaining protective layer 110 is removed, and the capping layer 100 is further removed. In some embodiments, when the capping layer 100 is made of HMDS, the photoresist layer 110 and the capping layer 100 are removed by an oxygen-based plasma. Figure 10

[0065] Figure 11 One of the various stages of a semiconductor device manufacturing process according to embodiments of the present application is shown. Subsequently, the fin structure 20 is further oxidized with the sacrificial gate dielectric layer 41 to form an interface dielectric layer 43. In some embodiments, the interface dielectric layer 43 is formed using one or more of a thermal oxidation process, a plasma oxidation process, and / or a chemical oxidation process. In some embodiments, the process temperature of the thermal oxidation is in the range from about 500 °C to about 800 °C. In some embodiments, the process temperature of the plasma oxidation is in the range from about 300 °C to about 500 °C. The chemical oxidation can be implemented using deionized water + ozone (DIO3), NH4OH + H2O2+ H2O (APM), or other methods. In some embodiments, due to the oxidation operation, the exposed portion of the fin structure becomes thinner after the oxidation operation than before. In one side of the fin structure, the amount of thinning is about 0.1 nm to about 0.5 nm. In some embodiments, the thinning creates a step in the fin structure.

[0066] In other embodiments, the interface layer 43 is formed by a deposition method such as CVD and ALD. In this case, the interface layer 43 is formed on the remaining sacrificial layer 41.

[0067] ​In some embodiments, the thickness T3 of the interface dielectric layer 43 is in the range of about 0.2 nm to about 3.0 nm, and in other embodiments, in the range of about 0.3 nm to about 1.5 nm. In some embodiments, the thickness T4 (>T3) of the remaining sacrificial gate dielectric layer 41 in the first circuit is in the range of about 0.4 nm to about 4 nm, and in other embodiments, in the range of about 1 nm to about 3 nm. In some embodiments, the thickness T5 of the sacrificial gate dielectric layer 41 in the second circuit is in the range of about 0.2 nm to about 4 nm, and in other embodiments, in the range of about 0.3 nm to about 3 nm. In some embodiments, T4 is equal to T5, and in other embodiments, T4 is different from T5, i.e., T4>T5 or T4

[0068] Figure 12 One of the various stages of a semiconductor device manufacturing process according to embodiments of the present application is shown. In some embodiments, the interface layer 43 and the sacrificial gate dielectric layer 41 serve as the gate dielectric layer of the FET. In some embodiments, the interface layer 43 is removed, and the sacrificial gate dielectric layer 41 is thinned. Subsequently, a gate electrode 65 is formed over the gate dielectric layer. In some embodiments, one or more work function adjustment layers 66 are formed, and a main metal layer 68 is formed over the work function adjustment layer 66. The work function adjustment layer 66 is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For n-channel FinFETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for p-channel FinFETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer.

[0069] In some embodiments, one or more additional conductive layers are formed over the gate dielectric layer, such as a barrier layer made of Ti, Ta, TiN, TiSiN, and / or TaN.

[0070] In some embodiments, the main metal layer 68 includes a metallic material selected from the group consisting of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr. In some embodiments, the main metal layer 68 includes a metal selected from the group consisting of TiN, WN, TaN, and Ru. Metal alloys such as Ti-Al, Ru-Ta, Ru-Zr, Pt-Ti, Co-Ni, and Ni-Ta can be used, and / or alloys such as WN xTiN x MoN x TaN x and TaSi x N y Metal nitrides of N, Ti, Mo, Ta, and TaSi can be used. Suitable processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plating, or combinations thereof can be used to form the work function adjustment layer and the main metal layer.

[0071] As shown in Figure 12 , the dielectric layer covering the upper portions of the fin structures 20 over the isolation insulating layer 30 has a double U-shape, including an upper U-shape formed by the dielectric layer 43 and a lower U-shape formed by the sacrificial gate dielectric layer 41 between the adjacent two fin structures 20. In some embodiments, due to the double U-shape, a recess or indented portion is formed in the work function adjustment layer 66 (and the main metal layer 68) between the fin structures 20 in the first circuit, as shown in Figure 12 .

[0072] Figures 13-14 Various stages of a semiconductor device fabrication process according to another embodiment of the present application are shown. In the following embodiment, one or more high-k dielectric layers are formed on the sacrificial gate dielectric layer 41 to form a gate dielectric layer, and the remaining sacrificial gate dielectric layer 41 in the core first circuit and the sacrificial gate dielectric layer 41 in the second circuit serve as part of the gate dielectric layer.

[0073] As shown in Figure 13 , a high-k dielectric layer 62 is formed on the sacrificial gate dielectric layer 41. The high-k gate dielectric layer 62 includes one or more layers of Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, a hafnium oxide-aluminum oxide (Hf02- Al203) alloy, other suitable high-k dielectric materials. The gate dielectric layer 62 can be formed by CVD, ALD, or any suitable method. In some embodiments, the thickness of the high-k dielectric layer 62 is in the range of about 1 nm to about 6 nm. As shown in Figure 14 , a gate electrode 65 is then formed over the high-k dielectric layer.

[0074] It should be appreciated that the FinFET is subjected to further CMOS processes to form various components, such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0075] Figures 15-22 Various stages of a semiconductor device fabrication process according to another embodiment of the present application are shown. It should be appreciated that the process can be performed in a manner similar to that described above with respect to the first embodiment. Figures 15-22The illustrated process is preceded, during, and followed by additional operations, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of operations / processes can be interchanged. In the following embodiments, materials, processes, configurations, dimensions, and / or operations described in the foregoing embodiments can be employed, and detailed descriptions thereof can be omitted.

[0076] In the following embodiments, the capping layer 100 is formed prior to forming the sacrificial gate electrode 45 over the fin structures 20.

[0077] After the fin structures 20 are formed as shown in Figure 1 , a sacrificial gate dielectric layer 141 is formed over the exposed fin structures 20, as shown in Figure 15 . The sacrificial gate dielectric layer 141 can be formed in the same manner as the sacrificial gate dielectric layer 41.

[0078] The capping layer 100 is then formed by using similar or identical operations as described with reference to Figures 6-8 . As shown in Figure 16 , the capping layer 100 (e.g., remaining HMDS) covers the bottom portions of the upper portions of the fin structures 20 in the first circuit, and completely covers the upper portions of the fin structures 20 in the second circuit. The protective layer 110 is removed in the second circuit (see Figure 7 ).

[0079] Subsequently, a sacrificial gate electrode layer 145 is formed over the fin structures with the capping layer 100 and the sacrificial gate dielectric layer 141, as shown in Figure 17 . The sacrificial gate electrode layer 145 can be formed in the same manner as the sacrificial gate electrode layer 145. In addition, sidewall spacers are also formed on opposite sides of the sacrificial gate electrode layer 145. Furthermore, the source / drain epitaxial layers 60 are formed by using similar or identical operations as described with reference to Figure 3 .

[0080] After the source / drain epitaxial layers 60 are formed, the sacrificial gate electrode layer 145 is removed by using similar or identical operations as described with reference to Figures 5A-5C , thereby forming gate spacers 149, as shown in Figure 18 .

[0081] The protective layer 110 is then formed by using similar or identical operations as described with reference to Figure 8 , as shown in Figure 19 . In addition, the exposed sacrificial gate dielectric layer 141 is removed to expose the upper portions of the fin structures 20 by using similar or identical operations as described with reference to Figure 9 , as shown in Figure 20 .

[0082] Subsequently, the source / drain epitaxial layers 60 are formed by using similar or identical operations as described with reference to Figure 10Similar or identical operations as described above are performed to remove the remaining protective layer 110 and further remove the capping layer 100, as shown in Figure 21 Figure 11 Using similar or identical operations as described above, the fin structure 20 can be further oxidized with the sacrificial gate dielectric layer 141 to form the interface dielectric layer 43, as shown in Figure 22 Figures 12-14 A metal gate electrode is then formed.

[0083] In the present disclosure, the FinFET for the first circuit has a thin gate dielectric layer 43 at the upper portion of the fin structure above the isolation insulating layer 30 and a thick gate dielectric layer 41 at the bottom portion of the fin structure. The effective channel region is the upper portion of the fin structure 20 in the first circuit. Therefore, the FinFET in the first circuit has low power consumption and low current leakage compared to the FinFET with a uniform thin gate dielectric layer (with a higher fin structure above the isolation insulating layer).

[0084] As described above, a multiple patterning process in combination with photolithography and self-alignment process typically forms a pair of fin structures. In some embodiments, a pair of fin structures (two fin structures) is used for one FinFET. If the FinFET includes one fin structure, one of the pair of fin structures is removed, which requires a fine photolithography and etching operation. In some embodiments, one circuit (e.g., a core circuit) requires lower power consumption and lower current driving capability than other circuits (e.g., an I / O region). In this case, one circuit uses a FinFET with one fin structure, while another circuit uses a FinFET with two (or more) fin structures. However, as described above, forming a FinFET with one fin structure requires one or more additional fin photolithography and etching operations.

[0085] According to embodiments of the present disclosure, similar to the FinFET with one fin structure, a FinFET with lower power consumption and lower current driving capability can be implemented by a pair of fin structures with a shorter channel height (H5), as shown in Figure 10 When the height H5 is about 30-70% or 40-60% of the height H4, Figure 12 or Figure 14 The current driving capability of the FinFET shown in

[0086] It should be understood that not all advantages are discussed herein, not all of which need to be, and other embodiments or examples can provide different advantages. ​​

[0087] According to aspects of the present application, in a method for manufacturing a semiconductor device, a fin structure is formed over a substrate, an isolation insulating layer is formed over the substrate so that an upper portion of the fin structure protrudes from the isolation insulating layer, a first dielectric layer is formed on the upper portion of the fin structure, a capping layer is formed on the first dielectric layer, the capping layer is removed from an upper portion of the upper portion of the fin structure having the first dielectric layer, the first dielectric layer is removed from the upper portion of the upper portion of the fin structure, a second dielectric layer is formed on the upper portion of the upper portion of the fin structure, and a gate electrode is formed on the second dielectric layer and the first dielectric layer disposed on a lower portion of the upper portion of the fin structure. In one or more of the foregoing or following embodiments, the first dielectric layer is formed by a deposition method. In one or more of the foregoing or following embodiments, the second dielectric layer is formed by an oxidation method. In one or more of the foregoing or following embodiments, a thickness of the first dielectric layer is in a range of 0.4 nm to 4 nm. In one or more of the foregoing or following embodiments, a thickness of the second dielectric layer is less than the thickness of the first dielectric layer. In one or more of the foregoing or following embodiments, the thickness of the first dielectric layer is in a range of 0.2 nm to 1.0 nm. In one or more of the foregoing or following embodiments, the capping layer is formed by applying hexamethyldisilazane on the first dielectric layer. In one or more of the foregoing or following embodiments, the capping layer is a monolayer of an organic material. In one or more of the foregoing or following embodiments, a high-k dielectric layer is formed on the first and second dielectric layers before forming the gate electrode. In one or more of the foregoing or following embodiments, after the capping layer is partially removed, a height of the remaining capping layer is 30% to 70% of a height of the upper portion of the fin structure measured from an upper surface of the isolation insulating layer.

[0088] According to another aspect of the present application, in a method of manufacturing a semiconductor device, a first pair of fin structures is formed over a substrate, an isolation insulating layer is formed over the substrate so that upper portions of the first pair of fin structures protrude from the isolation insulating layer, a first dielectric layer is formed on the upper portions of the first pair of fin structures, a cover layer is formed on the first dielectric layer, the cover layer is partially removed from an upper portion of the upper portions of the first pair of fin structures having the first dielectric layer, the first dielectric layer is removed from the upper portion of the upper portions of the first pair of fin structures, a second dielectric layer is formed on the upper portion of the upper portions of the first pair of fin structures, and a gate electrode is formed on the second dielectric layer and the first dielectric layer provided on a lower portion of the upper portions of the first pair of fin structures. In one or more of the foregoing or following embodiments, the cover layer is formed by applying hexamethyldisilazane on the first dielectric layer. In one or more of the foregoing or following embodiments, the cover layer is a single layer of an organic material. In one or more of the foregoing or following embodiments, the second dielectric layer is formed by an oxidation method. In one or more of the foregoing or following embodiments, the cover layer is removed after the first dielectric layer is removed from the upper portion of the upper portions of the first pair of fin structures. In one or more of the foregoing or following embodiments, the cover layer is removed by using an oxygen-containing plasma.

[0089] According to another aspect of the present application, in a method of manufacturing a semiconductor device, a first pair of fin structures and a second pair of fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate so that upper portions of the first pair of fin structures and upper portions of the second pair of fin structures protrude from the isolation insulating layer, a first dielectric layer is formed on the upper portions of the first pair of fin structures and the upper portions of the second pair of fin structures, a cover layer is formed on the first dielectric layer, the cover layer is removed from an upper portion of the upper portions of the first pair of fin structures having the first dielectric layer, the first dielectric layer is removed from the upper portion of the upper portions of the first pair of fin structures, a second dielectric layer is formed on the upper portion of the upper portions of the first pair of fin structures, a first gate electrode is formed on the second dielectric layer and the first dielectric layer provided on a lower portion of the upper portions of the first pair of fin structures, and a second gate electrode is formed on the first dielectric layer of the second pair of fin structures. In one or more of the foregoing or following embodiments, a protective layer is formed to cover the second pair of fin structures before the cover layer is partially removed, and the protective layer is removed after the first dielectric layer is removed from the upper portion of the upper portions of the first pair of fin structures. In one or more of the foregoing or following embodiments, the cover layer is removed after the first dielectric layer is removed from the upper portion of the upper portions of the first pair of fin structures. In one or more of the foregoing or following embodiments, the cover layer is formed before the protective layer is formed.

[0090] According to an aspect of the present application, a semiconductor device includes: a fin structure disposed above a substrate; an isolation insulating layer, an upper portion of the fin structure protruding from the isolation insulating layer; a first dielectric layer disposed on a lower portion of the upper portion of the fin structure; a second dielectric layer disposed on an upper portion of the upper portion of the fin structure; and a gate electrode disposed above the first and second dielectric layers. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. In one or more of the above or below embodiments, the thickness of the second dielectric layer is 0.2 nm to 1.0 nm. In one or more of the above or below embodiments, the thickness of the first dielectric layer is 0.4 nm to 4.0 nm. In one or more of the above or below embodiments, at least the upper portion of the fin structure includes SiGe. In one or more of the above or below embodiments, a height of the upper portion of the upper portion is 30% to 70% of a height of the upper portion of the fin structure measured from an upper surface of the isolation insulating layer. In one or more of the above or below embodiments, the first and second dielectric layers are made of silicon oxide. In one or more of the above or below embodiments, the semiconductor device further includes a high-k dielectric layer disposed on the first and second dielectric layers.

[0091] According to another aspect of the present application, a semiconductor device includes: a pair of fin structures disposed above a substrate; an isolation insulating layer; upper portions of the pair of fin structures protruding from the isolation insulating layer; a first dielectric layer disposed on lower portions of the upper portions of the pair of fin structures; a second dielectric layer disposed on upper portions of the upper portions of the pair of fin structures; and a gate electrode disposed above the first and second dielectric layers of the pair of fin structures. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. In one or more of the above or below embodiments, the thickness of the second dielectric layer is 0.3 nm to 0.8 nm. In one or more of the above or below embodiments, the thickness of the first dielectric layer is 1.0 nm to 3.0 nm. In one or more of the above or below embodiments, a height of the upper portion of the upper portion is 40% to 60% of a height of the upper portion of the fin structure measured from an upper surface of the isolation insulating layer. In one or more of the above or below embodiments, the first and second dielectric layers are made of silicon oxide. In one or more of the above or below embodiments, the semiconductor device further includes a high-k dielectric layer disposed on the first and second dielectric layers.

[0092] According to another aspect of the present application, a semiconductor device includes a pair of first and second fin structures disposed above a substrate; an isolation insulating layer; an upper portion of the first fin structure and an upper portion of the second fin structure of the pair protrude from the isolation insulating layer; a first dielectric layer disposed on a lower portion of the upper portion of the first fin structure of the pair; a second dielectric layer disposed on an upper portion of the upper portion of the first fin structure of the pair, a third dielectric layer disposed on the upper portion of the second fin structure; a first gate electrode disposed above the first and second dielectric layers of the pair of fin structures; and a second gate electrode disposed above the third dielectric layer of the second fin structure. The second dielectric layer has a thickness that is less than a thickness of the first dielectric layer. In one or more of the foregoing or following embodiments, the second dielectric layer has a thickness that is less than a thickness of the third dielectric layer. In one or more of the foregoing or following embodiments, the second dielectric layer has a thickness of 0.3 nm to 0.8 nm. In one or more of the foregoing or following embodiments, the first dielectric layer has a thickness of 1.0 nm to 3.0 nm. In one or more of the foregoing or following embodiments, the upper portion has a height of the upper portion that is 40% to 60% of a height of the upper portion of the first fin structure measured from an upper surface of the isolation insulating layer. In one or more of the foregoing or following embodiments, the first, second, and third dielectric layers are made of silicon oxide. In one or more of the foregoing or following embodiments, the semiconductor device further includes a high-k dielectric layer disposed on the first and second dielectric layers and on the third dielectric layer.

[0093] The features outlined herein facilitate an understanding of aspects of the application by persons of ordinary skill in the art. Those skilled in the art will readily understand that the present application can be varied in many ways and that the application can be applied to other fields of endeavor with modifications that those skilled in the art will readily suggest. Those skilled in the art will further appreciate that the disclosure is by way of example only and is not intended to limit the scope of the application.

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a first fin structure and a second fin structure over a substrate; forming an isolation insulating layer over the substrate such that upper portions of the first fin structure and the second fin structure protrude from the isolation insulating layer, and lower portions of the first fin structure and the second fin structure are embedded in the isolation insulating layer; forming a first dielectric layer on the upper portions of the first fin structure and the second fin structure after forming the isolation insulating layer; forming a capping layer on the first dielectric layer; removing the capping layer from an upper portion of the upper portion of the first fin structure having the first dielectric layer; removing the first dielectric layer from the upper portion of the upper portion of the first fin structure; forming a second dielectric layer on the upper portion of the upper portion of the first fin structure; and forming a gate electrode on the second dielectric layer and the first dielectric layer, lower portions of the upper portions of the first fin structure and the second fin structure being located above an upper surface of the isolation insulating layer, wherein the first dielectric layer is disposed on the lower portion of the upper portion of the first fin structure and on the lower portion and the upper portion of the upper portion of the second fin structure, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer disposed on the first fin structure and the second fin structure, wherein the upper portion of the upper portion is 40-60% of a height of the upper portion of the first fin structure and the second fin structure measured from the upper surface of the isolation insulating layer to an uppermost surface of the first fin structure and the second fin structure. The first dielectric layer is formed by a deposition method.

2. The method of claim 1, wherein, The second dielectric layer is formed by an oxidation method.

3. The method of claim 1, wherein, The thickness of the first dielectric layer is in a range of 0.4 nm to 4 nm.

4. The method of claim 1, wherein, The gate electrode includes a work function adjusting layer.

5. The method of claim 1, wherein, The thickness of the second dielectric layer is in a range of 0.2 nm to 1.0 nm.

6. The method of claim 5, wherein, The capping layer is formed by applying hexamethyldisilazane on the first dielectric layer.

7. The method of claim 1, wherein, The capping layer is a monolayer of an organic material.

8. The method of claim 7, wherein, A high-k dielectric layer is formed on the first dielectric layer and the second dielectric layer before forming the gate electrode.

9. The method of claim 1, wherein, The thickness of the second dielectric layer is 0.2 nm to 1.0 nm.

10. The method of claim 1, wherein, 11. A method of manufacturing a semiconductor device, comprising: forming a first pair of fin structures and a second pair of fin structures over a substrate; forming an isolation insulating layer over the substrate such that upper portions of the first pair of fin structures and the second pair of fin structures protrude from the isolation insulating layer, and lower portions of the first pair of fin structures and the second pair of fin structures are embedded in the isolation insulating layer; forming a first dielectric layer on the upper portions of the first pair of fin structures and the second pair of fin structures after forming the isolation insulating layer; forming a capping layer on the first dielectric layer; partially removing the capping layer from an upper portion of the upper portion of the first pair of fin structures such that a lower portion of the upper portion of the first pair of fin structures remains above an upper surface of the isolation insulating layer; removing the first dielectric layer from the upper portion of the upper portion of the first pair of fin structures; forming a second dielectric layer on the upper portion of the upper portion of the first pair of fin structures; and ​ ​ forming a gate electrode over the second dielectric layer and the first dielectric layer, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer disposed over the first pair of fin structures and the second pair of fin structures, 12. The method of claim 11, wherein, wherein a height of the upper portion of the upper portion of the upper portion of the first pair of fin structures and the second pair of fin structures is 30-70% of a height of the upper portion of the first pair of fin structures and the second pair of fin structures measured from an upper surface of the isolation insulating layer to an uppermost surface of the first pair of fin structures and the second pair of fin structures.

13. The method of claim 12, wherein, the capping layer is formed by applying hexamethyldisilazane over the first dielectric layer.

14. The method of claim 12, wherein, the capping layer is a single layer of an organic material. the second dielectric layer is formed by an oxidation method.

16. The method of claim 15, wherein, 15. The method of claim 12, further comprising, after removing the first dielectric layer from the upper portion of the upper portion of the first pair of fin structures, further removing the remaining capping layer. the remaining capping layer is removed by using an oxygen-containing plasma.

17. A semiconductor device, comprising: a first pair of fin structures and a second pair of fin structures disposed over a substrate; an isolation insulating layer, an upper portion of the first pair of fin structures and the second pair of fin structures protruding from the isolation insulating layer, a lower portion of the first pair of fin structures and the second pair of fin structures embedded within the isolation insulating layer, wherein the upper portion of the first pair of fin structures and the second pair of fin structures includes an upper portion sidewall and a lower portion sidewall; a first dielectric layer disposed on the lower portion sidewall of the upper portion of the first pair of fin structures and on the lower portion sidewall and the upper portion sidewall of the upper portion of the second pair of fin structures; a second dielectric layer disposed on the upper portion sidewall of the upper portion of the first pair of fin structures; and a gate electrode disposed over the first dielectric layer and the second dielectric layer, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer disposed over the first pair of fin structures and the second pair of fin structures, 18. The semiconductor device of claim 17, wherein, wherein a height of the upper portion sidewall of the upper portion of the first pair of fin structures and the second pair of fin structures is 40-60% of a height of the upper portion of the first pair of fin structures and the second pair of fin structures measured from an upper surface of the isolation insulating layer to an uppermost surface of the first pair of fin structures and the second pair of fin structures.

19. The semiconductor device of claim 17, wherein, the thickness of the second dielectric layer is 0.2 nm to 1.0 nm.

20. The semiconductor device of claim 17, wherein, the thickness of the first dielectric layer is 0.4 nm to 4.0 nm. at least an upper portion of the first pair of fin structures includes SiGe.

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