Co-integration of iii-v devices with iv devices

Abstract

In a first aspect, the present invention relates to a method comprising: (a) providing Si x Ge 1‑x (100) Substrate (10), where x is 0-1; (b) Selecting a first region (21) for forming a group IV device (50) therein and a second region (22) for forming a III-V device (80) therein, the first region and the second region (22) each comprising Si x Ge 1‑x (100) A portion of the substrate (10); (c) Forming a trench isolation (30) for at least the III-V device (80); (d) Providing Si in the first region (21) y Ge 1‑y (100) Surface (15), where y is 0 to 1; (e) Si in the first region (21) y Ge 1‑y (100) A group IV device (50) is formed at least partially on the surface (15); (f) An exposed Si is formed in the second region (22). x Ge 1‑x (100) The trench (60) of the substrate (10) relative to the Si in the first region (21) y Ge 1‑y (100) Surface (15), trench (60) having a depth of at least 200 nm, preferably at least 500 nm, more preferably at least 1 μm, most preferably at least 2 μm, for example 4 μm; (g) using aspect ratio capture to grow III-V material (71, 72) in trench (60); and (h) forming III-V device (80) on III-V material (71, 72), III-V device (80) including at least one contact region (83), the height of which differs from the height of contact region (53) of group IV device (50) by less than 100 nm, preferably less than 50 nm, more preferably less than 20 nm, most preferably less than 10 nm.

Description

TECHNICAL FIELD

[0001] The present invention relates to the co-integration of III-V devices with Group IV devices, and more specifically to such integration on Si x Ge 1-x substrates. BACKGROUND

[0002] III-V materials (e.g. GaAs, InGaAs or InP) generally exhibit higher electron mobility and saturation velocity compared to Group IV materials (e.g. Si or Ge). As a result, they are widely used in radio frequency (RF) applications such as mobile communications, radars and satellite communications. III-V devices can also provide more power at high frequencies (e.g. above 1 GHz) compared to Group IV devices. As a result, for example, heterojunction bipolar transistors (HBTs) made with III-V materials are particularly useful in ultra-high frequency (e.g. GHz to THz range) applications where Si devices cannot be effectively used.

[0003] Most millimeter-wave RF circuits are nowadays fabricated on III-V substrates (e.g. GaAs or InP substrates) which are typically small in size (e.g. maximum 6 inches) and very expensive. In contrast, Group IV devices such as Group IV complementary metal-oxide-semiconductor (CMOS) devices are fabricated on large substrates (e.g. 200 to 300 mm) and are useful for building (very) large scale integrated circuits. The combination of III-V devices with Group IV devices on the same substrate therefore opens up some interesting applications and possibilities. For example, the co-integration of III-V HBT power amplifiers with Group IV CMOS envelope tracking is attractive for mobile communications (3G, 4G or 5G) where the HBT power amplifiers can be combined with CMOS baseband signal processing.

[0004] US20190006171A1 discloses different methods for integrating III-N transistors and Si-based transistors. In one method, the method comprises - starting from a silicon-on-insulator (SOI) substrate - epitaxially growing a III-N semiconductor stack on a (111) silicon layer within a first region of the substrate, epitaxially growing a raised (100) silicon from a (100) silicon substrate layer within a second region of the substrate, forming a plurality of III-N transistors within the first substrate region, forming a plurality of Si transistors within the second substrate region, and interconnecting the different transistors. However, this starting substrate which simultaneously comprises a (111) silicon layer and a (100) silicon substrate layer is not widely available and its fabrication is complex and expensive. Moreover, III-V materials and devices are generally more temperature sensitive than Group IV devices, so forming Group IV devices after III-V devices either adds additional constraints to them or results in degradation of the III-V devices.

[0005] Therefore, there is still a need in the art for a better method to integrate III-V devices with group IV devices on a single substrate. SUMMARY

[0006] It is an object of the present invention to provide a good method for co-integrating III-V devices with group IV devices on a Si x Ge 1-x substrate. It is a further object of the present invention to provide good structures relating thereto. This object is achieved by the method and semiconductor structure according to the present invention.

[0007] It is an advantage of embodiments of the present invention that III-V devices and group IV devices can be well integrated on the same substrate. It is a further advantage of embodiments of the present invention that different kinds of III-V and group IV devices can be integrated.

[0008] It is an advantage of embodiments of the present invention that the substrate can be a relatively cheap and widely available substrate, such as a Si (100) wafer.

[0009] It is an advantage of embodiments of the present invention that the difference in vertical space required for III-V devices compared to group IV devices can be compensated for. It is an advantage of embodiments of the present invention that the height deviation can be achieved in a variety of ways.

[0010] It is an advantage of embodiments of the present invention that III-V devices and group IV devices can be integrated such that the contact areas in the III-V devices and group IV devices are located at about the same height level. It is a further advantage of embodiments of the present invention that metallization (e.g. forming metal contact interconnections to the contact areas) is thereby facilitated.

[0011] It is an advantage of embodiments of the present invention that the thermal sensitivity of the different materials and structures used can be taken into account, since the steps can be ordered such that steps that require or would benefit from higher temperatures are performed first, before introducing materials or structures that are more temperature sensitive.

[0012] It is an advantage of embodiments of the present invention that the III-V material - at least one of the active layers thereof - can comprise a low level of growth defects; for example, by using aspect ratio trapping and - optionally - V-shaped pedestals defined by (111) oriented surfaces of the substrate. It is a further advantage of embodiments of the present invention that the III-V material can be provided in a beneficial form, for example as nanoridges.

[0013] An advantage of embodiments of the invention is that different surfaces can be achieved on or from a substrate, for example on the one hand a surface more suitable for forming a group IV device thereon and on the other hand a surface more suitable for forming a III-V device thereon.

[0014] An advantage of embodiments of the invention is that passivation around the III-V material can be improved.

[0015] An advantage of embodiments of the invention is that it can be performed in a relatively simple and economic manner.

[0016] In a first aspect, the invention relates to a method comprising: (a) providing a Si x Ge 1-x (100) substrate, wherein x is 0 to 1 ; (b) selecting a first region for forming a group IV device therein and a second region for forming a III-V device therein, the first and second regions each comprising a portion of the Si x Ge 1-x (100) substrate; (c) forming trench isolation for at least the III-V device; (d) providing a Si y Ge 1-y (100) surface in the first region, wherein y is 0 to 1 ; (e) forming at least a group IV device on the Si y Ge 1-y (100) surface in the first region; (f) forming a trench in the second region exposing the Si x Ge 1-x (100) substrate relative to the Si y Ge 1-y (100) surface in the first region, the trench having a depth of at least 200 nm, preferably at least 500 nm, more preferably at least 1 μm, most preferably at least 2 μm, for example 4 μm; (g) using the aspect ratio trap in the trench to grow III-V material; and (h) forming a III-V device on the III-V material, the III-V device comprising at least one contact region having a height differing from a height of a contact region of the group IV device by within 100 nm, preferably within 50 nm, more preferably within 20 nm, most preferably within 10 nm.

[0017] In a second aspect, the invention relates to a semiconductor structure comprising: (i) a Si x Ge 1-x (100) substrate, wherein x is 0 to 1 ; (ii) trench isolation on the Si x Ge 1-x (100) substrate; (iii) a first region comprising a portion of the Si x Ge 1-x(100) The first portion of the substrate, and in Si y Ge 1-y (100) A group IV device at least partially formed on the surface, wherein y is 0 to 1; and (iv) a second region comprising Si x Ge 1-x (100) The second part of the substrate, exposing Si x Ge 1-x (100) Substrate and trenches filled with III-V material, relative to Si in the first region y Ge 1-y (100) Surface, wherein the depth of the trench is at least 200 nm, preferably at least 500 nm, more preferably at least 1 μm, and most preferably at least 2 μm, and a III-V device on a III-V material, the III-V device comprising at least one contact area, the height of which differs from the height of the contact area of ​​the group IV device by less than 100 nm, preferably less than 50 nm, more preferably less than 20 nm, and most preferably less than 10 nm.

[0018] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features in the dependent claims may be appropriately combined with features in the independent and other dependent claims, and are not limited to those expressly stated in the claims.

[0019] While improvements, modifications, and developments in the apparatus have been ongoing in the art, the concepts of the present invention are considered to represent sufficiently new and novel improvements, including changes to existing practices, resulting in a more efficient, stable, and reliable apparatus that provides this property.

[0020] The above and other features, characteristics, and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate the principles of the invention by way of example. This specification is for illustrative purposes only and is not intended to limit the scope of the invention. The references to the drawings cited below refer to the accompanying drawings. Attached Figure Description

[0021] Figures 1 to 7 The semiconductor structure at different stages of the method according to a first exemplary embodiment of the present invention is illustrated schematically.

[0022] Figures 8 to 14 The semiconductor structure at different stages of the method according to a second exemplary embodiment of the present invention is illustrated schematically.

[0023] Figures 15 to 19 The semiconductor structure at different stages of the method according to a third exemplary embodiment of the present invention is illustrated schematically.

[0024] Figure 20An electron microscope image of a semiconductor structure according to the application is depicted.

[0025] In the different figures, same reference numerals show same or similar elements. DETAILED DESCRIPTION

[0026] The application will be described with respect to the figures and a specific embodiment, but the application is not limited thereto and only defined by the claims. The figures are only illustrative and non-limiting. In the figures, the dimensions of some elements can be exaggerated and not drawn to scale for illustrative purposes. The dimensions and relative dimensions do not correspond to actual reductions of practice of the application.

[0027] Furthermore, the terms first, second, third, etc. can be used in this disclosure to describe various elements, but do not necessarily have to be used in all cases in this description and claims. It should be understood that the terms so used are also interchangeable under appropriate circumstances and embodiments of the application described herein are capable of operating according to other sequences than described or illustrated herein.

[0028] Furthermore, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are inter- changeable under appropriate circumstances and embodiments of the application described herein are capable of operating according to other sequences than described or illustrated herein.

[0029] It should be noted that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted that the listed features are indicative of essential features of the application, but this does not exclude the possi- bility that one or more other features are also essential for the application. Therefore, depending on the specific embodiments, the term "comprising" can mean "consisting of", "consisting essentially of" or "including". The scope of the expression "comprising" should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted that the listed features are indicative of essential features of the application, but this does not exclude the possi- bility that one or more other features are also essential for the application. The scope of the expression "consisting of should not be interpreted as being restricted to the means listed thereafter; it does not exclude the presence of other features or steps. It is thus to be interpreted that the listed features are essential features of the application, but this does not exclude the possi- bility that one or more other features are also essential for the application. The scope of the expression "consisting essentially of should not be interpreted as being restricted to the means listed thereafter; it does not exclude the presence of other features or steps. It does, however, exclude any other features or steps not expressly specified. It is thus to be interpreted that the listed features are essential features of the application, but this does not exclude the possi- bility that one or more other features are also essential for the application.

[0030] Similarly, it is to be noticed that the term "coupled" should not be interpreted as being restricted to direct connections only. The terms "coupled" and "connected" along with their derivatives are to be interpreted in a broad sense. Consequently, as used herein, "coupled" and "connected" are to be interpreted as contemporaneously or prior to be in either direct or indirect connection especially where relying on known functionality of the electrical components. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] Reference throughout this specification to "one implementation" or "an implementation" means that a particular feature, structure, or characteristic described in connection with the implementation is included in at least one implementation of the application. Thus, the appearances of the phrases "in one implementation" or "in an implementation" in various places throughout this specification are not necessarily all referring to the same implementation, but can be referring to different implementations. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more implementations.

[0032] Similarly, it is to be understood that the features of the application described in the specification can be combined in any suitable manner without departing from the scope of the application. Furthermore, where the steps of any method or procedure have been described, replacements and / or equivalents of those steps can be employed to perform the same or similar function without departing from the scope of the application. Accordingly, the application is not to be construed as limited to the specific forms shown in the drawings or described above.

[0033] Also, when some of the implementations described herein include a plurality of features, the combination of these features can not be necessary to practice the application, and the combination of these features in certain implementations can not be included in the application. For example, the application can be practiced in some implementations without the need for including all of the features of the described implementations. Furthermore, the described features can be combined in any suitable manner without departing from the scope of the application. For example, in the appended claims, any of the claimed implementations can be used in any combination.

[0034] Numerous specific details are set forth in the description herein. However, it is understood that embodiments of the application can be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been described in detail in order to not obscure the understanding of this description.

[0035] Reference transistors. These are devices having a first main electrode (e.g. drain or emitter), a second main electrode (e.g. source or collector) and a control electrode (e.g. gate or base) for controlling the flow of charge between the first and second main electrodes.

[0036] The following terms are provided merely to aid in the understanding of the present invention.

[0037] As used herein, and unless otherwise specified, a III-V device is a device that includes a III-V material (e.g. GaAs, InGaAs or InP) as an active material. Likewise, a Group IV device is a device that includes a Group IV material (e.g. Si, Ge or SiGe) as an active material. In particular embodiments, a Group IV device can include both Group IV and III-V active materials. For example, a Group IV complementary metal-oxide semiconductor device (CMOS) can include a Ge p-channel metal-oxide semiconductor field effect transistor (p-channel MOSFET or PMOS) and a III-V n-channel MOSFET (NMOS).

[0038] In a first aspect, the present invention relates to a method comprising: (a) providing a Si x Ge 1-x (100) substrate, wherein x is 0-1 ; (b) selecting a first region for forming a Group IV device therein and a second region for forming a III-V device therein, the first and second regions each comprising a portion of the Si x Ge 1-x (100) substrate; (c) forming trench isolation for at least the III-V device; (d) providing a Si y Ge 1-y (100) surface in the first region, wherein y is 0 to 1 ; (e) forming a Group IV device at least partially on the Si y Ge 1-y (100) surface in the first region; (f) forming a trench in the second region that exposes the Si x Ge 1-x (100) substrate relative to the Si y Ge 1-y (100) surface in the first region, the trench having a depth of at least 200 nm, preferably at least 500 nm, more preferably at least 1 μm, most preferably at least 2 μm, e.g. 4 μm; (g) using aspect ratio trapping to grow III-V material in the trench; and (h) forming a III-V device on the III-V material, the III-V device comprising at least one contact region having a height that differs from the height of a contact region of the Group IV device by no more than 100 nm, preferably no more than 50 nm, more preferably no more than 20 nm, most preferably no more than 10 nm.

[0039] In embodiments, Si x Ge 1-x The (100) substrate can be a Si (100) substrate (i.e. x can be 1), a Ge substrate (i.e. x can be 0) or a mixture thereof (i.e. x can be between 0 and 1); preferably a Si (100) substrate. In embodiments, Si y Ge 1-y The (100) surface can be a Si (100) surface (i.e. y can be 1), a Ge surface (i.e. y can be 0) or a mixture thereof (i.e. y can be between 0 and 1); preferably a Si (100) surface. Si (100) substrates and surfaces are generally advantageously easier and / or cheaper to provide (such as for example obtained in the form of Si (100) wafers, or produced, e.g. grown on top of a substrate) and otherwise handled (e.g. processed) than SiGe or Ge substrates and surfaces; this is therefore the reason why they are often the preferred substrates and / or surfaces in the present application.

[0040] In embodiments, the III-V device can be a vertical device or a planar device; preferably a vertical device. In fact, the present application is beneficial for both vertical and planar III-V devices, but the height difference problem (see below) is generally more severe for vertical devices than for planar devices. In embodiments, the III-V device can be a heterojunction bipolar transistor (HBT) or a high electron mobility transistor (HEMT); preferably a HBT. In embodiments, the group IV device can be a complementary metal-oxide-semiconductor device (CMOS). In embodiments, the CMOS device can be a fin-type field-effect transistor (FinFET).

[0041] The selection of the first and second regions in step b generally involves selecting the locations where the group IV and III-V devices are to be fabricated. These regions do not necessarily have to be delimited by physically distinguishable boundaries, but they each comprise a portion (typically different) of a Si x Ge 1-x (100) substrate and a region above said substrate encompassing one of the above locations; thereby each forming a 3D space in which the respective device is to be fabricated. The first and second regions can generally be selected in such a way that they do not overlap but are adjacent to each other (e.g. abut each other) - at the same height with respect to the substrate.

[0042] In embodiments, the trench isolation can be shallow trench isolation (e.g., having a depth of up to 1 pm) and / or deep trench isolation (e.g., having a depth of from 1 pm to 4 pm). The depth can be measured, for example, as the height difference between the bottom (e.g., the lowest surface) and the top (e.g., the highest surface) of the trench isolation. To obtain good aspect ratio trapping in step g, it is generally advantageous for the depth to be at least twice the size (e.g., width or length) of the active region of III-V material in the final III-V device. Thus, for typical active region sizes of 20 to 200 nm, this translates to a minimum depth of 40 to 400 nm. The greater the ratio between the trench isolation depth and the active region size, the more defects can generally be trapped in step g. Optionally, step c can further comprise forming a trench isolation for the group IV device. However, such trench isolation can also be provided at a later stage (e.g., as part of step d or e).

[0043] To enable good co-integration of the III-V device and the group IV device, it is advantageous to match the top planes (e.g., the contact regions) of the III-V and group IV devices (e.g., to be within 100 nm of each other, preferably within 50 nm, more preferably within 20 nm, most preferably within 10 nm of each other). However, III-V devices (whether planar or vertical) typically require significantly more vertical space (e.g., 500 nm to 2 pm) than group IV devices. For example, they can typically require a buffer layer below the actual III-V active layer (e.g., for reducing the number of growth defects therein). This buffer layer can typically already require a thickness of tens or hundreds of nanometers (e.g., before reducing the number of growth defects to a desired level). For group IV devices, such a buffer layer is typically not required - or at least not to the same thickness - as the group IV active layer itself can be Si x Ge 1-x (100) substrate, or can be grown directly on the substrate and have minimal growth defects. To overcome this difference in vertical space, the present invention enables a height offset between the III-V and group IV devices; i.e., the starting plane of III-V material growth on one hand and the Si y Ge 1-y (100) surface on the other hand.

[0044] In embodiments, the trench isolation formed in step c can have a bottom, and step d can comprise providing a Si y Ge 1-y (100) surface in the first region at least 200 nm, preferably at least 500 nm, more preferably at least 1 pm, most preferably at least 2 pm, e.g., 4 pm, above the trench isolation bottom.

[0045] In an implementation, step d may include in Si x Ge 1-x (100) A dielectric layer (e.g., SiO2) is deposited on the substrate. In embodiments, the thickness of the dielectric layer can be at least 100 nm, preferably at least 200 nm, more preferably at least 500 nm, and most preferably at least 1 μm, such as 2 μm or 4 μm. The dielectric layer is typically used in conjunction with embodiments of the first or second type, see below. In use, the dielectric layer advantageously allows overcoming trench isolation at the top and the Si to be implemented y Ge 1-y (100) The vertical distance between the planes of the surface. In addition, the dielectric layer also plays a role in achieving the degree of planarization between the first region and the second region.

[0046] It can be Si in multiple ways y Ge 1-y (100) The surface provides the desired height deviation. In a first type of implementation, step d may include transferring Si in the first region. x Ge 1-x (100) Substrate exposed, and Si grown (e.g., regrown) thereon. y Ge 1-y To form Si y Ge 1-y (100) Surface. In the embodiment, Si y Ge 1-y Can be with Si x Ge 1-x (100) Substrate lattice matching. In the embodiment, Si x Ge 1-x (100) The exposed portion of the substrate may be used for growing Si thereon. y Ge 1-y Si x Ge 1-x (100) Substrate. In an embodiment, when forming trench isolation in step c, the Si may have already been defined. x Ge 1-x (100) Base.

[0047] In the second type of implementation, step d may include including Si y Ge 1-y (100) Si surface y Ge 1-y Layer transfer to Si x Ge 1-x (100) On the substrate. In an embodiment, the Si layer may be transferred onto the dielectric layer.

[0048] Thus, the first or second type of embodiment advantageously allows to achieve the required height deviation of the Si x Ge 1-x (100) surface on top of the trench isolation, i.e. the Si y Ge 1-y (100) substrate.

[0049] In the third type of embodiment, the trench isolation provided in step c can be a deep trench isolation (see above), and the Si x Ge 1-x (100) substrate provided in step a can comprise the Si y Ge 1-y (100) surface of step d. The third type of embodiment does not provide the Si y Ge 1-y (100) surface at a certain height above the top of the trench isolation, but achieves the required height deviation by lowering the plane at which the III-V material is to be grown.

[0050] Since deep trench isolation is generally more difficult to form than shallow trench isolation, the trench isolation used in the first or second type of embodiment is generally shallow. However, it will be clear that in embodiments different approaches can be combined, e.g. the required height deviation for the first part is achieved by a deeper trench isolation and the height deviation for the remaining part is achieved as described in the first or second type of embodiment.

[0051] Forming at least partially the group IV device in step e can comprise performing at least some steps of forming the group IV device in which a desired temperature to be used exceeds the thermal budget of the III-V material. In embodiments, step e can comprise forming a functional gate for the group IV device or forming a dummy gate for the group IV device. In a first gate process flow, the functional gate can generally already be formed in step e. In contrast, in a last gate process flow, the dummy gate can be formed during step e and can be replaced in a replacement metal gate (RMG) module after step g (e.g. before, during or after step h). In embodiments, step e can further comprise forming a protective layer (e.g. a zero level dielectric, ILD0) above the at least partially formed group IV device.

[0052] In embodiments, forming the trench in the second region in step f can comprise etching down through the dielectric layer (if present) and through the trench isolation to an opening of the Si x Ge 1-x (100) substrate. In embodiments, forming the trench can further comprise etching partially into the Si x Ge 1-xthe second region. Note that the trenches in the second region are different from the trench isolation formed in step c.

[0053] In embodiments, the trenches formed in step f can comprise a lower trench portion having a first trench width and an upper trench portion having a second trench width. In embodiments, the first trench width can be 0.05 to 0.75 times, preferably 0.1 to 0.5 times, the second trench width. Thus, the trenches can be shaped to allow formation of nanoridges therein (see below). In embodiments, the lower trench portion can be adapted for aspect ratio trapping of the III-V material, while the upper trench portion can be adapted for growth confinement of the III-V material. As described previously in the context of trench isolation, a minimum depth of 40 to 400 nm is typically required to achieve good aspect ratio trapping. As such, the bottom trench portion can have a trench depth of at least 40 nm, preferably at least 100 nm, more preferably at least 200 nm, most preferably at least 400 nm. In embodiments, the bottom of the trench (e.g. the bottom of the lower portion) and the bottom of the trench isolation can be at comparable heights (e.g. within 5 to 50 nm of each other, e.g. within 5 to 20 nm or 5 to 10 nm of each other). Preferably, the bottom of the trench can be substantially aligned with or above the bottom of the trench isolation. When the trench has a V-shaped pedestal (see below), at least two ends of the V can be aligned with or above the bottom of the trench isolation; the point of the V can optionally be above, aligned with, or below the bottom of the trench isolation.

[0054] The depth of the trench is typically such that its bottom is at the same height as, or slightly higher (e.g. 5 to 50 nm) than, the bottom of the shallow trench isolation for the III-V device.

[0055] In embodiments, the trenches formed in step f can have a lower trench portion and an upper trench portion defined by Si x Ge 1-x a (111) oriented surface of a (100) substrate defines a V-shaped pedestal. In embodiments, the lower trench portion can be in contact with the V-shaped pedestal. In embodiments, the V-shaped pedestal can have an internal angle of approximately 70.6°. Preferably, the orientation of the V can be such that the point of the V faces "downwards" (i.e. towards the Si x Ge 1-x (100) substrate) and the ends of the V face "upwards" (i.e. away from the Si x Ge 1-xsubstrate) ; i.e. oriented "V" instead of "A". The (111) oriented surface advantageously facilitates growth of III-V material thereon and has less defects, allowing for sufficient defect-free III-V material to be achieved after ART already within a smaller growth thickness (as compared to growing III-V material on a flat bottom - performing ART). Nonetheless, the V-shaped bottom profile is not strictly necessary, e.g. a flat bottom can also be used, provided the depth and / or aspect ratio of the trench - especially of the lower part of the trench (e.g. sufficiently high to achieve the required low defect level) - is chosen accordingly.

[0056] As known to the skilled person, in step g, the aspect ratio capture is used to reduce a number of growth defects (e.g. threading dislocations) in the III-V material. Obviously, the acceptable remaining number of defects typically depends on the integrity and / or reliability sought for the final device. The number also depends on the type of III-V device manufactured, e.g. HBT devices are typically more sensitive to defects than HEMT devices. However, in broad terms, the number of threading dislocations in the top part of the III-V material (e.g. in the active layer) can be less than 1 x 1010defects / cm2, preferably less than 1 x 1011defects / cm2, more preferably less than 1 x 1012defects / cm2. 9 2 6 2 .

[0057] ​​​In embodiments, growing a III-V material in step g can comprise growing a layer stack comprising at least one III-V material (e.g. at least one layer can consist of a III-V material). In embodiments, the layer stack can consist of a III-V material. In embodiments, the layer stack can comprise a buffer layer; for example, a buffer layer made of a III-V material (e.g. GaAs, InGaAs or InP). In embodiments, the layer stack can comprise one or more further III-V layers; for example at least one III-V active layer (e.g. an emitter layer). In embodiments, the III-V layer(s) can comprise (e.g. consist of) a material selected from the group consisting of: GaAs, InAs, GaSb, InP, InSb, GaP, InGaAs, InAlAs, InGaP, InGaSb, AlGaAs, AlGaP, InAlP, AlGaSb and InAlP. For example, the III-V layer(s) can comprise an InGaP emitter layer on a GaAs collector or an InP emitter layer on an InGaAs buffer layer. The buffer layer is advantageously used to trap growth defects therein and to provide a suitable (relatively) defect-free surface on which to grow one or more further III-V layers. Nonetheless, the III-V material can also consist of a single III-V material, the bottom of which can occupy a buffer layer and the top of which can function as an active layer.

[0058] In a preferred embodiment, the III-V material grown in trenching step g can be a III-V nanoridge. In embodiments, the III-V nanoridge can comprise a lower nanoridge portion having a first nanoridge width, an upper nanoridge portion having a second nanoridge width, and an intermediate nanoridge portion tapering between and from the upper nanoridge portion to the lower nanoridge portion. In embodiments, the first nanoridge width can be 0.05 to 0.75 times, preferably 0.1 to 0.5 times, the second nanoridge width. In embodiments, there can be an air gap immediately adjacent the tapering intermediate nanoridge portion (e.g. in the upper trench portion). The method of forming the III-V nanoridge constitutes the subject matter of European patent application 19195256.3, which is incorporated herein by reference; thus, the III-V nanoridge can be formed as described therein, for example. An actual example is described in, for example, on page 13, line 4 to page 14, line 4. Note that the “trench” mentioned in EP application 19195256.3 corresponds to the “lower trench portion” herein, while “outside the trench” corresponds to the “upper trench portion” herein. In embodiments, forming the III-V nanoridge can comprise starting growth of the III-V nanoridge in the lower trench portion, thereby forming a fill layer of the nanoridge within the lower trench portion, and continuing growth on top of the fill layer in the upper trench portion, thereby forming the intermediate nanoridge portion and the upper nanoridge portion, wherein at least one surfactant is added in the chamber while the nanoridge is grown in the upper trench portion. Suitable surfactants are described in EP application 19195256.3.

[0059] In embodiments, after step g, the III-V material can be embedded in a dielectric material (e.g. SiO2). In embodiments, the method can comprise a further step g’ after step g: (g’1) at least partially removing the dielectric material adjacent (e.g. in contact with) the III-V material; (g’2) coating at least the side (and optionally the top) of the III-V material with a passivation layer; and (g’3) re-embedding the III-V material in a dielectric material (e.g. SiO2). In embodiments, step g’3 can comprise re-filling the opening formed by step g’1 with the same dielectric material removed in step g’1 or a further dielectric material. For example, step g’ can be performed before or simultaneously with step h, but typically before the metal contacts are made in step i. In embodiments, the passivation layer can be made of a dielectric (e.g. SiN or Al2O3) or a high bandgap, undoped III-V material (e.g. InGaP or InP). The passivation layer can for example have a bandgap greater than or equal to the emitter layer (if present) of the III-V device. In embodiments, the passivation layer can have a thickness of 2 to 20 nm. Reference is made to Figure 20The quality of the interface (indicated by the arrow) between the III-V material and the dielectric material is generally relatively poor. Furthermore, Figure 20 b shows that when the dielectric material is partially recessed (e.g. partial wet Si02 removal), the situation is further worsened; where due to the weak III-V / dielectric interface, the dielectric also etches from this interface, leaving a gap (indicated by the arrow) next to the III-V material. However, by partially removing the dielectric next to the III-V material, depositing a passivation layer (indicated by the arrow) around the III-V material, and then filling the remaining gap (the result of which is shown in Figure 20 c), the interface with the III-V material (i.e. between the III-V material and the passivation layer) is significantly improved. The improved interface can for example enable better recombination, thereby reducing the number of surface defects.

[0060] In embodiments, forming a III-V device on the III-V material in step h can comprise etching an emitter for the HBT device in the III-V material. In embodiments, step h can comprise forming at least one contact region for the III-V device to enable contact of the III-V device to a metal contact (see below).

[0061] In embodiments where the Group IV device is not fully formed in step e, the method can further comprise fully forming the Group IV device prior to step i (e.g. before, during or after step h). This can for example comprise performing a replacement metal gate process.

[0062] In embodiments, the method can further comprise, after step h, step i: (i) forming a metal contact to a contact region of the III-V device and a contact region of the Group IV device.

[0063] In embodiments, any feature of any embodiment of the first aspect can be described independently in relation to any embodiment of any other aspect.

[0064] In a second aspect, the present application relates to a semiconductor structure comprising: (i) a Si x Ge 1-x (100) substrate, wherein x is 0 to 1 ; (ii) a trench isolation on the Si x Ge 1-x (100) substrate; (iii) a first region comprising a first portion of the Si x Ge 1-x (100) substrate, and at least a partially formed Group IV device on a Si y Ge 1-y (100) surface, wherein y is 0 to 1 ; and (iv) a second region comprising a second portion of the Si x Ge1-x a second portion of the (100) substrate, exposing Si x Ge 1-x a trench of the (100) substrate and filled with III-V material, opposite the Si in the first region y Ge 1-y a (100) surface, the trench having a depth of at least 200 nm, preferably at least 500 nm, more preferably at least 1 pm, most preferably at least 2 pm, and a III-V device on the III-V material, the III-V device comprising at least one contact region having a height that differs from a height of a contact region of the group IV device by at most 100 nm, preferably at most 50 nm, more preferably at most 20 nm, most preferably at most 10 nm. Such a semiconductor structure can be obtained by the method according to the first aspect.

[0065] In embodiments, the III-V material can be a III-V nanoridge. In embodiments, the III-V nanoridge can comprise a lower nanoridge portion having a first nanoridge width, an upper nanoridge portion having a second nanoridge width, and an intermediate nanoridge portion tapering between and from the upper nanoridge portion to the lower nanoridge portion. In embodiments, the first nanoridge width can be 0.05 to 0.75 times, preferably 0.1 to 0.5 times, the second nanoridge width.

[0066] In embodiments, the trench has a V-shaped seat defined by a (111) oriented surface of the (100) substrate. x Ge 1-x a V-shaped seat defined by a (111) oriented surface of the (100) substrate.

[0067] In embodiments, any feature of any embodiment of the second aspect can be described independently accordingly to any embodiment of any other aspect.

[0068] The application will now be described by a detailed description of several embodiments of the application. It is clear that other embodiments of the application can be constructed without departing from the true technical teaching of the application, which is only limited by the claims attached hereto.

[0069] Example 1 : IV-group regrowth based approach

[0070] Reference will now be made to Figure 1A Si(100) wafer (10) is provided and first and second regions (21, 22) are selected, each comprising a portion of the Si substrate (10) in which a Group IV device (50) and a III-V device (80) respectively are to be formed. A shallow trench isolation (30) for the III-V device (80) is then formed using a SiO2 dielectric. The shallow trench isolation (30) also defines a Si(100) base (11) in the first region (21) for (re)growth of Si thereon.

[0071] Reference is now made to Figure 2 A SiO2 dielectric layer (40) is deposited over the shallow trench isolation (30) and a window is opened therein over the Si(100) base (11). Silicon (12) is then selectively regrown on the Si(100) base (11) so as to have a height offset (h o ) of the Si(100) surface (15) (e.g. at least 200 nm, preferably at least 500 nm, more preferably at least 1 μm, most preferably at least 2 μm, e.g. 4 μm) relative to the bottom (32) of the trench isolation (30). This height offset (h o ) will bring the contact regions (53, 83) of the final III-V (60) and Group IV (50) devices to a similar height (e.g. within 100 nm, preferably within 50 nm, more preferably within 20 nm, most preferably within 10 nm of each other); despite the typically greater difference in vertical space required for the III-V device (80) as compared to the Group IV device (50).

[0072] Reference is now made to Figure 3 A shallow trench isolation (35) for the Group IV device (50) is formed in the regrown Si (12) with a SiO2 dielectric to define a Group IV active region (51).

[0073] Reference is now made to Figure 4 One or more dummy gates (52) are defined over the active region (51), the sides of which are gate spacers.

[0074] Reference is now made to Figure 5 The partially formed Group IV device (50) is covered by a SiO2 zero level interlevel dielectric (ILD0; 55). Next, a trench (60) is formed in the second region (22) down into and partially into the Si(100) substrate (10). The trench (60) typically has a depth (d t), such that its bottom (61) is at the same height or slightly higher (e.g., 5 to 50 nm) than the bottom (32) of the shallow trench isolation (30) for the III-V device (80). The trench (60) has a shape suitable for aspect ratio trapping (ART). For example, the trench (60) can have a narrower lower trench portion (63) for ART and a wider upper trench portion (64) for III-V growth confinement. Preferably, the lower trench portion (63) is in contact with the V-shaped pedestal (62) defined by the (111)-oriented surface of the Si (100) substrate (10), which promotes low-defect growth of III-V material thereon.

[0075] Referring now to Figure 6 . The III-V buffer layer (71) (e.g., GaAs, InP, or InGaAs) is grown in the trench (60) using ART. Subsequently, the III-V layer (72) for the III-V device (80) (e.g., a heterojunction bipolar transistor, HBT) is grown on the III-V buffer layer (71) (see above). The III-V material (71, 72) forms a nanoridge (75) that includes a lower nanoridge portion (76) that is narrower in the lower trench portion (63), an upper nanoridge portion (78) that is wider in the upper trench portion (64), and an intermediate nanoridge portion (77) that tapers from the upper nanoridge portion to the lower nanoridge portion (76). Due to the tapering of the intermediate nanoridge portion (77), an air gap (78) is formed at the bottom of the upper trench portion (64).

[0076] Referring now to Figure 7 . The ILD0 (55) above the dummy gate (52) in the first region (21) is opened, and if a replacement metal gate process is performed on it, the Group IV device (50) is subsequently covered with a protective layer, e.g., an oxide- or nitride-based dielectric material (e.g., SiO2, SiN, SiCN, SiON, or Al2O3). Next, the III-V device (80) is formed, e.g., by etching an HBT emitter and exposing an HBT base layer, which is then cut to expose an HBT subcollector (out of the plane of the figure). The remaining gap in the second region (22) is then filled with an oxide- or nitride-based dielectric material (90) (e.g., SiO2) and planarized relative to the protective layer in the first region (21). After that, an HBT emitter cap is optionally formed. As before, the III-V device (80) and the Group IV device (50) are formed such that the respective contact regions (53, 83) are at similar heights. Finally, the contact regions (53, 83) of the III-V (80) and Group IV (50) devices are zero-level (MO) and first-level (Ml) metallized (91).

[0077] Example 2: IV-group layer transfer based approach

[0078] Referring now to Figure 8 . A Si(100) wafer (10) is provided and a first region (21) and a second region (22) are selected, each region comprising a portion of the Si substrate (10) to form a Group IV device (50) and a III-V device (80) respectively therein. A shallow trench isolation (30) for the III-V device (80) is then formed with a SiO2 dielectric.

[0079] Referring now to Figure 9 . A SiO2 dielectric layer (40) is deposited on the shallow trench isolation (30) and a Si(100) layer (13) is transferred onto it, thereby providing a height offset (h o ) of the Si(100) surface (15) (e.g. at least 200 nm, preferably at least 500 nm, more preferably at least 1 μm, most preferably at least 2 μm, e.g. 4 μm) relative to the bottom (32) of the trench isolation (30). This height offset (h o ) will bring the contact areas (53, 83) of the final III-V (80) and Group IV (50) devices to a similar height (e.g. within 100 nm, preferably within 50 nm, more preferably within 20 nm, most preferably within 10 nm of each other); despite the larger difference in vertical space typically required for the III-V device (80) compared to the Group IV device (50).

[0080] Referring now to Figure 10 . The Si(100) layer is patterned to delineate the Group IV active region (51) and a SiO2 dielectric shallow trench isolation (30) - or mesa isolation - for the Group IV device (50) is formed with a SiO2 dielectric without the need for SiO2 re-filling (when the thickness of the transferred layer is less than 100 nm). One or more dummy gates (52) are then defined above the active region (51), the sides of which are gate spacers.

[0081] Referring now to Figure 11 . The partially formed Group IV device (50) is covered by a SiO2 zero level interlayer dielectric (ILD0; 55). Next, a trench (60) is formed in the second region (22) down into and partially into the Si(100) substrate (10). The trench (60) typically has a depth (d t), such that its bottom (61) is at the same height or slightly higher (e.g., 5 to 50 nm) than the bottom (32) of the shallow trench isolation (30) for the III-V device (80). The trench (60) has a shape suitable for aspect ratio trapping (ART). For example, the trench (60) can have a narrower lower trench portion (63) for ART and a wider upper trench portion (64) for III-V growth confinement. Preferably, the lower trench portion (63) is in contact with the V-shaped pedestal (62) defined by the (111)-oriented surface of the Si (100) substrate (10), which promotes low-defect growth of III-V material thereon.

[0082] Referring now to Figure 12 . The III-V buffer layer (71) (e.g., GaAs, InP, or InGaAs) is grown in the trench (60) using ART. The buffer forms a nanoridge (75) that includes a lower nanoridge portion (76) that is narrower in the lower trench portion (63), an upper nanoridge portion (78) that is wider in the upper trench portion (64), and an intermediate nanoridge portion (77) that tapers from the upper nanoridge portion to the lower nanoridge portion (76). Due to the tapering of the intermediate nanoridge portion (77), an air gap (78) is formed at the bottom of the upper trench portion (64). Subsequently, the III-V layer (72) for the III-V device (80) (e.g., heterojunction bipolar transistor, HBT) is grown on the III-V buffer layer (71) (see above).

[0083] Referring now to Figure 13 . The ILD0 (55) above the dummy gate (52) in the first region (21) is opened, and if a replacement metal gate process is performed on it, the Group IV device (50) is subsequently covered with a protective layer, such as an oxide- or nitride-based dielectric material (e.g., Si02, SiN, SiCN, SiON, or AI203). Next, the III-V device (80) is formed, such as by etching the HBT emitter and exposing the HBT base layer, which is then cut to expose the HBT subcollector (out of the plane of the figure). The remaining gap in the second region (22) is then filled with an oxide- or nitride-based dielectric material (90) (e.g., Si02) and planarized with respect to the protective layer in the first region (21). After that, the HBT emitter cap (94) is optionally formed.

[0084] Referring now to Figure 14. Contact regions (53, 83) of the III-V device (80) and the Group IV device (50) are formed. As previously described, the III-V device (80) and the Group IV device (50) are formed such that the respective contact regions (53, 83) are at a similar height. The contact regions (53, 83) of the III-V (80) and Group IV (50) devices are then zero-level (M0) and first-level (Ml) metallized (91).

[0085] Example 3: III-V device (80) based deep trench isolation (30) approach

[0086] Reference is now made to Figure 15 . A Si (100) wafer (10) is provided and a first region (21) and a second region (22) are selected, each region comprising a portion of the Si substrate (10) to form a Group IV device (50) and a III-V device (80) respectively therein. Deep trench isolation (30) for the III-V device (80) and the Group IV device (50) is then formed using a SiO2 dielectric, thereby providing a height offset (h o ) in the first region (21) of the Si (100) surface (15) (e.g. an offset of at least 200 nm, preferably at least 500 nm, more preferably at least 1 μm, most preferably at least 2 μm, e.g. 4 μm). This height offset (h o ) will result in the contact regions (53, 83) of the final III-V (80) and Group IV (50) devices being at a similar height (e.g. within 100 nm, preferably within 50 nm, more preferably within 20 nm, most preferably within 10 nm of each other); notwithstanding the greater difference in vertical space typically required for the III-V device (80) as compared to the Group IV device (50).

[0087] Reference is now made to Figure 16 . One or more dummy gates (52) are defined above the active region (51), the sides of which are gate spacers.

[0088] Reference is now made to Figure 17 . The partially formed Group IV device (50) is covered by a SiO2 zero-level interlevel dielectric (ILD0; 55). Next, a trench (60) is formed in the second region (22) down into and partially into the Si (100) substrate (10). The trench (60) typically has a depth (d t), such that its bottom (61) is at the same height or slightly higher (e.g., 5 to 50 nm) than the bottom (32) of the shallow trench isolation (30) for the III-V device (80). The trench (60) has a shape suitable for aspect ratio trapping (ART). For example, the trench (60) can have a narrower lower trench portion (63) for ART and a wider upper trench portion (64) for III-V growth confinement. Preferably, the lower trench portion (63) is in contact with the V-shaped pedestal (62) defined by the (111)-oriented surface of the Si (100) substrate (10), which promotes low-defect growth of III-V material thereon.

[0089] Referring now to Figure 18 . A III-V buffer layer (71) (e.g., GaAs, InP, or InGaAs) is grown in the trench (60) using ART. The buffer forms a nanoridge (75) that includes a lower nanoridge portion (76) that is narrower in the lower trench portion (63), an upper nanoridge portion (78) that is wider in the upper trench portion (64), and an intermediate nanoridge portion (77) that tapers from the upper nanoridge portion to the lower nanoridge portion (76). Due to the tapering of the intermediate nanoridge portion (77), an air gap (78) is formed at the bottom of the upper trench portion (64). Subsequently, III-V layers (72) for the III-V device (80) (e.g., a heterojunction bipolar transistor, HBT) are grown on the III-V buffer layer (71) (see above).

[0090] Referring now to Figure 19 . The ILD0 (55) above the dummy gate (52) in the first region (21) is opened, and if a replacement metal gate process is performed on it, the Group IV device (50) is subsequently covered with a protective layer, e.g., an oxide- or nitride-based dielectric material (e.g., Si02, SiN, SiCN, SiON, or AI2O3). Next, the III-V device (80) is formed, e.g., by etching an HBT emitter and exposing an HBT base layer, which is then cut to expose an HBT subcollector (out of the plane of the figure). The remaining gap in the second region (22) is then filled with an oxide- or nitride-based dielectric material (90) (e.g., Si02) and planarized relative to the protective layer in the first region (21). After that, an HBT emitter cap is optionally formed. As before, the III-V device (80) and the Group IV device (50) are formed such that the respective contact regions (53, 83) are at similar heights. Finally, the contact regions (53, 83) of the III-V (80) and Group IV (50) devices are zero-level (M0) and first-level (M1) metallized (91).

[0091] It should be understood that while the preferred embodiments, specific constructions and configurations of the device of the present application have been discussed herein, various changes or modifications in form and detail can be made without departing from the scope and spirit of this application. For example, any of the steps given above can represent only a single transformation that can be used. Functionality can be added or deleted from the block diagrams, and operations can be interchanged among functional blocks. Steps added for the described methods can be added or removed from the described methods within the scope of the present application.

Claims

1. A method comprising: a. providing Si x Ge 1-x (100) substrate, wherein x is 0-1; b. selecting a first region for forming a Group IV device therein and a second region for forming a III-V device therein, the first region and the second region each comprising Si x Ge 1-x a portion of a (100) substrate; c. at least a III-V device on Si x Ge 1-x forming trench isolation in a second region of the (100) substrate; d. After step c, Si x Ge 1-x is provided in a first region of the (100) substrate y Ge 1-y (100) surface, wherein y is 0 to 1; e. Si in the first region after step d but before step f y Ge 1-y (100) surface at least partially forming a group IV device; f. After step e but before step g, Si x Ge 1-x (100) substrate in a second region of the substrate x Ge 1-x (100) substrate in a second region of the substrate x Ge 1-x (100) substrate in a second region of the substrate y Ge 1-y (100) substrate in a second region of the substrate g. after step f but before step h, growing III-V material in the trench using an aspect ratio trap; and h. after step g, forming a III-V device on the III-V material in the trench, the III-V device comprising at least one contact region having a height that differs from a height of a contact region of the group IV device by less than 100 nm.

2. The method of claim 1, wherein, The trench (60) has a bottom (64) defined by Si x Ge 1-x A V-shaped seat (62) defined by a (111)-oriented surface of the (100) substrate (10).

3. The method of claim 1 or 2, wherein, The III-V device (80) is a heterojunction bipolar transistor.

4. The method of claim 1 or 2, wherein, Si x Ge 1-x The (100) substrate (10) is a Si (100) substrate (10), and / or the Si y Ge 1-y The (100) surface (15) is a Si (100) surface (15).

5. The method of claim 1 or 2, wherein, The trench isolation (30) formed in step c has a bottom (32), wherein step d comprises providing Si y Ge 1-y (100) surface (15).

6. The method of claim 1 or 2, wherein, Step d comprises depositing a dielectric layer (40) having a thickness of at least 100 nm on the Si x Ge 1-x (100) substrate (10).

7. The method of claim 1 or 2, wherein, Step d comprises exposing the Si x Ge 1-x (100) substrate (10) and growing Si thereon to form a Si y Ge 1-y (100) surface (15).

8. The method of claim 1 or 2, wherein, Step d comprises transferring the Si y Ge 1-y layer (13) of the (100) surface (15) onto a Si x Ge 1-x substrate (10).

9. The method of claim 1 or 2, wherein, The trench isolation (30) provided in step c is a deep trench isolation (30), wherein the Si x Ge 1-x The (100) substrate comprises the Si y Ge 1-y (100) surface (15) of step d.

10. The method of claim 1 or 2, wherein, After step g, the III-V material (71, 72) is embedded in a dielectric material.

11. The method of claim 10, comprising a further step g’ after step g: g’1. at least partially removing the dielectric material adjacent to the III-V material (71, 72); g’2. coating at least the side of the III-V material (71, 72) with a passivation layer; and g’3. re-embedding the III-V material (71, 72) in a dielectric material.

12. The method of claim 1 or 2, wherein, The trench (60) formed in step f comprises: - a lower trench portion (63) having a first trench width, and - an upper trench portion (64) having a second trench width; wherein the first trench width is 0.05 to 0.75 times the second trench width.

13. The method of claim 1 or 2, wherein, The III-V material (71, 72) grown in the trench (60) of step g is a III-V nanoridge (75), said III-V nanoridge (75) comprising: - a lower nanoridge portion (76) having a first nanoridge width, - an upper nanoridge portion (78) having a second nanoridge width, and - an intermediate nanoridge portion (77) tapering between and from the upper nanoridge portion (78) to the lower nanoridge portion (76); wherein the first nanoridge width is 0.05 to 0.75 times the second nanoridge width.

14. A semiconductor structure comprising: i. Si x Ge 1-x (100) substrate (10), wherein x is 0 to 1 ; ii. Si x Ge 1-x Trench isolation (30) on a (100) substrate (10); iii. a first region (21) comprising: - Si x Ge 1-x a first portion of the (100) substrate (10), and - in Si y Ge 1-y at least partially formed group IV device (50) on a (100) surface (15), wherein y is 0 to 1; and iv. a second region (22) comprising: - Si x Ge 1-x a second portion of the (100) substrate (10), - exposed Si x Ge 1-x (100) substrate (10) and filled with III-V material (71, 72), relative to Si in the first region (21) y Ge 1-y (100) surface (15), the depth of the trench (60) is at least 200 nm; - a III-V device (80) on the III-V material (71, 72), the III-V device (80) comprising at least one contact region (83) having a height that differs from a height of a contact region (53) of the group IV device (50) by less than 100 nm; characterized in that the III-V material (71, 72) is a III-V nanoridge (75), the III-V nanoridge (75) comprising: - a lower nanoridge portion (76) having a first nanoridge width, - an upper nanoridge portion (78) having a second nanoridge width, and - an intermediate nanoridge portion (77) tapering between and from the upper nanoridge portion (78) to the lower nanoridge portion (76); wherein the first nanoridge width is 0.05 to 0.75 times the second nanoridge width.

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