Narrow semiconductor mesa devices

Abstract

A narrow semiconductor mesa device is disclosed. A first trench and a second trench are provided in a semiconductor body. A mesa separation structure is provided between the first trench and the second trench and includes a non-semiconductor material. A first semiconductor mesa is provided between the first trench and the non-semiconductor material of the mesa separation structure. The first semiconductor mesa includes an emitter region, a body region, and a drift region. The first trench and the second trench are formed by a mask etching technique and have a minimum trench separation distance, and the first semiconductor mesa is provided to have a lateral width less than the minimum trench separation distance.

Description

Technical Field

[0001] The present application relates to semiconductor devices and, in particular, to techniques for forming narrow semiconductor regions for vertical semiconductor devices. Background Art

[0002] Semiconductor transistors, particularly field-effect controlled switching devices such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs), have been used in a variety of applications, including but not limited to use as switches in power supplies and power converters, electric vehicles, air conditioners, and even stereo systems. In many of these applications, semiconductor transistors must be designed to accommodate large currents and / or large voltages. For example, power semiconductor transistors are typically required to control currents on the order of 1A (ampere), 10A, 100A, 500A, or more and / or control voltages on the order of 20V (volts), 100V, 500V, 1000V, or more.

[0003] Power dissipation, which contributes to conduction losses and switching losses, is an important performance parameter for power semiconductor transistors. In IGBTs, one approach to improving power dissipation is to increase the charge carrier density at the emitter / source side of the device. This makes it easier to remove a larger proportion of charge carriers from the drift region of the device during turn-off. Current techniques for increasing the charge carrier density at the emitter / source side of power semiconductor transistors are approaching the practical limits of semiconductor processing technology. Summary of the Invention

[0004] A semiconductor device is disclosed. According to an embodiment, the semiconductor device includes a semiconductor body, the semiconductor body including: a main surface and a back surface opposite the main surface; a first trench and a second trench, which are laterally separated from each other and each extend from the main surface into the substrate; a mesa separation structure, which is laterally between the first trench and the second trench and includes a non-semiconductor material; and a first semiconductor mesa between the first trench and the mesa separation structure. The first semiconductor mesa includes: a first sidewall extending coextensive with a first sidewall of the first trench; a second sidewall directly connected to the non-semiconductor material of the mesa separation structure; a source region extending to the main surface and having a first conductivity type; a body region below the source region and having a second conductivity type opposite to the first conductivity type; and a drift region below the body region and having the first conductivity type. The aspect ratio of the first semiconductor mesa, defined by the lateral width of the first semiconductor mesa divided by the vertical depth of the first semiconductor mesa, is less than or equal to 0.2.

[0005] Separately or in combination, a ratio between an aspect ratio of the first trench and an aspect ratio of the first semiconductor mesa is greater than or equal to 0.5, wherein the aspect ratio of the first trench is equal to a lateral width of the first trench divided by a vertical depth of the first trench.

[0006] Separately or in combination, the semiconductor device further includes a carrier extraction region extending to the main surface and having the second conductivity type, the carrier extraction region being configured to provide a conducting path for carriers of the second conductivity type flowing from the back surface to the main surface.

[0007] Separately or in combination, the semiconductor device includes a second semiconductor mesa between a second trench and a mesa separation structure, the second semiconductor mesa includes a first sidewall extending together with a first sidewall of the second trench and a second sidewall directly connected to a non-semiconductor material of the mesa separation structure, and a carrier extraction region is disposed in the second semiconductor mesa.

[0008] Separately or in combination, the mesa separation structure includes two monolithic insulating structures and a central semiconductor mesa disposed laterally between the two monolithic insulating structures, and the carrier extraction region is disposed in the central semiconductor mesa.

[0009] Separately or in combination, the mesa-isolating structure includes an electrically insulating material and a conductive material, and the conductive material is formed in a central region of the mesa-isolating structure that is insulated from the semiconductor body by the electrically insulating material.

[0010] Separately or in combination, the mesa separation structure includes a central trench and two monolithic insulating structures disposed on either side of the central trench, the conductive material includes a polysilicon region disposed in the central trench, the semiconductor device includes an emitter metallization, the emitter metallization is electrically connected to the source region and the carrier extraction region, and the body region is electrically disconnected from the emitter metallization.

[0011] Separately or in combination, the semiconductor device includes an auxiliary trench disposed between the first trench and the second trench, and the mesa separation structure includes a monolithic insulating structure completely occupying a lateral region between the first semiconductor mesa and the auxiliary trench.

[0012] Separately or in combination, the mesa separation structure includes a monolithic insulating structure, and the semiconductor device further includes a contact trench formed in the monolithic insulating structure and a conductive emitter contact filling the contact trench, and a sidewall of the emitter contact directly contacts the emitter region and the body region.

[0013] A method for producing a semiconductor device is disclosed. According to an embodiment, the method includes providing a semiconductor body, the semiconductor body including a main surface and a back surface opposite the main surface; providing a first trench and a second trench, the first trench and the second trench being laterally separated from each other and each extending from the main surface into a substrate; providing a mesa separation structure, the mesa separation structure laterally between the first trench and the second trench and comprising a non-semiconductor material; and providing a first semiconductor mesa between the first trench and the mesa separation structure. The first semiconductor mesa includes: a first sidewall coextensive with a first sidewall of the first trench; a second sidewall directly adjoining the non-semiconductor material of the mesa separation structure; a source region extending to the main surface and having a first conductivity type; a body region below the source region and having a second conductivity type opposite to the first conductivity type; and a drift region below the body region and having the first conductivity type. The first trench and the second trench are formed by a mask etching technique with a minimum trench separation distance, and the first semiconductor mesa is provided to have a lateral width less than the minimum trench separation distance, the lateral width of the first semiconductor mesa being the shortest distance between the first sidewall and the second sidewall of the first semiconductor mesa.

[0014] Separately or in combination, the first trench and the second trench are formed to have a lateral separation distance greater than a minimum trench separation distance, and providing a mesa separation structure includes: forming at least one central trench, the at least one central trench being between the first trench and the second trench and being laterally separated from the first trench by a distance equal to or greater than the minimum trench separation distance; performing an insulator growth process, the insulator growth process filling the central trench with an insulator material and consuming semiconductor material; and controlling parameters of the insulator growth process so that the insulator material consumes semiconductor material between the trench and the first trench to a point at which the first semiconductor mesa is narrower than the minimum trench separation distance.

[0015] Separately or in combination, providing a mesa separation structure includes: forming a plurality of central trenches between a first trench and a second trench, each central trench having a width smaller than a width of the first trench and the second trench; and performing an insulator growth process so that each central trench is completely filled with an insulator material.

[0016] Separately or in combination, a plurality of central trenches are formed separated from each other by intermediate semiconductor mesas, and an insulator growth process is performed such that each intermediate semiconductor mesa is completely consumed by insulator material to form a monolithic insulating structure from the plurality of central trenches.

[0017] Separately or in combination, the method further includes forming an auxiliary trench disposed between the first trench and the second trench, and the monolithic insulating structure is formed to completely occupy a lateral region between the first semiconductor mesa and the auxiliary trench.

[0018] Separately or in combination, the method further includes forming a first gate electrode in the first gate trench, forming a second gate electrode in the second gate trench, and forming a conductive region in the auxiliary trench, the formation of the first gate electrode and the second gate electrode and the conductive region including: depositing a doped first polysilicon layer to simultaneously fill the first gate trench, the second gate trench and the auxiliary trench with doped polysilicon; removing the doped polysilicon from the auxiliary trench; depositing an undoped second polysilicon layer in the auxiliary trench after removing the doped polysilicon from the auxiliary trench; and planarizing the substrate so as to remove portions of the first polysilicon layer and the second polysilicon layer above the first gate trench, the second gate trench and the auxiliary trench.

[0019] Separately or in combination, the method further includes: forming a contact trench in the monolithic insulating structure; and filling the contact trench with a conductive material, thereby forming an emitter contact, and the sidewalls of the emitter contact directly contact the emitter region and the body region.

[0020] Separately or in combination, a mesa separation structure is provided comprising two monolithic insulating structures and a central semiconductor mesa disposed laterally between the two monolithic insulating structures, and providing the mesa separation structure comprises: providing a first plurality of central trenches, each of the first plurality of central trenches being formed to be separated from each other by an intermediate semiconductor mesa; providing a second plurality of central trenches, each of the second plurality of central trenches being formed to be separated from each other by an intermediate semiconductor mesa; providing a permanent semiconductor mesa between the first plurality of central trenches and the second plurality of central trenches, the permanent semiconductor mesa being wider than the intermediate semiconductor mesa; and performing an insulator growth process such that each of the intermediate semiconductor mesas is completely consumed by the insulator material and such that the permanent semiconductor mesa remains intact after the insulator growth process.

[0021] Separately or in combination, the first trench and the second trench having a minimum trench separation distance and the plurality of center trenches are simultaneously formed by a mask etching technique.

[0022] Separately or in combination, a first trench and a second trench are formed by a first mask etching step, a plurality of center trenches are formed by a second mask etching step performed before or after the first mask etching step, and the bottom of at least one of the plurality of center trenches is disposed at a different distance from the main surface than the bottoms of both the first trench and the second trench.

[0023] Separately or in combination, the first semiconductor mesa is provided such that an aspect ratio of the first semiconductor mesa is less than or equal to 0.2, the aspect ratio of the first semiconductor mesa being a lateral width of the first semiconductor mesa divided by a vertical depth of the first semiconductor mesa. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The elements in the drawings are not necessarily to scale with respect to each other. The same reference numerals designate corresponding similar components. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and are described in detail in the subsequent description.

[0025] Figure 1 A vertical insulated gate bipolar transistor according to an embodiment is illustrated.

[0026] Figure 2 A vertical insulated gate bipolar transistor having a mesa separation structure according to an embodiment is illustrated.

[0027] Figures 3 to 8 Selected processing steps for forming a vertical insulated gate bipolar transistor with a mesa separation structure are illustrated in accordance with an embodiment.

[0028] Figure 9 FIG. 1 illustrates a vertical insulated gate bipolar transistor having a mesa separation structure according to another embodiment.

[0029] Figure 10 FIG. 1 illustrates a vertical insulated gate bipolar transistor having a mesa separation structure according to another embodiment.

[0030] Figure 11 FIG. 1 illustrates a vertical insulated gate bipolar transistor having a mesa separation structure according to another embodiment.

[0031] Figure 12 FIG. 1 illustrates a vertical insulated gate bipolar transistor having a mesa separation structure according to another embodiment.

[0032] Figure 13 FIG. 1 illustrates a vertical insulated gate bipolar transistor having a mesa separation structure according to another embodiment.

[0033] Figure 14 FIG. 1 illustrates a vertical insulated gate bipolar transistor having a mesa separation structure according to another embodiment.

[0034] Figure 15 FIG. 1 illustrates a vertical insulated gate bipolar transistor having a mesa separation structure according to another embodiment.

[0035] Figure 16 FIG. 1 illustrates a vertical insulated gate bipolar transistor having a mesa separation structure according to another embodiment.

[0036] Figure 17 FIG. 1 illustrates a vertical insulated gate bipolar transistor having a mesa separation structure according to another embodiment. DETAILED DESCRIPTION

[0037] Embodiments of a vertical IGBT having a source region disposed in a semiconductor mesa are described herein, the semiconductor mesa advantageously having a low aspect ratio (i.e., the ratio of the width of the semiconductor mesa to the depth). The vertical IGBT includes two trench gate electrodes separated from each other in the laterally direction. A mesa separation structure is provided between the two trench gate electrodes. The mesa separation structure includes a non-semiconductor material, which may include an insulator and a conductor. The mesa separation structure defines at least a first semiconductor mesa adjacent to a first gate trench. The first sidewall of the first semiconductor mesa is directly connected to the first gate trench, and the second sidewall of the first semiconductor mesa is directly connected to the non-semiconductor material of the mesa separation structure. The emitter region and the body region of the vertical IGBT are provided in the first semiconductor mesa. Due to the advantageous techniques described herein, the first semiconductor mesa can be formed with a low aspect ratio while maintaining a deep and wide gate trench. By narrowing the semiconductor mesa through which the first type of charge carriers are extracted from the drift region, the concentration of the first type of charge carriers in the emitter side of the device is increased. Because of the charge neutrality principle, this in turn leads to an increase in the concentration of charge carriers of the opposite type (i.e., the second type). This increased emitter-side charge carrier density results in a low on-state voltage drop and low turn-off losses, since most of the charge carriers are removed at a low voltage when the device is turned off.

[0038] Reference Figure 1 , depicts a cross-sectional view of a vertical insulated gate bipolar transistor (IGBT) 100 according to an embodiment. The vertical IGBT 100 is formed in a semiconductor body having a main surface 102 and a back surface 104 opposite the main surface 102. The vertical IGBT 100 includes a first gate trench 106 and a second gate trench 108 separated from each other in the laterally direction. Each of the first gate trench 106 and the second gate trench 108 extends from the main surface 102 into the semiconductor body. A first gate electrode 110 and a second gate electrode 112 are provided in the first gate trench 106 and the second gate trench 108, respectively. The first gate electrode 110 and the second gate electrode 112 are formed of a conductive material such as metal or highly doped polysilicon. Each of the first gate electrode 110 and the second gate electrode 112 is insulated from the semiconductor body by a gate dielectric 114 of an electrically insulating material such as silicon dioxide (SiO2), silicon nitride (SiN), or the like.

[0039] The vertical IGBT 100 includes a source region 116, a body region 118, a drift region 120, and a collector region 122. The source region 116 and the drift region 120 are n-type semiconductor regions, with the drift region having a lower relative dopant concentration. The body region 118 and the collector region 122 are p-type semiconductor regions. The source region 116 extends to the main surface 102 and directly adjoins the first and second gate trenches 106, 108. The body region 118 and the source region 116 form a first pn junction below the main surface 102 and directly adjoin the first and second gate trenches 106, 108. The drift region 120 and the body region 118 form a second pn junction below the main surface 102 and extend below the first and second gate trenches 106, 108. On the back side of the device, the drift region 120 and the collector region 122 form a third pn junction. A conductive emitter metallization 124 is disposed on the main surface 102. The emitter metallization 124 is insulated from the first gate electrode 110 and the second gate electrode 112 by a passivation layer 126, which includes one or more layers of an electrically insulating material, such as SiO2, SiN, etc. A low-ohmic connection between the emitter metallization 124 and the emitter region 116 and the body region 118 can be provided by an emitter contact 128, which can be a plug formed of a conductive metal such as tungsten. A conductive collector metallization 130 is disposed on the back surface 104. The collector metallization 130 can form a low-ohmic connection with the collector region 122 via direct contact. In other embodiments, additional doped regions may be provided. For example, a highly doped region of any conductivity type may be provided to act as a field stop and / or barrier region at the back side of the device.

[0040] The operating principle of the vertical IGBT 100 is as follows. When a gate-emitter voltage exceeding the threshold voltage is applied to the first gate electrode 110 and the second gate electrode 112, a conductive electron channel is formed in the body region 118 adjacent to the first gate trench 106 and the second gate trench 108. Under a positive emitter-collector bias, electrons are injected from the source region 116 through the body region 118 and into the drift region 120. At the back side of the device, the pn junction between the collector region 122 and the drift region is forward biased, and holes are thus injected into the drift region 120. A vertical IGBT 100 operating under the same operating principle, but with opposite carrier type currents, can be obtained by reversing the conductivity types of the source region 116, the body region 118, the drift region 120, and the collector region 122.

[0041] An important performance-related parameter of the vertical IGBT 100 is the emitter-side charge carrier density profile. The emitter-side charge carrier density profile is the profile of the number of carriers (holes and electrons) per unit volume in the drift region between the first trench 106 and the second trench 108 and extending below the body region in the semiconductor mesa below the trench. Increased emitter-side charge carrier density reduces the device's on-state voltage drop, V CEON The increased emitter-side charge carrier density also facilitates easier removal of charge carriers from the drift region 120 during turn-off operation of the device. Consequently, the power consumption of the device attributable to switching is beneficially reduced.

[0042] One way to increase the emitter-side charge carrier density of the vertical IGBT 100 is through geometrical modifications. Reducing the aspect ratio of the semiconductor mesa 117 between the first gate trench 106 and the second gate trench 108—that is, the ratio of the width of the semiconductor mesa 117 to the depth of the semiconductor mesa 117—reduces the volume of the region through which holes are extracted from the drift region 120. However, in Figure 1 In devices with a CMOS process, the ability to do so is limited by the processing technology used to form the device. Specifically, the width of the semiconductor mesa 117 between the first gate trench 106 and the second gate trench 108 cannot be reduced below a minimum separation distance associated with the technology used to form the first gate trench 106 and the second gate trench 108. Furthermore, the ability to reduce the width of the semiconductor mesa 117 between the first gate trench 106 and the second gate trench 108 is constrained by the area requirements for the emitter contact 128. At low widths, it becomes difficult or impossible to reliably form an emitter contact 128 with sufficient current carrying capacity.

[0043] Reference Figure 2 , depicts a cross-sectional view of a vertical IGBT 100 according to another embodiment. Figure 1 The vertical IGBT100 is different. Figure 2 The embodiment includes a mesa separation structure 132 between the first gate trench 106 and the second gate trench 108. This arrangement can represent a transistor cell in which the depicted pattern is repeated multiple times in succession in the semiconductor body. The mesa separation structure 132 includes a non-semiconductor material. Generally speaking, the non-semiconductor material can include any of a variety of electrical insulators (e.g., oxides, nitrides, etc.) and electrical conductors (e.g., metals such as copper, tungsten, aluminum, or highly doped polysilicon).

[0044] The mesa-separating structure 132 defines a first semiconductor mesa 134 in the semiconductor body between the mesa-separating structure 132 and the first gate trench 106. The first semiconductor mesa 134 has a first sidewall 136 that is coextensive with a first sidewall 138 of the first gate trench 106 and a second sidewall 140 that is directly connected to the non-semiconductor material of the mesa-separating structure 132. In this embodiment, the mesa-separating structure 132 additionally defines a second semiconductor mesa 142 between the mesa-separating structure 132 and the second gate trench 108. The second semiconductor mesa 142 has a first sidewall 144 that is coextensive with a first sidewall 146 of the second gate trench 108 and a second sidewall 148 that is directly connected to the non-semiconductor material of the mesa-separating structure 132.

[0045] According to an embodiment, the mesa separation structure 132 consists only of a monolithic insulating structure 176. The monolithic insulating structure 176 is a region of a type of insulator material that extends from the main surface 102 and includes opposing outer sidewalls facing the first gate trench 106 and the second gate trench 108. More generally, the mesa separation structure 132 can include multiple electrically insulating materials combined with each other and / or can include multiple monolithic insulating structures combined with conductive regions. In any case, the interfacial sidewalls of the mesa separation structure 132 include insulating material that confines carriers to the first semiconductor mesa 134 and the second semiconductor mesa 142.

[0046] Each of the first semiconductor mesa 134 and the second semiconductor mesa 142 includes a source region 116 extending to the main surface 102 and having a first conductivity type (e.g., n-type), a body region 118 below the source region 116 and having a second conductivity type opposite to the first conductivity type (e.g., p-type), and a drift region 120 below the body region 118 and having the first conductivity type (e.g., n-type). The first gate electrode 110 and the second gate electrode 112 are configured according to the above reference to Figure 1 The described operating principle controls the conduction current flowing through the first semiconductor mesa 134 and the second semiconductor mesa 142 , respectively, by controlling the conduction channel in each body region 118 .

[0047] The various dimensions of the vertical IGBT 100 will now be described. For the sake of brevity, only the dimensions of the first gate trench 106 and the first semiconductor mesa 134 will be described. These dimensions also apply to the second gate trench 108 and the second semiconductor mesa 142. The dimensions of the first gate trench 106 and the first semiconductor mesa 134 can be, but need not be, the same as the dimensions of the second gate trench 108 and the second semiconductor mesa 142, respectively.

[0048] According to an embodiment, the vertical depth 150 of the first gate trench 106 is between 2 μm (micrometers) and 10 μm. In a specific example, the vertical depth 150 is about 4 μm. The vertical depth 150 of the first gate trench 106 is the shortest distance between the main surface 102 and the bottom of the first gate trench 150.

[0049] According to an embodiment, the width 152 of the first gate trench 106 is between 500 nm (nanometers) and 2.0 μm. In a specific example, the width 152 of the first gate trench 106 is approximately 800 nm. The width 152 of the first gate trench 106 is the shortest distance between the first sidewall 138 and the second sidewall opposite the first sidewall 138.

[0050] According to an embodiment, width 154 of first semiconductor mesa 134 is between 5 nm and 800 nm. In a specific example, width 154 is approximately 400 nm. Width 154 of first semiconductor mesa 134 is the shortest distance between first sidewall 136 and second sidewall 140 of first semiconductor mesa 134.

[0051] According to an embodiment, the vertical depth 156 of the mesa-separating structure 132 is between 2 μm (micrometers) and 10 μm. In a specific example, the vertical depth 156 of the mesa-separating structure 132 is approximately 4 μm. The vertical depth 156 of the mesa-separating structure 132 is the shortest distance between the main surface 102 and the bottom of the mesa-separating structure 132.

[0052] According to an embodiment, width 158 of mesa separation structure 132 is between 300 nm and 2 μm. In a specific example, width 158 is approximately 1450 nm. The width of mesa separation structure 132 is the shortest distance between second sidewall 140 of first semiconductor mesa 134 and second sidewall 148 of second semiconductor mesa 142.

[0053] According to an embodiment, a width 160 of the opening in the passivation layer 126 directly above the source region 116 and the body region 118 is between 300 nm and 3 μm. In a specific example, the width 160 is approximately 2 μm. The width 160 of the opening in the passivation layer 126 is the shortest distance between the edge sides of the passivation layer 126 directly above the first semiconductor mesa 134 and the second semiconductor mesa 142.

[0054] According to an embodiment, the aspect ratio of the first semiconductor mesa 134 is less than or equal to 0.2. The aspect ratio of the first semiconductor mesa 134 is the lateral width 154 of the first semiconductor mesa 134 divided by the vertical depth of the first semiconductor mesa 134. The vertical depth of the first semiconductor mesa 134 is the longer of the vertical depth 156 of the mesa separation structure 132 or the vertical depth 150 of the first gate trench 106.

[0055] According to an embodiment, the ratio between the aspect ratio of the first gate trench 106 and the aspect ratio of the first semiconductor mesa 134 is greater than or equal to 0.5. The aspect ratio of the first gate trench 106 is equal to the width 152 of the first gate trench 106 divided by the vertical depth 150 of the first gate trench 106. The ratio between the aspect ratio of the first gate trench 106 and the aspect ratio of the first semiconductor mesa 134 is equal to the aspect ratio of the first gate trench 106 divided by the aspect ratio of the first semiconductor mesa 134. Therefore, in an embodiment in which the first semiconductor mesa 134 has an aspect ratio less than or equal to 0.2, if the aspect ratio of the gate trench is greater than or equal to 0.1, the ratio requirement of 0.5 is met.

[0056] Thus, the benefits of the low-aspect-ratio semiconductor mesa with respect to emitter-side charge carrier density, as described above, are achieved while maintaining a relatively deep and / or wide gate trench. Thus, other considerations related to the geometry of the gate structure, such as transconductance, are not sacrificed by forming a narrow-width source region. At the same time, the width 160 of the opening in the passivation layer 126 is advantageously kept large, for example, between approximately 300 nm and 3 μm, or, for purposes of this connection, at least twice the width 152 of the first gate trench 150. Thus, the emitter contact 128 can be easily and reliably formed between the first gate trench 106 and the second gate trench 108.

[0057] The advantageous geometric characteristics discussed above are made possible by advantageous techniques associated with the formation of the mesa separation structure 132. As will be described in further detail below, by intentionally forming the first gate trench 106 and the second gate trench 108 a large distance (e.g., at least three times the minimum trench separation distance) apart from each other and providing the mesa separation structure 132 therebetween, the first semiconductor mesa 134 and the second semiconductor mesa 142 that are narrower than the minimum trench separation distance can be reliably formed.

[0058] exist Figure 3, mask steps for forming a semiconductor device having a mesa separation structure 132 according to an embodiment are depicted. According to the technology, a semiconductor body is provided including a main surface 102 and a back surface 104 opposite to the main surface 102. In general, the semiconductor body can include a variety of semiconductor materials, including compound IV semiconductor materials such as silicon, silicon carbide (SiC) or silicon germanium (SiGe), and III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), etc. The semiconductor body can include: a commercially available bulk semiconductor wafer, such as a silicon wafer, which extends to the back surface 104; and an epitaxial material region extending to the main surface 102. The epitaxial material region can have an intrinsic doping concentration (e.g., n-type) that provides a drift region doping concentration.

[0059] An etch-resistant mask 162 is formed on the main surface 102 of the semiconductor body. Generally speaking, the material of the etch-resistant mask 162 can be any material that can effectively prevent an etchant (e.g., a wet chemical etchant or plasma) from penetrating the semiconductor body. The etch-resistant mask 162 can be formed of a hard mask material, such as carbon, a carbon-containing material (e.g., diamond-like carbon (DLC)), a semiconductor oxide and nitride, such as silicon nitride (SiN), silicon dioxide (SiO2), etc. Alternatively, the etch-resistant mask 162 can be formed of a photoresist material, such as a photopolymerized photoresist, a photodegradable photoresist, a photocrosslinked photoresist, etc.

[0060] The etch-resistant mask 162 is patterned to include openings that expose portions of the major surface 102. These openings include a first wider opening 164 and a second wider opening 166 and a plurality of narrower central openings 168 between the wider openings 164, 166. The widths of the first wider opening 164 and the second wider opening 166 are selected to be greater than the widths of the narrower central openings 168. In addition, the distance between immediately adjacent narrower central openings 168 is selected to be less than the distance between one of the wider openings 164, 166 and the closest narrower central opening 168. In terms of relationship, the widths of the first wider opening 164 and the second wider opening 166 can be at least twice the widths of the narrower central openings 168, and the separation distance between immediately adjacent narrower central openings 168 can be no greater than half the separation distance between one of the first wider opening 164 and the second wider opening 166 and the closest narrower central opening 168. In numerical examples, the width of the first wider opening 164 and the second wider opening 166 can be in the range of 500-700 nm, the width of the narrower central opening 168 can be in the range of 100-200 nm, the separation distance between immediately adjacent narrower central openings 168 can be in the range of 100-200 nm, and the separation distance between one of the first wider opening 164 and the second wider opening 166 and the closest narrower central opening 168 can be in the range of 200-400 nm.

[0061] Reference Figure 4 , an etching step is performed. In a generally known manner, the etching step removes semiconductor material from the exposed areas of the semiconductor body. Generally speaking, this can be performed according to various etching techniques, such as wet chemical etching techniques, dry etching techniques such as deep reactive ion etching, etc. As a result of the etching step, a first gate trench 106 and a second gate trench 108 are formed. Additionally, a plurality of narrow central trenches 170 are formed between the first gate trench 106 and the second gate trench 108. Each of the plurality of narrow central trenches 170 is separated from each other by an intermediate semiconductor mesa 172. The width of these features is related to the selected dimensions of the anti-etching mask 162 as described above.

[0062] Reference Figure 5, for example, removing the etch-resistant mask 162 using known techniques. Subsequently, an insulator layer 174 is grown on the exposed surface of the semiconductor body. The insulator layer 174 may be grown using a thermal oxidation technique or a thermal nitridation technique, wherein the surface of the semiconductor body is exposed to a reactive agent (e.g., oxygen or nitrogen) at an elevated temperature (e.g., between about 800 and 1200° C.). The formed insulator layer may include an oxide, a nitride, or an oxynitride, such as silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ), or silicon oxynitride (SiO 2 ) in the case of a silicon semiconductor body. x N Y ).

[0063] The insulator growth process is performed so that the narrow central trench 170 is completely filled with the insulator layer 174. In addition, the insulator layer 174 completely consumes the intermediate semiconductor mesa 172. Insulator formation techniques such as thermal oxidation or thermal nitridation form an insulating layer that grows upward while consuming semiconductor material downward according to a known ratio (e.g., 2:1 upward: downward). The parameters of the insulator growth process (e.g., time and temperature) can be selected to ensure that the formed insulator layer 174 has a thickness equal to at least half the width of the narrow central trench 170, thereby ensuring that these trenches are completely filled. In addition, the parameters of the insulator growth process can be selected to ensure that the formed insulator layer 174 extends across the entire width of the intermediate semiconductor mesa 172. At the same time, because the first gate trench 106 and the second gate trench 108 are substantially wider than the narrow central trench 170, the formed insulator layer 174 does not completely fill the first gate trench 106 and the second gate trench 108.

[0064] As a result of the insulator growth process, the first semiconductor mesa 134 and the second semiconductor mesa 142 are formed with a monolithic insulating structure 176 provided therebetween. Advantageously, the above-described techniques can form the first semiconductor mesa 134 and the second semiconductor mesa 142 having a lateral width less than a minimum trench separation distance between the first gate trench 106 and the second gate trench 108, the minimum trench separation distance being determined by the reference 176. Figures 3 to 5 As a result, the aspect ratio of the first semiconductor mesa 134 and the second semiconductor mesa 142 is advantageously lower than the aspect ratio of the semiconductor mesa directly between the two gate trenches. This can be attributed to the Figure 5The insulator formation process described in the foregoing is independent of the trench formation process and is highly controllable. Specifically, the rate of insulator material consumption is highly controllable and predictable through the known relationship between time and temperature. Furthermore, due to their smaller size, there is less variation in the width of the narrow central trench 170 compared to the width of the first and second gate trenches 106 and 108. Thus, the starting point of insulator growth is highly predictable, and the end point of the insulator material consumption of the semiconductor material is highly controllable.

[0065] Applying the above concepts, according to an embodiment, the control reference Figures 3 to 5 The process parameters of the etching step and the insulator growth step are described so that the width of one or both of the first semiconductor mesa 134 and the second semiconductor mesa 142 is less than the minimum trench separation distance used to form the first gate trench 106 and the second gate trench 108. In this embodiment, the lateral separation distance between the first gate trench 106 and the second gate trench 108 is selected to be greater than the minimum trench separation distance, for example, at least three times the minimum trench separation distance. Using the first semiconductor mesa 134 as an example, the lateral separation distance between the first gate trench 150 and the closest narrow central trench 170 is selected to be equal to or slightly greater than the minimum trench separation distance, for example, no greater than 125% of the minimum trench separation distance. The parameters of the insulator growth process (e.g., time and temperature) are controlled so that the insulator material consumes the semiconductor material to a point where the first semiconductor mesa 134 is narrower than the minimum trench separation distance.

[0066] Reference Figure 6 , removing the insulator layer 174. This can be accomplished using, for example, a wet etching technique or a dry etching technique. This technique is performed so that the formed insulator layer 174 is completely removed from the first gate trench 106 and the second gate trench 108. Additionally, a small thickness of insulator material is removed from the upper side of the monolithic insulating structure 176. However, the majority of the monolithic insulating structure 176 remains intact.

[0067] Reference Figure 7 , several processing steps are performed to form various features of the vertical IGBT. These processing steps include forming a gate dielectric 114 in the first gate trench 106 and the second gate trench 108. The gate dielectric 114 can be formed by depositing a layer of insulating material that lines the sidewalls of the first gate trench 106 and the second gate trench 108 using a technique such as vapor deposition, thermal oxidation, etc. The gate dielectric 114 formed can include an oxide, a nitride, or an oxynitride, such as silicon nitride (SiN), silicon dioxide (SiO2), or silicon oxynitride (SiO x N YA planarization technique or a polishing technique (eg, CMP) may be performed to remove the deposited insulating material layer from the main surface 102 .

[0068] After forming the gate dielectric 114, the first gate electrode 110 and the second gate electrode 112 may be formed. This may be accomplished by depositing a conductive material (e.g., polysilicon) or a conductive metal (e.g., aluminum or tungsten) that fills the first gate trench 106 and the second gate trench 108. A planarization technique or a polishing technique (e.g., CMP) may be performed to remove the deposited conductive material layer from the main surface 102.

[0069] The source region 116 and the body region 118 are formed in the first semiconductor mesa 134 and the second semiconductor mesa 142. Optionally, a highly doped body contact region 119 may be formed locally in the body region 118. The highly doped body contact region 119 may be a second conductivity type region having a higher doping concentration than the body region 118, thereby providing a low ohmic contact to the emitter contact 128. These regions may be formed using known doping techniques such as implantation or diffusion. The doping process may be performed after forming the monolithic insulating structure 176. In one example, the monolithic insulating structure 176 is partially etched to expose the sidewall surfaces of the first semiconductor mesa 134 and the second semiconductor mesa 142. Subsequently, dopants are implanted into the exposed sidewall portions of the first semiconductor mesa 134 and the second semiconductor mesa 142 by an angled implantation technique, and the dopants are subsequently activated. Alternatively, at least some of the doped regions described above may be formed before forming the monolithic insulating structure 176. In one example, in Figures 3 to 5 Prior to the steps described in , doped layers with a doping of the body region 118 are formed in the semiconductor body, wherein an upper one of the doped layers provides the source region 116 and a lower one of the doped layers provides the body region 118 .

[0070] After forming the gate structure and the active doped regions, a passivation layer 126 is formed on the main surface 102 of the semiconductor body and over the first gate trench 106 and the second gate trench 108. The passivation layer 126 may be formed using techniques such as vapor deposition, thermal oxidation, etc. The passivation layer 126 may be a multilayer structure having different thicknesses and material types, such as a thin SiN layer and a thick SiO2 layer in one example.

[0071] Reference Figure 8, for example, using a mask etching technique, an emitter contact trench 175 is formed that penetrates the passivation layer 126 and extends into the monolithic insulating structure 176. The sidewalls of the contact trench 175 are in contact with the source region 116 and the body region 118. In an embodiment, a highly doped body contact region 119 is formed by implanting dopants into the sidewalls of the emitter contact trench. The contact trench is filled with a conductive material (e.g., tungsten, nickel, etc.), thereby forming the emitter contact 128. By forming the emitter contact 128 to contact both the source region 116 and the body region 118, the device has improved carrier extraction capability because carriers of the first conductivity type (e.g., electrons) are injected from the source region 116 and carriers of the second conductivity type (e.g., holes) are extracted from the body region 116. In another embodiment, instead of forming a discrete emitter contact, the emitter metallization layer 124 may be deposited directly in the opening of the passivation layer 126 over the source region 116 so as to directly contact the source region 116 and the body region 118 .

[0072] In reference Figures 3 to 8 In the described technique, the first and second gate trenches 106, 108, and the narrow central trench 170 are formed simultaneously through a single mask etch step. Therefore, the depths of each of these trenches are related because they are formed through the same etching conditions. As a result, the bottom of the monolithic insulating structure 176 is approximately the same depth as the depth of the first and second gate trenches 106, 108 (e.g., within 10%), with the depth of the narrow central trench 170, and therefore the depth of the monolithic insulating structure, typically being slightly shallower than the first and second gate trenches 106, 108. Alternatively, the first and second gate trenches 106, 108 can be formed through a first mask etch step, and the narrow central trench 170 formed through a second mask etch step performed before or after the first mask etch step. This allows the narrow central trench 170 to be formed at any desired depth independent of the depths of the first and second gate trenches 106, 108, for example, greater than or less than 10% of the depth of the first and second gate trenches 106, 108. Therefore, the depth of the monolithic insulating structure 176 may be controlled independently of the depths of the first gate trench 106 and the second gate trench 108 .

[0073] Reference Figures 3 to 8The described technique forms a single monolithic insulating structure 176 that completely occupies the lateral region between the first semiconductor mesa 134 and the second semiconductor mesa 142. Alternatively, a similar concept can be used to form multiple monolithic insulating structures 176 between the first semiconductor mesa 134 and the second semiconductor mesa 142, with other structures comprising conductive, insulating, and / or semiconductor materials between each of these monolithic insulating structures. In one example of this concept, a mesa separation structure is provided that includes two monolithic insulating structures and a central semiconductor mesa disposed laterally between the two monolithic insulating structures. The mesa separation structure is provided by forming a first plurality of narrow central trenches 170, wherein each of the first plurality of narrow central trenches 170 is formed to be separated from one another by an intermediate semiconductor mesa 172 according to the dimensional values ​​and relationships described above. Additionally, a second plurality of narrow central trenches 170 is formed, wherein each of the second plurality of narrow central trenches 170 is formed to be separated from one another by an intermediate semiconductor mesa 172 according to the dimensional values ​​and relationships described above. The mask is patterned such that permanent semiconductor mesas are disposed between the first and second plurality of narrow central trenches that are wider than the intermediate semiconductor mesas 172. The insulator growth process is performed such that each intermediate semiconductor mesa 172 is completely consumed by the insulator material and such that the permanent semiconductor mesas are only partially consumed, wherein a portion of the permanent semiconductor mesas remains intact after the insulator growth process.

[0074] In other embodiments, one or more trenches may be formed in the semiconductor body between two monolithic insulating structures. Alternatively, these trenches may be formed within one of the monolithic insulating structures. These trenches may be filled with an electrical insulator and a conductor and may be configured to perform various functions independent of or consistent with the operation of the vertical IGBT. Various embodiments of the device will be described in further detail below.

[0075] Reference Figure 9 , depicts a vertical IGBT 100 according to another embodiment. This device can be compared in all respects to the first embodiment except that the second semiconductor mesa 142 is configured differently. Figure 2 The vertical IGBT 100 is similar to the vertical IGBT 100 of FIG. In this example, the second semiconductor mesa 142 includes a carrier extraction region 178 . The carrier extraction region 178 has a doping type opposite to that of the source region 116 , for example, a second conductivity type when the source region 116 is a first conductivity type region. The carrier extraction region 178 is located between the main surface 102 and the pn junction of the second semiconductor mesa 142 with the drift region 120 . Optionally, a contact region having the same conductivity type as the carrier extraction region 178 and a higher dopant concentration may be provided in the carrier extraction region 178 to facilitate a low-ohmic contact with the emitter.

[0076] Figure 9 The working principle of the vertical IGBT 100 is as follows. The first gate electrode 110 is configured as previously referred to Figure 1 The described approach controls the flow of carriers of the first conductivity type (e.g., electrons) in the first semiconductor mesa 134. During the forward conduction state, the carrier extraction region 178 in the second semiconductor mesa 142 is a reverse-biased pn junction that provides a conduction path for carriers of the second conductivity type (e.g., holes) to flow from the collector region 122 toward the emitter metallization 124. In this way, the second semiconductor mesa 142 provides a conduction path for carriers of the second conductivity type to be removed from the semiconductor body.

[0077] Reference Figure 10 , depicts a vertical IGBT 100 according to another embodiment. Figure 9 Similar to the embodiment of the present invention, the device includes a carrier extraction region 178. Unlike the previous embodiment, the mesa separation structure 132 includes two monolithic insulating structures 176 and a central semiconductor mesa 180 between the two monolithic insulating structures 176. This configuration can be obtained according to the technology described previously. The first semiconductor mesa 134 and the second semiconductor mesa 142 are disposed on either side of the two monolithic insulating structures 176 and are configured in a manner similar to that described previously. The carrier extraction region 178 is provided in the central semiconductor mesa and is configured to provide a return path for carriers of the second conductivity type in a manner similar to that described previously. In another embodiment, the device can be configured so that the emitter metallization 124 contacts only the source regions 116 in the first semiconductor mesa 134 and the second semiconductor mesa 142. In this case, carrier extraction of the second conductivity type occurs exclusively at the carrier extraction region 178.

[0078] Reference Figure 11 , depicts a vertical IGBT 100 according to another embodiment. This device can be similar in all respects to the IGBT 100 except that the mesa separation structure 132 comprises both electrically insulating and conductive materials. Figure 2 The electrical insulating material may be provided by forming one of the monolithic insulating structures 176 according to the previously described techniques. Conductive region 182 is formed in the central region of mesa separation structure 132, which is insulated from the semiconductor body by the insulating material of monolithic insulating structure 176. Conductive region 182 may include metals such as tungsten, aluminum, copper, and alloys thereof, or may include highly doped polycrystalline semiconductor material.

[0079] The conductive region 182 may be formed in several different ways. In one example, the reference Figure 4The technique described is such that wider grooves are provided between narrow central grooves 170. Figure 5 The wider trench is not completely filled during the insulator formation process described. A conductive material, such as polysilicon, is then deposited in the wider trench. Alternatively, in performing the insulator formation process described with reference to Figure 5 Following the described processing, conductive region 182 may be formed by etching trenches in monolithic insulating structure 176 and depositing an electrical conductor, such as polysilicon, in the trenches. In yet another example, similar etching and deposition steps may be performed after forming first gate electrode 110 and second gate electrode 122.

[0080] According to the reference Figure 4 After forming a plurality of narrow central trenches 170 using the described techniques, one of the narrow trenches is filled with a conductive material, for example using a deposition technique. Figure 5 The insulator growth process is performed in a similar manner as described.

[0081] In general, the conductive region 182 can be configured for various device functions. In one example, the conductive region 182 is configured to be electrically floating, i.e., electrically disconnected from all nodes and terminals of the device. In this case, the conductive region 182 can be configured as a shielding structure that prevents cross-coupling between the two devices. In another example, the conductive region 182 can be configured as a passive element connected to the vertical IGBT 100. For example, the conductive region 182 can be configured as a resistor. The resistance value of the resistor can be selected by customizing the physical properties (such as length, width, cross-sectional area, etc.) of the conductive region. The resistor can be connected to the gate electrode 112 via a connecting portion (not shown) to add a gate resistor to the vertical IGBT 100. In another example, the resistor can be configured as a functional element that works independently of the vertical IGBT 100. For example, the resistor can be configured as a temperature sensor.

[0082] If desired, the thickness of the insulator material between conductive region 182 and first semiconductor mesas 134 and / or second semiconductor mesas 142 can be controlled such that the conductive region does not substantially affect the flow of charge carriers in first semiconductor mesas 134 and / or second semiconductor mesas 142. This means that the electromagnetic fields generated by the charges flowing in conductive region 182 are sufficiently mitigated such that they do not affect the charges present in first semiconductor mesas 134 and / or second semiconductor mesas 142.

[0083] Reference Figure 12, depicts a vertical IGBT 100 according to another embodiment. Similar to the previously discussed embodiments, the mesa separation structure 132 includes both electrically insulating and conductive materials. However, in this case, the conductive material is provided by a polysilicon region 184 disposed in a central trench 186. This configuration can be achieved by forming the central trench 186 between the first and second gate trenches 106, 108, wherein the central trench 186 can have similar or identical dimensions to the first and second gate trenches 106, 108. A plurality of narrow central trenches 170 and intervening semiconductor mesas 172 can be provided on either side of the central trench 186 and subsequently filled and replaced with insulating material according to the previously described techniques to form a monolithic insulating structure 176. In this case, the process is controlled so that the monolithic insulating structure 176 reaches the sidewalls of the central trench 186. A polysilicon layer is then deposited, filling the central trench 186 and forming the polysilicon region 184. In this technique, undoped or lightly doped polysilicon can be deposited simultaneously in the first and second gate trenches 106, 108, and the central trench 186. During the doping of the gate trenches, the central trench 186 can be fully or partially masked. Alternatively, doped polysilicon can be deposited simultaneously in the first and second gate trenches 106, 108, and the central trench 186. The doped polysilicon is then fully or partially removed from the central trench 186. A second polysilicon layer is then deposited to fill the central trench 186. A planarization step can be used to remove the two polysilicon layers formed outside the trenches.

[0084] Figure 12 The polysilicon region 184 of the embodiment can be configured to serve a variety of device functions. These device functions include as shown in FIG. Figure 10 Any configuration of the conductive region 182 described. In another example, the polysilicon region 184 can be configured as a pn junction diode. For example, the pn junction diode can be configured as a temperature sensing diode. In one arrangement, the polysilicon region 184 includes a first conductive type region (e.g., n-type) in the bottom of the central trench 186 and a second conductive type region (e.g., p-type) in the top of the central trench 186. As a result, the polysilicon region 184 includes a pn junction extending along a plane approximately parallel to the main surface 102. In another arrangement, the polysilicon region 184 includes a first conductive type region (e.g., n-type) in the first lateral section that completely fills the central trench 186 and a second conductive type region (e.g., p-type) in the second lateral section that completely fills the central trench 186 in the length direction of the trench behind the first lateral section. As a result, the polysilicon region 184 includes a pn junction extending along a plane approximately perpendicular to the main surface 102. In either case, electrical connection to various doped polysilicon can be achieved by known techniques.

[0085] Reference Figure 13 , depicts a vertical IGBT 100 according to another embodiment. This device can be similar in all respects to Figure 12 The vertical IGBT 100 is identical to that of FIG. 1 , except that it includes more than one central trench 186, wherein a polysilicon region 184 is provided in each central trench 186. The structure may be in accordance with the reference Figure 12 1 , wherein a plurality of central trenches 186 are formed adjacent to one another and separated by semiconductor mesas having similar or the same width as the intermediate semiconductor mesas 172 as previously described.

[0086] The polysilicon region 184 in the central trench 186 can be configured to serve various device functions, including reference Figure 11 and Figure 12 In one example, each polysilicon region 184 is configured as a series-connected resistor, wherein the multi-trench configuration provides a greater resistance value per unit area. Alternatively, the polysilicon regions 184 in the center trench 186 can be configured differently. For example, the center one of the polysilicon regions 184 can be connected to the gate potential or the source potential to, for example, increase resistance or capacitance, and the outer polysilicon regions 184 can be electrically floating to provide electrical shielding.

[0087] Reference Figure 14 , depicts a vertical IGBT 100 according to another embodiment. This device can be compared in all respects to the IGBT 100 except that two different polysilicon regions are provided in the central trench 186. Figure 12 The polysilicon regions are formed at different processing stages. The polysilicon region 184 in the lower region of the central trench 186 is formed simultaneously with the polysilicon forming the gate electrodes 110, 112. After partially removing the gate polysilicon, the polysilicon region 188 in the upper region of the central trench 186 is formed. A planarization step can be used to remove the two polysilicon layers formed outside the trench. This technique represents a similar process to the reference Figure 12 The described technique utilizes fewer processing steps than methods of forming a pn junction in the central trench 186 .

[0088] Reference Figure 15 , depicts a vertical IGBT 100 according to another embodiment. This device can be similar in all respects to the one in FIG. 1 , except that the mesa separation structure 132 comprises two monolithic insulating structures 176 with an auxiliary trench 192 disposed therebetween. Figure 2The vertical IGBT 100 is the same as that of FIG. 1 . The monolithic insulating structure 176 is formed to be directly connected to the auxiliary trench 192. One of the monolithic insulating structures 176 completely occupies the lateral area between the first semiconductor mesa 134 and the auxiliary trench 192. On the opposite side of the auxiliary trench 192, another of the monolithic insulating structures 176 completely extends to reach another semiconductor mesa (not shown). This pattern is repeated successively so that the gate trenches are alternately disposed between the auxiliary trenches 192. Semiconductor mesas are provided on either side of each gate trench and are configured as a vertical IGBT structure according to the operating principles described previously.

[0089] Figure 15 The device can be used to refer to Figures 3 to 8 The auxiliary trenches 192 may be formed with the same spacing and width as the second gate trenches 108 described above. Figures 3 to 5 Unlike the techniques described in , the narrow central trench 170 is formed close enough to the auxiliary trench 192 so that the insulator material reaches the sidewalls of the auxiliary trench 192 during the insulator growth process. The auxiliary trench 192 can be filled with a conductive metal or polysilicon according to the previously described techniques and can be configured to provide any of the functions of the polysilicon region 184 or the conductive region 182 as previously described.

[0090] Reference Figure 16 , depicts a vertical IGBT 100 according to another embodiment. This device can be similar in all respects to the first embodiment except that the third semiconductor mesa 194 on the opposite side of the first gate trench 106 includes a carrier extraction region 178 instead of the emitter and body regions 118, 120. Figure 2 The carrier extraction region 178 is configured as previously described with reference to Figure 9 The described approach provides a conduction path for carriers of the second conductivity type (e.g., holes). This basic unit configuration can be repeated successively so that every other gate trench includes a semiconductor mesa with a vertical IGBT region on one side and a semiconductor mesa with a carrier extraction region 178 on the other side.

[0091] Reference Figure 17 , depicts a vertical IGBT 100 according to another embodiment. This device can be similar in all respects to the first embodiment except that the mesa separation structure 132 has a sidewall that is coextensive with the first sidewall 146 of the second gate trench 108. Figure 2The same as the vertical IGBT 100 of the present invention. One advantage of this device is that it allows large contact holes to reach the planarized polysilicon within the gate trenches 106, 108. These contact holes can overlap with the adjacent mesa separation structure 132. As a result, simpler and less costly processing steps can be performed to contact the gate polysilicon. Alternatively, in devices in which the polysilicon filling the gate trenches 106, 108 is not planarized, the mesa separation structure 132 provides a region for the polysilicon that extends laterally above and covers the mesa separation structure 132. Due to the presence of the mesa separation structure 132 below the polysilicon, the contribution of the polysilicon outside the gate trench to the gate-collector capacitance is kept low.

[0092] Figure 17 The device can be used to refer to Figures 3 to 8 The described technique forms a semiconductor mesa between the second trench 108 and its closest narrow central trench 170 that is narrow enough so that it is completely consumed during the formation of the insulator layer 174 .

[0093] The vertical IGBT 100 discussed herein represents only one example of a wide variety of device types to which the presently disclosed technology may be applied. For example, other types of vertical power semiconductor devices such as diodes, insulated gate bipolar transistors, thyristors, MOSFETs, etc. may similarly include a high aspect ratio mesa structure with appropriate active device regions (e.g., source, body, anode, etc.). In a specific example, each vertical IGBT 100 described herein may be alternatively configured as a MOSFET device by omitting the collector region.

[0094] This specification refers to dopants of "first" conductivity type and "second" conductivity type. These terms refer to the majority carrier type of the doped semiconductor region. The first conductivity type can be n-type and the second conductivity type can be p-type (or vice versa). In any of the embodiments described herein, the doping types can be reversed to obtain a device that operates with a similar operating principle. For example, an n-channel device can be converted to a p-channel device by changing the first conductivity type region to the second conductivity type region, and vice versa. This specification covers all such embodiments.

[0095] As used herein, "minimum trench separation distance" refers to a process-specific design rule that defines how close two trenches can nominally be spaced laterally from each other. In semiconductor technology, design rules are often used to ensure acceptable yields. Design rules exist because the techniques used to form semiconductor features (e.g., mask lithography, etching, etc.) have inherent and unavoidable variability. Furthermore, after the semiconductor features are formed, subsequent processing steps (e.g., high-temperature steps, contact formation, back-end wiring processing, etc.) may cause further changes and variations in the geometry of the formed features. As a result, the precise geometry of any one feature to be formed may only be predicted within a statistical distribution of results. Specifically, with respect to trench formation, the lithography technique and the subsequent etching of the semiconductor material each introduce variability into the process, such that the precise dimensions of the trench to be formed (e.g., length, width, depth, etc.) may only be predicted within a specific range of the statistical distribution. This variability may be compounded by further processing steps (e.g., annealing, doping, etc.). Furthermore, the minimum trench separation distance may be limited by the minimum size of overlying structures, such as contact holes and / or metallization, used to form electrical connections to the conductive regions within the trenches. "Minimum trench separation distance," as used herein, accounts for this variation by defining the required spacing between two trenches to ensure that, within an outer range (e.g., 3σ) of statistical variation in trench geometry, such as between two adjacent trenches, the trenches are sufficiently spaced apart from one another to prevent device failure.

[0096] As used herein, the term "approximately" encompasses absolute conformance to the requirements and minor deviations from absolute conformance to the requirements due to manufacturing process variations. The term "approximately" encompasses any value within these deviations provided that the deviations are within an acceptable process window and the components described herein can function according to the application requirements.

[0097] In this specification, "first conductivity type" and "second conductivity type" refer to the majority dopant concentration of a semiconductor material that can be n-doped or p-doped. The first conductivity type and the second conductivity type are opposite conductivity types, such that the first conductivity type can refer to n-type doping, wherein the second conductivity type refers to p-type doping, or vice versa.

[0098] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" are used to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device other than those depicted in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, and the like and are not intended to be limiting. Throughout the description, like terms refer to like elements.

[0099] As used herein, the terms "having," "comprising," "including," and "comprising" are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The quantifiers "a," "an," and the pronoun "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0100] With the above scope and application in mind, it should be understood that the present invention is not limited by the foregoing description, nor by the accompanying drawings, but rather is limited only by the following claims and their legal equivalents.

Claims

1. A semiconductor device comprising: a semiconductor substrate including a main surface and a back surface opposite to the main surface; a first trench and a second trench laterally separated from one another and each extending from the major surface into the substrate; a mesa separation structure laterally between the first trench and the second trench and comprising a non-semiconductor material; a first semiconductor mesa between the first trench and the mesa separation structure, the first semiconductor mesa comprising: a first sidewall coextensive with the first sidewall of the first trench; a second sidewall directly contacting the non-semiconductor material of the mesa separation structure; a source region extending to the main surface and having a first conductivity type; a body region underlying the source region and having a second conductivity type opposite to the first conductivity type; and a drift region below the body region and having a first conductivity type; wherein an aspect ratio of the first semiconductor mesa defined by dividing the lateral width of the first semiconductor mesa by the vertical depth of the first semiconductor mesa is less than or equal to 0.2, The mesa separation structure is formed by performing an insulator growth process in at least one central trench formed between a first trench and a second trench and laterally separated from the first trench, wherein the insulator growth process fills the at least one central trench with an insulator material and consumes semiconductor material between the central trench and the first trench.

2. The semiconductor device according to claim 1, wherein A ratio between an aspect ratio of the first trench, defined by a lateral width of the first trench divided by a vertical depth of the first trench, and an aspect ratio of the first semiconductor mesa is greater than or equal to 0.

5.

3. The semiconductor device according to claim 1, wherein The semiconductor device further includes a carrier extraction region extending to the main surface and having the second conductivity type, wherein the carrier extraction region is configured to provide a conducting path for carriers of the second conductivity type flowing from the back surface to the main surface.

4. The semiconductor device according to claim 3, wherein The semiconductor device includes a second semiconductor mesa between a second trench and a mesa separation structure, wherein the second semiconductor mesa includes a first sidewall extending together with a first sidewall of the second trench, and a second sidewall directly connected to a non-semiconductor material of the mesa separation structure, and wherein a carrier extraction region is disposed in the second semiconductor mesa.

5. The semiconductor device according to claim 3, wherein The mesa separation structure comprises two monolithic insulating structures and a central semiconductor mesa disposed laterally between the two monolithic insulating structures, wherein the carrier extraction region is disposed in the central semiconductor mesa, wherein the semiconductor device comprises an emitter metallization, wherein the emitter metallization is electrically connected to the source region and the carrier extraction region, and wherein the body region is electrically disconnected from the emitter metallization. The semiconductor device according to claim 1 , wherein: The mesa separation structure includes an electrically insulating material and a conductive material, and wherein the conductive material is formed in a central region of the mesa separation structure that is insulated from the semiconductor substrate by the electrically insulating material.

7. The semiconductor device according to claim 6, wherein The mesa separation structure includes a central trench and two monolithic insulating structures disposed on either side of the central trench, and wherein the conductive material includes a polysilicon region disposed in the central trench.

8. The semiconductor device according to claim 1, wherein The semiconductor device includes an auxiliary trench disposed between the first trench and the second trench, and wherein the mesa separation structure includes a monolithic insulating structure completely occupying a lateral region between the first semiconductor mesa and the auxiliary trench.

9. The semiconductor device according to claim 1, wherein The mesa separation structure includes a monolithic insulating structure, wherein the semiconductor device further includes a contact trench formed in the monolithic insulating structure and a conductive emitter contact filling the contact trench, and wherein sidewalls of the emitter contact directly contact the emitter region and the body region.

10. A method for producing a semiconductor device, the method comprising: providing a semiconductor substrate including a main surface and a back surface opposite to the main surface, providing a first trench and a second trench, the first trench and the second trench being laterally separated from one another and each extending from the major surface into the substrate; providing a mesa separation structure laterally between the first trench and the second trench and comprising a non-semiconductor material; A first semiconductor mesa is provided between the first trench and the mesa separation structure, the first semiconductor mesa comprising: a first sidewall coextensive with the first sidewall of the first trench; a second sidewall directly contacting the non-semiconductor material of the mesa separation structure; a source region extending to the main surface and having a first conductivity type; a body region underlying the source region and having a second conductivity type opposite to the first conductivity type; and a drift region below the body region and having a first conductivity type; and wherein the first trench and the second trench are initially formed at a first trench separation distance from each other by a mask etching technique, and wherein the first semiconductor mesa is provided to have a lateral width that is less than the first trench separation distance, the lateral width of the first semiconductor mesa being the shortest distance between a first sidewall and a second sidewall of the first semiconductor mesa, The countertop partition structures provided include: forming at least one central groove between the first groove and the second groove and laterally separated from the first groove; performing an insulator growth process that fills the central trench with an insulator material and consumes the semiconductor material; and Parameters of the insulator growth process are controlled such that the insulator material consumes semiconductor material between the central trench and the first trench to further narrow the first semiconductor mesa.

11. The method according to claim 10, wherein: Provided countertop partition structure includes: forming a plurality of central trenches between the first trench and the second trench, each of the central trenches having a width smaller than a width of the first trench and the second trench; and An insulator growth process is performed such that each of the central trenches is completely filled with insulator material.

12. The method according to claim 11, wherein The plurality of central trenches are formed separated from one another by intervening semiconductor mesas, and wherein an insulator growth process is performed such that each of the intervening semiconductor mesas is completely consumed by insulator material to form a monolithic insulating structure from the plurality of central trenches.

13. The method according to claim 12, further comprising forming an auxiliary trench disposed between the first trench and the second trench, and wherein, A monolithic insulating structure is formed to completely occupy a lateral region between the first semiconductor mesa and the auxiliary trench.

14. The method according to claim 13 , further comprising forming a first gate electrode in the first gate trench, forming a second gate electrode in the second gate trench, and forming a conductive region in the auxiliary trench, wherein forming the first gate electrode, the second gate electrode and the conductive region comprises: Depositing a doped first polysilicon layer that simultaneously fills the first gate trench, the second gate trench, and the auxiliary trench using doped polysilicon; removing the doped polysilicon from the auxiliary trench; depositing an undoped second polysilicon layer in the auxiliary trench after removing the doped polysilicon from the auxiliary trench; The substrate is planarized to remove portions of the first and second polysilicon layers above the first and second gate trenches and the auxiliary trench.

15. The method according to claim 12, further comprising: forming a contact trench in the monolithic insulating structure; as well as filling the contact trench with a conductive material, thereby forming an emitter contact; The sidewalls of the emitter contact are directly connected to the emitter region and the body region.

16. The method according to claim 12, wherein A mesa separation structure is provided comprising two monolithic insulating structures and a central semiconductor mesa disposed laterally between the two monolithic insulating structures, and wherein providing the mesa separation structure comprises: providing a first plurality of central trenches, wherein each central trench of the first plurality of central trenches is formed to be separated from one another by an intervening semiconductor mesa; providing a second plurality of central trenches, wherein each central trench of the second plurality of central trenches is formed to be separated from one another by an intervening semiconductor mesa; providing permanent semiconductor mesas between the first plurality of central trenches and the second plurality of central trenches, the permanent semiconductor mesas being wider than the intermediate semiconductor mesas; and The insulator growth process is performed such that each of the intermediate semiconductor mesas is completely consumed by the insulator material and such that the permanent semiconductor mesas remain at least partially intact after the insulator growth process.

17. The method according to claim 11, wherein The first trench, the second trench, and the plurality of center trenches are simultaneously formed by a mask etching technique.

18. The method according to claim 11, wherein The first and second trenches are formed by a first mask etching step, wherein the plurality of central trenches are formed by a second mask etching step performed before or after the first mask etching step, and wherein the central trenches are formed at a different depth than the first and second trenches.

19. The method according to claim 10, wherein The first semiconductor mesa is provided such that an aspect ratio of the first semiconductor mesa is less than or equal to 0.2, wherein the aspect ratio of the first semiconductor mesa is a lateral width of the first semiconductor mesa divided by a vertical depth of the first semiconductor mesa.

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