A programmable intelligent power filter

Abstract

The present invention belongs to the field of data and signal processing technology, and specifically relates to a programmable intelligent power filter, wherein a central processing unit is respectively connected to a signal unit, a collection unit, a storage unit, and a coding control unit, and the central processing unit is respectively connected to a second switching switch I and a second switching switch II, and a power supply unit is connected to a power supply filter circuit through a first switching switch, and the power supply unit is respectively connected to a central processing unit, a signal unit, a collection unit, a storage unit, and a coding control unit, and one end of a standard load is respectively connected to a signal unit and a working mode switch through a third switching switch I. The present invention designs a combinable multi-stage common-mode and differential-mode filter circuit, which is convenient for selection according to needs; the present invention can select and configure the equivalent capacitance, inductance, and resistance parameters in the power supply filter circuit through programming, and achieves the goal of generating maximum common-mode and differential-mode insertion losses in the filter circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of data and signal processing, and in particular relates to a programmable intelligent power filter. Background Art

[0002] In the increasingly harsh electromagnetic environment, if appropriate electromagnetic protection measures are not taken, the electromagnetic interference between electronic devices will become increasingly serious, the performance of electronic devices will decline, and even the security of information will be endangered due to electromagnetic signal leakage. In order to ensure that electronic equipment can work normally in a complex electromagnetic environment without interfering with other equipment and being unaffected by the interference of other equipment, strict electromagnetic compatibility design must be carried out in terms of structure, technology, etc. in the early stage of equipment design.

[0003] At present, in terms of electromagnetic compatibility design, power filters must be added to the power supply units of electronic equipment to suppress electromagnetic noise in the power line. However, the electrical characteristic parameters of commonly used filter products cannot be adjusted and cannot adapt to changes in the environment of electronic equipment, especially electronic equipment used in important fields, such as computers, servers, network equipment, etc., whose electromagnetic emission and sensitivity requirements must meet the strict standards used by confidentiality departments and the military. The power filter is a key component for electronic equipment to suppress noise and improve the immunity of the equipment. The filter must be designed and selected according to the electromagnetic environment and load characteristics of the entire electronic equipment to achieve "targeted" and ensure that the entire electronic equipment meets relevant standards. At present, although programmable filters (such as MAX262, etc.) have appeared in the foreign market, they can only be used for ordinary signal filtering. The programmable adjustable parameters are center frequency, quality factor and working mode. It is composed of a second-order switched capacitor filter, and the filter network structure is single, without power driving capability, and cannot meet the special use requirements of the power filter. Summary of the invention

[0004] In view of the technical problem that the electrical characteristic parameters of the above-mentioned filter cannot be adjusted and cannot adapt to changes in the electronic equipment environment, the present invention provides a programmable intelligent power filter with strong anti-interference ability, high degree of automation and high efficiency.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A programmable intelligent power filter comprises a power filter circuit, a control system, a working mode switch, and a load. The working mode switch is connected to the power filter circuit through the control system. The control system comprises a central processing unit, a signal unit, a collection unit, a storage unit, a coding control unit, a power supply unit, a standard load, a first switching switch, a second switching switch I, a second switching switch II, a third switching switch I, and a third switching switch II. The central processing unit is respectively connected to the signal unit, the collection unit, the storage unit, and the coding control unit. The central processing unit is respectively connected to the second switching switch I and the second switching switch II. The power supply unit is connected to the power supply through the first switching switch. The filter circuit is connected, the power supply unit is respectively connected with the central processing unit, the signal unit, the acquisition unit, the storage unit, and the encoding control unit, one end of the standard load is respectively connected with the signal unit and the working mode switch through the third switching switch I, the other end of the standard load is respectively connected with the acquisition unit and the working mode switch through the third switching switch II, one end of the load is respectively connected with the power filter circuit and the signal unit through the second switching switch I, the other end of the load is respectively connected with the power filter circuit and the acquisition unit through the second switching switch II, and the working mode switch is respectively connected with the central processing unit, the first switching switch, the third switching switch I, and the third switching switch II.

[0007] The power supply filter circuit includes a capacitor array, a first-level common-mode inductor array, a second-level common-mode inductor array, a differential-mode inductor array, and a resistor array. The capacitor array includes a first-level differential-mode capacitor array, a second-level differential-mode capacitor array, a third-level differential-mode capacitor array, a first-level common-mode capacitor array, and a second-level common-mode capacitor array. The two ends of the first-level differential-mode capacitor array are respectively connected to an input live wire and an input neutral wire. The two ends of the first-level differential-mode capacitor array are respectively connected to the two ends of the first-level common-mode inductor array. The two ends of the first-level common-mode inductor array are connected in parallel with a second-level differential-mode capacitor array. The two ends of the second-level differential-mode capacitor array are connected in parallel with a resistor array. , the two ends of the resistor array are connected in parallel with the first-level common-mode capacitor array, the two ends of the first-level common-mode capacitor array are connected in parallel with the second-level common-mode inductor array, the two ends of the second-level common-mode inductor array are connected in parallel with the differential-mode inductor array, the two ends of the differential-mode inductor array are connected in parallel with the third-level differential-mode capacitor array, the two ends of the third-level differential-mode capacitor array are connected in parallel with the second-level common-mode capacitor array, the second-level common-mode capacitor array is connected to the two ends of the standard load through the second switching switch I and the second switching switch II respectively, the two ends of the standard load are connected to the output live wire and the output neutral wire respectively, and the first-level common-mode capacitor array and the second-level common-mode capacitor array are both connected to the ground wire.

[0008] The capacitor array includes n capacitors and n first switch tubes, where n≥2, the n capacitors are connected in parallel, and each capacitor is connected in series with a first switch tube; when the first switch tube is in a closed state, the capacitors in the capacitor array are connected to the capacitor array circuit and are in a working state; when the first switch tube is in an open state, the capacitors in the capacitor array are not connected to the capacitor array circuit and are in a non-working state; the closing or opening of the first switch tube of the capacitor array is determined by the output signal of the encoding control unit.

[0009] The first-stage common-mode inductor array and the second-stage common-mode inductor array both include 2n first inductor coils, 2n second switch tubes I, and two second switch tubes II, wherein n≥2, the 2n first inductor coils are paired in pairs to form n common-mode inductors, the n common-mode inductors are connected in parallel, the two second switch tubes II are connected in series to the live line of the filter and the neutral line of the filter respectively, the two second switch tubes II are connected in parallel to the common-mode inductors, each first inductor coil is connected in series to a second switch tube I, and the two ends of the n common-mode inductors are connected to the live line of the filter and the neutral line of the filter respectively; When the two switch tubes I are in a closed state, the first inductor coil is connected to the first-level common-mode inductor array or the second-level common-mode inductor array circuit and is in a working state; when the second switch tube I is in an open state, the first inductor coil is not connected to the first-level common-mode inductor array or the second-level common-mode inductor array circuit and is in a non-working state; when the two second switch tubes II are turned on and closed, the first-level common-mode inductor array or the second-level common-mode inductor array has no inductance characteristics, which is reflected in a conduction state with impedance close to zero; the closing or opening of the second switch tube I is determined by the output signal of the encoding control unit.

[0010] The differential mode inductor array includes 2n second inductor coils, 2n third switch tubes I, and two third switch tubes II, wherein n≥2, and the 2n second inductor coils are paired in pairs to form n differential mode inductors, the n differential mode inductors are connected in parallel, the two third switch tubes II are respectively connected in series to the live line of the filter and the neutral line of the filter, the two third switch tubes II are both connected in parallel to the differential mode inductor, each second inductor coil is connected in series to a third switch tube I, and the two ends of the n differential mode inductors are respectively connected to the live line of the filter and the neutral line of the filter; when the third switch tube I is in a closed state, the second inductor coil is connected to the differential mode inductor array circuit and is in a working state; when the third switch tube I is in an open state, the second inductor coil is not connected to the differential mode inductor array circuit and is in a non-working state; when the two third switch tubes II are turned on and closed, the differential mode inductor array has no inductance characteristics, which is reflected in a conduction state with impedance close to zero; the closing or opening of the third switch tube I is determined by the output signal of the encoding control unit.

[0011] The resistor array includes n resistors and n fourth switch tubes, where n≥2, the n resistors are connected in parallel, and each resistor is connected in series with a fourth switch tube; when the fourth switch tube is in a closed state, the resistors in the resistor array are connected to the resistor array circuit and are in a working state; when the fourth switch tube is in an open state, the resistors in the resistor array are not connected to the resistor array circuit and are in a non-working state; the closing or opening of the fourth switch tube of the resistor array is determined by the output signal of the encoding control unit.

[0012] The encoding control unit is respectively connected to a first-level differential mode capacitor array, a second-level differential mode capacitor array, a third-level differential mode capacitor array, a first-level common mode inductor array, a second-level common mode inductor array, a differential mode inductor array, a first-level common mode capacitor array, a second-level common mode capacitor array, and a resistor array.

[0013] The power supply unit is respectively connected to an input live wire and an input neutral wire through a first switching switch, and the power supply unit converts 220V alternating current of the input live wire into 5V direct current.

[0014] The central processing unit adopts a high-performance single-chip microcomputer or an ARM processor, the acquisition unit adopts an analog-to-digital conversion circuit, and the standard load adopts a 50-ohm standard resistor.

[0015] The encoding control unit outputs an encoding signal through a central processing unit, and the encoding signal adopts binary encoding.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The present invention designs a combinable multi-stage common-mode and differential-mode filter circuit, which is convenient for selection according to needs; the present invention can select and configure the equivalent capacitance, inductance and resistance parameters in the power filter circuit through programming, thereby achieving the goal of generating maximum common-mode and differential-mode insertion losses in the filter circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a circuit principle structure diagram of the present invention;

[0019] Figure 2 is a schematic diagram of a capacitor array of the present invention;

[0020] Figure 3 It is the principle diagram of the common mode inductor array of the present invention;

[0021] Figure 4 It is a schematic diagram of the differential mode inductor array of the present invention;

[0022] Figure 5This is a schematic diagram of the resistor array of the present invention.

[0023] Among them: 1 is the power filter circuit, 2 is the control system, 3 is the working mode switch, ZL is the load, 201 is the central processing unit, 202 is the signal unit, 203 is the acquisition unit, 204 is the storage unit, 205 is the encoding control unit, 206 is the power supply unit, Z0 is the standard load, K1 is the first switch, K2-1 is the second switch I, K2-2 is the second switch II, K3-1 is the third switch I, K3-2 is the third switch II, CX1 is the first-level differential mode capacitor array, CX2 is the second-level differential mode capacitor array, CX3 is the third-level differential mode capacitor array, L1 is the first-level common mode inductor array, L2 is the second-level common mode inductor array, L3 is the differential mode inductor array, CY1 is the first-level common mode capacitor array, CY2 is the second-level common mode capacitor array, R1 is the resistor array, P is the input live wire, N is the input neutral wire, P′ is the output live wire, N′ is the output neutral wire, P2 is the filter live wire, and N2 is the filter neutral wire. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] A programmable intelligent power filter, such as Figure 1As shown, it includes a power filter circuit 1, a control system 2, a working mode switch 3, and a load ZL. The working mode switch 3 is connected to the power filter circuit 1 through the control system 2. The working mode switch 3 is provided to the user to manually set its working state. The control system 2 includes a central processing unit 201, a signal unit 202, a collection unit 203, a storage unit 204, a coding control unit 205, a power unit 206, a standard load Z0, a first switching switch K1, a second switching switch I K2-1, a second switching switch II K2-2, a third switching switch I K3-1, and a third switching switch II K3-2. The central processing unit 201 is respectively connected to the signal unit 202, the collection unit 203, the storage unit 204, and the coding control unit 205. The power supply unit 206 is connected to the power supply filter circuit 1 through the first switching switch K1. The power supply unit 206 is respectively connected to the central processing unit 201, the signal unit 202, the acquisition unit 203, the storage unit 204, and the encoding control unit 205. The signal unit 205 is a circuit that can generate a variety of waveforms (including sine waves, square waves, triangle waves, etc.), and the frequency, amplitude, pulse width, duty cycle and other parameters of the waveform can be controlled by the central processing unit 201. One end of the standard load Z0 is connected to the signal unit 202 and the working mode switch 3 through the third switching switch IK3-1, and the other end of the standard load Z0 is connected to the acquisition unit 203 and the working mode switch 3 through the third switching switch IIK3-2. One end of the load ZL is connected to the power supply filter circuit 1 and the signal unit 202 through the second switching switch IK2-1, and the other end of the load ZL is connected to the power supply filter circuit 1 and the acquisition unit 203 through the second switching switch IIK2-2. The working mode switch 3 is connected to the central processing unit 201, the first switching switch K1, the third switching switch IK3-1, and the third switching switch IIK3-2.The present invention uses a single-phase AC power supply as an input signal (for example, AC220V). The input end of the power filter circuit 1 includes an input live wire P, an input neutral wire N and a ground wire E. The ground wire E is used to connect the housing of the device and the earth. The input live wire P and the input neutral wire N pass through the filter device power filter circuit 1 of the filter to the output live wire P' and the output neutral wire N' and are then used to connect the load ZL. From the perspective of the device or product, a group of working mode switches 3 are designed, and the user can manually switch this group of working mode switches as needed. The d1 in the working mode switch 3 is used to control (set) the closed or open state of the first switching switch K1 at the input end of the power supply unit. When the first switching switch K1 is set to a closed state through d1, the input live wire P and the input neutral wire N of the power supply filter circuit 1 are connected to the power supply unit 206, and the power supply unit 206 converts the AC power into a low DC voltage (for example, DC5V). This DC power provides working power for the central processing unit 201, the signal unit 202, the acquisition unit 203, the storage unit 204, the encoding control unit 205, etc.; when K1 is set to a disconnected state through d1, the central processing unit 201, the signal unit 202, the acquisition unit 203, the storage unit 204, and the encoding control unit 205 are in an unpowered state, and the power supply filter is in an offline working mode.

[0026] The offline working mode means that after the programming working mode is completed, the control coding signal aki (i=1,2…9) output by the coding control unit 205 has been locked and maintained, and the coding control unit 205 adopts a non-volatile latch circuit device to achieve the retention of the coding data after power failure; in the offline working mode, the first switching switch K1 of the power supply unit 206 is controlled by d1 in the working mode switch 3, and the storage unit adopts a non-volatile storage device to achieve the retention of the programming data after power failure.

[0027] D3 in the working mode switch 3 is a plurality of rotary switches (dip switches), and different working modes are set by combining the dip switch codes. The central processing unit 201 reads the dip switch codes to set the working mode of the power supply filter. The working modes include calibration working mode, programming working mode, filtering working mode, etc.;

[0028] In this embodiment, the dip switches are coded by 4 bits as follows, but are not limited to these combinations.

[0029]

[0030]

[0031] Further, the power supply filter circuit 1 includes a capacitor array, a first-stage common-mode inductor array L1, a second-stage common-mode inductor array L2, a differential-mode inductor array L3, and a resistor array R1. The capacitor array includes a first-stage differential-mode capacitor array CX1, a second-stage differential-mode capacitor array CX2, a third-stage differential-mode capacitor array CX3, a first-stage common-mode capacitor array CY1, and a second-stage common-mode capacitor array CY2. The two ends of the first-stage differential-mode capacitor array CX1 are respectively connected to the input live line P and the input neutral line N. The two ends of the first-stage differential-mode capacitor array CX1 are respectively connected to the two ends of the first-stage common-mode inductor array L1. The two ends of the first-level common-mode inductor array L1 are connected in parallel with the second-level differential-mode capacitor array CX2, the two ends of the second-level differential-mode capacitor array CX2 are connected in parallel with the resistor array R1, the two ends of the resistor array R1 are connected in parallel with the first-level common-mode capacitor array CY1, the two ends of the first-level common-mode capacitor array CY1 are connected in parallel with the second-level common-mode inductor array L2, the two ends of the second-level common-mode inductor array L2 are connected in parallel with the differential-mode inductor array L3, the two ends of the differential-mode inductor array L3 are connected in parallel with the third-level differential-mode capacitor array CX3, and the two ends of the third-level differential-mode capacitor array CX3 are connected in parallel with the second-level common-mode capacitor array CY2.

[0032] Furthermore, the capacitor array is composed of a number of capacitors and control switches, the inductor array is composed of a number of inductors and control switches, and the resistor array is composed of a number of resistors and control switches; when the control switch is in a closed state, the capacitor, inductor and resistor components in the corresponding loop are connected to the array circuit and are in a working state; when the control switch is in an open state, the capacitor, inductor and resistor components in the corresponding loop are not connected to the array circuit and are in a non-working state; the closing or opening (on or off) of the control switches in the capacitor array, the inductor array and the resistor array is determined by the output signal of the encoding control unit 205.

[0033] Further, the capacitor array includes n capacitors and n first switch tubes, n≥2, the n capacitors are connected in parallel, and each capacitor is connected in series with a first switch tube; when the first switch tube is in a closed state, the capacitors in the capacitor array are connected to the capacitor array circuit and are in a working state; when the first switch tube is in an open state, the capacitors in the capacitor array are not connected to the capacitor array circuit and are in a non-working state; the closing or opening of the first switch tube of the capacitor array is determined by the output signal of the encoding control unit 205. Figure 2As shown, the capacitor array is composed of n capacitors C1, C2, ... Cn and n switch tubes T1, T2, ... Tn, and the switch tubes are not limited to selecting transistors, micro-electromechanical switches, solid-state relays and other devices; these n capacitors adopt a parallel circuit relationship, when the control signal aki (i = 1, 2 ... n) of the switch tube Ti (i = 1, 2 ... n) is effective, Ti is turned on and closed, and the capacitor Ci in the corresponding loop is connected to the external connection line 1c end and the connection line 2c end of the capacitor array; the external equivalent capacitance of this capacitor array is reflected in different combinations of capacitances between the connection line 1c end and the connection line 2c end, and the calculation of the equivalent capacitance follows the basic circuit principle and is not explained here; in the present invention, n is at least greater than 1, but the size of n is not limited.

[0034] Further, the first-stage common-mode inductor array L1 and the second-stage common-mode inductor array L2 each include 2n first inductor coils, 2n second switch tubes I, and two second switch tubes II, where n≥2, and the 2n first inductor coils are paired in pairs to form n common-mode inductors, the n common-mode inductors are connected in parallel, the two second switch tubes II are respectively connected in series to the live line P2 of the filter and the neutral line N2 of the filter, the two second switch tubes II are both connected in parallel to the common-mode inductors, each first inductor coil is connected in series with a second switch tube I, and the two ends of the n common-mode inductors are respectively connected to the live line P2 of the filter and the neutral line N2 of the filter; the second When the switch tube I is in the closed state, the first inductor coil is connected to the first-stage common-mode inductor array L1 or the second-stage common-mode inductor array L2 circuit and is in the working state; when the second switch tube I is in the open state, the first inductor coil is not connected to the first-stage common-mode inductor array L1 or the second-stage common-mode inductor array L2 circuit and is in the non-working state; when the two second switch tubes II are turned on and closed, the first-stage common-mode inductor array L1 or the second-stage common-mode inductor array L2 has no inductance characteristics, which is reflected in the conduction state with impedance close to zero; the closing or opening of the second switch tube I is determined by the output signal of the encoding control unit 205. Figure 3As shown in the schematic diagram of the common-mode inductor array, the common-mode inductor array is composed of 2*n inductors L11, L12, L21, L22...Ln1 and Ln2 and 2*(n+1) switches T01, T02, T11, T12, T21, T22,...Tn1 and Tn2, wherein the switches are not limited to selecting transistors, micro-electromechanical switches, solid-state relays and other devices; wherein the 2*n inductors are paired with n pairs of inductors, for example, the inductor L11 and the inductor L12 constitute a group of common-mode inductors, and the winding method of the common-mode inductor is not explained here. In this case, n groups of common-mode inductors are connected in parallel. When the control signal aki (i=1, 2…n) is valid, the corresponding switch tubes Ti1 and Ti2 (i=1, 2…n) are turned on and closed, and the common-mode inductors Li1 and Li2 (i=1, 2…n) in the corresponding loops are respectively connected to the live and neutral loops of the power filter. The equivalent inductance of the common-mode inductor array to the outside is reflected in the output coding of the control signal aki (i=1, 2…n) to achieve a combination of different common-mode inductors; in the present invention, when only the control signal ak0 is valid, the corresponding switch tubes T01 and T02 are turned on and closed, and the common-mode inductor array has no inductance characteristics, which is reflected in the conduction state with impedance close to zero.

[0035] Further, the differential mode inductor array L3 includes 2n second inductor coils, 2n third switch tubes I, and two third switch tubes II, n≥2, the 2n second inductor coils are paired in pairs to form n differential mode inductors, the n differential mode inductors are connected in parallel, the two third switch tubes II are respectively connected in series to the live line P2 of the filter and the neutral line N2 of the filter, the two third switch tubes II are connected in parallel to the differential mode inductor, each second inductor coil is connected in series with a third switch tube I, and the two ends of the n differential mode inductors are respectively connected to the live line P2 of the filter and the neutral line N2 of the filter. P2, filter neutral line N2; when the third switch tube I is in the closed state, the second inductor coil is connected to the differential mode inductor array L3 circuit and is in the working state; when the third switch tube I is in the open state, the second inductor coil is not connected to the differential mode inductor array L3 circuit and is in the non-working state; when the two third switch tubes II are turned on and closed, the differential mode inductor array L3 has no inductance characteristics, which is reflected in the conduction state with impedance close to zero; the closing or opening of the third switch tube I is determined by the output signal of the encoding control unit 205. Figure 4As shown, the differential mode inductor array is composed of 2*n inductors L11, L12, L21, L22 ... Ln1 and Ln2 and 2*(n+1) switch tubes T01, T02, T11, T12, T21, T22, ... Tn1 and Tn2, and the switch tubes are not limited to selecting transistors, micro-electromechanical switches, solid-state relays and other devices; wherein, the 2*n inductors are paired with n pairs of inductors, for example, the inductor L11 and the inductor L12 constitute a group of differential mode inductors, and the winding method of the differential mode inductor is not explained here. In this case, n groups of differential-mode inductors are connected in parallel. When the control signal aki (i=1,2…n) is valid, the corresponding switch tubes Ti1 and Ti2 (i=1,2…n) are turned on and closed, and the differential-mode inductors Li1 and Li2 (i=1,2…n) in the corresponding loop are respectively connected to the live and neutral loops of the power filter. The external equivalent inductance of the differential-mode inductor array is reflected in the output coding of the control signal aki (i=1,2…n) to achieve the combination of different differential-mode inductors; in this case, when only the control signal ak0 is valid, the corresponding switch tubes T01 and T02 are turned on and closed, and the differential-mode inductor array has no inductance characteristics, which is reflected in the conduction state with impedance close to zero. Differential-mode inductor array composition and principle and Figure 3 The common-mode inductor array is similar, but the difference is that the n pairs of inductor coils in the differential-mode inductor array are paired in pairs to form n groups of differential-mode inductors.

[0036] Further, the resistor array R1 includes n resistors and n fourth switch tubes, n≥2, the n resistors are connected in parallel, and each resistor is connected in series with a fourth switch tube; when the fourth switch tube is in a closed state, the resistors in the resistor array R1 are connected to the resistor array R1 circuit and are in a working state; when the fourth switch tube is in an open state, the resistors in the resistor array R1 are not connected to the resistor array R1 circuit and are in a non-working state; the closing or opening of the fourth switch tube of the resistor array R1 is determined by the output signal of the encoding control unit 205. Figure 5 As shown, the resistor array schematic diagram, this resistor array is composed of n resistors R1, R2, ... Rn and n switch tubes T1, T2, ... Tn, and the switch tubes are not limited to select transistors, micro-electromechanical switches, solid-state relays and other devices; these n resistors adopt a parallel circuit relationship, when the control signal aki (i = 1, 2 ... n) of the switch tube Ti (i = 1, 2 ... n) is effective, Ti is turned on and closed, and the resistor Ri in the corresponding loop is connected between the connecting line 1r end and the connecting line 2r end of the resistor array; the equivalent resistance of this resistor array to the outside is reflected in the different combinations of resistances between the connecting line 1r end and the connecting line 2r end, and the calculation of the equivalent resistance follows the basic circuit principle; in the present invention, n is at least greater than 1, but the size of n is not limited.

[0037] Furthermore, the second-stage common-mode capacitor array CY2 is connected to both ends of the standard load Z0 through the second switch IK2-1 and the second switch IIK2-2 respectively.

[0038] Furthermore, two ends of the standard load Z0 are connected to an output live wire P′ and an output neutral wire N′ respectively.

[0039] Furthermore, the first-stage common-mode capacitor array CY1 and the second-stage common-mode capacitor array CY2 are both connected to a ground line E.

[0040] Furthermore, the encoding control unit 205 is respectively connected to the first-level differential mode capacitor array CX1, the second-level differential mode capacitor array CX2, the third-level differential mode capacitor array CX3, the first-level common mode inductor array L1, the second-level common mode inductor array L2, the differential mode inductor array L3, the first-level common mode capacitor array CY1, the second-level common mode capacitor array CY2, and the resistor array R1.

[0041] Furthermore, the power supply unit 206 is respectively connected to the input live line P and the input neutral line N through the first switch K1 , and the power supply unit 206 converts the 220V AC power of the input live line P into 5V DC power.

[0042] Furthermore, the first-stage common-mode capacitor array CY1 and the second-stage common-mode capacitor array CY2 are paired in an upper and lower pairing manner.

[0043] Furthermore, the central processing unit 201 adopts a high-performance single-chip microcomputer or an ARM processor, the acquisition unit 203 adopts an analog-to-digital conversion circuit, and the standard load Z0 adopts a 50-ohm standard resistor.

[0044] Furthermore, the encoding control unit 205 outputs an encoding signal through the central processing unit 201, and the encoding signal adopts binary encoding.

[0045] The workflow of the present invention is:

[0046] Step 1, the central processing unit first sends a control signal bk1, and the control signal bk1 passes through the second switching switch I and the second switching switch II, so that the two ends of the load are disconnected from the output live wire and the neutral wire respectively, so that one end of the load is switched to the signal unit and the other end of the load is switched to the acquisition unit;

[0047] Step 2, the central processing unit first sends a control signal bk2, the control signal bk2 starts the signal unit, the signal unit sends a signal s1, and the signal s1 becomes a signal s2 after passing through the load;

[0048] Step 3, the central processing unit sends a control signal bk3, the control signal bk3 starts the acquisition unit, the acquisition unit acquires the s2 signal and sends the acquired data to the central processing unit;

[0049] Step 4: The central processing unit performs digital signal processing on the signal s1 and the signal s2 to obtain the impedance value of the load, and stores the impedance value of the load in the storage unit as a basis for the parameters of the power supply filter circuit;

[0050] Step 5, the central processing unit reads the switch code of the coding control unit to set the working mode of the power supply filter circuit. When the working mode is the programming working mode, the equivalent circuit structure of the power supply filter circuit is determined at the same time. The equivalent circuit includes: one-stage common mode filtering, two-stage common mode filtering, one-stage common mode and one-stage differential mode filtering, and two-stage common mode and one-stage differential mode filtering;

[0051] Step 6: The central processing unit determines the equivalent transfer function based on the equivalent circuit, and further determines the number of equivalent capacitance and equivalent inductance that need to be calculated;

[0052] Step 7. After obtaining the impedance value of the load, the coding control unit is programmed to calculate the equivalent capacitance, equivalent inductance and equivalent resistance value theory of the capacitor array, inductor array and resistor array. The central processing unit calculates and outputs the coding signal to the coding control unit based on the best matching principle. The coding control unit converts the coding signal into aki (i = 1, 2...9) to realize the programming method to set the circuit parameters of the filter circuit.

[0053] In the present invention, the working mode switch uses a manual method to set the working state of the filter, but is not limited to this method. The working mode of the filter can also be set in various ways such as connecting other control devices through various interfaces, other devices issuing working mode commands or remotely controlled by a remote device.

[0054] The principle structure diagram of a programmable intelligent power filter of the present invention is illustrated by filtering in a single-phase AC power supply environment. At the same time, the present invention is not only applicable to a single-phase AC power supply, but also to a three-phase AC power supply (including a three-phase three-wire system and a three-phase four-wire system). Similarly, the principle and method of the present invention are also applicable to a DC power supply filter; in addition, an overcurrent protection circuit, a surge protection circuit, etc. can be added to the filter circuit as needed, which will not be described in detail here.

[0055] Only the preferred embodiments of the present invention are described in detail above, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention, and various changes should be included in the protection scope of the present invention.

Claims

1. A programmable intelligent power filter, characterized in that: The invention comprises a power filter circuit (1), a control system (2), a working mode switch (3), and a load (ZL). The working mode switch (3) is connected to the power filter circuit (1) through the control system (2). The control system (2) comprises a central processing unit (201), a signal unit (202), a collection unit (203), a storage unit (204), a coding control unit (205), a power supply unit (206), a standard load (Z0), a first switching switch (K1), a second switching switch I (K2-1), a second switching switch II (K2-2), a third switching switch I (K3-1), and a third switching switch II (K3-2). The central processing unit (201) is connected to the signal unit (202), the collection unit (203), the storage unit (204), and the coding control unit (205) respectively. The central processing unit (201) is connected to the second switching switch I (K2-1) and the second switching switch II (K2-2) respectively. The power supply unit (206) is connected to the power filter circuit (1) through the first switching switch (K1). The circuit (1) is connected, the power supply unit (206) is respectively connected to the central processing unit (201), the signal unit (202), the collection unit (203), the storage unit (204), and the encoding control unit (205), one end of the standard load (Z0) is respectively connected to the signal unit (202) and the working mode switch (3) through a third switching switch I (K3-1), and the other end of the standard load (Z0) is respectively connected to the collection unit (203), the working mode switch (3) through a third switching switch II (K3-2). mode switch (3), one end of the load (ZL) is respectively connected to the power filter circuit (1) and the signal unit (202) through the second switch I (K2-1), the other end of the load (ZL) is respectively connected to the power filter circuit (1) and the acquisition unit (203) through the second switch II (K2-2), and the working mode switch (3) is respectively connected to the central processing unit (201), the first switch (K1), the third switch I (K3-1), and the third switch II (K3-2); The power supply filter circuit (1) comprises a capacitor array, a first-stage common-mode inductor array (L1), a second-stage common-mode inductor array (L2), a differential-mode inductor array (L3), and a resistor array (R1); the capacitor array comprises a first-stage differential-mode capacitor array (CX1), a second-stage differential-mode capacitor array (CX2), a third-stage differential-mode capacitor array (CX3), a first-stage common-mode capacitor array (CY1), and a second-stage common-mode capacitor array (CY2); two ends of the first-stage differential-mode capacitor array (CX1) are respectively connected to an input live line (P) and an input neutral line (N); two ends of the first-stage differential-mode capacitor array (CX1) are respectively connected to two ends of the first-stage common-mode inductor array (L1); two ends of the first-stage common-mode inductor array (L1) are connected in parallel to a second-stage differential-mode capacitor array (CX2); two ends of the second-stage differential-mode capacitor array (CX2) are connected in parallel to a resistor array (R1); A first-stage common-mode capacitor array (CY1) is connected in parallel to both ends of the resistor array (R1), a second-stage common-mode inductor array (L2) is connected in parallel to both ends of the first-stage common-mode capacitor array (CY1), a differential-mode inductor array (L3) is connected in parallel to both ends of the second-stage common-mode inductor array (L2), a third-stage differential-mode capacitor array (CX3) is connected in parallel to both ends of the differential-mode inductor array (L3), a second-stage common-mode capacitor array (CY2) is connected in parallel to both ends of the third-stage differential-mode capacitor array (CX3), the second-stage common-mode capacitor array (CY2) is connected to both ends of a standard load (Z0) through a second switching switch I (K2-1) and a second switching switch II (K2-2), the two ends of the load (ZL) are connected to an output live line (P′) and an output neutral line (N′), and the first-stage common-mode capacitor array (CY1) and the second-stage common-mode capacitor array (CY2) are both connected to a ground line (E); The first-stage common-mode inductor array (L1) and the second-stage common-mode inductor array (L2) both include 2n first inductor coils, 2n second switch tubes I, and two second switch tubes II, wherein n≥2, the 2n first inductor coils are paired in pairs to form n common-mode inductors, the n common-mode inductors are connected in parallel, the two second switch tubes II are respectively connected in series to the live line (P2) and the neutral line (N2) of the filter, the two second switch tubes II are both connected in parallel to the common-mode inductors, each first inductor coil is connected in series to a second switch tube I, and the two ends of the n common-mode inductors are respectively connected to the live line (P2) and the neutral line (N2) of the filter; the second switch tube I is connected to the When in a closed state, the first inductor coil is connected to the first-stage common-mode inductor array (L1) or the second-stage common-mode inductor array (L2) circuit and is in a working state; when the second switch tube I is in an open state, the first inductor coil is not connected to the first-stage common-mode inductor array (L1) or the second-stage common-mode inductor array (L2) circuit and is in a non-working state; when the two second switch tubes II are turned on and closed, the first-stage common-mode inductor array (L1) or the second-stage common-mode inductor array (L2) has no inductance characteristic, which is reflected in a conduction state with impedance close to zero; the closing or opening of the second switch tube I and the second switch tube II is determined by the output signal of the encoding control unit (205); The differential mode inductor array (L3) comprises 2n second inductor coils, 2n third switch tubes I, and two third switch tubes II, wherein n≥2, and the 2n second inductor coils are paired in pairs to form n differential mode inductors, the n differential mode inductors are connected in parallel, the two third switch tubes II are respectively connected in series to the live line (P2) and the neutral line (N2) of the filter, the two third switch tubes II are both connected in parallel to the differential mode inductor, each second inductor coil is connected in series to a third switch tube I, and the two ends of the n differential mode inductors are respectively connected to the live line (P2) and the neutral line (N2) of the filter; when the third switch tube I is in a closed state, the second inductor coil is connected to the differential mode inductor array (L3) circuit and is in a working state; when the third switch tube I is in an open state, the second inductor coil is not connected to the differential mode inductor array (L3) circuit and is in a non-working state; When the two third switch tubes II are turned on and closed, the differential mode inductor array (L3) has no inductance characteristics, which is reflected in the conduction state with impedance close to zero; The closing or opening of the third switch tube I and the third switch tube II is determined by the output signal of the encoding control unit (205).

2. A programmable intelligent power filter according to claim 1, characterized in that: The capacitor array comprises n capacitors and n first switch tubes, wherein n≥2, the n capacitors are connected in parallel, and each capacitor is connected in series with a first switch tube; when the first switch tube is in a closed state, the capacitors in the capacitor array are connected to the capacitor array circuit and are in a working state; when the first switch tube is in an open state, the capacitors in the capacitor array are not connected to the capacitor array circuit and are in a non-working state; the closing or opening of the first switch tube of the capacitor array is determined by an output signal of an encoding control unit (205).

3. A programmable intelligent power filter according to claim 1, characterized in that: The resistor array (R1) comprises n resistors and n fourth switch tubes, wherein n is greater than or equal to 2, the n resistors are connected in parallel, and each resistor is connected in series with a fourth switch tube; when the fourth switch tube is in a closed state, the resistors in the resistor array (R1) are connected to the resistor array (R1) circuit and are in a working state; when the fourth switch tube is in an open state, the resistors in the resistor array (R1) are not connected to the resistor array (R1) circuit and are in a non-working state; the closing or opening of the fourth switch tube of the resistor array (R1) is determined by an output signal of an encoding control unit (205).

4. The programmable intelligent power filter according to claim 1, characterized in that: The encoding control unit (205) is respectively connected to a first-stage differential mode capacitor array (CX1), a second-stage differential mode capacitor array (CX2), a third-stage differential mode capacitor array (CX3), a first-stage common mode inductor array (L1), a second-stage common mode inductor array (L2), a differential mode inductor array (L3), a first-stage common mode capacitor array (CY1), a second-stage common mode capacitor array (CY2), and a resistor array (R1).

5. The programmable intelligent power filter according to claim 1, characterized in that: The power supply unit (206) is respectively connected to an input live wire (P) and an input neutral wire (N) via a first switching switch (K1), and the power supply unit (206) converts 220V alternating current of the input live wire (P) into 5V direct current.

6. The programmable intelligent power filter according to claim 1, characterized in that: The central processing unit (201) adopts a high-performance single-chip microcomputer or an ARM processor, the acquisition unit (203) adopts an analog-to-digital conversion circuit, and the standard load (Z0) adopts a 50-ohm standard resistor.

7. The programmable intelligent power filter according to claim 1, characterized in that: The coding control unit (205) outputs a coding signal through the central processing unit (201), and the coding signal adopts binary coding.

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