Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. There is room for improvement in data transmission for reduction of operating current flowing on a signal bus and correct acquisition of a large amount of data. Each of data, a first clock signal, and a second clock signal has an amplitude smaller than an amplitude of a power supply voltage, a phase of the second clock signal is shifted from the first clock signal by a predetermined amount, and each of the semiconductor device and a memory device performs input of data in synchronization with a rising edge of the first clock signal and a rising edge of the second clock signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Japanese Patent Application No. 2019-188734, filed on October 15, 2019, the contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to semiconductor systems. For example, this invention relates to a semiconductor system in which data is transferred between a memory and a system-on-a-chip device, each of which is made of a single chip of silicon. Background Technology

[0004] AI (Artificial Intelligence) and System-on-Chip (SoC) devices used in cognitive applications require the integration of neural network-compatible functionalities (such as large-scale multiply-accumulate (add) computation circuitry) to process massive amounts of data simultaneously. The necessity of repeatedly writing / reading large amounts of data necessitates high-speed information such as neural network weights and large-capacity memory configurations in broadband environments. Furthermore, increased power consumption during operation has become a concern. Therefore, reducing the current-consuming signal bus operation current within memory chips or SoC chips is even more critical.

[0005] Japanese Patent Application Publication No. 2007-208616 (Patent Document 1) describes a semiconductor system that receives and latches data using a multiphase clock signal. Summary of the Invention

[0006] However, the semiconductor system described in Patent Document 1 has room for improvement in terms of reducing the operating current flowing on the signal bus and correctly acquiring large amounts of data during data transmission.

[0007] One objective of this embodiment is to enhance the reliability of high-speed data transmission operations by reducing the current consumption of the semiconductor system. Other objectives and novel features will become apparent from the description and accompanying drawings.

[0008] A semiconductor system according to one embodiment includes: a semiconductor device having a central processing unit and logic circuitry formed on a semiconductor chip; and a memory device formed on the semiconductor chip, wherein each of the semiconductor device and the memory device includes a driver circuitry and a receiver circuitry. The driver circuitry outputs: data (having an amplitude lower than the amplitude of a power supply voltage applied to the driver circuitry), a first clock signal, and a second clock signal, the phase of the second clock signal being shifted from the first clock signal by a predetermined amount, and the receiver circuitry inputs data synchronously with the rising edges of the first and second clock signals.

[0009] In a semiconductor system according to one embodiment, the operating current on the signal bus can be reduced, and the reliability of high-speed data transmission operation can be improved. Attached Figure Description

[0010] Figure 1 This is a data transmission diagram of the first embodiment;

[0011] Figure 2 It is a waveform diagram of the signal generated using the first embodiment;

[0012] Figure 3 This is a data transmission diagram of the second embodiment;

[0013] Figure 4 This is a diagram showing the data transmission waveform generated when using a four-phase clock signal;

[0014] Figure 5 This is a data transmission diagram illustrating signal transmission at low amplitude using a low-voltage power supply circuit in the third embodiment;

[0015] Figure 6 This is a circuit diagram of a low-amplitude driver circuit that is subjected to a low voltage.

[0016] Figure 7 yes Figure 6 The operating waveform diagram of the low amplitude driver circuit;

[0017] Figure 8 This is a data transmission diagram generated when a P-type MOSFET is used in the output circuit in the fourth embodiment;

[0018] Figure 9 This is the output circuit diagram of a low-amplitude driver circuit using a P-type MOSFET;

[0019] Figure 10 yes Figure 9 The operating waveform diagram of the low amplitude driver circuit;

[0020] Figure 11 This is the fifth embodiment. Figure 6 and Figure 9 A diagram showing the combination of driver circuits used in a low-amplitude data bus.

[0021] Figure 12 It is shown in Figure 11 A diagram showing the waveform of data transmission during data transfer on a low-amplitude data bus;

[0022] Figure 13 This is a configuration diagram of the shared power supply between the low-amplitude driver circuits NNDr and PPDr;

[0023] Figure 14 This is a diagram illustrating another modified example of the combined use of the low-amplitude driver circuit NNDr / low-amplitude receiver circuit Rv and the low-amplitude driver circuit PPDr / low-amplitude receiver circuit Rv;

[0024] Figure 15 This is a diagram illustrating yet another modified example of the combined use of the low-amplitude driver circuit NNDr / low-amplitude receiver circuit Rv and the low-amplitude driver circuit PPDr / low-amplitude receiver circuit Rv;

[0025] Figure 16 This is a diagram illustrating yet another modified example of the combined use of the low-amplitude driver circuit NNDr / low-amplitude receiver circuit Rv and the low-amplitude driver circuit PPDr / low-amplitude receiver circuit Rv;

[0026] Figure 17 This is a diagram illustrating yet another modified example of the combined use of the low-amplitude driver circuit NNDr / low-amplitude receiver circuit Rv and the low-amplitude driver circuit PPDr / low-amplitude receiver circuit Rv;

[0027] Figure 18 This is a circuit diagram of a low-amplitude receiver circuit;

[0028] Figure 19 This is the circuit diagram of a low-amplitude receiver circuit;

[0029] Figure 20 This is the circuit diagram of a low-amplitude receiver circuit;

[0030] Figure 21 It is a planar layout diagram of SoC chips stacked using through electrodes;

[0031] Figure 22 It is a planar layout diagram of memory chips stacked using through electrodes;

[0032] Figure 23 It is a planar layout diagram of SoC chips stacked using wires;

[0033] Figure 24 It is a planar layout diagram of memory chips stacked using wires;

[0034] Figure 25 It is a cross-sectional view of a SoC chip and a memory chip stacked using through electrodes;

[0035] Figure 26 It is a cross-sectional view of the SoC chip and memory chip stacked by using wires;

[0036] Figure 27 This is a schematic diagram of data transmission using a low-amplitude driver circuit;

[0037] Figure 28 This is a circuit diagram of a low-amplitude driver circuit;

[0038] Figure 29 This is a graph showing the frequency characteristics of the signal delay between the low-amplitude driver circuit and the receiver circuit;

[0039] Figure 30 This is a graph showing the frequency dependence of the operating waveform in a low-amplitude driver circuit; and

[0040] Figure 31 It is a diagram showing the waveform of each signal input to the receiver circuit via the data bus using a low-amplitude driver circuit. Specific Implementation

[0041] In the following, a semiconductor system according to one embodiment will be described in detail with reference to the accompanying drawings. Note that throughout the specification and drawings, the same or corresponding components are indicated by the same reference numerals, and repeated descriptions will be omitted. In the drawings, configurations may be omitted or simplified for ease of explanation. At least some of the embodiments and modified examples can be appropriately combined with each other.

[0042] (First Embodiment)

[0043] Configuration of Semiconductor Systems

[0044] Figure 25 This is a cross-sectional view of a SoC chip and a memory chip using through-silicon vias (TSVs).

[0045] In the attached diagram, reference numeral "1" indicates the printed circuit board, reference numeral "2" indicates the SoC chip, reference numeral "3" indicates the memory chip, and reference numeral "4" indicates the wiring used to connect the electrodes to the printed circuit board for each chip. Figure 25 As seen, the SoC chip 2 and memory chip 3, located between the board 1 at the bottom layer and the memory chip at the top layer, are connected to each other by vertically penetrating wiring 4.

[0046] Figure 26 It is a layer cross-sectional view of a SoC chip and a memory chip using wires.

[0047] Figure 26 and Figure 25 The difference is that board 1, SoC chip 2 and memory chip 3 are connected to each other via wire 5.

[0048] Figure 21 It is a planar layout diagram of a SoC chip using through-electrode stacking.

[0049] The SoC chip 2 includes a central processing unit (CPU), a computing unit (EU), an input / output port (IOU), a wiring area "tsv" (which is connected to the memory chip in the top layer and the board in the bottom layer via wiring 4), and a driver circuit unit (DrU).

[0050] The driver circuit unit DrU provides signals received from wiring 4 to the central processing unit (CPU), computing unit (EU), or input / output port (IOU), and also provides signals received from the CPU, EU, or IOU to wiring 4. The signals described herein are control signals, including data, address, and clock signals.

[0051] Figure 22 It is a planar layout diagram of memory chips stacked using through-electrode layers.

[0052] The memory chip 3 includes a memory array MA, a control circuit MCONT (controlling the memory array), a wiring area "tsv" (which is connected to the chip in the top or bottom layer via wiring 4), and a driver circuit unit DrU.

[0053] The driver circuit unit DrU provides signals received from wiring 4 to the control circuit MCONT, or provides signals received from the control circuit MCONT to wiring 4. The signals described here are control signals that include data, address, and clock signals.

[0054] The control circuit MCONT is connected to the local bus LBUS inside the memory array MA via the global bus GBUS.

[0055] For example, Figure 25 and Figure 26 The memory chip 3 is a synchronous DRAM, which writes and reads data synchronously with the clock signal provided from the SoC chip 2.

[0056] Figure 23 It is a planar layout diagram of a SoC chip using stacked wires.

[0057] SoC chip 2 includes wire bonding regions "wpd1" and "wpd2". SoC chip 2 and memory chip 3 are interconnected via wires in wire bonding region wpd1. SoC chip 2 is connected to board 1 via wires in wire bonding region wpd1.

[0058] Figure 24 It is a planar layout diagram of memory chips using stacked wires.

[0059] The memory chip 3 includes a wire bonding region "wpd". The memory chip 3 is connected to the top layer, bottom layer or board via wires in the wire bonding region wpd.

[0060] <<Details of the driver circuit unit (comparative example)>>

[0061] Figure 27 This is a schematic diagram of data transmission using a low-amplitude driver circuit.

[0062] The low-amplitude driver circuit NNDr, the low-amplitude receiver circuit Rv, the latch circuits DFF0 and DFF1, and the inverter circuit INV are included. Figure 21 , Figure 22 , Figure 23 and Figure 24 The driver circuit unit DrU is shown. In one example, Figure 21 The SOC chip 2 in the middle sends signals to the through-hole electrode (tsv wiring area) to transmit signals. Figure 22 The memory chip 3 has a low amplitude driver circuit NNDr included in the driver circuit unit DrU inside the SoC chip 2, and a low amplitude receiver circuit Rv and the like are included in the driver circuit unit DrU inside the memory chip 3.

[0063] In another example, Figure 27 The configuration shown is applicable not only to circuits that transfer data between chips, but also to circuits that transfer data within the SoC chip 2 or within the memory chip 3.

[0064] The low-amplitude driver circuit NNDr has an output circuit made of N-type MOSFETs that accepts an n-bit (n-bit width) parallel input of data "DIN" and outputs data with an amplitude lower than the voltage amplitude of the data DIN to the n-bit data bus DBUS. The low-amplitude driver circuit NNDr also accepts a clock signal CLKIN as input and outputs a clock signal with an amplitude lower than the voltage amplitude of the clock signal CLKIN to the clock signal line CLKT.

[0065] The low-amplitude receiver circuit Rv receives clock signals and data with low amplitudes from the low-amplitude driver circuit NNDr. n-bit latch circuits DFF0 and DFF1 are arranged, and the non-inverted clock signal received by the low-amplitude receiver circuit Rv and the n-bit data Dout are provided in parallel to latch circuit DFF0. Simultaneously, the inverted clock signal generated by the inverter circuit INV and the n-bit Dout are provided in parallel to latch circuit DFF1.

[0066] The latch circuit DFF0 latches the even-numbered data "DOUTE" (0, 2, 4...) of the n-bit data Dout synchronously with the non-inverting clock signal, and outputs the latched n-bit data in parallel. The latch circuit DFF1 latches the odd-numbered data "DOUTO" (1, 3, 5...) of the n-bit data Dout synchronously with the inverting clock signal, and outputs the latched n-bit data in parallel.

[0067] The symbol " / n" shown in the following figures indicates the presence of signal lines corresponding to the number of "n" bits, allowing n bits of data to be transmitted in parallel. For simplicity, the illustrated latch circuits for even-numbered or odd-numbered data latching n bits are shown as a single circuit. However, the latch circuits are arranged to correspond to the number of "n" bits.

[0068] Figure 28 This is a circuit diagram of a low-amplitude driver circuit.

[0069] The power supply voltage VDD and ground potential VSS, used as operating power, are provided to the low-amplitude driver circuit NNDr. The low-amplitude driver circuit receives the input signal IN from the input terminal TIN and outputs the output signal OUT from the output terminal TOUT. N-type MOSFETs 1 and 2 are connected in series. The power supply voltage VDD (e.g., 1.0V) is applied to the drain of N-type MOSFET 1, and the input signal IN is provided to the gate of N-type MOSFET 1 from the intermediate terminal TIN. The source of N-type MOSFET 1 is connected to the output terminal TOUT. Ground potential VSS (e.g., 0V) is applied to the source of N-type MOSFET 2, and the inverted signal of the input signal IN is provided to the gate of N-type MOSFET 2 from the input terminal TIN. The drain of N-type MOSFET 2 is connected to the output terminal TOUT.

[0070] When a high-level input signal IN is provided, N-type MOSFET 1 turns on to output, and a signal with a voltage lower than the supply voltage VDD than the voltage Vth of N-type MOSFET 1 is output as the output signal OUT to the output terminal TOUT. Therefore, when N-type MOSFET 1 and MOSFET 2 are used in the low-amplitude driver circuit NNDr, the amplitude of the output signal is reduced, and the charging / discharging current to / from the load capacitor is reduced. The charging / discharging current increases with the length of the data bus DBUS wiring, and the drive current for the data bus DBUS can be reduced.

[0071] Note that the input signal IN is Figure 27The data DIN or clock signal CLKIN is shown. The low-amplitude driver circuit NNDr that receives the data DIN is arranged to correspond to the number of "n" bits.

[0072] Figure 29 This is a graph showing the frequency characteristics of the signal delay between the low-amplitude driver circuit and the receiver circuit.

[0073] The horizontal axis indicates frequency, and the vertical axis indicates delay "tPD". The symbol "RE" indicates the rise delay characteristic with respect to the frequency of the signal's rising edge, and the symbol "FE" indicates the fall delay characteristic with respect to the frequency of the signal's falling edge. Although the rise delay time of the signal is a constant independent of frequency, the fall delay time of the signal's falling edge increases with increasing frequency. (Refer to...) Figure 30 Further explanation of this phenomenon.

[0074] Figure 30 This is a graph showing the frequency dependence of the operating waveform of a low-amplitude driver circuit.

[0075] The symbol "Vrcv" indicates the threshold at which the output voltage of the low-amplitude driver circuit changes from low to high (or from high to low). When the output potential increases... Figure 28 The gate-source voltage Vg of the N-type MOSFET 1 in the output circuit shown decreases, and the performance of increasing the output voltage rapidly decreases near VDD-Vth. Therefore, when the output voltage is high for a short time, the high-level voltage tends to be low, and when the output voltage is high for a long time, the high-level voltage tends to be high. Thus, the starting voltage for the action that causes the output voltage to drop differs, and therefore, the time delay (tPDF1) for the change from high to low level changes. <tPDF2<tPDF3)。

[0076] Figure 31 It is a diagram showing the waveform of each signal input to the receiver circuit via the data bus using a low-amplitude driver circuit.

[0077] The low-amplitude driver circuit NNDr outputs the clock signal CLKIN to the clock signal line CLKT, and serially outputs the even-numbered and odd-numbered data of the n-bit data DIN to the data bus DBUS, so that the even-numbered data is output first, followed by the odd-numbered data. Based on the data and clock signal output from the low-amplitude driver circuit, the potentials of the clock signal line CLKT and the data bus DBUS change from ground potential VSS to VDD-Vth, and then from VDD-Vth back to ground potential VSS. In this case, in the clock signal output from the low-amplitude driver circuit (which causes the clock signal CLKOUT output from the low-amplitude receiver circuit Rv), the rising edge delay time tPDR is stable, while the falling edge delay time tPDF changes (e.g., ...). Figure 29 (as shown in the image).

[0078] In systems where data is written and read based on clock signals, when a bus made of long wiring is used to transmit data, changes in the edge delay of the clock signal adversely reduce the data window, which is used to correctly acquire data on the data receiving side (i.e., latch circuits DFF0 and DFF1). Furthermore, the data acquisition time varies, and therefore, high-speed operation performance is significantly and adversely degraded.

[0079] <<Details of the driver circuit unit (in the first embodiment)>>

[0080] Figure 1 This is a data transmission diagram of the first embodiment. Figure 1 In this circuit, a low-amplitude driver circuit is used to output a two-phase clock signal. Figure 28 Similarly, N-type MOSFETs are used in the output circuit of low-amplitude driver circuits.

[0081] The low-amplitude driver circuit NNDr1 is configured to accept parallel input of n-bit data DIN and output data with an amplitude lower than that of data DIN to the data bus DBUS in parallel. Furthermore, the low-amplitude driver circuit NNDr1 accepts inputs of a non-inverting clock signal CLKIN and an inverting clock signal CLKBIN, and outputs a clock signal with an amplitude lower than that of the non-inverting clock signal CLKIN to the clock signal line CLKT, and outputs a clock signal with an amplitude lower than that of the inverting clock signal CLKBIN to the non-inverting clock signal line CLKB.

[0082] The low-amplitude receiver circuit Rv receives n bits of data in parallel, the n bits of data having a low amplitude output from the low-amplitude driver circuit NNDr1, and receives both a non-inverting clock signal and an inverting clock signal. The non-inverting clock signal and data Dout received by the low-amplitude receiver circuit Rv are provided to the latch circuit DFF0, and the inverting clock signal and data Dout received by the low-amplitude receiver circuit Rv are provided to the latch circuit DFF1.

[0083] The latch circuit DFF0 latches the even-numbered data DOUTE (0, 2, 4...) of data Dout synchronously with the rising edge of the non-inverting clock signal, and outputs the latched data. The latch circuit DFF1 latches the odd-numbered data DOUTO (1, 3, 5...) of data Dout synchronously with the rising edge of the inverting clock signal, and outputs the latched data.

[0084] The low-amplitude driver circuit NNDr1 and the low-amplitude receiver circuit Rv are included. Figure 21 , Figure 22 , Figure 23 and Figure 24 The driver circuit unit DrU shown is shown.

[0085] Figure 2 This is a waveform diagram of the signal using the first embodiment.

[0086] The even-numbered data Dout(0) already received by the low-amplitude receiver circuit Rv is latched by latch circuit DFF0 to synchronize with the rising edge of the non-inverting clock signal CLKOUT already received by the low-amplitude receiver circuit Rv. Next, the odd-numbered data Dout(1) already received by the low-amplitude receiver circuit Rv is latched by latch circuit DFF1 to synchronize with the rising edge of the inverting clock signal CLKBOUT already received by the low-amplitude receiver circuit Rv. As described above, subsequently, the even-numbered data Dout is output after being latched by latch circuit DFF0 to synchronize with the rising edge of the non-inverting clock signal CLKOUT, and the odd-numbered data Dout is output after being latched by latch circuit DFF1 to synchronize with the rising edge of the inverting clock signal CLKBOUT.

[0087] By using this method, both latch circuits DFF0 and DFF1 can latch data synchronously with the rising edge of the clock signals (CLKOUT and CLKBOUT), which is consistent with... Figure 27 The situation is different. In this way, compared to Figure 27Compared to the previous method, the data window used to correctly acquire data can be expanded. Furthermore, variations in data acquisition time can be suppressed. As a result, the reliability of high-speed data transmission operations can be improved. Moreover, by using a signal with low amplitude, the operating current on the signal bus can be reduced.

[0088] (Second Embodiment)

[0089] <<Details of the driver circuit unit in the second embodiment>>

[0090] Figure 3 This is a data transmission diagram of the second embodiment. Figure 3 In this process, data is transmitted using a four-phase clock signal.

[0091] The output interface circuit OIF includes a data latch circuit DLT0, a four-phase clock generation circuit CGEN, and a low-amplitude driver circuit NNDr2, and n-bit data DIN and clock signal CLKIN are provided to this circuit.

[0092] The data latch circuit DLT0 includes latch circuits DFF00 and DFF01. The four-phase clock generation circuit CGEN includes latch circuits DFF02 to DFF05. The low-amplitude driver circuit NNDr2 includes output circuits OC0 to OC5, and output circuits OC0 and OC1 are arranged to correspond to the number of "n" bits so as to input and output n bits of data in parallel.

[0093] Each of the output circuits OC0 to OC5 has Figure 28 The circuit configuration shown outputs a signal with an amplitude lower than that of the voltage amplitude of the N-type MOSFET 1 than that of the input signal.

[0094] The non-inverting clock signal is provided to latch circuits DFF00, DFF02 and DFF04, and the inverting clock signal is provided to latch circuits DFF01, DFF03 and DFF05.

[0095] The latch circuit DFF00 latches even-numbered data DIN (0, 2, 4...) synchronously with a non-inverting clock signal and outputs the latched data to the output circuit OC0. The latch circuit DFF01 latches odd-numbered data DIN (1, 3, 5...) synchronously with an inverting clock signal and outputs the latched data to the output circuit OC1.

[0096] The output signals of latch circuits DFF02 and DFF03 are fed back to the inputs of their respective latch circuits. Additionally, signals inverted by inverter circuits are input to these latch circuits. The output signal of latch circuit DFF02 is fed back to latch circuit DFF04 as its input signal. The output signal of latch circuit DFF03 is fed back to latch circuit DFF05 as its input signal.

[0097] Latch circuit DFF02 outputs clock signal CLK0, and latch circuit DFF03 outputs clock signal CLK1, with the phase of clock signal CLK1 shifted by 90° from the phase of clock signal CLK0. Latch circuit DFF04 outputs clock signal CLK2, with the phase of clock signal CLK2 shifted by 180° from the phase of clock signal CLK0, and latch circuit DFF05 outputs clock signal CLK3, with the phase of clock signal CLK3 shifted by 270° from the phase of clock signal CLK0.

[0098] The low-amplitude driver circuit NNDr2 outputs even-numbered data DE (0, 2, 4…) to the even-numbered data bus BBUSE with an “n”-bit width, and outputs odd-numbered data DO (1, 3, 5…) to the odd-numbered data bus BBUSO with an “n”-bit width. The low-amplitude driver circuit NNDr2 also outputs clock signals CLK0 to CLK3 to the clock signal line CLKL.

[0099] The input interface circuit IIF includes a data latch circuit DLT1, a clock recovery circuit CRC, and a low-amplitude receiver circuit Rv. Each signal from the even-numbered data bus BBUSE, the odd-numbered data bus BBUSO, and the clock signal line CLKL is provided to this input interface circuit.

[0100] The low-amplitude receiver circuit Rv includes input circuits IC0 through IC5. Input circuit IC0 outputs even-numbered data to data latch circuit DLT1, and input circuit IC1 outputs odd-numbered data to data latch circuit DLT1. Each of input circuits IC2 through IC5 outputs each clock signal to clock recovery circuit CRC.

[0101] Input circuits IC0 and IC1 are arranged to correspond to the number of “n” bits so that n bits of data can be input and output in parallel.

[0102] The clock recovery circuit (CRC) is made of multiple NAND logic circuits and generates a two-phase clock signal from the input four-phase clock signal. The two-phase clock signal is made of clock signal CLKOUT and clock signal CLKBOUT. Clock signal CLKBOUT is the inverted signal of clock signal CLKOUT, and the two-phase clock signal is output.

[0103] The data latch circuit DLT1 includes latch circuits DFF10 and DFF11. Latch circuit DFF10 latches even-numbered data synchronously with the rising edge of the clock signal CLKOUT and outputs the latched data. Latch circuit DFF11 latches odd-numbered data synchronously with the rising edge of the clock signal CLKBOUT and outputs the latched data.

[0104] Figure 3 Each circuit shown is included Figure 21 , Figure 22 , Figure 23 and Figure 24 The driver circuit unit DrU shown is shown.

[0105] Figure 4 This is a diagram showing the waveform of data transmission obtained when using a four-phase clock signal.

[0106] The four-phase clock signals CLK0 to CLK3 are generated from the clock signal CLKIN using the four-phase clock generation circuit CGEN.

[0107] Even-numbered data DE is provided to the input interface circuit IIF via the even-numbered data bus BBUSE, and odd-numbered data DO is provided to the input interface circuit IIF via the odd-numbered data bus BBUSO.

[0108] The data DE and data DO, which have been provided by the even-numbered data bus BBUSE and the odd-numbered data bus BBUSO, are sequentially latched by latch circuits DFF10 and DFF11 in sync with the corresponding rising edges of the two-phase clock signals CLKOUT and CLKBOUT, which have been recovered from the four-phase clock signals CLK0 to CLK3.

[0109] In this data transmission method, the peak current in the bus driver is allocated, and the power supply noise is reduced, thus improving the degradation of high-frequency transmission characteristics caused by power supply noise.

[0110] (Third Embodiment)

[0111] <<Details of the driver circuit unit (in the third embodiment)>>

[0112] Figure 5 This diagram illustrates a data transmission method using a low-voltage power supply circuit for low-amplitude signal transmission in the third embodiment. A power supply voltage VDD (e.g., 1.0V) is applied to the low-voltage power supply circuit VDDG_Gen to generate a low voltage VDDG (e.g., 0.5V). The low voltage VDDG is supplied to the low-amplitude driver circuit NNDr3 and the low-amplitude receiver circuit Rv1.

[0113] The low-amplitude driver circuit NNDr3, the low-amplitude receiver circuit Rv1, and the low-voltage power supply circuit VDD_Gen are included. Figure 21 , Figure 22 , Figure 23 and Figure 24 The driver circuit unit DrU shown is shown.

[0114] Figure 6 A circuit diagram of a low-amplitude driver circuit to which a low voltage is applied is shown. A low voltage VDDG, generated from a low-voltage supply VDDG_Gen, is supplied to the drain of N-type MOSFET 1. When an input signal IN with a high level is supplied from the input terminal TIN, the level at gate node A of N-type MOSFET 1 becomes high, and the level at gate node B of N-type MOSFET 2 becomes low. In this case, N-type MOSFET 1 is turned on, therefore, compared to... Figure 28 In cases where the voltage is low, a low voltage VDDG (such as the voltage of the N-type MOSFET 1 that is lower than the supply voltage VDD) is output to the output terminal TOUT.

[0115] The input signal IN is Figure 5 The data shown is either DIN or clock signals CLKIN and CLKBIN.

[0116] Figure 7 It is shown Figure 6 The diagram shows the operating waveforms of the low-amplitude driver circuit.

[0117] When the input signal IN of the low-amplitude driver circuit NNDr3 changes from low (VSS) to high (VDD), the gate potential A of N-type MOSFET 1 becomes high (VDD), turning on N-type MOSFET 1, and the gate potential B of N-type MOSFET 2 becomes low (VSS), turning off N-type MOSFET 2. In this case, the low voltage VDDG is output to the output terminal TOUT through N-type MOSFET 1 as the output signal OUT.

[0118] When the input signal IN of the low-amplitude driver circuit NNDr3 changes from high (VDD) to low (VSS), the gate potential A of N-type MOSFET 1 becomes low (VSS), turning off N-type MOSFET 1, and the gate potential B of N-type MOSFET 2 becomes high (VDD), turning on N-type MOSFET 2. In this case, the ground potential VSS is output to the output terminal TOUT as the output signal OUT.

[0119] As described above, when the low-amplitude driver circuit NNDr3 outputs a high-level signal, the level of the output signal OUT becomes a low voltage VDDG, which is lower than "VDD-Vth". In this way, the voltage of the output signal OUT can be prevented from increasing until the low-amplitude driver circuit NNDr3 (N-type MOSFET 1) is almost turned off, and therefore, the causes of changes in the dependence of the high level of the low-amplitude driver circuit NNDr3 on the output rate (such as cyclic dependence) can be reduced.

[0120] Furthermore, the signal amplitude of the bus signal system can be reduced by using a low voltage VDDG, and thus, a greater power reduction effect can be achieved.

[0121] (Fourth Embodiment)

[0122] <<Details of the driver circuit unit in the fourth embodiment>>

[0123] Figure 8 This is a data transmission diagram obtained in the fourth embodiment when a P-type MOSFET is used in the output circuit.

[0124] A power supply voltage VDD and a low voltage VDDG (0.5V) are applied to the low amplitude driver circuit PPDr and the low amplitude receiver circuit Rv as the corresponding operating voltages. The low voltage VDDG is generated by the low voltage generation circuit VDDG2_Gen, which is connected to ground potential VSS.

[0125] The low-amplitude driver circuit PPDr, the low-amplitude receiver circuit Rv, and the low-voltage power supply circuit VDD2_Gen are included. Figure 21 , Figure 22 , Figure 23 and Figure 24 The driver circuit unit DrU shown is shown.

[0126] Figure 9 This is the output circuit diagram of a low-amplitude driver circuit using a P-type MOSFET.

[0127] When the power supply voltage VDD and the low voltage VDDG are provided as operating power, the low amplitude driver circuit PPDr accepts the input signal IN from the input terminal TIN and outputs the output signal OUT from the output terminal TOUT.

[0128] P-type MOSFETs 1 and 2 are connected in series. A power supply voltage VDD (1.0V) is applied to the source of P-type MOSFET 1. The input signal IN from the input terminal TIN is provided to its gate, and its drain is connected to the output terminal TOUT. VDDG is applied to the drain of P-type MOSFET 2. The inverted signal of the input signal IN from the input terminal TIN is provided to its gate, and its source is connected to the output terminal TOUT.

[0129] When a high-level input signal IN is provided, P-type MOSFET 1 is turned on, so that a low-voltage signal VDD is output to the output terminal TOUT as the output signal OUT.

[0130] When a low-level input signal IN is provided, P-type MOSFET 2 is turned on, so that a low voltage VDDG is output to the output terminal TOUT as the output signal OUT.

[0131] In other words, the output voltage of an output circuit made with a P-type MOSFET has an amplitude that swings between the supply voltage VDD and the low voltage VDDG. In this way, similar to the output circuit of a low-amplitude driver circuit using an N-type MOSFET, the amplitude of the signal to be output is reduced. Therefore, as the data bus DBUS wiring becomes longer, the increased charging / discharging current on the load capacitor becomes lower, allowing for a reduction in the drive current of the data bus DBUS.

[0132] The input signal IN is either data DIN or clock signals CLKIN and CLKBIN.

[0133] Figure 10 yes Figure 9 The operating waveform diagram of the low amplitude driver circuit.

[0134] When the input signal IN changes from low (VSS) to high (VDD), the gate potential A of P-type MOSFET 1 becomes low (VSS), turning on P-type MOSFET 1, and the gate potential B of P-type MOSFET 2 becomes high (VDD), turning off P-type MOSFET 2. At this time, through P-type MOSFET 1, the voltage of the output signal OUT at the output terminal TOUT changes from low voltage VDDG to the power supply voltage VDD.

[0135] When the input signal IN changes from high (VDD) to low (VSS), the gate potential A of P-type MOSFET 1 becomes high (VDD), turning off P-type MOSFET 1, and the gate potential B of P-type MOSFET 2 becomes low (VSS), turning on P-type MOSFET 2. At this time, the low voltage VDDG is output to the output terminal TOUT as the output signal OUT.

[0136] As mentioned above, when the low level of the output voltage increases the Vth of the PMOS, the amplitude of the signal to be transmitted over a long wiring decreases.

[0137] The operating waveform of the output circuit of a low-amplitude driver circuit using a P-type MOSFET is obtained by inverting the voltage relationship between the high and low levels of the output circuit of a low-amplitude driver circuit using an N-type MOSFET. In other words, in a low-amplitude driver circuit using a P-type MOSFET, the use of the falling edge of the clock signal is a countermeasure to improve the accuracy of high-speed operation.

[0138] When the low voltage VDDG is higher than the threshold Vth of the P-type MOSFET, it can be used as a low-power data transmission circuit. This circuit can, for example, effectively prevent noise from propagating from the common GND power supply to nearby analog circuits.

[0139] (Fifth Embodiment)

[0140] Figure 11 In the fifth embodiment Figure 6 and Figure 9 The diagram shows the combination of driver circuits used in the low-amplitude data bus.

[0141] Figure 11 The diagram illustrates a configuration for transmitting signals with low amplitude over long wiring, which uses a combination of a low amplitude driver circuit NNDr3 (using an N-type MOSFET) and a low amplitude driver circuit PPDr (using a P-type MOSFET) as a low amplitude drive system before and after a repeater (placed in the middle of the wiring).

[0142] The operating power supplies for the low-amplitude driver circuit NNDr3 are the low voltage VDDG and the ground voltage VSS, while the operating power supplies for the low-amplitude driver circuit PPDr are the power supply voltage VDD and the low voltage VDDG. The low voltage VDDG is generated by the internal power generation circuit and is set to approximately half the power supply voltage VDD as the common power supply potential between the low-amplitude driver circuits NNDr3 and PPDr.

[0143] Figure 11 Each circuit shown is included Figure 21, Figure 22 , Figure 23 and Figure 24 The driver circuit unit DrU shown is shown.

[0144] Figure 12 It is shown in Figure 11 The diagram shows the waveform of data transmission during data transfer on a low-amplitude data bus.

[0145] from Figure 12 It can be seen that the rising edges of the non-inverting clock signal CLKT_NN and the inverting clock signal CLKB_NN are synchronized in the low-amplitude driver circuit NNDr3, and the falling edges of the non-inverting clock signal CLKT_PP and the inverting clock signal CLKB_PP are synchronized in the low-amplitude driver circuit PPDr. Therefore, the accuracy of signal transmission and latching synchronized with the clock signal is improved.

[0146] Figure 13 This is a configuration diagram of the common power supply between the low-amplitude driver circuits NNDr3 and PPDr.

[0147] Because the low voltage VDDG is supplied to the low amplitude driver circuits NNDr3 and PPDr via the power line VDDGL as their operating power (e.g., Figure 11 As shown in the diagram, the discharge current (Iout0) of the low-amplitude driver circuit PPDr flows into the power line VDDGL, but at the same time it flows out as a charging current (Iout1) on the driver circuit side of the low-amplitude driver circuit NNDr3, thus achieving a charge reuse effect. Therefore, it is expected that the power consumption will be significantly reduced to about 1 / 2 of that in the first to fourth embodiments.

[0148] The low-amplitude driver circuit NNDr3, the low-amplitude driver circuit PPDr, and the low-voltage power supply circuit VDD_Gen are included. Figure 21 , Figure 22 , Figure 23 and Figure 24 The driver circuit unit DrU shown is shown.

[0149] Figures 14 to 17 Each of the figures is a diagram illustrating another modified example of the combined use of the low-amplitude driver circuit NNDr / low-amplitude receiver circuit NNRv and the low-amplitude driver circuit PPDr / low-amplitude receiver circuit PPRv.

[0150] Figures 14 to 16 The low-amplitude driver circuit NNDr, the low-amplitude receiver circuit NNRv, the low-amplitude driver circuit PPDr, and the low-amplitude receiver circuit PPRv are included. Figure 21 , Figure 22 , Figure 23 and Figure 24 In the driver circuit unit DrU. Figure 17 The low-amplitude driver circuit NNDr is included Figure 22 and Figure 24 The driver circuit unit DrU shown is included in the memory array MA, and the low amplitude driver circuit PPDr is included in the memory array MA.

[0151] Figure 14 The first example of modification is shown. Figure 14 An example is shown where n-bit data is divided into two groups: odd-numbered data and even-numbered data.

[0152] The odd-numbered data DIN1 and the clock signal CLK1 of the odd-numbered data are output by the low-amplitude driver circuit PPDr (including the output circuit made of P-type MOSFETs) to the bus OBUS of the odd-numbered data, and are then carried to the low-amplitude receiver circuit PPRv (including the output circuit made of P-type MOSFETs).

[0153] The even-numbered data DIN0 and the clock signal CLK0 are output by the low-amplitude driver circuit NNDr (including the output circuit made of N-type MOSFETs) to the even-numbered data bus EBUS, and are then carried to the low-amplitude receiver circuit NNRv (including the output circuit made of N-type MOSFETs).

[0154] Figure 15 A second modified example is shown. Figure 15 An example is shown where n-bit data is divided into two groups based on the direction (destination) of signal transmission.

[0155] The write data WDIN and write data clock signal WCLK are output to the write data bus WBUS by the low amplitude driver circuit PPDr (including the output circuit made of P-type MOSFETs) and are carried to the low amplitude receiver circuit PPRv (including the output circuit made of P-type MOSFETs).

[0156] The read data RDOUT and read data clock signal RCLK are output to the read data bus RBUS by the low amplitude driver circuit NNDr (including the output circuit made of N-type MOSFETs) and are then carried to the low amplitude receiver circuit NNRv (including the output circuit made of N-type MOSFETs).

[0157] Figure 16 A third modified example is shown. Figure 16 An example is shown where n-bit data is divided into two groups based on the operating frequency.

[0158] The low-frequency clock signal LCLK and the instruction INST are received by the low-amplitude driver circuit PPDr (including the output circuit made of P-type MOSFETs) and output to the instruction bus IBUS.

[0159] The high-frequency clock signal HCLK and data Data are received by the low-amplitude driver circuit NNDr (including the output circuit made of N-type MOSFETs) and output to the data bus DBUS.

[0160] Low-frequency clock signals have frequencies of several hundred MHz (e.g., 200 MHz), while high-frequency clock signals have frequencies of several GHz (e.g., above 1 GHz).

[0161] Figure 17 The fourth modification example is shown. Figure 17 An example is shown of a case where n-bit data is divided into two groups based on, for example, a hierarchical bus system in memory.

[0162] The data DIN, which has been input via the global bus GBUS, is received by the low-amplitude driver circuit NNDr (including the output circuit made of N-type MOSFETs) and output to the local bus LBUS.

[0163] The data DIN, which has been input via the local bus LBUS, is received by the low-amplitude driver circuit PPDr (including the output circuit made of P-type MOSFETs) and output to the local bus LBUS.

[0164] For example, the global bus GBUS is made of a metallic material such as aluminum, while the local bus LBUS is made of silicon, a material different from metallic materials.

[0165] Figures 18 to 20 Each of these is a circuit diagram of a low-amplitude receiver circuit.

[0166] Figure 18 A typical level shifter circuit is shown. This circuit is supplied with a power supply voltage VDD and a ground potential VSS as its operating voltages, and receives a low voltage VDDG as an input signal IN, which is lower than the power supply voltage VDD. The input signal IN is a data or clock signal, and data and clock signals with a voltage amplitude larger than that of the input signal IN are output as the output signal OUT.

[0167] Figure 19 Showing has Figure 18 The first receiver circuit has further improved performance, and Figure 20 It shows having Figure 18 A second receiver circuit with further improved performance.

[0168] When a high-speed receiver circuit (with a significantly improved PMOS or NMOS performance ratio at internal connection points C or D of the low-amplitude receiver circuits NNRv or PPRv) is used as the low-amplitude receiver circuits NNRv and PPRv, the signal propagation delay caused by the low amplitude is improved. This also means that the output waveform of the receiver circuit becomes sharper, which leads to an improvement in the H / L data difference generated in the receiver circuit. Therefore, the accuracy of control clock transmission variations and the accuracy of data acquisition in data transmission can be comprehensively improved.

[0169] The description of the embodiments has already described that data and clock signals are transmitted at low amplitude. However, not only data and clock signals, but also address signals and control signals (such as RAS and CAS, which are not described) are transmitted at low amplitude.

[0170] The present invention has been described above based on embodiments. However, it goes without saying that the present invention is not limited to the configurations of the foregoing embodiments, and includes various modifications and changes that can be made by those skilled in the art within the scope of the present invention.

Claims

1. A semiconductor system, comprising: A semiconductor device having a central processing unit and logic circuitry, the central processing unit and logic circuitry being formed on a semiconductor chip; as well as Memory devices are formed on a semiconductor chip. Each of the semiconductor device and the memory device includes: The driver circuit is configured to output data and clock signals; as well as The receiver circuit is configured to receive both data and clock signal inputs. The driver circuit of the semiconductor device is coupled to the receiver circuit of the memory device. The driver circuit of the memory device is coupled to the receiver circuit of the semiconductor device. A first power supply voltage is applied to each driver circuit in the driver circuitry, and each driver circuit outputs data, a first clock signal, and a second clock signal to the receiver circuitry, wherein the phase of the second clock signal is shifted from the first clock signal by a predetermined amount. The data, as well as the amplitude of each of the first and second clock signals, is less than the amplitude of the first power supply voltage. The semiconductor device and the memory device input data synchronously with the rising edge of the first clock signal and the rising edge of the second clock signal.

2. The semiconductor system according to claim 1, The driver circuit includes: Output terminals; as well as The output circuit includes a first N-type MOSFET and a second N-type MOSFET. The first power supply voltage is applied to the first electrode of the first N-type MOSFET. Ground voltage is applied to the first electrode of the second N-type MOSFET, and The second electrode of each of the first N-type MOSFET and the second N-type MOSFET is connected to the output terminal.

3. The semiconductor system according to claim 2, The output circuit includes: A data output circuit is configured to output the data; as well as The clock output circuit is configured to output the first clock signal and the second clock signal. The data output circuit is connected to the receiver circuit via a data signal line, and The clock output circuit is connected to the receiver circuit via a clock signal line.

4. The semiconductor system according to claim 3, The second clock signal is a signal whose phase is shifted by 180° from that of the first clock signal.

5. The semiconductor system according to claim 4, The memory device includes multiple latch circuits. The plurality of latch circuits include: The first set of latch circuits is configured to latch data synchronously with the rising edge of the first clock signal; as well as The second set of latch circuits is configured to latch data synchronously with the rising edge of the second clock signal.

6. The semiconductor system according to claim 5, The first group of latch circuits latches odd-numbered data, and The second set of latch circuits latches even-numbered data.

7. The semiconductor system according to claim 6, The plurality of said memory devices are arranged such that they are stacked on the semiconductor device, and The memory devices, except for the top memory device, penetrate each chip and are coupled to the semiconductor device.

8. The semiconductor system according to claim 6, The plurality of said memory devices are arranged such that they are stacked on the semiconductor device, and The plurality of memory devices and the semiconductor devices are connected to each other by bonding wires.

9. The semiconductor system according to claim 2, The driver circuit includes a voltage generation circuit configured to generate a second power supply voltage that is lower than the first power supply voltage and higher than the ground voltage. The second power supply voltage is applied to the first electrode of the first N-type MOSFET.

10. The semiconductor system according to claim 2, The driver circuit includes: Output terminals; as well as The output circuit includes a first P-type MOSFET and a second P-type MOSFET. The first power supply voltage is applied to the first electrode of the first P-type MOSFET. A voltage higher than the ground voltage and lower than the first power supply voltage is applied to the first electrode of the second P-type MOSFET, and The second electrode of each of the first P-type MOSFET and the second P-type MOSFET is coupled to the output terminal.

11. The semiconductor system according to claim 10, The output circuit includes: A data output circuit is configured to output the data; as well as The clock output circuit is configured to output the first clock signal and the second clock signal; The data output circuit is coupled to the receiver circuit via a data signal line, and The clock output circuit is coupled to the receiver circuit via a clock signal line.

12. The semiconductor system according to claim 11, The phase of the second clock signal is shifted by 180° from the phase of the first clock signal.

13. The semiconductor system according to claim 12, The memory device includes multiple latch circuits. The plurality of latch circuits include: The first set of latch circuits is configured to latch data synchronously with the rising edge of the first clock signal; as well as The second set of latch circuits is configured to latch data synchronously with the rising edge of the second clock signal.

14. The semiconductor system according to claim 13, The first group of latch circuits latches odd-numbered data, and The second set of latch circuits latches even-numbered data.

15. The semiconductor system according to claim 14, The plurality of said memory devices are arranged such that they are stacked on the semiconductor device, and The memory devices, except for the top memory device, penetrate each chip and are coupled to the semiconductor device.

16. The semiconductor system according to claim 14, The plurality of said memory devices are arranged such that they are stacked on the semiconductor device, and The plurality of memory devices and the semiconductor devices are coupled to each other via bonding wires.

17. A semiconductor system, comprising: The driver circuit is configured to output data and clock signals; as well as The receiver circuit is configured to receive data and clock signals that have been output from the driver circuit. A first power supply voltage is applied to the driver circuit, and the driver circuit outputs data, a first clock signal, and a second clock signal, wherein the phase of the second clock signal is shifted from the first clock signal by a predetermined amount. The data, as well as the amplitude of each of the first and second clock signals, is less than the amplitude of the first power supply voltage. The receiver circuit inputs data synchronously with the rising edges of the first clock signal and the second clock signal.

18. The semiconductor system according to claim 17, The driver circuit includes: Output terminals; as well as The output circuit includes a first N-type MOSFET and a second N-type MOSFET. The first power supply voltage is applied to the first electrode of the first N-type MOSFET. Ground voltage is applied to the first electrode of the second N-type MOSFET, and The second electrode of each of the first N-type MOSFET and the second N-type MOSFET is coupled to the output terminal.

19. The semiconductor system according to claim 18, The driver circuit includes a voltage generation circuit configured to generate a second power supply voltage that is lower than the first power supply voltage and higher than the ground voltage. The second power supply voltage is applied to the first electrode of the first N-type MOSFET.

20. The semiconductor system according to claim 18, The driver circuit includes: Output terminals; as well as The output circuit includes a first P-type MOSFET and a second P-type MOSFET. The first power supply voltage is applied to the first electrode of the first P-type MOSFET. A voltage higher than the ground voltage and lower than the first power supply voltage is applied to the first electrode of the second P-type MOSFET, and The second electrode of each of the first P-type MOSFET and the second P-type MOSFET is coupled to the output terminal.

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