Display substrate and display device

Abstract

A display substrate and a display device. The display substrate (100) comprises a substrate (110), a plurality of sub-pixel groups (120) arranged on the substrate (110) along a row direction and a column direction; and a first spacer (131), a second spacer (132) and a third spacer (133), each sub-pixel group (120) comprises a first sub-pixel (121), a second sub-pixel (122) and a third sub-pixel (123), in a row of sub-pixel groups (120), the first spacer (131) is located between adjacent first sub-pixels (121) and second sub-pixels (122), the second spacer (132) is located between adjacent second sub-pixels (122) and third sub-pixels (123), and the third spacer (133) is located between adjacent third sub-pixels (123) and first sub-pixels (121), the number of first spacers (131), the number of second spacers (132) and the number of third spacers (133) are substantially equal. Therefore, the display substrate (100) can effectively improve, even avoid the color deviation phenomenon caused by uneven distribution of spacers.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0002] With the continuous development of display technology, organic light-emitting diode (OLED) display panels have been increasingly used in various electronic devices due to their advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and high response speed. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a display substrate, comprising: a substrate; a plurality of sub-pixel groups arranged on the substrate along row and column directions; and a first spacer, a second spacer, and a third spacer, each of the sub-pixel groups including a first sub-pixel, a second sub-pixel, and a third sub-pixel. In a row of the sub-pixel groups, the first spacer is located between adjacent first sub-pixels and second sub-pixels, the second spacer is located between adjacent second sub-pixels and third sub-pixels, and the third spacer is located between adjacent third sub-pixels and first sub-pixels. The number of first spacers, the number of second spacers, and the number of third spacers are approximately equal.

[0004] For example, in a display substrate provided in one embodiment of this disclosure, the first spacer, the second spacer, and the third spacer are sequentially and cyclically arranged in a row of the sub-pixel group.

[0005] For example, in a display substrate provided in one embodiment of this disclosure, each of the sub-pixel groups includes at most one first spacer, one second spacer, or one third spacer.

[0006] For example, in a display substrate provided in an embodiment of this disclosure, each sub-pixel group includes a first sub-pixel, a second sub-pixel, and a third sub-pixel pair. The third sub-pixel pair includes two third sub-pixels. In a row of sub-pixel groups, the first spacer is located between adjacent first sub-pixels and second sub-pixels, the second spacer is located between adjacent second sub-pixels and third sub-pixel pairs, and the third spacer is located between adjacent third sub-pixel pairs and first sub-pixels.

[0007] For example, in a display substrate provided in an embodiment of this disclosure, in each of the sub-pixel groups, the first sub-pixel, the second sub-pixel, and the third sub-pixel pair are arranged along the row direction to form three sub-pixel columns, and the two third sub-pixels in the third sub-pixel pair are arranged along the column direction.

[0008] For example, in a display substrate provided in an embodiment of this disclosure, in a row of the sub-pixel group, the first spacer and the second spacer are spaced apart by 1+3n sub-pixel columns, the second spacer and the third spacer are spaced apart by 1+3n sub-pixel columns, and the third spacer and the first spacer are spaced apart by 1+3n sub-pixel columns, where n is a positive integer greater than or equal to 1.

[0009] For example, in a display substrate provided in one embodiment of this disclosure, two adjacent rows of sub-pixel groups are staggered by 1 / 2 pitch, where the pitch is the distance between the centers of two first sub-pixels in two adjacent sub-pixel groups along the row direction.

[0010] For example, in a display substrate provided in one embodiment of this disclosure, the first sub-pixel is configured to emit light of a first color, the second sub-pixel is configured to emit light of a second color, and the third sub-pixel is configured to emit light of a third color.

[0011] For example, in a display substrate provided in one embodiment of this disclosure, the first color is blue, the second color is red, and the third color is green.

[0012] For example, in a display substrate provided in one embodiment of this disclosure, the first spacer is generally elongated, and the extension direction of the first spacer is generally parallel to the column direction; the second spacer is generally elongated, and the extension direction of the second spacer is generally parallel to the column direction; the third spacer is generally elongated, and the extension direction of the third spacer is generally parallel to the column direction.

[0013] For example, in a display substrate provided in one embodiment of this disclosure, the size of the first spacer in the column direction is smaller than the size of the first sub-pixel in the column direction, the size of the second spacer and the third spacer in the column direction is smaller than the size of the third sub-pixel pair in the column direction, and the centers of the first spacer, the second spacer, the third spacer, the first sub-pixel, the second sub-pixel, and the third sub-pixel pair are approximately located on a straight line approximately parallel to the row direction.

[0014] For example, in a display substrate provided in one embodiment of this disclosure, the first spacer, the second spacer, and the third spacer have the same size, the width of the first spacer along the row direction is in the range of 6-15 micrometers, the length of the first spacer along the column direction is in the range of 35-45 micrometers, and the height of the first spacer along the direction perpendicular to the substrate is in the range of 1.5-2.5 micrometers.

[0015] For example, in a display substrate provided in one embodiment of this disclosure, a first sub-pixel includes a first anode and a first light-emitting functional layer, a second sub-pixel includes a second anode and a second light-emitting functional layer, and a third sub-pixel includes a third anode and a third light-emitting functional layer. The display substrate further includes a pixel defining layer located on the side of the first anode, the second anode, and the third anode away from the substrate, and including a first opening, a second opening, and a third opening. The first opening exposes the first anode, the second opening exposes the second anode, and the third opening exposes the third anode. At least a portion of the first light-emitting functional layer is located in the first opening and covers the exposed portion of the first anode. At least a portion of the second light-emitting functional layer is located in the second opening and covers the exposed portion of the second anode. At least a portion of the third light-emitting functional layer is located in the third opening and covers the exposed portion of the third anode. The first spacer, the second spacer, and the third spacer are located on the surface of the pixel defining layer away from the substrate.

[0016] For example, in a display substrate provided in an embodiment of this disclosure, the orthographic projections of the first spacer, the second spacer, and the third spacer on the substrate do not overlap with the orthographic projections of the first opening, the second opening, and the third opening on the substrate.

[0017] For example, in a display substrate provided in one embodiment of this disclosure, the first spacer, the second spacer, and the third spacer are formed by a single masking process.

[0018] At least one embodiment of this disclosure also provides a display device including the display substrate described in any of the above claims.

[0019] At least one embodiment of this disclosure also provides a display substrate, comprising: a substrate; a plurality of sub-pixel groups arranged on the substrate along row and column directions; each sub-pixel group comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel pair, each third sub-pixel pair comprising two third sub-pixels, the first sub-pixel comprising a first anode and a first pixel driving circuit, the second sub-pixel comprising a second anode and a second pixel driving circuit, the third sub-pixel comprising a third anode and a third pixel driving circuit, the display substrate further comprising a first planarization layer located between the first anode and the first pixel driving circuit, between the second anode and the second pixel driving circuit, and between the third anode and the third pixel driving circuit, the first sub-pixel comprising a first via located in the first planarization layer, the second sub-pixel comprising a second via located in the first planarization layer, the third sub-pixel comprising a third via located in the first planarization layer, the first via being used for connecting the first anode to the first pixel driving circuit, the second via being used for connecting the second anode to the second pixel driving circuit, and the third via being used for connecting the third anode to the third pixel driving circuit, wherein the first via, the second via, and a portion of the third via in a row of the sub-pixel groups are substantially located on a first straight line.

[0020] For example, in a display substrate provided in one embodiment of this disclosure, the first straight line is substantially parallel to the row direction.

[0021] For example, in a display substrate provided in an embodiment of this disclosure, in each of the sub-pixel groups, the first sub-pixel, the second sub-pixel, and the third sub-pixel pair are arranged along the row direction, the two third sub-pixels in the third sub-pixel pair are arranged along the column direction, and the two third vias of the two third sub-pixels in the third sub-pixel pair are respectively located on two adjacent first straight lines.

[0022] For example, in a display substrate provided in an embodiment of this disclosure, the display substrate further includes: a second planarization layer located between the first planarization layer and the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit; a first connecting electrode, a second connecting electrode, and a third connecting electrode located between the second planarization layer and the first planarization layer; the first pixel driving circuit includes a first electrode; the second pixel driving circuit includes a second electrode; the third pixel driving circuit includes a third electrode; the first sub-pixel includes a fourth via located in the second planarization layer; the second sub-pixel includes a fifth via located in the second planarization layer; the third sub-pixel includes a sixth via located in the second planarization layer; the fourth via is used for connecting the first electrode and the first connecting electrode; the fifth via is used for connecting the second electrode and the second connecting electrode; the sixth via is used for connecting the third electrode and the third connecting electrode; and the fourth via, the fifth via, and a portion of the sixth via in a row of the sub-pixel group are substantially located on a second straight line.

[0023] For example, in a display substrate provided in an embodiment of this disclosure, the two sixth vias of the two third sub-pixels in the third sub-pixel pair are respectively located on two adjacent second straight lines.

[0024] For example, in a display substrate provided in one embodiment of this disclosure, the first straight line and the second straight line substantially overlap in a row of sub-pixel groups.

[0025] For example, in a display substrate provided in an embodiment of this disclosure, the fourth via, the first via, the sixth via, the third via, the fifth via, the second via, the sixth via, and the third via in a row of sub-pixel groups are arranged in a cyclical sequence.

[0026] For example, in a display substrate provided in an embodiment of this disclosure, the first via, the second via, the third via, the fourth via, the fifth via, and the sixth via are arranged at intervals.

[0027] For example, in a display substrate provided in one embodiment of this disclosure, the first via, the second via, and the third via are arranged at equal intervals.

[0028] For example, in a display substrate provided in one embodiment of this disclosure, the fourth via, the fifth via, and the sixth via are arranged at equal intervals.

[0029] For example, in a display substrate provided in one embodiment of this disclosure, the distance between the first via and the fourth via is less than the distance between the first via and the second via, the distance between the second via and the fifth via is less than the distance between the second via and the third via, and the distance between the third via and the sixth via is less than the distance between the second via and the third via.

[0030] For example, in a display substrate provided in one embodiment of this disclosure, the first straight line is located between two adjacent rows of sub-pixel groups.

[0031] At least one embodiment of this disclosure also provides a display device including the display substrate described in any of the above claims. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0033] Figure 1 This is a schematic diagram of the structure of an OLED display substrate;

[0034] Figure 2A This is a schematic diagram of the light emission of a sub-pixel in a display substrate;

[0035] Figure 2B This is a schematic diagram illustrating the light emission of sub-pixels in another type of display substrate;

[0036] Figure 3 This is a plan view of a display substrate provided according to an embodiment of the present disclosure;

[0037] Figure 4 This is a plan view of another display substrate provided according to an embodiment of the present disclosure;

[0038] Figure 5 This is a plan view of another display substrate provided according to an embodiment of the present disclosure;

[0039] Figure 6 This is a schematic diagram of the structure of a sub-pixel in a display substrate according to an embodiment of the present disclosure;

[0040] Figure 7 This is a plan view of a display substrate provided according to an embodiment of the present disclosure;

[0041] Figure 8 This is a schematic diagram of the structure of a sub-pixel in a display substrate according to an embodiment of the present disclosure; and

[0042] Figure 9This is a schematic diagram of the structure of a sub-pixel in another display substrate according to an embodiment of the present disclosure. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0045] Figure 1 This is a schematic diagram of the structure of an OLED display substrate. Figure 1 As shown, the OLED display substrate includes: a substrate 10, a pixel driving circuit 20, a planarization layer 30, an anode 40, a pixel defining layer 50, and a spacer (PS) 60. The pixel driving circuit 20 is disposed on the substrate 10; the planarization layer 30 is disposed on the side of the pixel driving circuit 20 away from the substrate 10; the anode 40 is disposed on the side of the planarization layer 30 away from the substrate 10 and can be electrically connected to the pixel driving circuit 20 through a via 35 in the planarization layer 30; the pixel defining layer 50 is disposed on the side of the anode 40 away from the substrate 10 and has an opening 52 that exposes the anode 40; the spacer 60 is disposed on the side of the pixel defining layer 50 away from the substrate 10. The orthographic projection of the spacer 60 on the substrate 10 does not overlap with the orthographic projection of the opening 52 on the substrate 10.

[0046] like Figure 1As shown, an opening 52 can be provided with a light-emitting layer (not shown in the figure), which is in contact with the anode 50. A cathode (not shown in the figure) can also be provided on the side of the light-emitting layer away from the anode 50. The light-emitting layer can emit light under the influence of the current between the anode and the cathode. Typically, the area of ​​the anode 50 is slightly larger than the area of ​​the opening 52, so the opening 52 can define the effective light-emitting area of ​​a sub-pixel. The spacer 60 is usually provided around the sub-pixel and can serve to support the fine metal mask (FMM) during the deposition of the light-emitting layer. However, typical spacer arrangements have the following problems: When the spacer density is high, the FMM placed on top of the spacers may scratch them, causing the scratched parts to detach and form particles, directly leading to particle risk and reducing product yield. On the other hand, when a spacer is placed on the first lateral side of a subpixel, the spacer restricts the emission angle of that subpixel on the first lateral side, while the second lateral side (opposite to the first lateral side) of the subpixel, without a spacer, does not restrict the emission angle of that subpixel on the second lateral side. The light emission angle of the side causes the brightness of the sub-pixel observed from the first lateral side to be different from that observed from the second lateral side when viewed from the first lateral side and the second lateral side at the same angle to the normal of the display substrate. This results in color shift at different viewing angles, that is, the color observed from the first lateral side is different from the color observed from the second lateral side. Furthermore, since the distribution of the spacers around the sub-pixels of different colors is different, the degree to which the sub-pixels of different colors are affected by the spacers is different, which will further cause the display substrate to produce color shift when viewing the image at different viewing angles.

[0047] Figure 2A This is a schematic diagram of the light emission of a sub-pixel in a display substrate. Figure 2B This is a schematic diagram illustrating the light emission of sub-pixels in another type of display substrate. Figure 2A and 2B The diagram shows a blue sub-pixel 71, a red sub-pixel 72, a pixel defining layer 50, and a spacer 60 located between the blue sub-pixel 71 and the red sub-pixel 72. Figure 2A and 2B As shown, due to the blocking effect of the spacer 60, the blue sub-pixel 71 is directed towards the first lateral side (e.g., Figure 2A The light emitted from the left side of the image will be blocked by the pixel limiting layer 50, while the blue sub-pixel 71 will emit light towards the second lateral side (such as...). Figure 2AThe light emitted from the right side of the pixel (in the image) is blocked by the pixel limiting layer 50 and the spacer 60. The spacer 60 is disposed on the pixel limiting layer 50, which causes the light emitted by the blue sub-pixel 71 to be blocked more severely. On the one hand, the brightness of the light emitted by the blue sub-pixel 71 to the second lateral side is less than the brightness of the light emitted by the blue sub-pixel 71 to the first lateral side. On the other hand, it also causes the viewing angle of the blue sub-pixel 71 on the second lateral side to be less than the viewing angle of the blue sub-pixel 71 on the first lateral side. Conversely, due to the blocking effect of the spacer 60, the light emitted by the red sub-pixel 72 to the first lateral side is blocked more severely. On the one hand, the brightness of the light emitted by the red sub-pixel 72 to the first lateral side is less than the brightness of the light emitted by the red sub-pixel 72 to the second lateral side. On the other hand, it also causes the viewing angle of the red sub-pixel 72 on the first lateral side to be less than the viewing angle of the red sub-pixel 72 on the second lateral side. Therefore, when viewed from the first lateral side and the second lateral side at the same angle to the normal of the display substrate, the brightness of the blue or red sub-pixel observed from the first lateral side is different from the brightness of the sub-pixel observed from the second lateral side. This results in color shift when viewing the image from different angles, i.e., the color observed from the first lateral side is different from the color observed from the second lateral side. In addition, due to the different distribution of the spacers around the blue and red sub-pixels, the brightness of the light emitted by the blue sub-pixel towards the second lateral side is less than the brightness of the light emitted by the blue sub-pixel towards the first lateral side, and the brightness of the light emitted by the red sub-pixel towards the first lateral side is less than the brightness of the light emitted by the red sub-pixel towards the second lateral side. This will further cause color shift when viewing the image from different angles.

[0048] In this regard, embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a substrate, a plurality of sub-pixel groups, a first spacer, a second spacer, and a third spacer. The plurality of sub-pixel groups are arranged on the substrate along row and column directions, and each sub-pixel group includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In a row of sub-pixel groups, the first spacer is located between adjacent first and second sub-pixels, the second spacer is located between adjacent second and third sub-pixels, and the third spacer is located between adjacent third and first sub-pixels. The number of first spacers, the number of second spacers, and the number of third spacers are approximately equal. Therefore, for a sub-pixel in a row of sub-pixel groups (e.g., the first sub-pixel, the second sub-pixel, or the third sub-pixel), since the number of the first spacers, the second spacers, and the third spacers are approximately equal, and the number of spacers on the first lateral side and the second lateral side of each sub-pixel is also approximately the same, the symmetry of the spacers in the row of sub-pixel groups is improved. This makes the brightness of a sub-pixel in the row of sub-pixel groups approximately the same when viewed from the first lateral side and the second lateral side at the same angle as the normal to the display substrate. This improves or even eliminates color shift when viewing the image from different viewing angles. Furthermore, since the number of the first spacers, the second spacers, and the third spacers are approximately equal, the number of spacers around different sub-pixels in a row of sub-pixel groups is also approximately the same. This makes the occlusion of different sub-pixels in a row of sub-pixel groups by spacers approximately the same, further improving or even eliminating color shift when viewing the image from different viewing angles. Therefore, this display substrate can effectively improve or even avoid color shift caused by uneven distribution of spacers.

[0049] The display substrate and display device provided in the embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0050] Figure 3 This is a planar schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 3As shown, the display substrate 100 includes a substrate 110, a plurality of sub-pixel groups 120, a first spacer 131, a second spacer 132, and a third spacer 133. The plurality of sub-pixel groups 120 are disposed on the substrate 110 and arranged along the row and column directions, and each sub-pixel group 120 includes a first sub-pixel 121, a second sub-pixel 122, and a third sub-pixel 123. In a row of subpixel groups 120, the first spacer 131 is located between adjacent first subpixels 121 and second subpixels 122, that is, the first spacer 131 is located in the interval region between adjacent first subpixels 121 and second subpixels 122; the second spacer 132 is located between adjacent second subpixels 122 and third subpixels 123, that is, the second spacer 132 is located in the interval region between adjacent second subpixels 122 and third subpixels 123; the third spacer 133 is located between adjacent third subpixels 123 and first subpixels 121, that is, the third spacer 133 is located in the interval region between adjacent third subpixels 123 and first subpixels 121; and the number of first spacers 131, the number of second spacers 132, and the number of third spacers 133 are approximately equal. It should be noted that... Figure 3 The first sub-pixel 121 shown can be the effective light-emitting area of ​​the first sub-pixel 121. Figure 3 The second sub-pixel 122 shown can be the effective light-emitting area of ​​the second sub-pixel 122. Figure 3 The third sub-pixel 123 shown can be the effective light-emitting area of ​​the third sub-pixel 123. In addition, in the display field, a pixel usually includes multiple sub-pixels that can display a single color (e.g., red, green, or blue). Different colors can be displayed by controlling the proportion of sub-pixels of different colors. Therefore, the first sub-pixel mentioned above can be a single-color sub-pixel.

[0051] In the display substrate provided in the embodiments of this disclosure, for a sub-pixel (e.g., first sub-pixel 121, second sub-pixel 122, or third sub-pixel 123) in a row of sub-pixel groups 120, since the number of first spacers 131, second spacers 132, and third spacers 133 are approximately equal, and the number of spacers on the first lateral side and the second lateral side of each sub-pixel is also approximately the same, the symmetry of the influence of spacers in a row of sub-pixel groups on the light emission of sub-pixels is improved, so that when viewed from the first lateral side and the second lateral side at the same angle as the normal of the display substrate, the brightness of a sub-pixel in a row of sub-pixel groups observed from the first lateral side and the second lateral side is approximately the same, thereby improving or even eliminating color shift when viewing the image from different viewing angles. For example, suppose that in a row of subpixel group 120, 100 first subpixels 121 have third spacers 133 on their first horizontal sides, and 100 second subpixels 122 have first spacers 131 on their second horizontal sides. In this case, due to the blocking effect of the third spacers 133, the light emitted from the 100 first subpixels 121 with third spacers 133 on their first horizontal sides towards the first horizontal side will be blocked by the third spacers 133, thus causing the light emitted from the 100 first subpixels 121 with third spacers 133 on their first horizontal sides towards the first horizontal side to be blocked. The brightness of the line is less than the brightness of the light emitted towards the second lateral side; conversely, the brightness of the light emitted towards the second lateral side by the 100 first sub-pixels 121 with the first spacer 131 on the second lateral side is less than the brightness of the light emitted towards the first lateral side; considering the first sub-pixels 121 in the row of sub-pixels 120 as a whole, the brightness of the light emitted towards the second lateral side by these first sub-pixels 121 is approximately equal to the brightness of the light emitted towards the first lateral side by these first sub-pixels 121, thereby improving or even eliminating color shift when viewing the image from different angles. For example, in some examples, in a row of sub-pixel groups 120, the number of first spacers 131, the number of second spacers 132, and the number of third spacers 133 are equal, thereby better improving or even eliminating color shift when viewing the image from different angles.

[0052] Figure 4 This is a planar schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 4As shown, the display substrate 100 includes a substrate 110, a plurality of sub-pixel groups 120, a first spacer 131, a second spacer 132, and a third spacer 133. The plurality of sub-pixel groups 120 are disposed on the substrate 110 and arranged along the row and column directions. Each sub-pixel group 120 includes a first sub-pixel 121, a second sub-pixel 122, and a third sub-pixel pair 126. The third sub-pixel pair 126 includes two third sub-pixels 123. In a row of subpixel groups 120, the first spacer 131 is located between adjacent first subpixels 121 and second subpixels 122, that is, the first spacer 131 is located in the gap area between adjacent first subpixels 121 and second subpixels 122; the second spacer 132 is located between adjacent second subpixels 122 and third subpixel pairs 126, that is, the second spacer 132 is located in the gap area between adjacent second subpixels 122 and third subpixel pairs 126; the third spacer 133 is located between adjacent third subpixel pairs 126 and first subpixels 121, that is, the third spacer 133 is located in the gap area between adjacent third subpixel pairs 126 and first subpixels 121; and the number of first spacers 131, the number of second spacers 132, and the number of third spacers 133 are approximately equal. It should be noted that... Figure 4 The first sub-pixel 121 shown can be the effective light-emitting area of ​​the first sub-pixel 121. Figure 4 The second sub-pixel 122 shown can be the effective light-emitting area of ​​the second sub-pixel 122. Figure 4 The third sub-pixel 123 shown can be the effective light-emitting area of ​​the third sub-pixel 123. In addition, in the display field, a pixel usually includes multiple sub-pixels that can display a single color (e.g., red, green, or blue). Different colors can be displayed by controlling the proportion of sub-pixels of different colors. Therefore, the first sub-pixel mentioned above can be a single-color sub-pixel.

[0053] In the display substrate provided in the embodiments of this disclosure, for a sub-pixel (e.g., first sub-pixel 121, second sub-pixel 122, or third sub-pixel 123) in a row of sub-pixel groups 120, since the number of first spacers 131, second spacers 132, and third spacers 133 are approximately equal, and the number of spacers on the first lateral side and the second lateral side of each sub-pixel is also approximately the same, the symmetry of the influence of spacers in a row of sub-pixel groups on the light emission of sub-pixels is improved, so that when viewed from the first lateral side and the second lateral side at the same angle as the normal of the display substrate, the brightness of a sub-pixel in a row of sub-pixel groups observed from the first lateral side and the second lateral side is approximately the same, thereby improving or even eliminating color shift when viewing the image from different viewing angles. For example, suppose that in a row of subpixel group 120, 100 first subpixels 121 have third spacers 133 on their first horizontal sides, and 100 second subpixels 122 have first spacers 131 on their second horizontal sides. In this case, due to the blocking effect of the third spacers 133, the light emitted from the 100 first subpixels 121 with third spacers 133 on their first horizontal sides towards the first horizontal side will be blocked by the third spacers 133, thus causing the light emitted from the 100 first subpixels 121 with third spacers 133 on their first horizontal sides towards the first horizontal side to be blocked. The brightness of the line is less than the brightness of the light emitted towards the second lateral side; conversely, the brightness of the light emitted towards the second lateral side by the 100 first sub-pixels 121 with the first spacer 131 on the second lateral side is less than the brightness of the light emitted towards the first lateral side; considering the first sub-pixels 121 in the row of sub-pixels 120 as a whole, the brightness of the light emitted towards the second lateral side by these first sub-pixels 121 is approximately equal to the brightness of the light emitted towards the first lateral side by these first sub-pixels 121, thereby improving or even eliminating color shift when viewing the image from different angles.

[0054] Furthermore, in the display substrate provided in this embodiment, for a type of sub-pixel (e.g., first sub-pixel 121, second sub-pixel 122, or third sub-pixel 123) in a row of sub-pixel groups 120, since the number of first spacers 131, second spacers 132, and third spacers 133 are approximately equal, the number of spacers surrounding different sub-pixels in a row of sub-pixel groups 120 is also approximately the same. This results in the same degree of occlusion by spacers (e.g., first spacers 131, second spacers 132, and third spacers 133) in a row of sub-pixel groups 120. In other words, the occlusion of first sub-pixel 121, second sub-pixel 122, and third sub-pixel 123 in a row of sub-pixel groups 120 is also approximately the same, thereby further improving or even eliminating color shift when viewing the image from different angles. Therefore, this display substrate can effectively improve or even avoid color shift caused by uneven distribution of spacers.

[0055] For example, the statement that the number of the first septum, the number of the second septum, and the number of the third septum are approximately equal can mean that the ratio of the number of the first septum, the number of the second septum, and the number of the third septum to the average number of the first septum, the number of the second septum, and the number of the third septum is in the range of 0.9-1.1.

[0056] For example, the first, second, and third spacers described above can be made of polyimide. Of course, the embodiments disclosed herein include, but are not limited to, the first, second, and third spacers described above can also be made of other materials such as silicone.

[0057] For example, the first, second, and third spacers can also be made of materials with high light transmittance, thereby reducing the light-blocking effect of the first, second, and third spacers.

[0058] For example, in some examples, such as Figure 4 As shown, in a row of subpixel groups 120, the first spacer 131, the second spacer 132, and the third spacer 133 are arranged sequentially and cyclically. That is, in a row of subpixel groups 120, the first spacer 131, the second spacer 132, and the third spacer 133 are continuously repeated as a group. Therefore, within a certain area of ​​a row of subpixel groups 120, the number of first spacers 131, the number of second spacers 132, and the number of third spacers 133 can be ensured to be approximately equal, thereby further improving or even eliminating color shift when viewing the image from different angles.

[0059] For example, a row of sub-pixel groups 120 is divided into N (N is a positive integer greater than or equal to 1) regions arranged sequentially. Each region includes M (M is a positive integer greater than or equal to 1) groups consisting of the aforementioned first spacer 131, second spacer 132, and third spacer 133. In this case, for each region, the number of spacers on the first lateral side and the second lateral side of each type of sub-pixel is approximately the same, thereby improving the symmetry of the influence of the spacers on the light emission of the sub-pixel in this region. This makes the brightness of a sub-pixel in this region approximately the same when viewed from the first lateral side and the second lateral side at the same angle as the normal to the display substrate. This further improves or even avoids color shift caused by uneven distribution of spacers. Similarly, for each region, for each type of sub-pixel in each region, the number of spacers around different sub-pixels in each region is approximately the same, making the occlusion of different sub-pixels in each region approximately the same. This further improves or even eliminates color shift when viewing the image from different viewing angles.

[0060] For example, in some examples, such as Figure 4 As shown, each sub-pixel group 120 includes at most one first spacer 131, one second spacer 132, or one third spacer 133, thereby reducing the density of the spacers and thus controlling particle risk.

[0061] For example, in some examples, such as Figure 4 As shown, in each subpixel group 120, the first subpixel 121, the second subpixel 122, and the third subpixel pair 126 are arranged along the row direction to form three subpixel columns 128, and the two third subpixels 123 in a third subpixel pair 126 are arranged along the column direction. That is, each subpixel group 120 may include three subpixel columns 128. Therefore, the pixel arrangement structure of this display substrate can be used with pixel borrowing technology, thereby improving the resolution of the display substrate.

[0062] For example, in some examples, such as Figure 4As shown, in a row of subpixel groups 120, the first spacer 131 and the second spacer 132 are spaced by 1+3n subpixel columns 128, the second spacer 132 and the third spacer 133 are spaced by 1+3n subpixel columns 128, and the third spacer 133 and the first spacer 131 are spaced by 1+3n subpixel columns 128, where n is a positive integer greater than or equal to 1. For OLED display substrates, the spacers serve two purposes: one is to support the FMM used for vapor deposition, and the other is to support the cover plate during encapsulation. Thus, on the one hand, the display substrate provided in this example can ensure that the number of the first spacers 131, the number of the second spacers 132, and the number of the third spacers 133 in a row of subpixel groups 120 are approximately equal; on the other hand, when the value of n is large, for example, when n is greater than or equal to 2, the display substrate provided in this example can further reduce the density of the spacers, thereby reducing the particle risk when supporting the FMM used for vapor deposition and improving product yield. Of course, the value of n can be set according to the needs of supporting FMM and reducing particle risk.

[0063] For example, in some examples, such as Figure 4 As shown, adjacent rows of sub-pixel groups 120 are offset by 1 / 2 pitch, where the pitch is the distance between the centers of two first sub-pixels 121 in two adjacent sub-pixel groups 120 along the row direction. It should be noted that the pitch can also be the distance between the centers of two second sub-pixels 122 or third sub-pixel pairs 126 in two adjacent sub-pixel groups 120 along the row direction; the aforementioned center can be the geometric center of the sub-pixel. Furthermore, adjacent rows of sub-pixel groups 120 are offset by 1 / 2 pitch along the row direction. Of course, embodiments of this disclosure include, but are not limited to, other offset distances for adjacent rows of sub-pixel groups 120.

[0064] For example, in some examples, such as Figure 4 As shown, the first sub-pixel 121 is configured to emit light of a first color, the second sub-pixel 122 is configured to emit light of a second color, and the third sub-pixel 123 is configured to emit light of a third color. It should be noted that embodiments of this disclosure include, but are not limited to, the following: one third sub-pixel in a third sub-pixel pair may be configured to emit light of a third color, while the other third sub-pixel in the third sub-pixel pair may be configured to emit light of a fourth color.

[0065] For example, the first color is blue, the second color is red, and the third color is green. Thus, the display substrate adopts a red-green-blue color scheme; of course, this disclosure includes, but is not limited to, other color schemes that the display substrate may also adopt.

[0066] For example, in some examples, such as Figure 4As shown, the effective light-emitting area of ​​the first sub-pixel 121 is roughly hexagonal or elliptical in shape, with the long axis of symmetry of the hexagon or the long axis of the ellipse being roughly parallel to the column direction.

[0067] For example, in some examples, such as Figure 4 As shown, the effective light-emitting area of ​​the second sub-pixel 122 is also roughly hexagonal or elliptical in shape, with the long axis of symmetry of the hexagon or the long axis of the ellipse being roughly parallel to the column direction.

[0068] For example, in some examples, such as Figure 4 As shown, the effective light-emitting area of ​​the third sub-pixel 123 is roughly pentagonal in shape, with the right-angled sides of the pentagon roughly parallel to the row direction.

[0069] It should be noted that the aforementioned effective light-emitting areas are generally designed with regular shapes, such as hexagons, pentagons, or ellipses. However, in actual manufacturing processes, the shape of the formed effective light-emitting areas will generally deviate somewhat from the designed regular shape. For example, the corners of the aforementioned regular shape may become rounded corners; therefore, the shape of the effective light-emitting areas (e.g., the first, second, or third effective light-emitting areas) can be a rounded shape. Furthermore, the shape of the actually manufactured effective light-emitting areas may also vary from the designed shape. For example, an effective light-emitting area designed as a hexagon may become approximately elliptical in actual manufacturing.

[0070] For example, in some examples, such as Figure 4 As shown, the first spacer 131 is generally elongated, and its extension direction is generally parallel to the column direction. The second spacer 132 is also generally elongated, and its extension direction is generally parallel to the column direction. The third spacer 133 is also generally elongated, and its extension direction is generally parallel to the column direction. Therefore, since the sub-pixels are typically also elongated (hexagonal or elliptical), the display substrate can fully utilize the spacing or gaps between the sub-pixels. For example, the shape of the aforementioned spacers (e.g., the first spacer, the second spacer, or the third spacer) is the shape of the orthographic projection of the spacer onto the substrate. Similarly, the shape of the effective light-emitting area of ​​the aforementioned sub-pixel (e.g., the first sub-pixel, the second sub-pixel, or the third sub-pixel) is the shape of the orthographic projection of the sub-pixel onto the substrate.

[0071] For example, in the embodiments of this disclosure, a strip shape refers to a length in one direction that is greater than the length in another direction, or a dimension in one direction that is greater than the dimension in other directions. The strip shape is not limited to a rectangle and can be other shapes, such as a long hexagon, a long ellipse, a trapezoid, or other shapes.

[0072] For example, in some examples, such as Figure 4 As shown, the size of the first spacer 131 in the column direction is smaller than the size of the first sub-pixel 121 in the column direction, and the sizes of the second spacer 132 and the third spacer 133 in the column direction are smaller than the size of the third sub-pixel pair 126 in the column direction. The centers of the first spacer 131, the second spacer 132, the third spacer 133, the first sub-pixel 121, the second sub-pixel 122, and the third sub-pixel pair 126 are approximately located on a straight line approximately parallel to the row direction.

[0073] For example, in some examples, such as Figure 4 As shown, the first spacer 131, the second spacer 132, and the third spacer 133 have the same dimensions. The width of the first spacer 131 along the row direction ranges from 6 to 15 micrometers, the length of the first spacer 131 along the column direction ranges from 35 to 45 micrometers, and the height of the first spacer 131 along a direction perpendicular to both the row and column directions ranges from 1.5 to 2.5 micrometers. For example, the height of the first spacer 131 along a direction perpendicular to both the row and column directions is 2 micrometers.

[0074] For example, in some examples, the effective light-emitting area of ​​the first sub-pixel 121 has a size range of 15-23 micrometers in the row direction and 35-45 micrometers in the column direction; the effective light-emitting area of ​​the second sub-pixel 122 has a size range of 11-21 micrometers in the row direction and 35-45 micrometers in the column direction; the effective light-emitting area of ​​the third sub-pixel 123 has a size range of 9-13 micrometers in the row direction and 9-13 micrometers in the column direction; and in a pair of third sub-pixels 116, the shortest distance between the two third sub-pixels 113 ranges from 13-15 micrometers.

[0075] Figure 5 This is a plan view of another display substrate provided according to an embodiment of the present disclosure. Figure 6 This is a schematic diagram illustrating the structure of a sub-pixel in a display substrate according to an embodiment of the present disclosure. To clearly illustrate the structure of the sub-pixel group in the display substrate, Figure 5 Only one sub-pixel group is shown. (Example) Figure 6 As shown, in the sub-pixel group 120, the first sub-pixel 121 includes a first anode 1212 and a first light-emitting functional layer 1214, the second sub-pixel 122 includes a second anode 1222 and a second light-emitting functional layer 1224, and the third sub-pixel 123 includes a third anode 1232 and a third light-emitting functional layer 1234. Figure 5 and 6As shown, the display substrate further includes a pixel defining layer 160 located on the side of the first anode 1212, the second anode 1222, and the third anode 1232 away from the substrate 110. The pixel defining layer 160 includes a first opening 171, a second opening 172, and a third opening 173. The first opening 171 exposes the first anode 1212, the second opening 172 exposes the second anode 1222, and the third opening 173 exposes the third anode 1232. At least a portion of a first light-emitting functional layer 1214 is located in the first opening 171 and covers the exposed portion of the first anode 1212. At least a portion of a second light-emitting functional layer 1224 is located in the second opening 172 and covers the exposed portion of the second anode 1222. At least a portion of a third light-emitting functional layer 1234 is located in the third opening 173 and covers the exposed portion of the third anode 1232. A first spacer 131, a second spacer 132, and a third spacer 133 are located on the surface of the pixel defining layer 160 away from the substrate 110. It should be noted that the area of ​​the first anode 1212 can be slightly larger than the area of ​​the first light-emitting functional layer 1214. Furthermore, the first light-emitting functional layer 1214 may include the electroluminescent layer itself and other functional layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer, etc. The area of ​​the second anode 1222 can be slightly larger than the area of ​​the second light-emitting functional layer 1224. Furthermore, the second light-emitting functional layer 1224 may include the electroluminescent layer itself and other functional layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer, etc. The area of ​​the third anode 1232 can be slightly larger than the area of ​​the third light-emitting functional layer 1234. Furthermore, the third light-emitting functional layer 1234 may include the electroluminescent layer itself and other functional layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer, etc. For example, in some examples, the orthographic projections of the first spacer 131, the second spacer 132, and the third spacer 133 on the substrate 101 do not overlap with the orthographic projections of the first opening 171, the second opening 172, and the third opening 173 on the substrate 101.

[0076] For example, in some examples, the orthographic projection of the first opening 171 on the substrate 101 is completely within the orthographic projection of the first anode 1212 on the substrate 101; the orthographic projection of the second opening 172 on the substrate 101 is completely within the orthographic projection of the second anode 1222 on the substrate 101; and the orthographic projection of the third opening 173 on the substrate 101 is completely within the orthographic projection of the third anode 1232 on the substrate 101.

[0077] For example, in some examples, the orthographic projection of the first opening 171 on the substrate 101 is completely within the orthographic projection of the first light-emitting functional layer 1214 on the substrate 101; the orthographic projection of the second opening 172 on the substrate 101 is completely within the orthographic projection of the second light-emitting functional layer 1224 on the substrate 101; and the orthographic projection of the third opening 173 on the substrate 101 is completely within the orthographic projection of the third light-emitting functional layer 1234 on the substrate 101.

[0078] For example, in some examples, the edges of the orthographic projection of the first anode 1212 on the substrate 101, the edges of the orthographic projection of the second anode 1222 on the substrate 101, and the edges of the orthographic projection of the third anode 1232 on the substrate 101 are covered by the orthographic projection of the pixel defining layer 160 on the substrate 101.

[0079] For example, in some examples, the first light-emitting functional layer 1214 may also partially cover the pixel-defining layer 160, the second light-emitting functional layer 1224 may also partially cover the pixel-defining layer 160, and the third light-emitting functional layer 1234 may also partially cover the pixel-defining layer 160.

[0080] For example, in some examples, the first spacer 131, the second spacer 132, and the third spacer 133 are formed in a single masking process. For example, a spacer layer may first be formed on the surface of the pixel defining layer 160 away from the substrate 110, and then the spacer layer may be patterned by a patterning process to form the first spacer 131, the second spacer 132, and the third spacer 133.

[0081] For example, in some examples, the first spacer 131, the second spacer 132, and the third spacer 133, and the pixel defining layer 160 are also formed by a single masking process. For example, the first spacer 131, the second spacer 132, and the third spacer 133, and the pixel defining layer 160 can be made of the same material. At least one embodiment of this disclosure also provides a display device including the aforementioned display substrate. Therefore, this display device can address both spacer density and color shift issues. On the one hand, it can improve or even eliminate color shift when viewing the image from different angles; on the other hand, it can reduce spacer density, thereby controlling particle risk and improving product yield. When the display device uses a display panel with the pixel arrangement structure provided in the embodiments of this disclosure, the resolution of the display device can be further improved, thus providing a display device with true high resolution. Furthermore, since the pixel arrangement structure provided in the embodiments of this disclosure can have good symmetry, the uniformity of pixel distribution can be improved, thereby enhancing the display effect of the display device.

[0082] For example, in some examples, the display device can be any product or component with display capabilities, such as a smartphone, tablet, television, monitor, laptop, digital photo frame, or navigator.

[0083] One embodiment of this disclosure provides a display substrate. Figure 7 This is a plan view of a display substrate provided according to an embodiment of the present disclosure. Figure 8 This is a schematic diagram of the structure of a sub-pixel in a display substrate according to an embodiment of the present disclosure. Figure 7 As shown, the display substrate includes a substrate 110 and a plurality of subpixel groups 120. The plurality of subpixel groups 120 are disposed on the substrate 110 and arranged along the row and column directions. Each subpixel group 120 includes a first subpixel 121, a second subpixel 122 and a third subpixel pair 126. The third subpixel pair 126 includes two third subpixels 123. Figure 8 A subpixel is shown along Figure 7 A cross-sectional view along the AA direction. (See diagram.) Figure 8 As shown, the first sub-pixel 121 includes a first anode 1212 and a first pixel driving circuit 1216; the second sub-pixel 122 includes a second anode 1222 and a second pixel driving circuit 1226; and the third sub-pixel 123 includes a third anode 1232 and a third pixel driving circuit 1236. The display substrate also includes a first planarization layer 140, which is located between the first anode 1212 and the first pixel driving circuit 1216, between the second anode 1222 and the second pixel driving circuit 1226, and between the third anode 1232 and the third pixel driving circuit 1236. The first sub-pixel 121 includes a first via 141 located in the first planarization layer 140, the second sub-pixel 122 includes a second via 142 located in the first planarization layer 140, and the third sub-pixel 123 includes a third via 143 located in the first planarization layer 140. The first via 141 is used to connect the first anode 1212 and the first pixel driving circuit 1216, the second via 142 is used to connect the second anode 1222 and the second pixel driving circuit 1226, and the third via 143 is used to connect the third anode 1232 and the third pixel driving circuit 1236. The first via 141, the second via 142, and part of the third via 143 in a row of sub-pixel groups 120 are approximately located on the same straight line. It should be noted that the portion of the first anode used for connection can cover and fill the corresponding first via, thereby connecting with the corresponding first pixel driving circuit; the portion of the second anode used for connection can cover and fill the corresponding second via, thereby connecting with the corresponding second pixel driving circuit; and the portion of the third anode used for connection can cover and fill the corresponding third via, thereby connecting with the corresponding third pixel driving circuit.

[0084] In the display substrate provided in this embodiment, since the first via 141, the second via 142, and a portion of the third via 143 in a row of sub-pixel groups 120 are approximately located on a first straight line, that is, the first via 141, the second via 142, and a portion of the third via 143 are arranged in a row with a spacing of one sub-pixel distance, when the process margin changes, the first via 141, the second via 142, and a portion of the third via 143 can move up and down simultaneously, thereby facilitating the control of process deviations. For example, when the process margin changes significantly, the simultaneous up and down movement of the first via 141, the second via 142, and a portion of the third via 143 will either result in defects for all of them or no defects for all of them, thus facilitating the control of process deviations. It should be noted that when defects occur in the first via 141, the second via 142, and a portion of the third via 143, these defects are easily detected, allowing for timely adjustments to the process.

[0085] For example, in some examples, such as Figure 7 As shown, in any two adjacent sub-pixel groups 120, the first via 141 of the first sub-pixel 121, the second via 142 of the second sub-pixel 122, and the third via 143 of the third sub-pixel 123 in the third pixel pair 126 are approximately located on the same straight line. Therefore, when the process margin changes, these first vias 141, second vias 142, and third vias 143 can move up and down simultaneously, facilitating the control of process deviations.

[0086] For example, in some examples, such as Figure 7 As shown, the first straight line mentioned above does not overlap with the effective light-emitting area of ​​each sub-pixel (e.g., the first sub-pixel, the second sub-pixel, and the third sub-pixel). In other words, the first straight line mentioned above is not located in the overlapping area of ​​the organic layer and the anode of each sub-pixel.

[0087] For example, in some examples, such as Figure 7 As shown, the first straight line is located between adjacent pixel groups.

[0088] For example, in some examples, such as Figure 7 As shown, the first straight line containing the first via 141, the second via 142, and part of the third via 143 in a row of subpixel group 120 is approximately parallel to the row direction. For example, in some examples, such as Figure 7As shown, in each sub-pixel group 120, the first sub-pixel 121, the second sub-pixel 122, and the third sub-pixel pair 126 are arranged along the row direction, and the two third sub-pixels 123 in the third sub-pixel pair 126 are arranged along the column direction. The two third vias of the two sub-pixels in the third sub-pixel pair are located on two adjacent first straight lines. That is, one of the two third vias 143 of the two third sub-pixels 123 arranged along the column direction in the third sub-pixel pair 126 is on the same straight line as the first via 141 and the second via 142 in the sub-pixel group row (which can be denoted as the Nth sub-pixel group row) to which the third sub-pixel pair 126 belongs, while the other is on the same straight line as the first via 141 and the second via 142 in the sub-pixel group row (which can be denoted as the N-1th sub-pixel group row) adjacent to the sub-pixel group row to which the third sub-pixel pair 126 belongs.

[0089] For example, in some examples, such as Figure 8 As shown, the first pixel driving circuit 1216 may include a first active layer 12161, a first gate insulating layer 12162, a first gate 12163, a first interlayer insulating layer 12164, and a first source / drain electrode layer 12165; the second pixel driving circuit 1226 may include a second active layer 12261, a second gate insulating layer 12262, a second gate 12263, a second interlayer insulating layer 12264, and a second source / drain electrode layer 12265; the third pixel driving circuit 1236 may include a third active layer 12361, a third gate insulating layer 12362, a third gate 12363, a third interlayer insulating layer 12364, and a third source / drain electrode layer 12365.

[0090] For example, the source and drain electrodes in the first source-drain electrode layer 12165 are connected to the source and drain regions of the first active layer 12161 respectively through vias in the first gate insulating layer 12162 and the first interlayer insulating layer 12164; the orthographic projection of the first gate 12163 on the substrate 101 overlaps with the orthographic projection of the channel region of the first active layer 12161 on the substrate 101. The source and drain electrodes in the second source-drain electrode layer 12265 are connected to the source and drain regions of the second active layer 12261 respectively through vias in the second gate insulating layer 12262 and the second interlayer insulating layer 12264; the orthographic projection of the second gate 12263 on the substrate 101 overlaps with the orthographic projection of the channel region of the second active layer 12261 on the substrate 101. The source and drain electrodes in the third source-drain electrode layer 12365 are connected to the source and drain regions of the third active layer 12361 respectively through vias in the third gate insulating layer 12362 and the third interlayer insulating layer 12364; the orthographic projection of the third gate 12363 on the substrate 101 overlaps with the orthographic projection of the channel region of the third active layer 12361 on the substrate 101. For example, in some examples, the first active layer 12161, the second active layer 12261, and the third active layer 12361 can be fabricated using the same semiconductor layer; for example, the first active layer 12161, the second active layer 12261, and the third active layer 12361 can be made of materials such as polycrystalline silicon, single-crystal silicon, and oxide semiconductor.

[0091] For example, in some examples, the first gate insulating layer 12162, the second gate insulating layer 12262, and the third gate insulating layer 12362 are the same gate insulating layer; for example, the first gate insulating layer 12162, the second gate insulating layer 12262, and the third gate insulating layer 12362 can be made of insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0092] For example, in some examples, the first gate 12163, the second gate 12263, and the third gate 12363 can be fabricated using the same conductive layer; for example, the first gate 12163, the second gate 12263, and the third gate 12363 can be fabricated using conductive materials such as molybdenum, titanium, aluminum, and copper.

[0093] For example, in some examples, the first interlayer insulation layer 12164, the second interlayer insulation layer 12264, and the third interlayer insulation layer 12364 are the same interlayer insulation layer; the first interlayer insulation layer 12164, the second interlayer insulation layer 12264, and the third interlayer insulation layer 12364 can be made of insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0094] For example, in some examples, the first source / drain electrode layer 12165, the second source / drain electrode layer 12265, and the third source / drain electrode layer 12365 may be made of the same conductive layer; for example, the first source / drain electrode layer 12165, the second source / drain electrode layer 12265, and the third source / drain electrode layer 12365 may be made of materials such as aluminum, titanium, copper, and molybdenum. Figure 9 This is a schematic diagram of the structure of a sub-pixel in another display substrate according to an embodiment of the present disclosure. Figure 9 As shown, the display substrate further includes: a second planarization layer 150, located between the first planarization layer 140 and the first pixel driving circuit 1216, the second pixel driving electrode 1226, and the third pixel driving circuit 1236; the first pixel driving circuit 1216 includes a first electrode 181, the second pixel driving circuit 1226 includes a second electrode 182, and the third pixel driving circuit 1236 includes a third electrode 183; the display substrate further includes a first connection electrode 191, a second connection electrode 192, and a third connection electrode 193, located between the second planarization layer 150 and the first planarization layer 140; the first sub-pixel 121 further includes a first connection electrode 191, a second connection electrode 192, and a third connection electrode 193, located between the second planarization layer 150 and the first planarization layer 140; and the first sub-pixel 121 further includes a first connection electrode 191, a second connection electrode 192, and a third connection electrode 193, located between the second planarization layer 150 and the first planarization layer 140. The fourth via 151 in the planarization layer 150, the second sub-pixel 122 also includes a fifth via 152 located in the second planarization layer 150, and the third sub-pixel 123 also includes a sixth via 153 located in the second planarization layer 150. The fourth via 151 is used to connect the first electrode 181 and the first connecting electrode 191, the fifth via 152 is used to connect the second electrode 182 and the second connecting electrode 192, and the sixth via 153 is used to connect the third electrode 183 and the third connecting electrode 193. The fourth via 151, the fifth via 152, and part of the sixth via 153 in a row of sub-pixel groups 120 are approximately located on the second straight line. It should be noted that the first electrode, the second electrode, and the third electrode mentioned above can be the drain electrode in the source-drain electrode layer of the corresponding pixel driving circuit.

[0095] In the display substrate provided in this embodiment, since the fourth via 151, the fifth via 152, and a portion of the sixth via 153 in a row of sub-pixel groups 120 are approximately located on a second straight line, that is, the fourth via 151, the fifth via 152, and a portion of the sixth via 153 are arranged in a row with a spacing of one sub-pixel distance, when the process margin changes, the fourth via 151, the fifth via 152, and a portion of the sixth via 153 can move up and down simultaneously, thereby facilitating the control of process deviations. For example, when the process margin changes significantly, the simultaneous up and down movement of the fourth via 151, the fifth via 152, and the sixth via 153 will either result in defects for all of them or no defects for all of them, thus facilitating the control of process deviations. It should be noted that when defects occur in all of the fourth via 151, the fifth via 152, and the sixth via 153, these defects are easily detected, allowing for timely adjustments to the process.

[0096] For example, in some examples, such as Figure 7 As shown, in any two adjacent sub-pixel pairs 120, the fourth via 151 of the first sub-pixel 121, the fifth via 152 of the second sub-pixel 122, and the sixth via 153 of the third sub-pixel 123 in the third sub-pixel pair 126 are approximately located on the second straight line. Therefore, when the process margin changes, these fourth vias 151, fifth vias 152, and sixth vias 153 can move up and down simultaneously, facilitating the control of process deviations.

[0097] For example, in some examples, such as Figure 7 As shown, the two sixth vias 153 of the two third sub-pixels 123 in the third sub-pixel pair 126 are located on two adjacent second straight lines. That is, one of the two sixth vias 153 of the two third sub-pixels 123 arranged along the column direction in the third sub-pixel pair 126 is on the same straight line as the fourth via 151 and the fifth via 152 in the sub-pixel group row (which can be denoted as the Nth sub-pixel group row) to which the third sub-pixel pair 126 belongs, while the other is on the same straight line as the fourth via 151 and the fifth via 152 in the sub-pixel group row (which can be denoted as the N-1th sub-pixel group row) adjacent to the sub-pixel group row to which the third sub-pixel pair 126 belongs.

[0098] For example, in some examples, such as Figure 7 As shown, the first and second straight lines in a row of sub-pixel group 120 roughly coincide, for example, they are the same straight line; that is, the first via 141, the second via 142, part of the third via 143, the fourth via 151, the fifth via 152, and part of the sixth via 153 in a row of sub-pixel group 120 are roughly located on the same straight line. Therefore, when the process margin changes, the first via 141, the second via 142, part of the third via 143, the fourth via 151, the fifth via 152, and part of the sixth via 153 can move up and down simultaneously, thus facilitating the control of process deviations. For example, when the process margin changes significantly, the simultaneous up and down movement of the first via 141, the second via 142, part of the third via 143, the fourth via 151, the fifth via 152, and part of the sixth via 153 will either all result in defects or none will result in defects, thus facilitating the control of process deviations. It should be noted that when defects occur in the first via 141, the second via 142, part of the third via 143, the fourth via 151, the fifth via 152, and part of the sixth via 153, these defects are easily detected, allowing for timely adjustments to the process.

[0099] For example, in some examples, such as Figure 7As shown, in any two adjacent sub-pixel groups 120, the first via 141 and the fourth via 151 of the first sub-pixel 121, the second via 142 and the fifth via 152 of the second sub-pixel 122, and the third via 143 and the sixth via 153 of a third sub-pixel 123 in the third sub-pixel pair 126 are approximately located on the same straight line. Therefore, when the process margin changes, these first vias 141, second vias 142, third vias 143, fourth vias 151, fifth vias 152, and sixth vias 153 can move up and down simultaneously, thus facilitating the control of process deviations.

[0100] For example, in some examples, such as Figure 7 As shown, the orthographic projections of the first via 141, the second via 142, the third via 143, the fourth via 151, the fifth via 152, and the sixth via 153 in a row of sub-pixel group 120 on the substrate 110 do not overlap.

[0101] For example, in some examples, such as Figure 7 As shown, the first via 141, the second via 142, and the third via 143 in a row of sub-pixel group 120 are set at equal intervals.

[0102] For example, in some examples, such as Figure 7 As shown, the fourth via 151, the fifth via 152, and the sixth via 153 in a row of sub-pixel group 120 are set at equal intervals.

[0103] For example, in some examples, the distances between the fourth via 151 and the first via 141, the distances between the fifth via 152 and the second via 142, and the distances between the sixth via 153 and the third via 143 are approximately equal. It should be noted that the distances between the fourth via 151 and the first via 141 mentioned above refer to the shortest distance between the fourth via 151 and the first via 141 within the same first sub-pixel. Similarly, the distances between the fifth via 152 and the second via 142 mentioned above refer to the shortest distance between the fifth via 152 and the second via 142 within the same second sub-pixel, and the distances between the sixth via 153 and the third via 143 mentioned above refer to the shortest distance between the sixth via 153 and the third via 143 within the same third sub-pixel. For example, in some examples, the distance between the first via 141 and the fourth via 151 is less than the distance between the first via 141 and the second via 142, the distance between the second via 142 and the fifth via 152 is less than the distance between the second via 142 and the third via 143, and the distance between the third via 143 and the sixth via 153 is less than the distance between the second via 142 and the third via 143.

[0104] For example, in some examples, such as Figure 7 As shown, the arrangement of the first sub-pixel 121, the second sub-pixel 122, and the third sub-pixel 123 in each sub-pixel group 120 can be found in [reference needed]. Figure 3 The pixel arrangement structure in the display substrate shown is such that the first sub-pixel 121, the second sub-pixel 122 and the third sub-pixel pair 126 are arranged along the row direction, and the two third sub-pixels 123 are arranged along the column direction.

[0105] For example, in some examples, such as Figure 7 As shown, the first via 141, the second via 142, and the third via 143 in a row of sub-pixel groups 120 are located between two adjacent rows of sub-pixel groups 120.

[0106] For example, in some examples, such as Figure 7 As shown, in each sub-pixel group 120, the first sub-pixel 121, the second sub-pixel 122, and the third sub-pixel pair including two third sub-pixels 123 are arranged along the row direction, and the two third sub-pixels 123 in the third sub-pixel pair are arranged along the column direction. In this pixel arrangement, the third via 143 and the sixth via 153, located on the same straight line, need to provide electrical connections to the anode and pixel driving circuit of the third sub-pixels in the two adjacent rows of pixel groups on that straight line. At this time, the fourth via 151, the first via 141, the sixth via 153, the third via 143, the fifth via 152, the second via 142, the sixth via 153, and the third via 143 are arranged cyclically in sequence.

[0107] For example, in some examples, where the first sub-pixel 121 is a blue sub-pixel, the second sub-pixel 122 is a red sub-pixel, and the third sub-pixel 123 is a green sub-pixel, the fourth via 151, the first via 141, the sixth via 153, the third via 143, the fifth via 152, the second via 142, the sixth via 153, and the third via 143 are sequentially arranged in a cycle. In this case, the fourth via 151 and the first via 141 provide electrical connection to the pixel driving circuit and anode of the blue sub-pixel in the first row; the fifth via 152 and the second via 142 provide electrical connection to the pixel driving circuit and anode of the red sub-pixel in the first row; the first group of sixth via 153 and third via 143 provides electrical connection to the pixel driving circuit and anode of the green sub-pixel in the second row; and the second group of sixth via 153 and third via 143 provides electrical connection to the pixel driving circuit and anode of the green sub-pixel in the first row.

[0108] For example, in some examples, such as Figure 7As shown, the distance between the fourth via 151 and the first via 141 is less than the distance between the first via 141 and the second via 142; the distance between the fifth via 152 and the second via 142 is less than the distance between the first via 141 and the second via 142; and the distance between the sixth via 153 and the third via 142 is less than the distance between the first via 141 and the second via 142. For example, in some examples, the first anode 1212 further includes a first connecting electrode block 12125, which is located on the side of the first anode 1212 away from the second sub-pixel 122 in the row direction. The first connecting electrode block 12125 is electrically connected to the first pixel driving electrode 1216 through a first via 141. The second anode 1222 further includes a second connecting electrode block 12225, which is electrically connected to the second pixel driving electrode 1226 through a second via 142. The third anode 1232 further includes a second connecting electrode block 12325, which is electrically connected to the third pixel driving electrode 1236 through a third via 143.

[0109] For example, in some examples, such as Figure 7 As shown, the first via 141 and the fourth via 151 are located on the side of the main body of the first anode 1212 (the part overlapping with the first effective light-emitting area) away from the main body of the adjacent second anode 1222 (the part overlapping with the second effective light-emitting area), and the fourth via 151 is located on the side of the first via 141 away from the main body of the adjacent first anode 1212.

[0110] For example, in some examples, such as Figure 7 As shown, the second via 142 is located directly below the main body of the second anode 1222, meaning that the orthographic projection of the second via 132 in the row direction overlaps with the orthographic projection of the main body of the second anode 1222 in the row direction. The fifth via 152 is located on the side of the second via 142 away from the adjacent third sub-pixel pair 126.

[0111] For example, in some examples, such as Figure 7 As shown, the two third vias 143 of the third sub-pixel pair 126 are located on two adjacent first straight lines, and these two third vias 143 are located on the upper and lower sides of the third sub-pixel pair 126, respectively. That is, the orthographic projections of the two third vias 143 in the row direction overlap with the orthographic projections of the third sub-pixel pair 126 in the row direction. The sixth via 153 is located on the side of the corresponding third via 143 away from the adjacent first sub-pixel 121.

[0112] An embodiment of this disclosure also provides a display device. The display device includes the aforementioned display substrate. Since the first via 141, the second via 142, and the third via 143 in a row of sub-pixel groups 120 are approximately located on the same straight line, that is, the first via 141, the second via 142, and the third via 143 are arranged in a row with a spacing of one sub-pixel distance, it is easier to control process deviations when the process margin changes. When the display device uses a display panel with the pixel arrangement structure given in the embodiments of this disclosure, the resolution of the display device can be further improved, thereby providing a display device with a truly high resolution. Furthermore, since the pixel arrangement structure given in the embodiments of this disclosure can have good symmetry, the uniformity of pixel distribution can be improved, thus improving the display effect of the display device. For example, in some examples, the display device can be any product or component with display function, such as a smartphone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0113] The following points need to be explained:

[0114] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0115] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0116] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: a substrate substrate; a plurality of sub-pixel groups arranged on the substrate substrate along a row direction and a column direction; and a first spacer, a second spacer and a third spacer, wherein each of the sub-pixel groups comprises a first sub-pixel, a second sub-pixel and a third sub-pixel pair, the third sub-pixel pair comprising two third sub-pixels, in a row of the sub-pixel groups, the first spacer is located between adjacent first sub-pixels and second sub-pixels, the second spacer is located between adjacent second sub-pixels and third sub-pixels, and the third spacer is located between adjacent third sub-pixels and first sub-pixels, the number of the first spacers, the number of the second spacers and the number of the third spacers are equal, the first sub-pixel comprises a first anode and a first pixel driving circuit, the second sub-pixel comprises a second anode and a second pixel driving circuit, and the third sub-pixel comprises a third anode and a third pixel driving circuit, the display substrate further comprises a first planarization layer located between the first anode and the first pixel driving circuit, between the second anode and the second pixel driving circuit, and between the third anode and the third pixel driving circuit, the first sub-pixel comprises a first via hole in the first planarization layer, the second sub-pixel comprises a second via hole in the first planarization layer, and the third sub-pixel comprises a third via hole in the first planarization layer, the first via hole is used for connection between the first anode and the first pixel driving circuit, the second via hole is used for connection between the second anode and the second pixel driving circuit, and the third via hole is used for connection between the third anode and the third pixel driving circuit, the two third sub-pixels of the third sub-pixel pair of each of the sub-pixel groups are connected to the third pixel driving circuit through two third via holes respectively, and the two third via holes are arranged along the column direction and located on both sides of the third sub-pixel pair, the third anodes of the third sub-pixel pairs of the sub-pixel groups in different rows are connected to different third pixel driving circuits through different third via holes, the first via holes, the second via holes and a part of the third via holes in a row of the sub-pixel groups are located on a first straight line, and the other part of the third via holes are located on a side of the row of the sub-pixel groups away from the first straight line. in a row of the sub-pixel groups, the first spacer, the second spacer and the third spacer are arranged in turn in a cycle, and the first straight line is located between adjacent two rows of the sub-pixel groups. 2.The display substrate of claim 1, wherein, each of the sub-pixel groups comprises at most one first spacer, one second spacer or one third spacer, and the first via hole and the second via hole of each of the sub-pixel groups are located on the same side of the sub-pixel group. 3.The display substrate of claim 1, wherein, ​ 4.The display substrate of any one of claims 1-3, wherein, In a row of the sub-pixel groups, the first spacers are located between adjacent first sub-pixels and second sub-pixels, the second spacers are located between adjacent second sub-pixels and third sub-pixel pairs, and the third spacers are located between adjacent third sub-pixel pairs and first sub-pixels. 5.The display substrate of claim 4, wherein, In each of the sub-pixel groups, the first sub-pixels, the second sub-pixels, and the third sub-pixel pairs are arranged along the row direction and form three sub-pixel columns, and two third sub-pixels in the third sub-pixel pair are arranged along the column direction, and two third vias of the two third sub-pixels in the third sub-pixel pair are located on two adjacent first straight lines, respectively. 6.The display substrate of claim 5, wherein, In a row of the sub-pixel groups, the first spacers and the second spacers are spaced apart by 1+3n sub-pixel columns, the second spacers and the third spacers are spaced apart by 1+3n sub-pixel columns, and the third spacers and the first spacers are spaced apart by 1+3n sub-pixel columns, where n is a positive integer greater than or equal to 1. 7.The display substrate of claim 4, wherein, Two adjacent rows of the sub-pixel groups are arranged with a 1 / 2 pitch offset, where the pitch is the distance between the centers of two first sub-pixels in two adjacent sub-pixel groups along the row direction. 8.The display substrate of any one of claims 1-3, wherein, The first sub-pixels are configured to emit light of a first color, the second sub-pixels are configured to emit light of a second color, and the third sub-pixels are configured to emit light of a third color, The display substrate further comprises: a second planar layer between the first planar layer and the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit; a first connection electrode, a second connection electrode, and a third connection electrode between the second planar layer and the first planar layer, wherein the first pixel driving circuit includes a first electrode, the second pixel driving circuit includes a second electrode, the third pixel driving circuit includes a third electrode, the first sub-pixels include fourth vias in the second planar layer, the second sub-pixels include fifth vias in the second planar layer, and the third sub-pixels include sixth vias in the second planar layer, the fourth vias are used for connection of the first electrode and the first connection electrode, the fifth vias are used for connection of the second electrode and the second connection electrode, and the sixth vias are used for connection of the third electrode and the third connection electrode, In a row of the sub-pixel groups, the fourth vias, the fifth vias, and part of the sixth vias are located on a second straight line. 9.The display substrate of claim 8, wherein, The first color is blue, the second color is red, and the third color is green, and in a row of the sub-pixel groups, the first straight line and the second straight line are substantially coincident. 10.The display substrate of claim 8, wherein, The first spacer is substantially long strip-shaped, the extending direction of the first spacer is substantially parallel to the column direction, the second spacer is substantially long strip-shaped, the extending direction of the second spacer is substantially parallel to the column direction, the third spacer is substantially long strip-shaped, the extending direction of the third spacer is substantially parallel to the column direction, the fourth via hole in the row of the sub-pixel group is located on the side of the first via hole away from the main body part of the adjacent first anode, the fifth via hole is located on the side of the second via hole away from the adjacent third sub-pixel pair, and the sixth via hole is located on the side of the corresponding third via hole away from the adjacent first sub-pixel. 11.The display substrate of claim 10, wherein, The size of the first spacer in the column direction is smaller than the size of the first sub-pixel in the column direction, the size of the second spacer and the third spacer in the column direction is smaller than the size of the third sub-pixel pair in the column direction, The center of the first spacer, the center of the second spacer, the center of the third spacer, the center of the first sub-pixel, the center of the second sub-pixel and the center of the third sub-pixel pair are located on a straight line substantially parallel to the row direction, The distance between the fourth via hole and the first via hole in the row of the sub-pixel group is smaller than the distance between the first via hole and the second via hole; the distance between the fifth via hole and the second via hole is smaller than the distance between the first via hole and the second via hole; The distance between the sixth via hole and the third via hole is smaller than the distance between the first via hole and the second via hole. 12.The display substrate according to any one of claims 1-3, wherein, The first spacer, the second spacer and the third spacer have the same size, the width of the first spacer along the row direction ranges from 6 to 15 microns, the length of the first spacer along the column direction ranges from 35 to 45 microns, and the height of the first spacer along the direction perpendicular to the substrate ranges from 1.5 to 2.5 microns. 13.The display substrate of any one of claims 1-3, wherein, The first sub-pixel includes a first anode and a first light-emitting functional layer, the second sub-pixel includes a second anode and a second light-emitting functional layer, and the third sub-pixel includes a third anode and a third light-emitting functional layer, and the display substrate further includes: A pixel defining layer located on the side of the first anode, the second anode and the third anode away from the substrate, and including a first opening, a second opening and a third opening, the first opening exposes the first anode, the second opening exposes the second anode, and the third opening exposes the third anode, At least a part of the first light-emitting functional layer is located in the first opening and covers the exposed part of the first anode, at least a part of the second light-emitting functional layer is located in the second opening and covers the exposed part of the second anode, at least a part of the third light-emitting functional layer is located in the third opening and covers the exposed part of the third anode, and the first spacer, the second spacer and the third spacer are located on the surface of the pixel defining layer away from the substrate. 14.The display substrate of claim 13, wherein, A normal projection of the first, second and third spacers on the substrate base plate does not overlap with a normal projection of the first, second and third openings on the substrate base plate. 15.The display substrate of claim 13, wherein, The first, second and third spacers are formed by a one-time mask process.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

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