Power-on reset circuit

Abstract

In the circuit (100), an input stage (110) includes a first transistor device (114) configured to generate a first output signal (116) in response to a first bias current (118) activating the first transistor device (114) by exceeding a first threshold voltage of the first transistor device (114). A compensation stage (130) includes a second transistor device (134) coupled to a third transistor device (138). The second transistor device (134) is activated in response to the first output signal (116) exceeding a second threshold voltage of the second transistor device (134). The third transistor device (138) is activated in response to the activation of the second transistor device (134) and the second bias current (140). The compensation stage (130) is configured to generate a second output signal (150) in response to the activation of the third transistor device (138). The output stage (160) is configured to generate a reset signal (164) in response to the second output signal (150) exceeding the third threshold voltage.

Description

Technical Field

[0001] This relates generally to circuits, and more particularly to power-on reset circuits. Background Art

[0002] In an integrated circuit, a power-on reset (POR) circuit generates a reset signal in response to detecting that power is applied to the integrated circuit. This helps the device start operating in a known desired voltage state before releasing the reset signal. In some examples, a simple resistor and capacitor (RC) filter can be applied to control the timing of the reset signal. Many power-on situations require higher precision and deterministic operation over the entire temperature range than an RC filter can provide. In some circuits, a low operating current may be required to operate the POR circuit. Therefore, scaling the resistor value to address the small current may require too much integrated circuit area and cause a long delay before the circuit activates the reset signal. Active switching components can be added to the POR circuit to increase the switching time, however, process and temperature variations between active components can cause circuit timing inaccuracies and other undesirable characteristics. Summary of the invention

[0003] In one example, a circuit includes an input stage including a first transistor device configured to generate a first output signal in response to a first bias current activating the first transistor device by exceeding a first threshold voltage of the first transistor device. A compensation stage includes a second transistor device coupled to a third transistor device. The second transistor device is activated in response to the first output signal exceeding a second threshold voltage of the second transistor device. The second transistor device is configured to set a second threshold voltage to compensate for process and temperature variations of the first transistor device. The third transistor device is activated in response to activation of the second transistor device and a second bias current. The compensation stage is configured to generate a second output signal in response to activation of the third transistor device. The output stage is configured to generate a reset signal voltage in response to the second output signal exceeding a third threshold voltage.

[0004] In another example, a circuit includes a first transistor device having a gate coupled to its drain, and a source coupled to a first voltage rail. A first current source is coupled between a second voltage rail and the drain of the first transistor device. A second transistor device includes a gate coupled to the drain of the first transistor device. The second transistor device has a drain coupled to the second voltage rail. A third transistor device has a gate coupled to its drain, and a source coupled to the source of the second transistor device. A second current source is coupled between the drain of the third transistor device and the first voltage rail. A fourth transistor device having a gate terminal is coupled to the gate terminal of the third transistor device. The fourth transistor device has a source terminal coupled to the second voltage rail and a drain terminal coupled to the third current source.

[0005] In another example, a method includes biasing a first transistor device by a first bias current to provide a first output voltage. The method includes activating a second transistor device in response to the first output voltage of the first transistor device. The method includes activating a third transistor device coupled to the second transistor device in response to the activation of the second transistor device and the second bias current to provide a third output signal. The method includes activating a fourth transistor device in response to the third output signal of the second transistor device and the third bias current to provide a reset signal voltage. At least one of the bias currents is adjusted to compensate for the reset signal voltage over a temperature range. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 An example block diagram of a circuit providing a power-on reset signal is shown.

[0007] Figure 2 An example circuit diagram showing a circuit that provides a power-on reset signal.

[0008] Figure 3 Show Figure 2 An example of a bias circuit.

[0009] Figure 4 An example circuit diagram showing a circuit that employs an elevated trip threshold level to provide a power-on reset signal.

[0010] Figure 5 An example of a method of generating a power-on reset signal is shown.

[0011] Figure 6 The power-on trip voltage threshold is shown with respect to temperature as process transistor parameters vary.

[0012] Figure 7 Shows the circuit delay time from the time the power rail reaches the voltage threshold to the time the power-on reset signal is asserted. DETAILED DESCRIPTION

[0013] In this specification, a power-on reset circuit monitors the operating voltage of a downstream circuit (e.g., a microprocessor circuit) in a monitoring mode, and releases a reset signal when the operating voltage is within a desired operating range. Various circuit stages are provided to achieve fast and reliable power-on switching speeds for a reset circuit using low operating currents in the nanoampere range, while also providing consistent switching performance over process and / or temperature variations. The circuit includes an input stage, the input stage including a first transistor device, the first transistor device being configured to generate an output signal in response to a bias current activating the first transistor device by exceeding a threshold voltage of the first transistor device. A current source providing a bias current to the first transistor device can be coupled to a high voltage rail. For example, the first transistor device can be an n-channel device such as having a positive threshold voltage. The compensation stage includes a second transistor device coupled to a third transistor device.

[0014] The second transistor device is activated in response to the output signal from the input stage minus the threshold voltage of the second transistor device. The second transistor device is configured so that it compensates for process variations of the first transistor device. In the example, if the first transistor device has a positive threshold value Vth1, and a related device with a threshold voltage Vth2 for the second transistor is used, it will compensate for process variations of the first transistor device. Such transistors can be manufactured in conjunction with each other on a silicon substrate (e.g., in an IC), and therefore, if the threshold of one transistor increases in one direction, the threshold of the other compensating transistor will also increase in the same direction, thereby providing process compensation for the first transistor device.

[0015] For the purposes of the circuits described herein, in order to facilitate the absence of false trips, the second transistor device in the compensation stage provides a negative threshold voltage (or a threshold voltage close to zero). The third transistor device in the compensation stage can be activated in response to the activation of the second transistor device and the second bias current. The compensation stage can be configured to generate a second output signal. The output stage can be configured to generate a reset signal in response to the power supply voltage exceeding the second output signal third threshold voltage. Process parameters such as bias current adjustment and / or transistor parameters including width and length parameters can be provided to allow the switching performance of the reset circuit to be adjusted within an operating temperature range.

[0016] As used herein, the term "circuit" may include a collection of active and / or passive elements that perform a circuit function, such as an analog circuit. Additionally or alternatively, for example, the term "circuit" may include an integrated circuit (IC) in which all or some circuit elements are fabricated on a common substrate (e.g., a semiconductor substrate such as a die or chip).

[0017] Figure 1An example of a circuit 100 providing a power-on reset signal voltage is shown. The circuit 100 includes an input stage 110 including a first transistor device 114 configured to generate a first output signal 116 by activating the first transistor device in response to a first bias current 118 from a first current source 120 by exceeding a first threshold voltage of the first transistor device. The compensation stage 130 includes a second transistor device 134 coupled to a third transistor device 138. The second transistor device 134 is activated in response to the first output signal 116 exceeding a second threshold voltage of the second transistor device. The second transistor device 134 is configured to compensate for process and temperature variations of the first transistor device. For example, if the threshold voltage of the first transistor device 114 increases during a given process manufacturing, the second transistor device 134 is configured to increase accordingly during a given process manufacturing, and vice versa. In response to the activation of the second transistor device 134 and the second bias current 140 set by the second current source 144, the third transistor device 138 is activated.

[0018] The compensation stage 130 is configured to generate a second output signal 150 in response to activation of the third transistor device 138. The output stage 160 is configured to generate a reset signal voltage 164 in response to the second output signal 150 exceeding a third threshold voltage (e.g., a voltage of another transistor device not shown). As shown, a voltage rail 170 (also referred to as a second voltage rail) (e.g., VDD) can provide power to the corresponding stages 110, 130, and 160, and a voltage rail 180 (also referred to as a first voltage rail) (e.g., VSS) can provide a return path (e.g., electrical ground) for each of the corresponding stages.

[0019] For example, the reset signal voltage 164 varies according to the threshold voltage of each transistor device in the circuit 100. The reset signal voltage 164 also varies according to the temperature in the circuit 100. Figure 2 Various equations are provided that illustrate the voltage threshold and temperature relationship of the reset signal voltage 164. At least one of the w and l parameters of one or more transistor devices can be configured to adjust the trip point of the circuit. In another example, at least one of the bias currents described herein can be adjusted according to a temperature coefficient correction term to achieve a corresponding temperature correction of the circuit 100. A Schmitt trigger (e.g., see Figure 2 ) to buffer the reset signal voltage 164.

[0020] Each of the bias currents described herein may be generated by a separate current source configured to generate each bias current. As an example, each such current source may include: an input connected to the drain of the corresponding transistor device; a resistor connected at one end of the source of the corresponding transistor device; and the other end of the resistor connected to the base of the corresponding transistor device (see, for example, Figure 3 In another example, the input stage 110 may include at least one other transistor device coupled in series with the first transistor device 114 to increase the threshold voltage level of the input stage (eg, see Figure 4 ). Thus, the compensation stage 130 may include at least one other compensation transistor device cascaded to the second transistor device to provide process compensation for at least one other transistor device in the input stage 110 (eg, see Figure 4 ).

[0021] Because transistor devices (see, for example, Figure 4 ) generates a bias current source, so the circuit 100 is self-powered only from the second voltage rail 170, and therefore no startup circuit is required. Here, based on a voltage comparison between the source voltage and the gate voltage of the final output transistor device in the output stage 160 (for example, see Figure 2 M4) to generate the reset signal voltage 164. The low quiescent current (I q ) has little effect on delay, and therefore, due to the coupled nature of the transistor devices between stages and the absence of intervening resistive paths, circuit 100 is very fast. The current is limited by the negative threshold of the transistor devices in the corresponding current source, and because this threshold is small, the value of the resistor used in the corresponding current source is small, thereby saving silicon circuit area.

[0022] Figure 2 The power-on reset signal voltage (V POR ) of the circuit 200. Figure 1 Similar to the circuit 100 shown and described, the circuit 200 includes an input stage 204, a compensation stage 206, and an output stage 208. In this example, the circuit 200 includes a first transistor device M1 having a gate coupled to its drain (e.g., a diode-connected transistor), and a source of M1 coupled to another voltage rail, shown as V in this example. SS The first current source I BIAS1 Coupled to the voltage rail (shown as V in this example) DD ) and the drain of the first transistor device M1.

[0023] In compensation stage 206, second transistor device M2 includes a gate coupled to the drain of first transistor device M1. Second transistor device M2 has a drain coupled to voltage rail VDD. Third transistor device M3 has a gate coupled to its drain (e.g., a diode-connected transistor) and a source of M3 coupled to the source of second transistor device M2. Second current source I BIAS2 The drain of the third transistor device M3 is coupled to the voltage rail V SS between.

[0024] The output stage 208 includes a fourth transistor device M4 having a gate terminal coupled to the gate terminal of the third transistor device M3. The fourth transistor device M4 also has a gate terminal coupled to the high voltage rail V SS and coupled to a third current source I BIAS3 The drain terminal of M4 provides a reset signal voltage 210, which is used to provide a power-on reset signal (V POR ), such as described herein. Figure 2 In the example of FIG. 1 , the reset signal voltage may be buffered by Schmitt trigger 220 and further adjusted by buffer 230 to generate V for downstream circuitry (not shown). POR .

[0025] As previously described, the drain terminal of the fourth transistor device M4 provides a reset signal voltage 210 for the circuit 200, which varies according to the threshold voltage of each device. The reset signal voltage 210 is based on a comparison between the source voltage and the gate voltage of M4. Figure 2 As an example, the reset signal voltage 210 can be expressed as shown in Equation 1. As an example, the reset signal (V POR ) can be expressed as follows:

[0026]

[0027] in

[0028] Vth1st is the threshold voltage of the first transistor device M1,

[0029] Vth2nd is the threshold voltage of the second transistor device M2,

[0030] Vth3rd is the threshold voltage of the third transistor device M3,

[0031] Vth4th is the threshold voltage of the fourth transistor device M4,

[0032] η is the subthreshold slope factor (e.g., between about 1 and about 1.5),

[0033] Vt is a constant that includes the Boltzmann constant, absolute temperature, and charge (q), and

[0034] ln represents the natural logarithm,

[0035] Ibias1 is the first bias current,

[0036] Ibias2 is the second bias current,

[0037] Ibias3 is the third bias current,

[0038] Beff1st is a transistor gain term affected by the width (w) and length (l) parameters of the first transistor device,

[0039] Beff2nd is a transistor gain term affected by the w and l parameters of the second transistor device,

[0040] Beff3rd is a transistor gain term affected by the w and l parameters of the third transistor device, and

[0041] Beff4th is the transistor gain term affected by the w and l parameters of the fourth transistor device. Also referred to as the temperature coefficient correction term (Tempco) described herein.

[0042] Because the threshold terms in Equation 1 appear in a differential state (for the related PMOS and NMOS devices described herein), process and temperature variations in the transistor devices are mitigated when setting the VPOR signal because the related devices (e.g., related by using similar manufacturing processes) track each other over the entire temperature range, such as shown in Equation 1. In one example, the second transistor device 134 can be a negative threshold transistor device or a depletion mode transistor device. In addition, by adjusting the temperature coefficient correction term (TempCo) (e.g., a term in Equation 1 that is independent of the threshold voltage), the reset signal voltage 164 can be made a desired function of temperature.

[0043] The first transistor device M1 may be an n-channel device having a positive threshold voltage, and the second transistor device M2 may be an n-channel device having a negative threshold voltage and configured to compensate for process variations in the threshold of the first transistor device. For example, the third transistor device and the fourth transistor device may be p-channel devices. M2 is also configured with its negative threshold to mitigate false tripping of the circuit 200. In some examples, at least one of the w and l parameters of at least one of the transistor devices MP1, MP2, MP3, and MP4 may be configured to adjust the corresponding Beff term (e.g., set in the design and layout of the IC chip implementing the device) and / or the voltage threshold of the corresponding device.

[0044] Additionally or alternatively, the bias current I BIAS1 ,I BIAS2 and I BIAS3 1 and / or I 2 (e.g., by configuring the corresponding current source) to adjust the operating behavior with respect to temperature. For example, by adjusting one or more Beff parameters of Equation 1 and / or I BIAS Parameters can mitigate temperature variations (e.g., net TempCo can be approximately zero). Thus, positive TempCo can be configured, negative TempCo can be configured, or flat TempCo can be configured based on adjustments to the Beff of each transistor device and / or the current source supplying the corresponding device. When VDD reaches a threshold, I BIAS1 Current is provided to turn on M1. When the drain terminal of M1 reaches the threshold, M2 turns on, which then turns on M3, which acts as a diode. This in turn engages M4, which when turned on pulls its output to VDD at 210. When 210 is pulled high, it is inverted by Schmitt trigger 220 and again inverted by buffer 230 to generate VPOR.

[0045] Figure 3 Show Figure 2 In this example, an example bias source IBIAS is shown implemented as a combination of a transistor device 300 and a resistor 310, however, other current source implementations are possible. For example, an IBIAS source including a transistor device 300 and a resistor 310 may be used to drive transistor M1, such as Figure 2 As shown in . The transistor device 300 is used as a current source, which includes an input connected to the drain of the corresponding transistor device. The resistor 310 is connected at one end of the source of the corresponding transistor device 300, and the other end of the resistor is connected to the base of the corresponding transistor device. By implementing the bias circuit in this way, the transistor device 300 provides a desired bias current due to its corresponding threshold voltage, so a relatively small resistor value can be used at 310 to reduce the circuit area.

[0046] Figure 4 An example circuit 400 is shown that uses an elevated trip threshold level to provide a corresponding power-on reset signal voltage. Similar to the examples previously described herein, the circuit 400 includes an input stage 404, a compensation stage 406, and an output stage 408. The input stage 404 includes a series connection to provide a corresponding bias current I BIAS14. The transistor devices M1 and M2 provide a combined threshold voltage that raises the overall reset trip threshold level of the circuit 400. The compensation stage 406 includes transistor devices M3 and M4 that provide false trip and process compensation for the threshold voltages of M1 and M2, respectively (e.g., fabricated in a similar silicon process and having thresholds that track but are opposite to those of M1 and M2). Transistor device M3 is connected to a transistor device configured to provide a corresponding bias current I BIAS2 The current source, and the transistor device M4 is connected to M5, which is in turn connected to a current source configured to provide a corresponding bias current I BIAS3 The gate and drain of M5 are connected to the gate of M6 in the output stage 408, where M6 is connected to a current source configured to provide a corresponding bias current I BIAS4 The drain of M6 drives the reset signal voltage 410, which can be buffered by the Schmitt trigger 420 and further buffered by the inverter 430 to generate the power-on reset signal V POR .

[0047] Thus, in this example, the input stage 404 includes one or more other transistor devices (e.g., M2) coupled in series with a first transistor device (e.g., M1) to increase the threshold voltage level of the input stage. The compensation stage 406 includes one or more other compensation transistor devices (e.g., M3) cascaded to a second transistor device (e.g., M4) to provide false tripping and process compensation for at least one other transistor device (e.g., M2) in the input stage 404. Thus, by implementing M1 and M2 as diode-connected transistor devices and including subsequent source followers M3 and M4 in the compensation stage, trip point adjustment can be provided for the circuit 400 while also eliminating process variations. For example, trip point adjustment can be performed by using multiple diode-connected NMOS transistor devices (such as M1 or a combination of normal and negative voltage threshold NMOS devices) in the first stage and adding subsequent negative voltage threshold-based source followers before and / or within the compensation stage 406 to eliminate variations within temperature, because one threshold will increase within a given temperature range, while the other threshold will decrease within a given temperature range. Instead of using a negative threshold PMOS such as M5, a source follower stage with a PMOS device (nominally with zero voltage or positive voltage threshold) can also be incorporated. Figure 2 When VDD reaches the threshold, I BIAS1Current is provided to turn on M1 and M2. When the drain terminal of M2 reaches the threshold, M3 turns on, and when the drain of M3 exceeds the threshold of M4, M4 turns on. M4 turns on, which then turns on M5, which acts as a diode. This in turn engages M6, which when turned on pulls its output to VDD at 410. When 410 is pulled high, it is inverted by Schmitt trigger 420 and again inverted by buffer 430 to generate VPOR.

[0048] In view of the above-mentioned structural and functional characteristics, reference Figure 5 The example method will be better understood. Although the method is shown and described as being performed serially for simplicity of illustration, it should be understood and appreciated that the method is not limited by the order shown, as parts of the method can occur in a different order and / or be obtained simultaneously from what is shown and described herein. For example, such a method can be performed by various hardware circuits, such as those disclosed herein.

[0049] Figure 5 An example of a method 500 for generating a power-on reset signal voltage is shown. At 510, the method 500 includes biasing a first transistor device by a first bias current to provide a first output voltage. At 520, the method 500 includes activating a second transistor device in response to the first output voltage of the first transistor device. At 530, the method 500 includes activating a third transistor device coupled to the second transistor device in response to the activation of the second transistor device and the second bias current to provide a third output signal. At 540, the method 500 includes activating a fourth transistor device in response to the third output signal of the second transistor device and the third bias current to provide a reset signal voltage. At least one of the bias currents is adjusted to compensate the reset signal voltage over a temperature range.

[0050] The reset signal voltage may vary according to the threshold voltage of each device, so that the reset signal voltage varies according to the above relative Figure 2 The equation 1 is adjusted. Figure 2 Describes how the threshold voltages between transistor devices are combined to generate a reset signal voltage. Figure 2 Equation 1 is described, for the respective transistor devices and / or for the associated current sources of the driver devices, with respect to the temperature adjustment with respect to the Beff term.

[0051] Figure 6600, which shows the power-on trip voltage threshold relative to temperature as the process transistor parameters vary. The Y axis of Figure 600 represents the POR trip voltage in volts, while the X axis represents temperature. Each line in lines 610, 620, 630, 640 and 650 represents a corresponding process corner. As used herein, the term "process corner" is an example of experimental design (DoE), which refers to the variation of manufacturing parameters used in applying integrated circuit design to semiconductor wafers. The process corner represents the limit of these parameter variations, within which the circuits that have been etched onto the wafer should operate correctly. At 630, the process corner indicates the model threshold path through the circuit described herein, where the process parameters for the corresponding transistor device are set for the nominal case. At 650, in a strong corner example, the threshold voltage of the NMOS device will be low, the mobility will be high, etc., which means a higher drive strength. At 610, a weak corner example is shown, where the threshold voltage of the NMOS device will be high, the mobility will be low, etc., which means a lower drive strength. At 620 and 640, the angled corners show that one of the PMOS or NMOS is stronger while the other is weaker.

[0052] Advantageously, Figure 2 and Figure 4 The circuit shown in can be operated with a desired power-on trip voltage threshold over transistor parameter variations, such as Figure 6 This is because the compensation stage described herein has an opposite threshold to the input stage, which mitigates false trips over the temperature range. In addition, by manufacturing the input stage transistor devices and the compensation stage transistor devices on the same area and processing them under the manufacturing conditions of the die, it is also possible to provide the same as above over the desired temperature range. Figure 6 Such voltage threshold performance is shown in .

[0053] Figure 7700 is a diagram showing the circuit delay time between the time when the power rail reaches the voltage threshold and the time when the power-on reset signal is asserted. The Y-axis of the diagram 700 represents the POR trip voltage delay in microseconds, and the X-axis represents the temperature. Each of the lines 710, 720, 730, 740, and 750 indicates a corresponding process corner. The time indicated on the Y-axis represents the delay from the time when VDD crosses the PoR trip point to the time when the POR voltage reaches the threshold. At 730, the process corner indicates the model threshold timing path through the circuit described herein, where the process parameters of the corresponding transistor device are set for the nominal case. At 750, in a strong corner example, the threshold voltage of the NMOS device will be low, the mobility will be high, etc., which means a higher drive strength, which affects the circuit timing shown. At 710, a weak corner example is shown, where the threshold voltage of the NMOS device will be high, the mobility will be low, etc., which means a lower drive strength, which affects the circuit timing shown. At 720 and 740, the skewed corners show that one of the PMOS or NMOS is stronger while the other is weaker.

[0054] Similar to the above Figure 6 The advantages described, Figure 2 and Figure 4 The circuit shown in Figure 6 The transistor parameter variations shown in FIG. 1 are operated with the desired delay time. This is due to the compensation transistor configuration designed herein, where low resistance values ​​can be used in the corresponding circuit. Low resistance values ​​can be used due to the process compensation between the input stage and the compensation stage described herein, and due to the use of alternating positive and negative thresholds in the input stage and the compensation stage to mitigate false transitions described herein.

[0055] Modifications may be made in the described embodiments and other embodiments are possible within the scope of the claims.

Claims

1. A circuit comprising: an input stage comprising a first transistor device configured to generate a first output signal in response to a first bias current activating the first transistor device by exceeding a first threshold voltage of the first transistor device; a compensation stage comprising a second transistor device coupled to a third transistor device, the second transistor device being activated in response to the first output signal exceeding a second threshold voltage of the second transistor device, the second transistor device being configured to set the second threshold voltage to compensate for process and temperature variations of the first transistor device, the third transistor device being activated in response to activation of the second transistor device and a second bias current, the compensation stage being configured to generate a second output signal in response to the activation of the third transistor device; as well as An output stage is configured to generate a reset signal voltage in response to the second output signal exceeding a third threshold voltage.

2. The circuit according to claim 1, wherein The output stage further includes a fourth transistor device configured to generate the reset signal voltage in response to the second output signal and a third bias current.

3. The circuit according to claim 2, wherein: The reset signal voltage is based on a sum of a threshold voltage of each of the first transistor device, the second transistor device, the third transistor device, and the fourth transistor device.

4. The circuit according to claim 3, wherein: The second transistor device is a negative threshold transistor device or a depletion mode transistor device.

5. The circuit according to claim 3, wherein: The reset signal voltage further varies according to a temperature coefficient correction term that varies according to each of the bias currents and a gain of each of the transistor devices.

6. The circuit according to claim 5, wherein: The first transistor device is an n-channel device having a positive threshold voltage, and the second transistor device is an n-channel device related to the first transistor device to compensate for process variations in the threshold voltage of the first transistor device.

7. The circuit according to claim 5, wherein: The third transistor device and the fourth transistor device are p-channel devices.

8. The circuit according to claim 5, wherein: At least one of a width parameter or a length parameter of at least one of the transistor devices is configured to adjust a trip point of the circuit.

9. The circuit according to claim 5, wherein: At least one of the bias currents is adjusted to achieve a corresponding temperature correction of the circuit according to the temperature coefficient correction term.

10. The circuit of claim 1, further comprising a Schmitt trigger to buffer the reset signal voltage.

11. The circuit according to claim 1, wherein: Each of the bias currents is generated by a separate current source, each separate current source includes an input connected to the drain of the corresponding transistor device, a resistor is connected to one end of the source of the corresponding transistor device, and the other end of the resistor is connected to the gate of the corresponding transistor device.

12. The circuit of claim 1, wherein: The input stage further includes at least one other transistor device coupled in series with the first transistor device to increase a threshold voltage level of the input stage, and the compensation stage includes at least one other compensation transistor device cascaded to the second transistor device to provide process compensation for the at least one other transistor device in the input stage.

13. A circuit comprising: a first transistor device having a gate coupled to its drain, and a source coupled to a first voltage rail; a first current source coupled between a second voltage rail and the drain of the first transistor device; a second transistor device including a gate coupled to the drain of the first transistor device, the second transistor device having a drain coupled to the second voltage rail; a third transistor device having a gate coupled to its drain and a source coupled to the source of the second transistor device; a second current source coupled between the drain of the third transistor device and the first voltage rail; as well as A fourth transistor device has a gate terminal coupled to the gate terminal of the third transistor device, the fourth transistor device having a source terminal coupled to the second voltage rail, and a drain terminal coupled to a third current source.

14. The circuit of claim 13, wherein: The drain terminal of the fourth transistor device provides a reset signal voltage for the circuit, the reset signal voltage being based on a sum of a threshold voltage of each of the first transistor device, the second transistor device, the third transistor device, and the fourth transistor device.

15. The circuit of claim 14, wherein: The reset signal voltage further varies according to a temperature coefficient correction term that varies according to a bias current of each of the transistor devices and a gain of each of the transistor devices.

16. The circuit of claim 15, wherein: At least one of a width parameter or a length parameter of at least one of the transistor devices is adjusted to adjust the temperature coefficient correction term, or at least one of the bias currents is adjusted to adjust the temperature coefficient correction term.

17. The circuit of claim 15, wherein: Each of the current sources includes an input connected to a drain of a corresponding transistor device, a resistor connected at one end to a source of the corresponding transistor device, and another end of the resistor connected to a base of the corresponding transistor device.

18. A method comprising: biasing the first transistor device with a first bias current to provide a first output voltage; activating a second transistor device in response to the first output voltage of the first transistor device; activating a third transistor device coupled to the second transistor device to provide a third output signal in response to the activation of the second transistor device and a second bias current; as well as activating a fourth transistor device to provide a reset signal voltage in response to the third output signal of the second transistor device and a third bias current, wherein at least one of the bias currents is adjusted to compensate for the reset signal voltage over a temperature range, Wherein, the reset signal voltage is based on the sum of the threshold voltages of each of the first transistor device, the second transistor device, the third transistor device and the fourth transistor device and a temperature coefficient correction term, and the temperature coefficient correction term varies according to each bias current in the bias current and the gain of each transistor device in the transistor devices.

19. The method of claim 18, further comprising adjusting at least one of a width parameter or a length parameter of at least one of the transistor devices to adjust the temperature coefficient correction term, or adjusting at least one of the bias currents to adjust the temperature coefficient correction term.

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