reset circuit

Abstract

This application relates to a reset circuit, which includes a clock module, a processor, and a reset control module. The reset control module is configured to: send a power-on reset signal to the processor during the power-on startup process of the system to which the reset circuit belongs; the power-on reset signal includes a low level of a first preset duration and a high level of a second preset duration; and clear a power-on reset flag to zero during the low-level period of the power-on reset signal; the processor is configured to: execute a power-on reset after receiving the power-on reset signal; and set the power-on reset flag to 1 after the power-on reset is completed; the reset control module is further configured to: detect the power-on reset flag during the high-level period of the power-on reset signal; and determine that the processor power-on reset is complete when the power-on reset flag is detected to be 1. Embodiments of this application can improve the reliability of the reset circuit.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a reset circuit. Background Technology

[0002] A reset circuit is a circuit used to control and ensure the correct startup of digital circuits. It initializes all relevant circuits to a known state when the system is powered on and forces the system to restart if necessary. The normal operation of a processor is inseparable from a reset circuit.

[0003] In related technologies, a reset IC (Integrated Circuit Chip) chip or an RC (Resistor-Capacitor) charging and discharging circuit is used to reset the processor upon power-on. However, the above-mentioned reset circuits are not very flexible and have poor reliability. In complex circuit environments, there is a risk that reset failure may lead to the processor malfunctioning. Therefore, there is an urgent need for a highly reliable reset circuit. Summary of the Invention

[0004] In view of this, a reset circuit is proposed.

[0005] In a first aspect, embodiments of this application provide a reset circuit, the reset circuit including a clock module, a processor, and a reset control module; the clock module is connected to the processor and the reset control module, and the processor is connected to the reset control module; the reset control module is implemented using a programmable logic device; the clock module is used to: provide a first clock signal to the processor and the reset control module; the reset control module is used to: during the power-on startup process of the system to which the reset circuit belongs, send a power-on reset signal to the processor according to the first clock signal, the power-on reset signal including a low level of a first preset duration and a high level of a second preset duration; during the period when the power-on reset signal is at a low level, clear the power-on reset flag to zero; the processor is used to: perform a power-on reset after receiving the power-on reset signal; after the power-on reset is completed, set the power-on reset flag to 1; the reset control module is also used to: detect the power-on reset flag during the period when the power-on reset signal is at a high level; when the power-on reset flag is detected to be 1, determine that the processor power-on reset is complete.

[0006] In some possible implementations, the reset control module further includes a reset state machine, which is in an idle state during the period when the power-on reset signal is low; after the power-on reset signal becomes high, the reset state machine jumps to the power-on reset handshake state.

[0007] In some possible implementations, the reset control module is configured to: send first information to the reset state machine when the power-on reset flag is detected to be 1, the first information being used to indicate that the power-on reset flag is 1; the reset state machine is configured to: jump to the watchdog wait state upon receiving the first information.

[0008] In some possible implementations, the reset control module is configured to: resend the power-on reset signal to the processor if it is detected that the power-on reset flag is always 0 during the period when the power-on reset signal is high.

[0009] In some possible implementations, the reset state machine is used to: in the watchdog wait state, wait for a third preset time according to the first clock signal, and then jump to the watchdog detection state.

[0010] In some possible implementations, the processor is configured to: continuously send a periodic square wave signal to the reset control module according to the first clock signal during the execution of the application; the reset control module is configured to: detect the signal value of the square wave signal and calculate the holding duration of the signal value when the reset state machine is in watchdog detection state; send second information to the reset state machine when the holding duration of the signal value is greater than or equal to a preset duration threshold, so that the reset state machine jumps to the watchdog reset state; and send a watchdog reset signal to the processor when the reset state machine is in the watchdog reset state, so that the processor performs a watchdog reset.

[0011] In some possible implementations, the reset control module is used to: clear the hold duration to zero when the signal value of the square wave signal changes.

[0012] In some possible implementations, the reset state machine is used to: jump to the watchdog wait state after the watchdog reset signal has ended.

[0013] In some possible implementations, the reset control module further includes a first register and a second register, wherein the first register is used to store the power-on reset flag and the second register is used to store the square wave signal.

[0014] In some possible implementations, the clock module includes a crystal oscillator and a clock buffer, the crystal oscillator being connected to the clock buffer, and the clock buffer being connected to the processor and the reset control module; the crystal oscillator is used to generate a second clock signal; the clock buffer is used to receive the second clock signal and fan out the first clock signal according to the second clock signal.

[0015] The reset circuit of this embodiment includes a clock module, a processor, and a reset control module implemented using a programmable logic device (PLD), used to reset the processor. During the system power-on startup process of the reset circuit, the reset control module sends a power-on reset signal to the processor (including a low level for a first preset duration and a high level for a second preset duration) and clears the power-on reset flag to zero during the low-level period of the power-on reset signal. After receiving the power-on reset signal, the processor performs a power-on reset and sets the power-on reset flag to 1 after the power-on reset is completed. Simultaneously, the reset control module detects the power-on reset flag during the high-level period of the power-on reset signal, and determines that the processor power-on reset is complete when the power-on reset flag is detected to be 1. In this embodiment, the reset circuit sends a power-on reset signal to the processor during power-on reset, and performs a handshake confirmation of the processor's power-on reset by the processor setting the power-on reset flag to 1 and the reset control module detecting the power-on reset flag. Moreover, the reset control module is implemented using a PLD, which is flexible in configuration and easy to use, thereby improving the reliability of the reset circuit and the robustness of the system.

[0016] These and other aspects of this application will become more apparent in the description of the following embodiments(s). Attached Figure Description

[0017] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0018] Figure 1 A schematic diagram of a reset circuit according to an embodiment of this application is shown;

[0019] Figure 2 A schematic diagram of a reset circuit according to an embodiment of this application is shown;

[0020] Figure 3 A schematic diagram of the state transition of a reset state machine according to an embodiment of this application is shown. Detailed Implementation

[0021] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0022] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0023] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0024] To address the aforementioned technical problems, this application provides a reset circuit. The reset circuit of this application includes a clock module, a processor, and a reset control module. The clock module is connected to the processor and the reset control module, and the processor is connected to the reset control module. The reset control module is implemented using a programmable logic device. The clock module is used to provide a first clock signal to the processor and the reset control module. The reset control module is used to send a power-on reset signal to the processor according to the first clock signal during the power-on startup process of the system to which the reset circuit belongs. The power-on reset signal includes a low level for a first preset duration and a high level for a second preset duration. During the period when the power-on reset signal is low, the power-on reset flag is cleared to zero. The processor is used to perform a power-on reset after receiving the power-on reset signal. After the power-on reset is completed, the power-on reset flag is set to 1. The reset control module is also used to detect the power-on reset flag during the period when the power-on reset signal is high. When the power-on reset flag is detected to be 1, the processor's power-on reset is determined to be complete.

[0025] The reset circuit of this application embodiment includes a clock module, a processor, and a reset control module implemented by a programmable logic device, used to perform reset processing on the processor. During the power-on startup process of the system to which the reset circuit belongs, the reset control module sends a power-on reset signal to the processor (including a low level for a first preset duration and a high level for a second preset duration) and clears the power-on reset flag to zero during the period when the power-on reset signal is low. After receiving the power-on reset signal, the processor performs a power-on reset and sets the power-on reset flag to 1 after the power-on reset is completed. At the same time, the reset control module detects the power-on reset flag during the period when the power-on reset signal is high, and determines that the processor power-on reset is complete when the power-on reset flag is detected to be 1.

[0026] In the reset circuit of this application embodiment, when the processor is powered on and reset, the reset control module sends a power-on reset signal to the processor, and the processor sets the power-on reset flag to 1 and the reset control module detects the power-on reset flag to confirm the power-on reset of the processor. Moreover, the reset control module is implemented by a programmable logic device, which is flexible in configuration and easy to use, thereby improving the reliability of the reset circuit and the robustness of the system.

[0027] Figure 1 A schematic diagram of a reset circuit according to an embodiment of this application is shown. Figure 1 As shown, the reset circuit 10 includes a clock module 110, a processor 120, and a reset control module 130. The clock module 110 is connected to the processor 120 and the reset control module 130, and the processor 120 is connected to the reset control module 130. The reset circuit 10 is used to reset the processor 120.

[0028] The clock module 110 serves as the clock source for the reset circuit 10, providing the processor 120 and reset control module 130 with the first clock signal required for their operation. The processor 120 and reset control module 130 can perform timing, counting, and other processing based on the first clock signal.

[0029] The processor 120 is used to run applications. The processor 120 can be a central processing unit (CPU), a digital signal processor (DSP), a system on chip (SoC), etc. This application does not limit the specific type of the processor 120.

[0030] The reset control module 130 can be used to perform reset processing on the processor 120, including power-on reset, power-on startup exception reset (i.e., continuing power-on reset after the processor fails the first power-on reset during startup), and watchdog reset (reset during processor operation). The reset control module 130 is implemented using a programmable logic device. For example, the reset control module 130 can be implemented using a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), etc. This application does not limit the specific type of programmable logic device.

[0031] Figure 2 A schematic diagram of a reset circuit according to an embodiment of this application is shown. Figure 2 As shown, the reset circuit 10 includes a clock module 110, a processor 120, and a reset control module 130. The reset circuit 10 is used to reset the processor 120.

[0032] The clock module 110 includes a crystal oscillator and a clock buffer. The crystal oscillator is connected to the clock buffer, which is in turn connected to the processor 120 and the reset control module 130. The crystal oscillator serves as a clock source, generating a second clock signal and sending it to the clock buffer. The clock buffer receives the second clock signal from the crystal oscillator and, based on this signal, fans out a first clock signal required for the operation of the processor 120 and the reset control module 130, thereby matching the clock signal to the operational requirements of the processor and the reset control module.

[0033] The reset control module 130 includes a first register, a second register, and a reset state machine. The first register stores a power-on reset flag; therefore, it can also be called the power-on reset flag register. The second register stores a periodic square wave signal sent by the processor to the reset control module during application execution. This periodic square wave signal can also be called a watchdog signal; therefore, the second register can also be called the watchdog signal register.

[0034] A reset state machine is used to set the various states required for the operation of the reset circuit and to complete state transitions when specific conditions are met. The reset state machine includes five states: idle (also called the initial state), power-on reset handshake state (por-hd), watchdog wait state (wdg-wait), watchdog detection state (wdg-chk), and watchdog reset state (wdg-rst). The reset state machine can be implemented using Very-High-Speed ​​Integrated Circuit Hardware Description Language (VHDL), hardware description languages ​​(such as Verilog Hardware Description Language, Verilog HDL), or through graphical input. Those skilled in the art can determine the specific implementation method of the reset state machine according to actual needs; this application does not impose any limitations on this.

[0035] The following is an exemplary description of the processor power-on reset process.

[0036] During the system power-on startup process of the reset circuit, after the reset control module has finished loading, it counts or times according to the first clock signal and sends a power-on reset signal to the processor. This power-on reset signal includes a low level (value 0) for a first preset duration (e.g., 20ms) and a high level (value 1) for a second preset duration (e.g., 80ms). The power-on reset signal is sent to the processor's reset pin. Upon receiving the power-on reset signal, the processor immediately performs a power-on reset. After the power-on reset is completed, the processor sets the power-on reset flag to 1. Simultaneously, the processor enters the application program, i.e., the processor begins executing the application program. If the power-on reset flag is stored in the first register, the processor can write 1 to the first register via the local bus, thus setting the power-on reset flag in the first register to 1.

[0037] In the above example, the power-on reset signal is active low (value 0). That is, during the first preset duration of the low level, the processor performs a power-on reset, and during the second preset duration of the high level, the processor and the reset control module perform a power-on reset handshake. In some embodiments, the power-on reset signal may also be active high (value 1), in which case the power-on reset signal may include a first preset duration of high level and a second preset duration of low level. This application embodiment uses an example of a power-on reset signal being active low.

[0038] During the period when the power-on reset signal is low, the reset control module clears the power-on reset flag, that is, sets the power-on reset flag to 0. When the power-on reset flag is stored in the first register, the reset control module sets the power-on reset flag in the first register to 0 during the period when the power-on reset signal is low. A power-on reset flag of 0 indicates that the processor did not perform a power-on reset or the power-on reset operation failed, while a power-on reset flag of 1 indicates that the processor's power-on reset operation was completed.

[0039] During the period when the power-on reset signal is low, the reset state machine is in an idle state. The idle state can be regarded as the initial state of the reset state machine.

[0040] During the period when the power-on reset signal is high, the reset control module can detect the power-on reset flag in the first register. When the power-on reset flag is detected as 1, it determines that the processor power-on reset is complete. Upon detecting that the power-on reset flag is 1, the reset control module sends a first message to the reset state machine, which indicates that the power-on reset flag is 1. Upon receiving the first message, the reset state machine transitions to the watchdog wait state.

[0041] In some possible implementations, if the reset control module detects that the power-on reset flag is consistently 0 while the power-on reset signal is high, it can be considered that the processor's power-on reset has failed. The reset control module then resends the power-on reset signal to the processor, causing the processor to re-execute the power-on reset process. This continues until the power-on reset flag is detected as 1, thus enabling automatic reset after a failed power-on reset due to interference, improving the reliability of the reset circuit. During the processor's re-execution of the power-on reset, the reset state machine remains in the power-on reset handshake state.

[0042] After powering on and resetting the processor in the manner described above, the processor enters the application program and begins executing it.

[0043] The following is an exemplary description of the watchdog reset (the reset that occurs when an application crashes in the processor).

[0044] During application execution, the processor can count or time according to the first clock signal, continuously sending a periodic square wave signal to the reset control module. This square wave signal can be considered as the processor's heartbeat signal, and its period can be, for example, 10ms. This application does not limit the specific period of the square wave signal. If the reset control module includes a second register, the processor can continuously write the periodic square wave signal to the second register.

[0045] In some possible implementations, when the reset state machine is in the watchdog wait state, it can count or time according to the first clock signal, and after waiting for a third preset duration (e.g., 300ms), it jumps to the watchdog detection state. This third waiting period is to ensure that the processor begins to run the application normally and to begin continuously writing periodic square wave signals to the second register.

[0046] In some possible implementations, when the reset state machine is in watchdog detection mode, the reset control module can detect the signal value of the square wave signal in the second register and calculate the hold duration of the signal value. When the signal value of the square wave signal changes (i.e., when the signal edge of the square wave signal changes), the hold duration is cleared to zero.

[0047] For example, assuming the period of a square wave signal is 10ms, and the signal values ​​are sequentially 0, 1, 0, 1..., then when the reset control module detects a signal value of 0, it starts calculating the hold duration of the signal value; when it detects a change from 0 to 1, it resets the hold duration to zero and restarts the calculation; when it detects a change from 1 to 0, it resets the hold duration to zero and restarts the calculation, and so on, to calculate the hold duration of the signal values. Since the period of the square wave signal is 10ms, the normal hold duration for each signal value is 5ms.

[0048] After calculating the holding time of the square wave signal value, the reset control module can determine whether the holding time is greater than or equal to a preset duration threshold (e.g., 300ms). If the holding time is less than the duration threshold, the application program in the processor can be considered to be running normally, and the detection of the square wave signal value can continue. During this process, the reset state machine remains in watchdog detection mode.

[0049] In some possible implementations, if the signal value is held for a duration greater than or equal to a preset threshold (e.g., 300ms), the reset control module considers that the processor has not sent a square wave signal (i.e., a heartbeat signal) for an extended period, and the application program in the processor has crashed. In this case, the reset control module sends a second message to the reset state machine, indicating that the square wave signal value has timed out. Upon receiving the second message, the reset state machine transitions to the watchdog reset state.

[0050] In watchdog reset mode, the reset control module sends a watchdog reset signal to the processor. This signal includes a low level for a fourth preset duration (e.g., 20ms). Upon receiving the watchdog reset signal, the processor performs a watchdog reset. The watchdog reset is a reset performed after an application crashes on the processor, and its purpose is to restore the processor to its initial state.

[0051] After the watchdog reset signal ends, the reset state machine transitions to the watchdog wait state. In the watchdog wait state, after waiting for a third preset duration, the reset state machine transitions to the watchdog detection state. In the watchdog detection state, the reset control module continues to detect the signal value and duration of the square wave signal using the methods described above.

[0052] In this way, the reset control module can dynamically detect the periodic square wave signal sent by the processor. If the duration of the square wave signal is greater than or equal to the duration threshold, it is considered that the application in the processor has crashed. Then, a watchdog reset signal is sent to the processor to make the processor perform a watchdog reset. This realizes the automatic reset of the processor in the case of application crash, thereby reducing the risk that the processor cannot be reset after the application crashes and improving the reliability of the reset circuit.

[0053] It should be noted that the specific values ​​of the first preset duration, the second preset duration, the third preset duration, the fourth preset duration, and the duration threshold in the above embodiments can be set by those skilled in the art according to the actual situation, and this application does not impose any restrictions on this.

[0054] Figure 3 A schematic diagram of the state transition of a reset state machine according to an embodiment of this application is shown. Figure 3 As shown, the reset state machine includes five states: initial state 31, power-on reset handshake state 32, watchdog wait state 33, watchdog detection state 34, and watchdog reset state 35.

[0055] During the power-on startup process of the system to which the reset circuit belongs, the reset state machine is in idle state 31 while the power-on reset signal is low. After the power-on reset signal goes high, the reset state machine transitions from idle state 31 to power-on reset handshake state 32.

[0056] In the power-on reset handshake state 32, when the reset control module detects that the power-on reset flag is 1, it sends a first message to the reset state machine, which indicates that the power-on reset flag is 1. Upon receiving the first message, the reset state machine transitions from the power-on reset handshake state 32 to the watchdog wait state 33. When the reset control module detects that the power-on reset flag is 0, it resends the power-on reset signal to the processor to cause the processor to re-execute the power-on reset. During this process, the reset state machine remains in the power-on reset handshake state 32.

[0057] In watchdog wait state 33, after the state machine is reset according to the first clock signal and waits for a third preset time, it jumps to watchdog detection state 34.

[0058] In watchdog detection state 34, during the execution of the application program, the processor continuously sends a periodic square wave signal to the reset control module according to the first clock signal; the reset control module detects the signal value of the square wave signal sent by the processor and calculates the holding time of the signal value; if the holding time of the signal value is greater than or equal to a preset duration threshold, it sends a second message to the reset state machine, which indicates that the holding time of the square wave signal value is greater than or equal to the duration threshold; upon receiving the second message, the reset state machine jumps from watchdog detection state 34 to watchdog reset state 35.

[0059] In watchdog reset state 35, the reset control module sends a watchdog reset signal of a fourth preset duration to the processor to cause the processor to perform a watchdog reset. After the watchdog reset signal ends, the reset state machine jumps from watchdog reset state 35 to watchdog wait state 33, thereby continuing to execute the above-mentioned related processes, which will not be elaborated here.

[0060] The reset circuit in this application supports power-on reset, power-on startup abnormal reset (i.e., after the processor fails to perform the first power-on reset during startup, it continues to perform power-on reset), and watchdog reset. This enables automatic reset when the processor fails to reset due to interference during power-on or when the application crashes, thereby improving the reliability of the reset circuit and the robustness of the system.

[0061] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved.

[0062] It should also be noted that each block in the block diagram and / or flowchart, as well as combinations of blocks in the block diagram and / or flowchart, can be implemented using hardware (such as circuits or ASICs (Application Specific Integrated Circuits)) that performs the corresponding function or action, or using a combination of hardware and software, such as firmware.

[0063] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0064] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A reset circuit, characterized in that, The reset circuit includes a clock module, a processor, and a reset control module; the clock module is connected to the processor and the reset control module, and the processor is connected to the reset control module; the reset control module is implemented using a programmable logic device. The clock module is used to: provide a first clock signal to the processor and the reset control module; The reset control module is used for: During the system power-on startup process of the reset circuit, a power-on reset signal is sent to the processor according to the first clock signal. The power-on reset signal includes a low level for a first preset duration and a high level for a second preset duration. During the period when the power-on reset signal is at a low level, the power-on reset flag is cleared to zero. The processor is used for: Upon receiving the power-on reset signal, a power-on reset is performed; after the power-on reset is completed, the power-on reset flag is set to 1. The reset control module is also used for: During the period when the power-on reset signal is high, the power-on reset flag is detected; when the power-on reset flag is detected to be 1, it is determined that the processor power-on reset is complete. The reset control module is configured to: when the power-on reset flag is consistently 0 during the period when the power-on reset signal is high, resend the power-on reset signal to the processor.

2. The reset circuit according to claim 1, characterized in that, The reset control module also includes a reset state machine. During the period when the power-on reset signal is low, the reset state machine is in an idle state. After the power-on reset signal becomes high, the reset state machine jumps to the power-on reset handshake state.

3. The reset circuit according to claim 2, characterized in that, The reset control module is used to: send first information to the reset state machine when the power-on reset flag is detected to be 1, wherein the first information is used to indicate that the power-on reset flag is 1; The reset state machine is used to: upon receiving the first information, jump to the watchdog waiting state.

4. The reset circuit according to claim 3, characterized in that, The reset state machine is used to: in the watchdog waiting state, according to the first clock signal, wait for a third preset time and then jump to the watchdog detection state.

5. The reset circuit according to claim 4, characterized in that, The processor is configured to: continuously send a periodic square wave signal to the reset control module according to the first clock signal during the running of the application; The reset control module is used to: detect the signal value of the square wave signal and calculate the holding time of the signal value when the reset state machine is in watchdog detection state; If the duration of holding the signal value is greater than or equal to a preset duration threshold, a second message is sent to the reset state machine to cause the reset state machine to jump to the watchdog reset state. When the reset state machine is in watchdog reset state, a watchdog reset signal is sent to the processor to cause the processor to perform a watchdog reset.

6. The reset circuit according to claim 5, characterized in that, The reset control module is used to: clear the hold duration to zero when the signal value of the square wave signal changes.

7. The reset circuit according to claim 5, characterized in that, The reset state machine is used to: jump to the watchdog waiting state after the watchdog reset signal ends.

8. The reset circuit according to claim 5, characterized in that, The reset control module further includes a first register and a second register, the first register being used to store the power-on reset flag, and the second register being used to store the square wave signal.

9. The reset circuit according to claim 1, characterized in that, The clock module includes a crystal oscillator and a clock buffer. The crystal oscillator is connected to the clock buffer, and the clock buffer is connected to the processor and the reset control module. The crystal oscillator is used to: generate a second clock signal; The clock buffer is used to: receive the second clock signal and fan out the first clock signal according to the second clock signal.

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