Memory devices and methods for operating memory devices

Abstract

The present disclosure relates to a memory device and a method for operating the memory device. A memory device includes: a plurality of memory cell arrays, each memory cell array is configured to include a plurality of memory cells; a plurality of peripheral circuits, each peripheral circuit is configured to perform operations on the plurality of memory cell arrays; a plurality of control logics, configured to control the plurality of peripheral circuits; and a control logic selector, configured to activate at least one control logic of the plurality of control logics according to the type of command received from a memory controller.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0130172 filed on October 18, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments relate generally to an electronic device, and more particularly to a semiconductor device and a method of operating the semiconductor device. Background Art

[0004] A storage device may store data in response to control of a host device such as a computer or a smart phone. A storage device may include a memory device that stores data and a memory controller that controls the memory device. A memory device may be divided into a volatile memory device and a non-volatile memory device.

[0005] Volatile memory devices can retain data when powered, and can lose stored data when power is lost. Types of volatile memory devices may include static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

[0006] Nonvolatile memory devices may not lose data even when there is no power. Types of nonvolatile memory devices may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the invention

[0007] According to one embodiment, a memory device may include: a plurality of memory cell arrays, each memory cell array being configured to include a plurality of memory cells; a plurality of peripheral circuits, each peripheral circuit being configured to perform operations on the plurality of memory cell arrays; a plurality of control logics being configured to control the plurality of peripheral circuits; and a control logic selector being configured to activate at least one of the plurality of control logics according to a type of command received from a memory controller.

[0008] According to one embodiment, a method of operating a memory device including a plurality of peripheral circuits controlling a plurality of memory cell arrays includes determining a type of command received from a host; and selectively activating a plurality of control logics controlling the plurality of peripheral circuits based on the type of command. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a storage device;

[0010] Figure 2 is a diagram illustrating multi-plane operations;

[0011] Figure 3 is a diagram illustrating a plane interleaving operation;

[0012] Figure 4 is a diagram illustrating a programming operation of a multi-plane scheme;

[0013] Figure 5 is a diagram illustrating a programming operation of a plane interleaving scheme;

[0014] Figure 6 is a diagram illustrating a memory device according to one embodiment;

[0015] Figure 7 is a diagram showing a memory device according to another embodiment;

[0016] Figure 8 is a diagram showing a control logic selector;

[0017] Fig. 9 is a diagram illustrating a method of operating a memory device;

[0018] Fig.10 is a diagram illustrating a method of operating a memory device;

[0019] Fig.11 is a diagram illustrating a memory device according to one embodiment;

[0020] Fig.12 It is shown Fig.11 A diagram of a memory block BLKi;

[0021] Fig.13 is a block diagram showing a memory card system to which a memory device according to one embodiment is applied;

[0022] Fig.14 is a block diagram showing an example of a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied; and

[0023] Fig.15 is a block diagram showing a user system to which a storage device according to one embodiment is applied. DETAILED DESCRIPTION

[0024] The structural or functional descriptions of the examples of embodiments of the concepts disclosed in this specification are only used to describe the examples of embodiments according to these concepts, and the examples of embodiments according to these concepts can be performed in various forms, but the descriptions are not limited to the examples of embodiments described in this specification.

[0025] Hereinafter, examples of embodiments of the present disclosure will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical spirit of the present disclosure.

[0026] Various embodiments may be directed to memory devices with improved current consumption management and methods of operating the same.

[0027] Figure 1 is a block diagram showing the storage device 50 .

[0028] refer to Figure 1 , the memory device 50 may include a memory device 100 and a memory controller 200 that controls operations of the memory device 100 .

[0029] The storage device 50 may be configured to store data in response to control of the host 300. Examples of the storage device 50 may include a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a television, a tablet computer, or an in-vehicle infotainment system.

[0030] The storage device 50 may be manufactured as one of various types of storage devices according to a host interface corresponding to a communication method with the host 300. For example, the storage device 50 may be configured as any of various storage devices, such as a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of SD, mini-SD, micro-SD, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, an international personal computer memory card association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a PCI Express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, a memory stick, and the like.

[0031] The memory device 50 may be manufactured by any of various types of packaging. For example, the memory device 50 may be manufactured as any of various types of packaging types, such as package-on-package (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), wafer-level stacked package (WSP), etc.

[0032] The memory device 100 may store data. The memory device 100 may operate in response to the control of the memory controller 200. The memory device 100 may include a memory cell array group 110. The memory cell array group 110 may include a plurality of memory cell arrays. Each of the plurality of memory cell arrays may include a plurality of memory cells storing data.

[0033] Each memory cell may be a single level cell (SLC) storing one data bit, a multi level cell (MLC) storing two data bits, a triple level cell (TLC) storing three data bits, or a quad level cell (QLC) storing four data bits.

[0034] The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. Each memory block may include a plurality of pages. According to one embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0035] In one embodiment, examples of the memory device 100 may include a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphic double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory device, a resistive random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM). For ease of explanation, it is assumed that the memory device 100 is a NAND flash memory.

[0036] The memory device 100 may include a peripheral circuit group 120. The peripheral circuit group 120 may include a plurality of peripheral circuits. Each of the plurality of peripheral circuits may perform a program, read, or erase operation on a memory block or page included in a plurality of memory cell arrays. For example, the peripheral circuit may apply an operating voltage to a word line coupled to the memory cell array, and apply a program permission voltage and a program inhibition voltage to a bit line coupled to the memory cell array. The peripheral circuit may perform an operation in response to the control of the control logic.

[0037] The memory device 100 may include control logic. The control logic group 130 may include a plurality of various control logics. The control logic may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic may be a control logic circuit that operates according to an algorithm and / or a processor that executes the control logic code. The control logic group 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic group 130 may include a plurality of control logic circuits that operate according to an algorithm and / or a processor that executes the control logic code. The control logic may receive commands, addresses, and data from the memory controller 200, and generate control signals to perform programming operations, read operations, or erase operations corresponding to the commands. The control logic may transmit control signals to peripheral circuits to perform operations corresponding to the commands.

[0038] The plurality of control logics included in the control logic group 130 may control the plurality of peripheral circuits included in the peripheral circuit group 120. The control logic group 130 may include common control logic and individual control logic. The common control logic may be implemented as hardware, software, or a combination of hardware and software. For example, the common control logic may be a common control logic circuit that operates according to an algorithm and / or a processor that executes the control logic code. The individual control logic may be implemented as hardware, software, or a combination of hardware and software. For example, the individual control logic may be an individual control logic circuit that operates according to an algorithm and / or a processor that executes the control logic code.

[0039] The common control logic may generate a common control signal, which is transmitted to the plurality of peripheral circuits included in the peripheral circuit group 120 in common. The plurality of peripheral circuits that have received the common control signal may perform operations corresponding to the command on the plurality of memory cell arrays included in the memory cell array group 110. Therefore, the common control logic may control the peripheral circuit group 120 so that operations may be performed on the plurality of memory cell arrays at the same time. For example, the common control logic may control the plurality of peripheral circuits so that the plurality of memory cell arrays may be operated simultaneously in a multi-plane manner.

[0040] The individual control logic may generate an individual control signal, which is transmitted to one peripheral circuit selected from a plurality of peripheral circuits included in the peripheral circuit group 120. The individual control logic may transmit the generated individual control signal to one peripheral circuit. Therefore, the individual control logic may control the peripheral circuit so that a programming, reading or erasing operation may be performed on one of the plurality of memory cell arrays included in the memory cell array group 110. Therefore, the peripheral circuits controlled by the plurality of individual control logics may be operated individually. The individual control logic may control the plurality of peripheral circuits so that the plurality of memory cell arrays may be operated individually in a planar interleaved manner.

[0041] The memory device 100 may include a control logic selector 140. The control logic selector 140 may receive a command from the memory controller 200 and select a control logic for controlling an operation corresponding to the received command. For example, the control logic selector 140 may selectively activate a common control logic and an individual control logic according to the type of command received. For example, after the control logic selector 140 receives a command for indicating a multi-plane operation, the control logic selector 140 may activate the common control logic and deactivate the individual control logic. Alternatively, after the control logic selector 140 receives a command for indicating a plane interleaving operation, the control logic selector 140 may activate the common control logic and the individual control logic. The control logic selector 140 may deactivate the individual control logic by power gating or clock gating. Power gating may be a technique for preventing power supply to control logic that is not used in a programming operation, a read operation, or an erase operation in response to a gating control signal. Clock gating may be a technique for blocking power supply to control logic not used in a program operation, a read operation, or an erase operation in response to a gating control signal.

[0042] The memory device 100 may reduce current consumption caused by unused individual control logics by selectively activating the individual control logics according to the type of command.

[0043] The memory device 100 may include a signal selector 150. The signal selector 150 may selectively provide a common control signal generated by a common control logic for controlling the peripheral circuit and an individual control signal generated by an individual control logic for controlling the peripheral circuit to the peripheral circuit. The signal selector 150 may select the common control signal and the individual control signal in response to a selection signal received from the control logic selector 140. When both the common control logic and the individual control logic are activated, the signal selector 150 may select the common control signal or the individual control signal and provide the selected control signal to the peripheral circuit.

[0044] The memory device 100 may receive a command and an address from the memory controller 200. The memory device 100 may be configured to access a selected area in the memory cell array in response to the received address. When the memory device 100 accesses the selected area, this means that the memory device 100 may perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. During the programming operation, the memory device 100 may program the area selected by the address with data. During the read operation, the memory device 100 may read data from the area selected by the address. During the erase operation, the memory device 100 may erase data from the area selected by the address.

[0045] When the storage device 50 is powered, the memory controller 200 may execute the firmware FW. The firmware FW may include: a host interface layer HIL that receives a request input from the host 300 or outputs a response to the host 300; a flash translation layer FTL that manages operations between an interface of the host 300 and an interface of the memory device 100; and a flash interface layer FIL that provides a command to the memory device 100 or receives a response from the memory device 100.

[0046] The memory controller 200 may receive data and a logical address LA from the host 300 and convert the logical address LA into a physical address PA indicating an address of a memory cell storing data in the memory device 100. The logical address LA may be a logical block address LBA and the physical address PA may be a physical block address PBA.

[0047] The memory controller 200 may control the memory device 100 so that a program operation, a read operation, or an erase operation may be performed in response to a request from the host 300. During a program operation, the memory controller 200 may provide a program command, a physical block address, and data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a physical block address to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command, a physical block address, and data to the memory device 100.

[0048] The memory controller 200 may control the memory device 100 so that a program operation, a read operation, or an erase operation may be performed regardless of a request from the host 300. For example, the memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation for performing background operations such as wear leveling, garbage collection, and read collection.

[0049] The host 300 may communicate with the storage device 50 using at least one of various communication methods, such as universal serial bus (USB), serial AT attachment (SATA), serial attached SCSI (SAS), high-speed inter-chip (HSIC), small computer system interface (SCSI), peripheral component interconnect (PCI), PCI Express (PCIe), non-volatile memory express (NVMe), universal flash memory (UFS), secure digital (SD), multimedia card (MMC), embedded MMC (eMMC), dual in-line memory module (DIMM), registered DIMM (RDIMM), and load-reduced DIMM (LRDIMM) communication methods.

[0050] Figure 2 is a diagram illustrating multi-plane operation.

[0051] refer to Figure 2 , the memory device 100_2 may include a first memory cell array 2010, a second memory cell array 2020, a first peripheral circuit 2030, a second peripheral circuit 2040, a control logic 2050, and an input / output circuit 2060. The control logic 2050 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 2050 may be a control logic circuit that operates according to an algorithm and / or a processor that executes a control logic code.

[0052] The input / output circuit 2060 may receive commands, addresses, and data from the memory controller 200. The input / output circuit 2060 may transmit data to the first peripheral circuit 2030 and the second peripheral circuit 2040. The input / output circuit 2060 may transmit data from the first peripheral circuit 2030 and the second peripheral circuit 2040. The input / output circuit 2060 may transmit data from the first peripheral circuit 2030 and the second peripheral circuit 2040 to the memory controller 200. The input / output circuit 2060 may transmit commands and addresses to the control logic 2050. The input / output circuit 2060 may receive first data to be stored in the first memory cell array 2010 and second data to be stored in the second memory cell array 2020 from the memory controller 200 in a sequential manner. In other words, after the input / output circuit 2060 receives the first data from the memory controller 200 and transmits the received first data to the first peripheral circuit 2030, the input / output circuit 2060 can receive the second data from the memory controller 200 and transmit the received second data to the second peripheral circuit 2040.

[0053] The control logic 2050 may receive a command and an address from the input / output circuit 2060 and generate a control signal for controlling the first peripheral circuit 2030 and the second peripheral circuit 2040 to perform an operation corresponding to the command on a region corresponding to the address. The control logic 2050 may transmit the control signal to the first peripheral circuit 2030 and the second peripheral circuit 2040 at the same time.

[0054] The first peripheral circuit 2030 and the second peripheral circuit 2040 may receive a control signal in common from the control logic 2050. The first peripheral circuit 2030 and the second peripheral circuit 2040 may simultaneously perform operations corresponding to commands based on the control signal received in common from the control logic 2050. For example, the first peripheral circuit 2030 and the second peripheral circuit 2040 may simultaneously program the memory cell array using data from the input / output circuit 2060. The first peripheral circuit 2030 and the second peripheral circuit 2040 may read data from the first memory cell array 2010 and the second memory cell array 2020, respectively. The first peripheral circuit 2030 and the second peripheral circuit 2040 may simultaneously erase data stored in the first memory cell array 2010 and the second memory cell array 2020.

[0055] The method of using one control logic to simultaneously control multiple peripheral circuits can be referred to as a multi-plane scheme. When one control logic reads data stored in multiple memory cell arrays based on a received address, data can be read from the same area in the multiple memory cell arrays. As a result, the random read performance of reading data from random areas may deteriorate.

[0056] Figure 3 is a diagram illustrating a plane interleaving operation.

[0057] refer to Figure 3 , the memory device 100_3 may include a first memory cell array 3010, a second memory cell array 3020, a first peripheral circuit 3030, a second peripheral circuit 3040, a first control logic 3050, a second control logic 3060, and an input / output circuit 3070. The first control logic may be implemented as hardware, software, or a combination of hardware and software. For example, the first control logic may be a first control logic circuit that operates according to an algorithm and / or a processor that executes a control logic code. The second control logic may be implemented as hardware, software, or a combination of hardware and software. For example, the second control logic may be a second control logic circuit that operates according to an algorithm and / or a processor that executes a control logic code.

[0058] The first control logic 3050 may receive a command and an address from the input / output circuit 3070 and generate a control signal for controlling the first peripheral circuit 3030 to perform an operation corresponding to the command on an area corresponding to the address among storage areas included in the first memory cell array 3010 .

[0059] The second control logic 3060 may receive a command and an address from the input / output circuit 3070 , and generate a control signal for controlling the second peripheral circuit 3040 to perform an operation corresponding to the command on an area corresponding to the address among storage areas included in the second memory cell array 3020 .

[0060] In other words, since the first control logic 3050 and the second control logic 3060 can receive different addresses, the area performing operations in the storage area included in the first memory cell array 3010 and the area performing operations in the storage area included in the second memory cell array 3020 can be accessed through different addresses.

[0061] The input / output circuit 3070 may receive data from the memory controller 200 and sequentially transmit the received data to the first peripheral circuit 3030 and the second peripheral circuit 3040. For example, the input / output circuit 3070 may receive first data and transmit the first data to the first peripheral circuit 3030, and then, may receive second data and transmit the second data to the second peripheral circuit 3040.

[0062] The data transmitted to the first peripheral circuit 3030 and the second peripheral circuit 3040 can be independently programmed by the first control logic 3050 and the second control logic 3060, respectively. For example, when the first data is transmitted to the first peripheral circuit 3030, the first control logic 3050 may not wait for the second peripheral circuit 3040 to receive the second data. In other words, the first control logic 3050 can control the first peripheral circuit 3030 to program the first memory cell array 3010 with the first data, regardless of whether the second data is transmitted to the second peripheral circuit 3040. In the same way, the second control logic 3060 can control the second peripheral circuit 3040 so that the second data can be programmed into the second memory cell array 3020, regardless of whether the first data is transmitted to the first peripheral circuit 3030. For ease of explanation, the programming operation has been described. However, the embodiment is not limited thereto. During a read operation or an erase operation, the first control logic 3050 and the second control logic 3060 can operate independently of each other.

[0063] The method of performing a program operation, a read operation, or a read operation on the first memory cell array 3010 and the second memory cell array 3020 in an independent manner may be referred to as a plane interleaving scheme. In other words, according to the plane interleaving scheme, each control logic may independently control each of the plurality of peripheral circuits to perform a program operation, a read operation, or an erase operation in each of the plurality of memory cell arrays.

[0064] Figure 4 is a diagram illustrating a multi-plane programming operation.

[0065] refer to Figure 4 , the first plane 410 may include a first memory cell array 411 and a first peripheral circuit 412. The second plane 420 may include a second memory cell array 421 and a second peripheral circuit 422. The input / output circuit 430 may transmit data to the first peripheral circuit 412 and the second peripheral circuit 422. The first peripheral circuit 412 and the second peripheral circuit 422 may be controlled by one control logic.

[0066] The input / output circuit 430 may transmit the first data DATA1 to the first peripheral circuit 412. The input / output circuit 430 may transmit the second data DATA2 to the second peripheral circuit 422. The first peripheral circuit 412 and the second peripheral circuit 422 may program the memory cell array with the first data DATA1 and the second data DATA2, respectively, at the same time. In other words, the first peripheral circuit 412 may program the first memory cell array 411 with the first data DATA1, and at the same time, the second peripheral circuit 422 may program the second memory cell array 421 with the second data DATA2.

[0067] The first peripheral circuit 412 and the second peripheral circuit 422 can perform programming operations by the same control logic. Therefore, data can be programmed into the area indicated by the address that has been received by the control logic. For example, the control logic can receive the first address ADDR1. The first peripheral circuit 412 can program the first data DATA1 into the storage area indicated by the first address ADDR1 in the storage area included in the first memory cell array 411. The second peripheral circuit 422 can program the second data DATA2 into the storage area indicated by the first address ADDR1 in the storage area included in the second memory cell array 421. In other words, since the operation is performed on the area indicated by the same address, the random programming performance may be degraded. For ease of explanation, the programming operation is provided as an example. However, when a read operation or an erase operation is performed in a multi-plane scheme, the random read performance and the random erase performance may also be degraded.

[0068] Referring to the diagram of operation time and operation position, during a program operation, the input / output circuit 430 may perform an I / O operation that receives data from the memory controller 200 and transmits the data to a peripheral circuit. For example, the input / output circuit 430 may receive first data DATA1 from the memory controller 200 and transmit the first data DATA1 to the first peripheral circuit 412. After the first data DATA1 is transmitted to the first peripheral circuit 412, the input / output circuit 430 may receive second data DATA2 from the memory controller 200 and transmit the second data DATA2 to the second peripheral circuit 422.

[0069] When the first peripheral circuit 412 and the second peripheral circuit 422 receive data, the control logic may control the first peripheral circuit 412 and the second peripheral circuit 422 so that the first data DATA1 and the second data DATA2 may be programmed into the first memory cell array 411 and the second memory cell array 421, respectively, at the same time. In other words, after the first peripheral circuit 412 of the first plane 410 receives the first data DATA1, the first plane 410 may wait for the waiting time tWAIT until the second peripheral circuit 422 receives the second data DATA2. In one embodiment, the word "simultaneously" with respect to occurrence as used herein refers to occurrences that occur within overlapping time intervals. For example, if a first occurrence occurs within a first time interval and a second occurrence occurs simultaneously within a second time interval, the first interval and the second interval at least partially overlap each other, so that there is a time when both the first occurrence and the second occurrence occur after the waiting time tWAIT.

[0070] Figure 5 is a diagram illustrating a programming operation according to a plane interleaving scheme.

[0071] refer to Figure 5 , the first plane 510 may include a first memory cell array 511 and a first peripheral circuit 512. The second plane 520 may include a second memory cell array 521 and a second peripheral circuit 522. The input / output circuit 530 may transmit data to the first peripheral circuit 512 and the second peripheral circuit 522. The first peripheral circuit 512 and the second peripheral circuit 522 may be controlled by a first control logic (not shown) and a second control logic (not shown), respectively.

[0072] The input / output circuit 530 may transmit the first data DATA1 to the first peripheral circuit 512. The input / output circuit 530 may transmit the second data DATA2 to the second peripheral circuit 522. The first peripheral circuit 512 and the second peripheral circuit 522 may program the memory cell array with the first data DATA1 and the second data DATA2, respectively, at the same time. In other words, the second peripheral circuit 522 may program the second memory cell array 521 with the second data DATA2, regardless of the operation of the first peripheral circuit 512 programming the first memory cell array 511 with the first data DATA1.

[0073] The first peripheral circuit 512 and the second peripheral circuit 522 may perform a programming operation through a first control logic (not shown) and a second control logic (not shown), respectively. Therefore, the address received by the first control logic (not shown) from the memory controller 200 may be different from the address received by the second control logic (not shown) from the memory controller 200. For example, the first control logic (not shown) may receive a first address ADDR1, and the second control logic (not shown) may receive a third address ADDR3.

[0074] The first peripheral circuit 512 may be controlled by a first control logic (not shown), and programs the first data DATA1 into a storage area indicated by a first address ADDR1 in a storage area included in the first memory cell array 511. The second peripheral circuit 522 may be controlled by a second control logic (not shown), and programs the second data DATA2 into a storage area indicated by a third address ADDR3 in a storage area included in the second memory cell array 521. In other words, since the operation is performed on an area indicated by a different address, random programming performance may be improved. For ease of explanation, a programming operation is provided as an example. However, when a read operation or an erase operation is performed in a plane interleaving scheme, random read performance and random erase performance may also be improved.

[0075] Referring to the diagram of operation time and operation position, the input / output circuit 530 may perform an I / O operation that receives data from the memory controller 200 and transmits the data to the peripheral circuit. For example, the input / output circuit 530 may receive first data DATA1 from the memory controller 200 and transmit the first data DATA1 to the first peripheral circuit 512. After the first data DATA1 is transmitted to the first peripheral circuit 512, the input / output circuit 530 may receive second data DATA2 from the memory controller 200 and transmit the second data DATA2 to the second peripheral circuit 522.

[0076] When the first peripheral circuit 512 receives the first data DATA1, the first control logic (not shown) may control the first peripheral circuit 512 to program the first memory cell array 511 with the first data DATA1. When the second peripheral circuit 522 receives the second data DATA2, the second control logic (not shown) may control the second peripheral circuit 522 to program the second memory cell array 521 with the second data DATA2. That is, the programming operation may be performed independently on the first plane 510 and the second plane 520.

[0077] and Figure 4 In contrast to the operation time shown, the first plane 510 may perform a program operation without waiting for the waiting time tWAIT after receiving the first data DATA1, so that the program completion time of the first plane 510 may be reduced by the waiting time tWAIT.

[0078] Figure 6 is a diagram illustrating a memory device 100 according to one embodiment.

[0079] refer to Figure 6 , the memory device 100 may include a memory cell array group 110 , a peripheral circuit group 120 , a control logic group 130 , a control logic selector 140 , a signal selector 150 , and a control logic driver 630 .

[0080] The memory cell array group 110 may include a first memory cell array 111, a second memory cell array 112, and a third memory cell array 113. The peripheral circuit group 120 may include a first peripheral circuit 121, a second peripheral circuit 122, and a third peripheral circuit 123. The signal selector 150 may include a first selection circuit 151, a second selection circuit 152, and a third selection circuit 153. The control logic group 130 may include a first control logic 131, a second control logic 132, and a third control logic 133.

[0081] The first control logic 131, the second control logic 132, and the third control logic 133 may control the first peripheral circuit 121, the second peripheral circuit 122, and the third peripheral circuit 123, respectively. One of the first control logic 131 to the third control logic 133 may be a common control logic. The common control logic may generate a common control signal, which is commonly transmitted to the first peripheral circuit 121 to the third peripheral circuit 123. According to one embodiment, the first control logic 131 may be a common control logic. The second control logic 132 and the third control logic 133 may be individual control logics. The individual control logic may generate an individual control signal, which is transmitted to one peripheral circuit selected from a plurality of peripheral circuits. According to one embodiment, the second control logic 132 and the third control logic 133 may be individual control logics. The second control logic 132 may generate an individual control signal transmitted to the second peripheral circuit 122. The third control logic 133 may generate an individual control signal transmitted to the third peripheral circuit 123.

[0082] For ease of explanation, the first control logic 131 may be a common control logic, and the second control logic 132 and the third control logic 133 may be individual control logics. However, the embodiment is not limited thereto.

[0083] The control logic driver 630 may generate a drive signal transmitted to the control logic group 130. The drive signal may be a power signal or a clock signal. For example, the control logic driver 630 may receive an external power supply from an external device and generate a power signal to be applied to each control logic. Alternatively, the control logic driver 630 may receive an external clock from an external device and generate a clock signal to be applied to each control logic.

[0084] The control logic selector 140 may receive a command from the memory controller 200 or the input / output circuit. The control logic selector 140 may determine the type of command received. For example, the control logic selector 140 may determine whether the received command is used to indicate an operation performed in a multi-plane scheme. Alternatively, the control logic selector 140 may determine whether the received command is used to indicate an operation performed in a plane interleaving scheme.

[0085] The control logic selector 140 may selectively provide a driving signal from the control logic driver 630 to the first control logic 131 to the third control logic 133. For example, the control logic selector 140 may selectively provide a power signal to the first control logic 131 to the third control logic 133 using a power gating scheme. Alternatively, the control logic selector 140 may selectively provide a power signal to the first control logic 131 to the third control logic 133 using a clock gating scheme.

[0086] The control logic selector 140 may selectively provide a driving signal to the first control logic 131 to the third control logic 133 according to the type of the command received from the control logic driver 630. For example, when the received command is for indicating a multi-plane operation, the control logic selector 140 may activate the first control logic 131 by transmitting a driving signal to the first control logic 131, and deactivate the second control logic 132 and the third control logic 133. For example, when the received command is for indicating an operation performed in a plane interleaving scheme, the control logic selector 140 may activate the first control logic 131 and the third control logic 133 by transmitting a driving signal to the first control logic 131 and the third control logic 133.

[0087] When the control logic does not receive the driving signal, current consumption may be reduced. In other words, the control logic selector 140 may reduce current consumption by selectively activating or deactivating the control logic according to the type of command.

[0088] In addition to the first peripheral circuit 121, the first control logic 131 may transmit a common control signal to the second peripheral circuit 122 and the third peripheral circuit 123. The second control logic 132 may transmit an individual control signal to the second peripheral circuit 122. The third control logic 133 may transmit an individual control signal to the third peripheral circuit 123. Therefore, when all of the first control logics 131 to the third control logics 133 are activated, the second peripheral circuit 122 and the third peripheral circuit 123 may receive the common control signal and the individual control signal.

[0089] Therefore, the signal selector 150 may transmit one of the common control signal and the individual control signal to the peripheral circuit.

[0090] The first selection circuit 151 may receive a common control signal from the first control logic 131, and transmit the common control signal to the first peripheral circuit 121. The second selection circuit 152 may receive a common control signal from the first control logic 131 and receive an individual control signal from the second control logic 132. The second selection circuit 152 may select a control signal between the received common control signal and the received individual control signal in response to the selection signal, and may transmit the selected control signal to the second peripheral circuit 122. The third selection circuit 153 may receive a common control signal from the first control logic 131 and receive an individual control signal from the third control logic 133. The third selection circuit 153 may select a control signal between the received common control signal and the received individual control signal in response to the selection signal, and may transmit the selected control signal to the third peripheral circuit 123.

[0091] The control logic selector 140 may generate a selection signal according to the type of command received from the memory controller 200. The control logic selector 140 may transmit the generated selection signal to the signal selector 150. For example, when the type of command corresponds to a command for indicating a multi-plane operation, the control logic selector 140 may generate a selection signal so that the first selection circuit 151 to the third selection circuit 153 may transmit the common control signal generated by the first control logic 131 to the first peripheral circuit 121 to the third peripheral circuit 123, respectively. When the type of command corresponds to a command for indicating an operation performed in a plane interleaving scheme, the control logic selector 140 may generate a selection signal so that the first selection circuit 151 may transmit the common control signal generated by the first control logic 131 to the first peripheral circuit 121. The control logic selector 140 may generate a selection signal so that the second selection circuit 152 may transmit the individual control signal generated by the second control logic 132 to the second peripheral circuit 122. The control logic selector 140 may generate a selection signal so that the third selection circuit 153 may transmit the individual control signal generated by the third control logic 133 to the third peripheral circuit 123 .

[0092] The first to third peripheral circuits 121 to 123 may respectively control the first to third memory cell arrays 111 to 113 included in the memory cell array group 110 in response to a control signal received from the signal selector 150 .

[0093] According to one embodiment, by deactivating some of the first to third control logics 131 to 133 according to the type of command, current consumption of control logics that are not used during an operation corresponding to the type of command may be reduced.

[0094] Figure 7 is a diagram illustrating a memory device according to another embodiment.

[0095] Apart from Figure 6 , also refer to Figure 7 , the signal selector 150 may not include the first selection circuit 151. The first peripheral circuit 121 may receive a common control signal generated by the first control logic 131 regardless of the type of command. On the other hand, the second peripheral circuit 122 and the third peripheral circuit 123 may receive a common control signal generated by the first control logic 131 or individual control signals generated by the second control logic 132 and the third control logic 133, depending on the type of command. Therefore, the signal selector 150 may include only the second selection circuit 152 and the third selection circuit 153. Therefore, the size ratio can be designed Figure 6 The memory device shown is a smaller memory device.

[0096] Figure 8 is a diagram showing the control logic selector 140 .

[0097] refer to Figure 8 , the control logic selector 140 may include a driving switch 141 and a command detector 142 .

[0098] The command detector 142 may receive a command from the memory controller 200. The command detector 142 may determine the type of command received. Alternatively, the command detector 142 may determine the number of control logics used to perform an operation corresponding to the received command. For example, the command detector 142 may determine whether the received command is used to indicate an operation performed in a plane interleaving scheme. For example, the command detector 142 may determine whether the received command is used to indicate an operation performed in a multi-plane scheme.

[0099] The command detector 142 may generate an enable signal according to the type of the command to provide to the drive switch 141. For example, when the command received from the memory controller 200 is for indicating an operation performed in a plane interleaving scheme, the command detector 142 may generate an enable signal to activate the common control logic and the individual control logic. When the command received from the memory controller 200 is for indicating an operation performed in a multi-plane scheme, the command detector 142 may generate an enable signal to activate the common control logic and deactivate the individual control logic.

[0100] The command detector 142 may generate a selection signal according to the type of the command to be provided to the driving switch 141. For example, when the command received from the memory controller 200 is for indicating an operation performed in a plane interleaving scheme, the command detector 142 may generate a selection signal so that the first peripheral circuit 121 receives a common control signal and the second peripheral circuit 122 and the third peripheral circuit 123 may receive individual control signals. For example, when the command received from the memory controller 200 is for indicating an operation performed in a multi-plane scheme, the command detector 142 may generate a selection signal so that the first peripheral circuit 121 to the third peripheral circuit 123 receive a common control signal.

[0101] The drive switch 141 may receive a drive signal from the control logic driver 630 and selectively provide the drive signal to the control logic group 130. The drive switch 141 may receive an enable signal from the command detector 142 and selectively provide the drive signal to the control logic group 130 in response to the enable signal. For example, when the command received from the memory controller 200 is used to indicate an operation performed in a plane interleaving scheme, the command detector 142 may generate an enable signal so that the first control logic 131 to the third control logic 133 may receive the drive signal. In other words, the first control logic 131 to the third control logic 133 may be activated. When the command received from the memory controller 200 is used to indicate an operation performed in a multi-plane scheme, the command detector 142 may generate an enable signal so that the first control logic 131 may be activated and the second control logic 132 and the third control logic 133 may be deactivated.

[0102] Fig. 9 is a diagram illustrating a method of operating the memory device 100 .

[0103] refer to Fig. 9 In step S901, the control logic selector 140 may receive a command from the memory controller 200. The command may be a program command, a read command, or an erase command. The command may indicate an operation performed in a plane interleaving scheme or an operation performed in a multi-plane scheme.

[0104] In step S903, the control logic selector 140 may determine the type of the received command. In other words, the control logic selector 140 may determine whether the received command is for instructing an operation performed in a plane interleaving scheme or an operation performed in a multi-plane scheme.

[0105] In step S905, the control logic selector 140 may selectively provide a driving signal to the plurality of control logics according to the type of the received command. For example, when operations are performed on a plurality of planes simultaneously, the driving signal may be provided to a common control logic. When operations are performed on a plurality of planes separately, the driving signal may be provided to a common control logic and an individual control logic.

[0106] In step S907, the signal selector 150 may selectively provide a control signal to the peripheral circuit according to a selection signal generated based on the type of the command. For example, when operations are performed on multiple planes, a common control signal received from a common control logic may be provided to multiple peripheral circuits. When operations are performed on multiple planes, respectively, one of a common control signal received from a common control logic and an individual control signal received from an individual control logic may be provided to a peripheral circuit.

[0107] At step S909, the peripheral circuit group 120 may perform an operation corresponding to the command in response to the common control signal or the individual control signal received from the signal selector 150. For example, the operation may be performed on a plurality of planes simultaneously or separately.

[0108] According to the method of operating a memory device, since a driving signal is selectively provided to a control logic according to a type of a command, current consumption caused by unused control logic may be reduced.

[0109] Fig.10 is a diagram illustrating a method of operating the memory device 100 .

[0110] refer to Fig.10 In step S1001, the control logic selector 140 may receive a command from the memory controller 200. The command may be a program command, a read command, or an erase command. The command may indicate an operation performed in a plane interleaving scheme or an operation performed in a multi-plane scheme.

[0111] In step S1003, the control logic selector 140 may determine whether the received command is used to indicate an operation performed in a multi-plane scheme, i.e., a multi-plane command. Alternatively, the control logic selector 140 may determine whether the received command is used to indicate an operation performed in a plane interleaving scheme, i.e., a plane interleaving command. When the received command is a multi-plane command, the process flow may proceed to step S1013.

[0112] In step S1005, the control logic selector 140 may activate the common control logic. The common control logic may be a control logic that generates a common control signal to be provided to a plurality of peripheral circuits. In other words, the common control logic may control a plurality of peripheral circuits. The control logic selector 140 may receive a drive signal from the control logic driver 630 and transmit the drive signal to the common control logic, thereby activating the common control logic. The drive signal may be a power signal or a clock signal.

[0113] In step S1005, the control logic selector 140 may activate the common control logic. The common control logic may be a control logic that generates a common control signal to be provided to a plurality of peripheral circuits. In other words, the common control logic may control a plurality of peripheral circuits. The control logic selector 140 may receive a drive signal from the control logic driver 630 and transmit the drive signal to the common control logic, thereby activating the common control logic. The drive signal may be a power signal or a clock signal.

[0114] In step S1007, the control logic selector 140 may activate the individual control logic. The individual control logic may be a control logic that generates individual control signals to be provided to a plurality of peripheral circuits, respectively. In other words, each individual control logic may control one peripheral circuit selected from the peripheral circuits. The control logic selector 140 may receive a drive signal from the control logic driver 630, and may not transmit the drive signal to the individual control logic, thereby deactivating the individual control logic.

[0115] At step S1009, the signal selector 150 may provide the common control signal received from the common control logic to the plurality of peripheral circuits. The signal selector 150 may select the common control signal between the common control signal and the individual control signals and provide the selected common control signal to the plurality of peripheral circuits.

[0116] In step S1013, the control logic selector 140 may activate the common control logic and the individual control logic. The control logic selector 140 may receive a drive signal from the control logic driver 630 and transmit the drive signal to the common control logic and the individual control logic, thereby activating the common control logic and the individual control logic. The drive signal may be a power signal or a clock signal.

[0117] In step S1015, the signal selector 150 may selectively provide the common control signal and the individual control signal to the peripheral circuit. For example, the signal selector 150 may select the control signal in response to the selection signal received from the control logic selector 140. For example, when the received command is a plane interleaving command, the signal selector 150 may transmit the individual control signal to the peripheral circuit.

[0118] According to the method of operating a memory device, since a driving signal is selectively provided to a control logic according to a type of a command, current consumption caused by unused control logic may be reduced.

[0119] Fig.11 is a diagram illustrating a memory device 1100 according to one embodiment.

[0120] refer to Fig.11 , the memory device 1100 may include a memory cell array 1110 , a peripheral circuit 1120 , and a control logic 1130 .

[0121] The memory cell array 1110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be coupled to a row decoder 1121 through a row line RL. The memory blocks BLK1 to BLKz may be coupled to a page buffer group 1123 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. According to one embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells coupled to the same word line may be defined as one page. Therefore, each memory block may include a plurality of pages.

[0122] The row line RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0123] Each memory cell included in the memory cell array 1110 may include a single level cell (SLC) storing a single data bit, a multi level cell (MLC) storing two data bits, a triple level cell (TLC) storing three data bits, or a quad level cell (QLC) storing four data bits.

[0124] The peripheral circuit 1120 may be configured to perform programming, reading, and erasing operations on a selected region of the memory cell array 1110 in response to the control of the control logic 1130. The peripheral circuit 1120 may drive the memory cell array 1110. For example, the peripheral circuit 1120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn, or may release the applied voltages in response to the control of the control logic 1130.

[0125] The peripheral circuit 1120 may include a row decoder 1121 , a voltage generator 1122 , a page buffer group 1123 , a column decoder 1124 , and an input / output circuit 1140 .

[0126] The row decoder 1121 may be coupled to the memory cell array 1110 via a row line RL. The row line RL may include at least one source selection line, a plurality of word lines, and at least one drain selection line. According to one embodiment, the word line may include a normal word line and a dummy word line. According to one embodiment, the row line RL may also include a pipeline selection line.

[0127] The row decoder 1121 may be configured to operate in response to the control of the control logic 1130. The row decoder 1121 may receive a row address RADD from the control logic 1130.

[0128] The row decoder 1121 may be configured to decode a row address RADD. The row decoder 1121 may select at least one memory block from the memory blocks BLK1 to BLKz according to the decoded block address. The row decoder 1121 may select at least one word line from the selected memory block so as to apply a voltage generated by the voltage generator 1122 to the at least one word line according to the decoded address.

[0129] For example, during a program operation, the row decoder 1121 may apply a program voltage to a selected word line, and apply a program pass voltage having a voltage level lower than the program voltage to unselected word lines. During a program verification operation, the row decoder 1121 may apply a verification voltage to a selected word line, and apply a verification pass voltage greater than the verification voltage to unselected word lines. During a read operation, the row decoder 1121 may apply a read voltage to a selected word line, and apply a read pass voltage greater than the read voltage to unselected word lines.

[0130] According to one embodiment, the erase operation of the memory cell array 1110 may be performed in units of memory blocks. During the erase operation, the row decoder 1121 may select one of the memory blocks according to the decoded address. During the erase operation, the row decoder 1121 may apply a ground voltage to a word line coupled to the selected memory block.

[0131] The voltage generator 1122 may be controlled by the control logic 1130. The voltage generator 1122 may be configured to generate a plurality of voltages by using an external power supply voltage provided to the memory device 1100. For example, the voltage generator 1122 may generate an operation voltage Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. For example, the voltage generator 1122 may generate a program voltage, a verification voltage, a pass voltage, a read voltage, and an erase voltage in response to the control of the control logic 1130.

[0132] According to one embodiment, the voltage generator 1122 may generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 1122 may be used as an operating voltage of the memory cell array 1110.

[0133] According to one embodiment, the voltage generator 1122 may generate a plurality of voltages by using an external power supply voltage or an internal power supply voltage.

[0134] For example, the voltage generator 1122 may include a plurality of pumping capacitors that receive an internal power supply voltage, and generate a plurality of voltages by selectively activating the plurality of pumping capacitors in response to the control of the control logic 1130 .

[0135] The plurality of generated voltages may be provided to the memory cell array 1110 through the row decoder 1121 .

[0136] The page buffer group 1123 may include first to n-th page buffers PB1 to PBn. The first to n-th page buffers PB1 to PBn may be coupled to the memory cell array 1110 through first to n-th bit lines BL1 to BLn, respectively. The first to n-th page buffers PB1 to PBn may operate in response to the control of the control logic 1130. For example, the first to n-th page buffers PB1 to PBn may operate in response to the page buffer control signal PBSIGNALS. For example, the first to n-th page buffers PB1 to PBn may temporarily store data received through the first to n-th bit lines BL1 to BLn, or may sense a voltage or current in the first to n-th bit lines BL1 to BLn during a read or verification operation.

[0137] For example, during a programming operation, when a programming pulse is applied to a selected word line during a programming operation, the first page buffer PB1 to the nth page buffer PBn can transmit the data DATA received through the input / output circuit 1140 to the selected memory cell through the first bit line BL1 to the nth bit line BLn. The memory cell of the selected page can be programmed according to the transmitted data DATA. The memory cell coupled to the bit line to which a programming permission voltage (e.g., a ground voltage) is applied can have an increased threshold voltage. The threshold voltage of the memory cell coupled to the bit line to which a programming inhibition voltage (e.g., a power supply voltage) is applied can be maintained. During a program verification operation, the first page buffer PB1 to the nth page buffer PBn can read page data from the selected memory cell through the first bit line BL1 to the nth bit line BLn, respectively.

[0138] During a read operation, the first to nth page buffers PB1 to PBn may read data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and output the read data DATA to the data input / output circuit 1125 in response to control of the column decoder 1124 .

[0139] During an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn.

[0140] The column decoder 1124 may transfer data between the input / output circuit 1140 and the page buffer group 1123 in response to the column address CADD. For example, the column decoder 1124 may exchange data with the first to nth page buffers PB1 to PBn through the data lines DL, or may exchange data with the input / output circuit 1140 through the column lines CL.

[0141] The input / output circuit 1140 can convert the command CMD and address ADD from the above reference Figure 1 The described memory controller 200 transmits data DATA to the control logic 1130 or may exchange data DATA with the column decoder 1124 .

[0142] During a read operation or a verification operation, the sensing circuit 1126 may generate a reference current in response to a permission bit signal VRYBIT and compare a sensing voltage VPB received from the page buffer group 1123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0143] The control logic 1130 can control the peripheral circuit 1120 by outputting an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and a permission bit signal VRYBIT in response to a command CMD and an address ADD. In addition, the control logic 1130 can determine whether the verification operation has passed or failed in response to a pass signal PASS or a fail signal FAIL.

[0144] For ease of illustration, one memory cell array 1110 is shown. However, the memory device 1100 may include a plurality of memory cell arrays. Figure 6 and 7 As shown, the memory device 1100 may include a memory cell array group 110. The memory cell array group 110 may include a first memory cell array 111, a second memory cell array 112, and a third memory cell array 113.

[0145] For ease of illustration, one peripheral circuit 1120 is shown. However, the memory device 1100 may include a plurality of peripheral circuits. Figure 6 and 7 As shown, the memory device 1100 may include a peripheral circuit group 120. The peripheral circuit group 120 may include a first peripheral circuit 121, a second peripheral circuit 122, and a third peripheral circuit 123.

[0146] For ease of illustration, one control logic 1130 is shown. However, the memory device 1100 may include multiple control logics. For example, Figure 6 and 7As shown, the memory device 1100 may include a control logic group 130. The control logic group 130 may include a first control logic 131, a second control logic 132, and a third control logic 133.

[0147] The input / output circuit 1140 may include a control logic selector 140 and a control logic driver 630. The input / output circuit 110 may receive a command and transmit the command to the control logic selector 140. The control logic selector 140 may selectively activate a plurality of control logics. For example, the control logic selector 140 may selectively activate a common control logic or an individual control logic. The input / output circuit 1140 may include a signal selector 150. The signal selector 150 may selectively transmit a common control signal generated by the common control logic or an individual control signal generated by the individual control logic to the peripheral circuit group 120 according to a signal received from the control logic selector 140.

[0148] Fig.12 It is shown Fig.11 Figure 2 shows a diagram of a memory block BLKi.

[0149] refer to Fig.12 , the memory block BLKi may be coupled to a plurality of word lines arranged in parallel between a first selection line and a second selection line. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. Specifically, the memory block BLKi may include a plurality of strings ST coupled between the bit lines BL1 to BLm and the source line SL. The bit lines BL1 to BLm may be coupled to the strings ST, respectively, and the source line SL may be coupled to the string ST in common. Since the strings ST may have the same configuration, the string ST coupled to the first bit line BL1 will be described by way of example.

[0150] The string ST may include a source selection transistor SST, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST, which are coupled in series between a source line SL and a first bit line BL1. Each string ST may include at least one source selection transistor SST, at least one drain selection transistor DST, and a plurality of memory cells MC1 to MC16, which are coupled in series between the source line SL and the first bit line BL1. Figure 3 The memory cells MC1 to MC16 shown are more memory cells.

[0151] The source of the source select transistor SST may be coupled to the source line SL, and the drain of the drain select transistor DST may be coupled to the first bit line BL1. The memory cells MC1 to MC16 may be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST may be coupled to the source select line SSL, the gates of the drain select transistors DST may be coupled to the drain select line DSL, and the gates of the memory cells MC1 to MC16 may be coupled to a plurality of word lines WL1 to WL16. A group of memory cells coupled to the same word line among the memory cells included in different strings ST may be referred to as a physical page PG. Therefore, the memory block BLKi may include as many physical pages PG as the number of word lines WL1 to WL16.

[0152] A single memory cell can store one bit of data. This memory cell is usually called a single-level cell (SLC). One physical page PPG can store one logical page (LPG) of data. One LPG data can include as many data bits as the number of cells included in one physical page PG.

[0153] In addition, a single memory cell can store two or more bits of data. One physical page PG can store data corresponding to two or more logical pages LPG.

[0154] Fig.13 is a block diagram illustrating an example of a memory card system 2000 to which a storage device according to an embodiment of the present disclosure is applied.

[0155] refer to Fig.13 , the memory card system 2000 may include a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0156] The memory controller 2100 may be coupled to the memory device 2200. The memory controller 2100 may access the memory device 2200. For example, the memory controller 2100 may control read, write, erase, and background operations of the memory device 2200. The memory controller 2100 may be configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 may be configured to drive firmware for controlling the memory device 2200.

[0157] In one embodiment, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an ECC block.

[0158] The memory controller 2100 may communicate with an external device through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) based on a communication protocol. For example, the memory controller 2100 may communicate with an external device through at least one of various communication protocols, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer small interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash memory (UFS), WiFi, Bluetooth, and a non-volatile memory Express (NVMe) protocol. For example, the connector 2300 may be defined by at least one of the various communication protocols described above.

[0159] In one embodiment, the memory device 2200 may be embodied as any of a variety of non-volatile memory devices, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin torque magnetic RAM (STT-MRAM).

[0160] The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device and form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick Multimedia Card (MMC, RS-MMC or MMCmicro), an SD card (SD, miniSD, microSD or SDHC), a Universal Flash Storage (UFS), etc.

[0161] Fig.14 is a block diagram illustrating an example of a solid state drive (SSD) system 3000 to which a storage device according to an embodiment of the present disclosure is applied.

[0162] refer to Fig.14 , the SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 may exchange a signal SIG with the host 3100 through a signal connector 3001, and may receive power PWR through a power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0163] In one embodiment, the SSD controller 3210 may perform the above reference Figure 1 The functions of the memory controller 200 are described.

[0164] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. According to one embodiment, the signal SIG may be a signal based on an interface of the host 3100 and the SSD 3200. For example, the signal SIG may be defined by at least one of various interfaces, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer mini interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash memory (UFS), a WiFi, a Bluetooth, and a non-volatile memory express (NVMe) interface.

[0165] The auxiliary power supply 3230 may be coupled to the host 3100 through the power connector 3002. The auxiliary power supply 3230 may be powered and charged from the host 3100 through the power PWR. When power cannot be supplied smoothly from the host 3100, the auxiliary power supply 3230 may provide power to the SSD 3200. For example, the auxiliary power supply 3230 may be located inside or outside the SSD 3200. For example, the auxiliary power supply 3230 may be provided in a mainboard and may provide auxiliary power to the SSD 3200.

[0166] The buffer memory 3240 may be used as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include a volatile memory such as DRAM, SDRAM, DDRSDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0167] Fig.15 is a block diagram showing a user system to which a storage device according to one embodiment is applied.

[0168] refer to Fig.15 , the user system 4000 may include an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0169] The application processor 4100 may run components included in the user system 4000, an operating system (OS), or a user program. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. for controlling components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0170] The memory module 4200 may be used as a main memory, a working memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR3 SDRAM, and LPDDR3 SDRAM, or a non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package-on-package (POP) and then provided as a single semiconductor package.

[0171] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth or WiFi communications. For example, the network module 4300 can be included in the application processor 4100.

[0172] The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may transmit data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 may be embodied as a non-volatile semiconductor memory device having a three-dimensional (3D) structure, such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory. For example, the storage module 4400 may be provided as a removable storage medium (i.e., a removable drive), such as a memory card or an external drive of the user system 4000.

[0173] For example, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be configured as described above with reference to Figures 10 to 13 The storage module 4400 can be operated in the same manner as the memory device described above. Figure 1 The storage device 50 operates in the same manner as described.

[0174] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or outputting data to an external device. According to one embodiment, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric device. The user interface 4500 may also include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a display.

[0175] According to one embodiment, a memory device and a method of operating the memory device may provide improved current consumption management performance.

[0176] It will be apparent to those skilled in the art that various modifications may be made to any of the above-described embodiments without departing from the spirit or scope of the present disclosure. Therefore, it is intended that the embodiments cover all such modifications as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A memory device, comprising: a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells; a plurality of peripheral circuits, each peripheral circuit being configured to perform operations on the plurality of memory cell arrays; Multiple control logics, including common control logic and individual control logic; as well as A control logic selector is configured to selectively activate the common control logic but not the individual control logic to control the plurality of peripheral circuits or activate the plurality of control logics including the common control logic and the individual control logic to respectively control the plurality of peripheral circuits according to a type of a command received from a memory controller.

2. The memory device of claim 1, wherein: Each of the individual control logics is configured to control a corresponding peripheral circuit of the plurality of peripheral circuits. 3 . The memory device of claim 2 , further comprising a signal selector that selectively transmits a common control signal generated by the common control logic and individual control signals generated by the individual control logic to the plurality of peripheral circuits. 4 . The memory device of claim 2 , wherein the control logic selector activates the common control logic when the command is a first type of command. 5 . The memory device of claim 4 , wherein the control logic selector deactivates the individual control logic when the command is a command of the first type. 6 . The memory device of claim 5 , wherein the first type of command indicates that the operation is to be performed on the plurality of memory cell arrays simultaneously.

7. The memory device of claim 3 , wherein when the command is a second type of command, the control logic selector activates the common control logic and the individual control logic, and The signal selector selectively provides one of the common control signal generated by the common control logic and the individual control signal generated by the individual control logic to the plurality of peripheral circuits. 8 . The memory device of claim 7 , wherein the second type of command instructs to perform the operations on the plurality of memory cell arrays, respectively.

9. The memory device of claim 1 , further comprising: a command detector that determines a type of the command received from the memory controller; as well as A drive switch selectively provides a drive signal to the plurality of control logics according to the type of the command. 10 . The memory device of claim 9 , wherein the driving signal is at least one of a power signal and a clock signal applied to the plurality of control logics.

11. A method of operating a memory device, the memory device comprising a plurality of peripheral circuits controlling a plurality of memory cell arrays, the method comprising: determining the type of command received from the host; as well as Based on the type of the command, a plurality of control logics including a common control logic and an individual control logic are selectively activated to control the plurality of peripheral circuits or the common control logic is activated but the individual control logic is not activated to control the plurality of peripheral circuits. 12 . The method of claim 11 , wherein the common control logic controls the plurality of peripheral circuits commonly, and the individual control logic controls the plurality of peripheral circuits individually.

13. The method according to claim 12, further comprising: A common control signal generated by the common control logic and individual control signals generated by the individual control logic are selectively transmitted to the plurality of peripheral circuits.

14. The method of claim 12, wherein selectively activating the plurality of control logics comprises: The common control logic is activated and the individual control logic is deactivated in response to information indicating that the command is a command of a first type.

15. The method of claim 14, wherein the first type of command indicates that operations are to be performed simultaneously on the plurality of memory cell arrays.

16. The method of claim 12, wherein selectively activating the plurality of control logics comprises: The common control logic and the individual control logic are activated in response to information indicating that the command is a command of a second type.

17. The method according to claim 16, further comprising: A control signal is provided, the control signal being selected from a common control signal generated by the common control logic and an individual control signal generated by the individual control logic according to the information indicating that the command is a command of the second type.

18. The method of claim 16, wherein the second type of command indicates to perform operations on the plurality of memory cell arrays respectively.

19. The method of claim 11, wherein selectively activating the plurality of control logics comprises: A drive signal is selectively provided to the plurality of control logics. 20 . The method of claim 19 , wherein the driving signal is at least one of a power signal and a clock signal applied to the plurality of control logics.

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