Semiconductor device

Abstract

A semiconductor device includes a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; a first source / drain pattern in a recess in the upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode on a top surface and side surfaces of the first channel pattern, wherein each of the first source / drain pattern includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer provided in the recess in this order, the first channel pattern and each of the first to third semiconductor layers include silicon germanium (SiGe), and the first semiconductor layer has a higher germanium concentration than a germanium concentration of the first channel pattern and a germanium concentration of the second semiconductor layer.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a semiconductor device. BACKGROUND

[0002] Semiconductor devices are considered important elements in the electronic industry due to their small size, multifunctional, and / or low cost characteristics. Semiconductor devices can include, for example, semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including both storage elements and logic elements. As the electronic industry develops, there is an increasing demand for semiconductor devices with improved characteristics. SUMMARY

[0003] Embodiments can be implemented by providing a semiconductor device including a substrate, a first active pattern extending on the substrate in a first direction, an upper portion of the first active pattern including at least one first channel pattern, a first source / drain pattern in a recess in an upper portion of the at least one first channel pattern, and a gate electrode extending on the first active pattern in a second direction crossing the first direction, the gate electrode being on a top surface and at least one side surface of the at least one first channel pattern, wherein each of the first source / drain pattern includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer provided in the recess in sequence, each of the at least one first channel pattern, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes silicon germanium (SiGe), the first semiconductor layer has a higher germanium concentration than a germanium concentration of the at least one first channel pattern and a germanium concentration of the second semiconductor layer.

[0004] Embodiments can be implemented by providing a semiconductor device including a substrate, a first active pattern extending on the substrate in a first direction, a first source / drain pattern in a recess in an upper portion of the first active pattern, and a gate electrode extending on the first active pattern in a second direction crossing the first direction, the gate electrode being on a top surface and at least one side surface of the first active pattern, wherein each of the first source / drain pattern includes a first semiconductor layer and a second semiconductor layer provided in the recess in sequence, the first semiconductor layer has a higher germanium concentration than a germanium concentration of the second semiconductor layer, the first active pattern includes a first channel pattern in an upper portion thereof, the first channel pattern includes a pair of first surfaces facing the first source / drain pattern and a pair of second surfaces connecting the pair of first surfaces to each other and overlapping the gate electrode, the first semiconductor layer includes a first portion on the first surface and a second portion on the second surface.

[0005] Implementations can be realized by providing a semiconductor device including a substrate, a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern, a first source / drain pattern in a recess in the upper portion of the first channel pattern, a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode on a top surface and at least one side surface of the first channel pattern, an active contact electrically connected to the first source / drain pattern, and an interface pattern between the active contact and the first source / drain pattern, wherein each of the first source / drain patterns includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer provided in the recess in order, each of the first channel pattern, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes silicon germanium (SiGe), a germanium concentration of the third semiconductor layer is higher than a germanium concentration of the second semiconductor layer, a germanium concentration of the first semiconductor layer is higher than the germanium concentration of the first channel pattern and the germanium concentration of the second semiconductor layer, the first channel pattern includes a pair of first surfaces opposite to each other and facing the first source / drain pattern, and a pair of second surfaces opposite to each other connecting the pair of first surfaces to each other and overlapping the gate electrode, and the first semiconductor layer includes a first portion on the first surfaces and a second portion on the second surfaces. BRIEF DESCRIPTION OF DRAWINGS

[0006] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of the example implementations in conjunction with the accompanying drawings, of which:

[0007] FIG. 1 A plan view of a semiconductor device according to an embodiment is shown.

[0008] FIGS. 2A-2D Cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of FIG. 1 are shown, respectively.

[0009] FIG. 3 An enlarged cross-sectional view of a region 'M' of FIG. 2A is shown.

[0010] FIG. 4 An enlarged plan view of a region 'N' of FIG. 1 is shown.

[0011] FIG. 5 and FIG. 6 enlarged plan views of the first semiconductor layer and the second semiconductor layer provided in the region 'N' are shown, respectively.

[0012] FIG. 7 A perspective view of the first semiconductor layer is shown.

[0013] FIG. 8 A plan view of FIG. 1A magnified plan view of region 'N'.

[0014] FIG. 9 An enlarged plan view of the first semiconductor layer in region 'N' is shown.

[0015] FIG. 10 , FIG. 13 , FIG. 15 , FIG. 17 , FIG. 19 , FIG. 21 and FIG. 23 A plan view showing a stage in a method for manufacturing a semiconductor device according to one embodiment.

[0016] FIG. 11 , FIG. 12 , FIG. 14A , FIG. 16A , FIG. 18A , FIG. 20A , FIG. 22A and FIG. 24A Showing along FIG. 10 , FIG. 13 , FIG. 15 , FIG. 17 , FIG. 19 , FIG. 21 and FIG. 23 A cross-sectional view taken from line A-A'.

[0017] FIG. 14B , FIG. 16B , FIG. 18B , FIG. 20B , FIG. 22B and FIG. 24B Showing along FIG. 13 , FIG. 15 , FIG. 17 , FIG. 19 , FIG. 21 and FIG. 23 The cross-sectional view taken by line B-B'.

[0018] FIG. 14C , FIG. 16C and FIG. 24C Showing along FIG. 13 , FIG. 15 and FIG. 23 The cross-sectional view taken from line C-C'.

[0019] FIG. 24D Show along FIG. 23 The cross-sectional view taken by line D-D'.

[0020] FIGS. 25A-25D Show along FIG. 1 Cross-sectional views taken along lines A-A', B-B', C-C', and D-D' are used to illustrate a semiconductor device according to one embodiment. DETAILED DESCRIPTION

[0021] FIG. 1 is a plan view of a semiconductor device according to an embodiment. FIGS. 2A-2D is a cross-sectional view taken along FIG. 1 lines A-A', B-B', C-C', and D-D' of FIG. 3 is a plan view of FIG. 2A an enlarged cross-sectional view of a region 'M' of FIG. 4 is a plan view of FIG. 1 an enlarged plan view of a region 'N' of FIG. 5 and FIG. 6 are enlarged plan views respectively showing a first semiconductor layer and a second semiconductor layer provided in the region 'N'. FIG. 7 is a perspective view of the first semiconductor layer.

[0022] Referring to FIG. 1 , FIGS. 2A-2D and FIG. 3 , a substrate 100 including a first active region PR and a second active region NR can be provided. The substrate 100 can be a semiconductor substrate made of, for example, silicon, germanium, silicon germanium, or a compound semiconductor material. In an implementation, the substrate 100 can be a silicon wafer.

[0023] In an implementation, the first active region PR and the second active region NR can be logic cell regions on which logic transistors are to be formed. In an implementation, the logic transistors can constitute a logic circuit of the semiconductor device. In an implementation, the logic transistors constituting the logic circuit can be on the logic cell regions of the substrate 100. The first active region PR and the second active region NR can include some of the logic transistors. The first active region PR can be a PMOSFET region, and the second active region NR can be an NMOSFET region.

[0024] The first active region PR and the second active region NR can be defined (e.g., separated) by a second trench TR2 formed in an upper portion of the substrate 100. The second trench TR2 can be between the first active region PR and the second active region NR. The first active region PR and the second active region NR can be spaced apart from each other in a first direction D1 with the second trench TR2 therebetween. Each of the first active region PR and the second active region NR can extend (e.g., longitudinally) in a second direction D2 that intersects the first direction D1.

[0025] The first active pattern AP1 and the second active pattern AP2 can be on the first active region PR and the second active region NR, respectively. The first active pattern AP1 and the second active pattern AP2 can extend in the second direction D2 (e.g., longitudinally) and can be parallel to each other. The first active pattern AP1 and the second active pattern AP2 can include portions of the substrate 100 that protrude vertically. Each of the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 can be shaped like a fin. The first trench TR1 can be defined between adjacent first active patterns in the first active pattern AP1 and between adjacent second active patterns in the second active pattern AP2. The first trench TR1 can be shallower (e.g., in a vertical direction or third direction D3 relative to an upper surface of the substrate 100) than the second trench TR2.

[0026] Each first active pattern AP1 can include an upper portion, a portion of which is a first channel pattern CH1. The first channel pattern CH1 can be formed of or include a semiconductor material different from the substrate 100. In an implementation, where the substrate 100 is a silicon substrate, the first channel pattern CH1 can be formed of or include silicon germanium. The first channel pattern CH1 can include silicon germanium, and mobility of charges in the first channel pattern CH1 can be improved.

[0027] A lower portion of the first active pattern AP1 (e.g., in the third direction D3) below the first channel pattern CH1 can be a protruding pattern that extends vertically from the substrate 100. In an implementation, the second channel pattern CH2 that is the upper portion of the second active pattern AP2 can be a portion of the substrate 100 and can be formed of or include silicon.

[0028] The device isolation layer ST can fill the first trench TR1 and the second trench TR2. The device isolation layer ST can be formed of or include silicon oxide. The upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 can be protruding patterns (see FIG. 2D ) that extend vertically (e.g., in the third direction D3) beyond the device isolation layer ST. The device isolation layer ST can not cover the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2. The device isolation layer ST can cover side surfaces of the lower portion of the first active pattern AP1 and the lower portion of the second active pattern AP2. In an implementation, the lower portion of the first channel pattern CH1 can be covered by the device isolation layer ST.

[0029] The first source / drain pattern SD1 can be provided in or on an upper portion of the first active pattern AP1. The first source / drain pattern SD1 can be an impurity region of a first conductivity type (e.g., p-type). The first source / drain pattern SD1 can be provided in or on an upper portion of the first channel pattern CH1. The second source / drain pattern SD2 can be provided in or on an upper portion of the second active pattern AP2. The second source / drain pattern SD2 can be an impurity region of a second conductivity type (e.g., n-type). The second channel pattern CH2 can be between each pair of the second source / drain pattern SD2. The second channel pattern CH2 can correspond to an upper portion of the second active pattern AP2.

[0030] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns that can be formed by a selective epitaxial growth (SEG) process. In an implementation, the first source / drain pattern SD1 and the second source / drain pattern SD2 can have a top surface that is coplanar with a top surface of the first channel pattern CH1 and a top surface of the second channel pattern CH2. In an implementation, the top surface of the first source / drain pattern SD1 and the top surface of the second source / drain pattern SD2 can be higher (e.g., in the third direction D3) than the top surface of the first channel pattern CH1 and the top surface of the second channel pattern CH2.

[0031] The first source / drain pattern SD1 can include a semiconductor element (e.g., Ge) that has a lattice constant that is greater than a lattice constant of a semiconductor element (e.g., Si) in the substrate 100. In an implementation, the first source / drain pattern SD1 can be formed of or include silicon germanium. The first source / drain pattern SD1 can exert a compressive stress on the first channel pattern CH1. In an implementation, the second source / drain pattern SD2 can include, for example, the same semiconductor element (e.g., Si) as the substrate 100.

[0032] The gate electrodes GE can cross the first active pattern AP1 and the second active pattern AP2 and extend in the first direction Dl (e.g., longitudinally). The gate electrodes GE can be spaced apart from each other in the second direction D2. When viewed in a plan view, the gate electrodes GE can overlap the first channel pattern CH1 and the second channel pattern CH2. Each gate electrode GE can face a top surface and an opposite side surface of a respective one of the first channel pattern CH1 and the second channel pattern CH2.

[0033] Referring back to FIG. 2DThe gate electrode GE can be on the first top surface TS1 and at least one side surface of the first channel pattern CH1. The gate electrode GE can be on the second top surface TS2 and at least one side surface of the second channel pattern CH2. The transistor according to the present embodiment can be a three-dimensional field effect transistor (e.g., FinFET) in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH2.

[0034] Referring back to FIG. 1 , FIGS. 2A-2D and FIG. 3 , a pair of gate spacers GS can be on two side surfaces of each gate electrode GE. The gate spacer GS can extend along the gate electrode GE and in the first direction D1. A top surface of the gate spacer GS can be higher (e.g., in the third direction D3) than a top surface of the gate electrode GE. The top surface of the gate spacer GS can be coplanar with a top surface of the first interlayer insulating layer 110, which will be described below. The gate spacer GS can be formed of, or include, at least one of SiCN, SiCON, and SiN. In an implementation, the gate spacer GS can be a multi-layer structure including at least two different materials selected from SiCN, SiCON, and SiN. As used herein, the term "at least one of...," and "and / or" mean any and all combinations of one or more of the associated listed items, for example, "A and / or B" will include A, B, or A and B.

[0035] A gate cap pattern GP can be on each gate electrode GE. The gate cap pattern GP can extend along the gate electrode GE and in the first direction D1. The gate cap pattern GP can be formed of, or include, a material having etch selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below. In an implementation, the gate cap pattern GP can be formed of, or include, at least one of SiON, SiCN, SiCON, and SiN.

[0036] A gate dielectric pattern GI can be between the gate electrode GE and the first active pattern API and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI can extend along a bottom surface of the gate electrode GE thereon. In an implementation, the gate dielectric pattern GI can cover the first top surface TS1 and side surfaces of the first channel pattern CH1. The gate dielectric pattern GI can cover the second top surface TS2 and side surfaces of the second channel pattern CH2. The gate dielectric pattern GI can cover a top surface of the device isolation layer ST underneath the gate electrode GE (see, e.g., FIG. 2D ).

[0037] In an implementation, the gate dielectric pattern GI can be formed of or include a high-k dielectric material having a dielectric constant higher than that of a silicon oxide layer. In an implementation, the high-k dielectric material can include, for example, hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead antimony tantalum oxide, and / or lead zinc niobate.

[0038] In an implementation, the gate dielectric pattern GI can be formed of or include a ferroelectric material. The gate dielectric pattern GI including the ferroelectric material can be used as a negative capacitor. The ferroelectric material of the gate dielectric pattern GI can include hafnium oxide containing (or doped with) zirconium (Zr), silicon (Si), aluminum (Al), and / or lanthanum (La).

[0039] The gate electrode GE can include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern can be on the gate dielectric pattern GI and can be adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal pattern can include a work function metal that can help adjust a threshold voltage of the transistor. By adjusting a thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be achieved.

[0040] The first metal pattern can include a metal nitride layer. In an implementation, the first metal pattern can include nitrogen (N) and at least one metal (e.g., titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and / or molybdenum (Mo)). The first metal pattern can also include carbon (C). The first metal pattern can include a plurality of work function metal layers stacked.

[0041] The second metal pattern can include a metallic material having a lower resistivity than the first metal pattern. In an implementation, the second metal pattern can include, for example, tungsten (W), aluminum (Al), titanium (Ti), and / or tantalum (Ta).

[0042] The first semiconductor layer SL1 can be between the gate dielectric pattern GI and the first channel pattern CH1. In an implementation, a second portion P2 of the first semiconductor layer SL1 can be between the gate dielectric pattern GI and the first channel pattern CH1. The second portion P2 of the first semiconductor layer SL1 can cover the first top surface TS1 and the side surface of the first channel pattern CH1, as shown in FIG. 2D The second portion P2 of the first semiconductor layer SL1 can be connected to a first portion PI and a third portion P3 to be described below, as shown in FIG. 7

[0043] ​A first interlayer insulating layer 110 can be on the substrate 100. The first interlayer insulating layer 110 can cover the gate spacers GS and the first and second source / drain patterns SD1 and SD2. A top surface of the first interlayer insulating layer 110 can be substantially coplanar with a top surface of the gate cap pattern GP and a top surface of the gate spacers GS. A second interlayer insulating layer 120 can be on the first interlayer insulating layer 110 to cover the gate cap pattern GP. A third interlayer insulating layer 130 can be on the second interlayer insulating layer 120. In an implementation, the first through third interlayer insulating layers 110, 120, and 130 can be formed of or include silicon oxide.

[0044] The active contacts AC can penetrate the first and second interlayer insulating layers 110 and 120 and can be electrically connected to the first and second source / drain patterns SD1 and SD2, respectively. Each active contact AC can be between a pair of gate electrodes GE.

[0045] The active contacts AC can be self-aligned contacts. In an implementation, the active contacts AC can be formed by a self-alignment process using the gate cap pattern GP and the gate spacers GS. In an implementation, the active contacts AC can cover at least a portion of a side surface of the gate spacers GS. In an implementation, the active contacts AC can cover a portion of a top surface of the gate cap pattern GP.

[0046] The interface patterns SC can be between the active contacts AC and the first source / drain patterns SD1 and between the active contacts AC and the second source / drain patterns SD2. The active contacts AC can be electrically connected to the first source / drain patterns SD1 or the second source / drain patterns SD2 through the interface patterns SC. The interface patterns SC can be formed of or include at least one of metal silicide materials, such as titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0047] The at least one gate contact GC can be on (e.g., above or aligned with) the device isolation layer ST filling the second trench TR2. The gate contact GC can penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and can be electrically connected to the gate electrode GE.

[0048] Each of the active contact AC and the gate contact GC can include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. In an implementation, the conductive pattern FM can be formed of or include a metal (e.g., aluminum, copper, tungsten, molybdenum, and / or cobalt). The barrier pattern BM can cover side surfaces and a bottom surface of the conductive pattern FM. The barrier pattern BM can include a metal layer and / or a metal nitride layer. The metal layer can be formed of or include titanium, tantalum, tungsten, nickel, cobalt, and / or platinum. The metal nitride layer can be formed of or include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and / or platinum nitride (PtN).

[0049] The first interconnect layer can be in the third interlayer insulating layer 130. The first interconnect layer can include a plurality of interconnect lines IL and a plurality of vias VI under the interconnect lines IL. The interconnect lines IL can extend in the second direction D2 (e.g., longitudinally) and can be parallel to each other. The interconnect lines IL can be arranged (e.g., spaced apart) in the first direction D1.

[0050] The via VI can be between a first interconnect line (which is one of the interconnect lines IL) and the active contact AC. The first interconnect line can be electrically connected to the active contact AC through the via VI. The via VI can also be between a second interconnect line (which is another one of the interconnect lines IL) and the gate contact GC. The second interconnect line can be electrically connected to the gate contact GC through the via VI.

[0051] In an implementation, a plurality of interconnect layers can be additionally stacked on the first interconnect layer. The logic units constituting the logic circuit can be connected to each other through the first interconnect layer and the additionally stacked interconnect layers.

[0052] Hereinafter, the first source / drain pattern SD1 will be described in more detail with reference to FIG. 2A , FIG. 2C and FIGS. 3-7 The recess RS can be formed in an upper portion of the first active pattern AP1 (e.g., the first channel pattern CH1). In an implementation, a plurality of recesses RS can be formed in an upper portion of each first channel pattern CH1. The first source / drain pattern SD1 can be provided in the recess RS.

[0053] The first source / drain pattern SD1 can include a buffer layer BL, a main layer ML on the buffer layer BL, and a cap layer CL on the main layer ML. In an implementation, the buffer layer BL can include a first semiconductor layer SL1 and a second semiconductor layer SL2. The main layer ML can include a third semiconductor layer SL3 and a fourth semiconductor layer SL4. The cap layer CL can include a fifth semiconductor layer SL5. In an implementation, the fourth semiconductor layer SL4 can be omitted, and the main layer ML can be composed of a single semiconductor layer. The main layer ML can be on the buffer layer BL and can cover the inner side surfaces of the buffer layer BL. The main layer ML can fill the recess RS (e.g., a remaining portion of the recess RS). The cap layer CL can cover the top surface of the main layer ML. The cap layer CL can be conformally formed on the exposed surfaces of the main layer ML. The cap layer CL can help protect the main layer ML.

[0054] As shown in FIG. 3 , the recess RS can include a pair of inner side surfaces RSw and a bottom surface RSb between the pair of inner side surfaces RSw. The buffer layer BL can cover the inner side surfaces RSw and the bottom surface RSb of the recess RS. When viewed in a cross-sectional view taken along the second direction D2, the buffer layer BL can have a “U”-shaped cross-section.

[0055] Referring to FIG. 2C , FIG. 2D and FIGS. 3-6 , the first channel pattern CH1 can include a pair of first side surfaces SW1 opposite to each other and facing the first source / drain pattern SD1 (see, e.g., FIG. 3 ) and a pair of second side surfaces SW2 opposite to each other connecting the pair of first side surfaces SW1 to each other and overlapping the gate electrode GE (see, e.g., FIG. 2D ). A first portion P1 of the first semiconductor layer SL1 can cover the first side surfaces SW1, and a second portion P2 of the first semiconductor layer SL1 can cover the second side surfaces SW2. In an implementation, four surfaces of the first channel pattern CH1 can be covered by the first semiconductor layer SL1 when viewed in a plan view.

[0056] The first portion P1 of the first semiconductor layer SL1 can be a portion of the first source / drain pattern SD1 and can be in the recess RS. The first portion P1 of the first semiconductor layer SL1 can include opposite side portions SP1 and a bottom portion BP1, as shown in FIG. 7 . The second portion P2 of the first semiconductor layer SL1 can cover a first top surface T1 and the second side surfaces SW2 of the first channel pattern CH1. The second portion P2 of the first semiconductor layer SL1 can include opposite side portions SP2 and a top portion TP. The side portions SP1 of the first portion P1 can be connected to surfaces of the second portion P2 exposed in the second direction D2.

[0057] The first semiconductor layer SL1 may include a third portion P3 extending from the second portion P2 into a region beneath the first portion P1. The third portion P3 may be formed simultaneously with the second portion P2 (as will be described below) and may be a portion retained after the upper part of the first semiconductor layer SL1 has been removed by the recess RS. The third portion P3 may include a side portion SP3 located beneath the first portion P1 and covering the side surface of the first channel pattern CH1. In one implementation, the third portion P3 may be omitted.

[0058] like FIG. 5 As shown, the first thickness t1 of the first portion P1 (in the second direction D2) can be greater than the second thickness t2 of the second portion P2 (in the first direction D1). In one implementation, the first thickness t1 can be about 1.1 to 3 times the second thickness t2. In another implementation, the first thickness t1 can be substantially equal to the second thickness t2. The third thickness t3 of the third portion P3 (in the first direction D1) can be substantially equal to the second thickness t2. Each of the first to third thicknesses t1, t2, and t3, and the fourth thickness described below, can be the maximum thickness of the corresponding layer or portion.

[0059] The first semiconductor layer SL1 may include multiple portions, which are spaced apart and provided separately on a first channel pattern CH1 spaced apart from each other along a first direction D1. In one implementation, first portions P1 on the first channel patterns CH1 that are adjacent to each other along the first direction D1 may be spaced apart from each other.

[0060] A second semiconductor layer SL2 may be provided on each first portion P1 of the first semiconductor layer SL1. In one implementation, the second semiconductor layer SL2 may include a plurality of portions spaced apart and provided separately on a first channel pattern CH1 spaced apart from each other along a first direction D1. The second semiconductor layer SL2 may include a side portion SP4 on a side portion SP1 of the first portion P1 of the first semiconductor layer SL1 and a bottom portion BP2 on a bottom portion BP1 of the first portion P1 of the first semiconductor layer SL1.

[0061] like FIG. 3 and FIG. 6As shown, the fourth thickness t4 of the second semiconductor layer SL2 (in the second direction D2) can be greater than the first thickness t1 of the first portion P1 of the first semiconductor layer SL1. In one implementation, the fourth thickness t4 can be about two to seven times the first thickness t1. In one implementation, the first thickness t1 can be in the range of about 1 nm to about 5 nm, and the fourth thickness t4 can be in the range of about 3 nm to about 9 nm. The thickness of the first semiconductor layer SL1 can be adjusted by a thermal processing process described below. Keeping the first thickness t1 at about 1 nm or greater can help prevent impurity diffusion problems described below. Keeping the first thickness t1 at about 5 nm or less can help reduce the likelihood and / or prevent stacking faults from occurring between the first semiconductor layer SL1 and the first channel pattern CH1 or between the first semiconductor layer SL1 and the second semiconductor layer SL2.

[0062] like FIG. 4 As shown, the third semiconductor layer SL3 can be a single layer covering the first semiconductor layer SL1, specifically the first portions P1 that are spaced apart from each other in the first direction D1. Similarly, the second semiconductor layer SL2, spaced apart from each other in the first direction D1, can share contact with the third semiconductor layer SL3. In one implementation, the first portions P1, which are separately provided on the first channel pattern CH1 spaced apart from each other along the first direction D1, can be connected to the third semiconductor layer SL3 via the second semiconductor layer SL2. The fifth thickness t5 of the third semiconductor layer SL3 (in the second direction D2) can be greater than the fourth thickness t4 of the second semiconductor layer SL2. In one implementation, the fifth thickness t5 of the third semiconductor layer SL3 can be in the range of 20 nm to 40 nm.

[0063] Each of the first channel pattern CH1, the buffer layer BL, and the main layer ML may include a semiconductor element whose lattice constant is greater than that of the semiconductor element of the substrate 100. In one implementation, if the substrate 100 comprises silicon (Si), the first channel pattern CH1, the buffer layer BL, and the main layer ML may include silicon germanium (SiGe). The lattice constant of germanium (Ge) may be greater than that of silicon (Si).

[0064] The germanium concentration of the second semiconductor layer SL2 can be higher than the germanium concentration of the first channel pattern CH1. The germanium concentration of the third semiconductor layer SL3 can be higher than the germanium concentration of the second semiconductor layer SL2. In an implementation, the germanium concentration of the third semiconductor layer SL3 can be higher than the germanium concentration of the first semiconductor layer SL1. The germanium concentration of the fourth semiconductor layer SL4 can be higher than the germanium concentration of the third semiconductor layer SL3. The germanium concentration of the first semiconductor layer SL1 can be higher than the germanium concentration of the first channel pattern CH1 and the germanium concentration of the second semiconductor layer SL2. The germanium concentration of the first semiconductor layer SL1 can be lower than the germanium concentration of the third semiconductor layer SL3. The concentration of germanium (Ge) in the main layer ML can increase in the third direction D3.

[0065] The germanium concentration of the first channel pattern CH1 can be in a range from, for example, about 15 at% to about 30 at%. The germanium concentration of the first semiconductor layer SL1 can be in a range from, for example, about 30 at% to about 50 at%. The germanium concentration of the second semiconductor layer SL2 can be in a range from, for example, about 20 at% to about 30 at%. The germanium concentration of the third semiconductor layer SL3 can be in a range from, for example, about 45 at% to about 60 at%. The germanium concentration of the fourth semiconductor layer SL4 can be in a range from, for example, about 50 at% to about 70 at%.

[0066] The portion of the first channel pattern CH1 that contacts the first semiconductor layer SL1 (e.g., the portion adjacent to or at the surface of the first channel pattern CH1) can have a lower germanium concentration than other portions of the first channel pattern CH1. Both the first portion PI and the second portion P2 of the first semiconductor layer SL1 can have a higher germanium concentration than the germanium concentration of the first channel pattern CH1 and the germanium concentration of the second semiconductor layer SL2. The first portion PI and the second portion P2 of the first semiconductor layer SL1 can have substantially the same germanium concentration. In an implementation, the first portion PI and the second portion P2 of the first semiconductor layer SL1 can have different germanium concentrations from each other. In an implementation, the germanium concentration of the first portion PI of the first semiconductor layer SL1 can be higher than the germanium concentration of the second portion P2 of the first semiconductor layer SL1.

[0067] The buffer layer BL and the main layer ML can include impurities (e.g., boron) that allow the first source / drain pattern SD1 to have p-type conductivity. The concentration (e.g., atomic percent) of the impurities in the main layer ML can be higher than the concentration of the impurities (e.g., atomic percent) in the buffer layer BL.

[0068] The fifth semiconductor layer SL5 (of the cap layer CL) can include the same semiconductor element as in the substrate 100. As an example, the fifth semiconductor layer SL5 can include single crystalline silicon (Si). The concentration of silicon (Si) in the fifth semiconductor layer SL5 can be in a range from 95 at% to 100 at%. The concentration of germanium (Ge) in the fifth semiconductor layer SL5 can be in a range from 0 at% to 5 at%. In an implementation, the germanium (Ge) in the fourth semiconductor layer SL4 can diffuse into the fifth semiconductor layer SL5, in which case the fifth semiconductor layer SL5 can contain a trace amount of germanium (Ge) (e.g., less than 5 at%).

[0069] Further referring to FIG. 2C , the main layer ML can be on the plurality of first active patterns AP1. In an implementation, the plurality of main layers ML on the plurality of first active patterns AP1, respectively, can merge to form a single main layer ML on the plurality of first active patterns AP1.

[0070] The main layer ML can include a first facet FA1, a second facet FA2, a third facet FA3, and a fourth facet FA4. The first to fourth facets FA1-FA4 can be surfaces of the third semiconductor layer SL3. The first to fourth facets FA1-FA4 can be substantially the same crystal facet. The first to fourth facets FA1-FA4 can be (111) crystal facets.

[0071] A corner SE of the main layer ML can be defined by the first facet FA1 and the second facet FA2 and / or by the third facet FA3 and the fourth facet FA4. The corner SE can horizontally protrude in a direction away from the first active pattern AP1. In an implementation, the corner SE can protrude in a direction parallel to the first direction D1.

[0072] The cap layer CL can be on the main layer ML. The cap layer CL can cover the first to fourth facets FA1-FA4 of the main layer ML. The cap layer CL can cover the corner SE of the main layer ML. The first source / drain pattern SD1 can have a maximum width in the first direction D1 at a height of the corner SE of the main layer ML.

[0073] The interface pattern SC and the active contact AC can be on the first source / drain pattern SD1. In an implementation, the interface pattern SC can not only contact the top surface of the main layer ML but also contact the top surface of the cap layer CL. In an implementation, due to the cap layer CL, the contact area between the first source / drain pattern SD1 and the interface pattern SC can be increased.

[0074] FIG. 8 is an enlarged plan view showing a region ‘N’ of FIG. 1 according to another embodiment. FIG. 9is an enlarged plan view showing the first semiconductor layer in the region 'N'. For the sake of brief description, the previously described elements can be identified by the same reference numerals without repeating the repetitive description thereof.

[0075] Referring to FIG. 8 and FIG. 9 , the first semiconductor layer SL1 according to the present embodiment can include the first portion P1, and can not include the second portion P2 and the third portion P3. The first portion P1 of the first semiconductor layer SL1 can cover the first side surface SW1 of the first channel pattern CH1. In an implementation, the first semiconductor layer SL1 can not be provided on the second side surface SW2 of the first channel pattern CH1, and the second side surface SW2 of each first channel pattern CH1 can be in contact with the gate insulating pattern GI. In an implementation, the first semiconductor layer SL1 can include the second portion P2 and the third portion P3, but can not include the first portion P1.

[0076] In an implementation, the first semiconductor layer SL1 having a relatively high germanium concentration can be between the first channel pattern CH1 and the second semiconductor layer SL2. Diffusion of impurities (e.g., boron) in the first source / drain pattern SD1 into the first channel pattern CH1 can be prevented, thereby improving the operating characteristics of the semiconductor device.

[0077] FIG. 10 , FIG. 13 , FIG. 15 , FIG. 17 , FIG. 19 , FIG. 21 and FIG. 23 are plan views showing stages in a method of manufacturing a semiconductor device according to an embodiment. FIG. 11 , FIG. 12 , FIG. 14A , FIG. 16A , FIG. 18A , FIG. 20A , FIG. 22A and FIG. 24A are cross-sectional views taken along lines FIG. 10 , FIG. 13 , FIG. 15 , FIG. 17 , FIG. 19 , FIG. 21 and FIG. 23 , respectively. FIG. 14B , FIG. 16B , FIG. 18B , FIG. 20B , FIG. 22B and FIG. 24B are cross-sectional views taken along lines FIG. 13 , FIG. 15 , FIG. 17 , FIG. 19 , FIG. 21and FIG. 23 The cross-sectional view taken by line B-B'. FIG. 14C , FIG. 16C and FIG. 24C They are respectively along FIG. 13 , FIG. 15 and FIG. 23 The cross-sectional view taken from line C-C'. FIG. 24D It is along FIG. 23 The cross-sectional view taken by line D-D'.

[0078] Reference FIG. 10 and FIG. 11 A substrate 100 may be provided, comprising a first active region PR and a second active region NR. A substrate layer may be provided on the first active region PR, wherein the substrate layer may be formed of a semiconductor material different from that of the substrate 100, or may comprise a semiconductor material different from that of the substrate 100. In one implementation, the substrate layer may be a silicon-germanium layer. In one implementation, the substrate layer may be formed to fill a recessed region, which may be formed in the first active region PR of the substrate 100 by etching the first active region PR.

[0079] The substrate 100 and the base layer can be patterned to form a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 can be formed on a first active region PR, and the second active pattern AP2 can be formed on a second active region NR. The base layer can be patterned to form a first channel pattern CH1. A first trench TR1 can be formed between the first active patterns AP1 and between the second active patterns AP2.

[0080] The substrate 100 may be patterned to form a second trench TR2 between the first active region PR and the second active region NR. The second trench TR2 may be formed to be deeper than the first trench TR1.

[0081] Reference FIG. 10 and FIG. 12 A device isolation layer ST can be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. The device isolation layer ST can be formed of or include an insulating material (e.g., silicon oxide). In one implementation, the device isolation layer ST may include a liner insulating layer conformally formed along the first trench TR1 and the second trench TR2. The device isolation layer ST can be recessed to expose the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2. The upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 may protrude beyond the device isolation layer ST in a vertical direction (e.g., third direction D3).

[0082] The forming of the device isolation layer ST can include performing an annealing process at least once. The annealing process can be performed at a temperature from about 700 °C to about 900 °C. As a result of the annealing process, a first semiconductor layer SL1 (e.g., a second portion P2) can be formed on a surface of the first channel pattern CH1. The second portion P2 can have a germanium concentration from about 30 at% to about 50 at%. The second portion P2 can be formed by a germanium migration phenomenon in which germanium atoms migrate toward the surface of the first channel pattern CH1 at a high temperature. The germanium migration phenomenon can be caused by a difference in diffusion speed between germanium and silicon at a high temperature. A third portion of the first semiconductor layer SL1 can also be manufactured in this step.

[0083] In the embodiments described with reference to FIG. 8 and FIG. 9 , the forming of the second portion P2 and the third portion P3 can be omitted. In an implementation, the annealing process can be omitted, or the temperature or process time of the annealing process can be adjusted such that the second portion P2 and the third portion P3 are not formed. In the following, embodiments of FIG. 1 and FIGS. 2A-2D will be described.

[0084] With reference to FIG. 13 and FIGS. 14A-C , the sacrificial pattern PP can be formed to cross the first active pattern AP1 and the second active pattern AP2. The sacrificial pattern PP can be formed to have a linear or strip shape extending in the first direction D1. In an implementation, the forming of the sacrificial pattern PP can include forming a sacrificial layer on the substrate 100, forming a hard mask pattern MA on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MA as an etching mask. The sacrificial layer can include a polysilicon layer.

[0085] A pair of gate spacers GS can be formed on two side surfaces of each of the sacrificial patterns PP. The gate spacers GS can also be formed on two side surfaces of each of the first active pattern AP1 and the second active pattern AP2. The two side surfaces of each of the first active pattern AP1 and the second active pattern AP2 can be portions that are not covered by the device isolation layer ST and the sacrificial pattern PP and are exposed.

[0086] The forming of the gate spacers GS can include conformally forming a gate spacer layer on the substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer can be formed of or include SiCN, SiCON, and / or SiN. In an implementation, the gate spacer layer can be a multi-layer structure including at least two of SiCN, SiCON, and SiN.

[0087] With reference to FIG. 15 and FIGS. 16A-CA recess RS can be formed in an upper portion of each of the first active pattern AP1 and the second active pattern AP2. A pair of recesses RS can be formed on both sides of each of the sacrificial patterns PP. The formation of the recess RS can include etching the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 using the hard mask pattern MA and the gate spacers GS as etch masks. During the etching process, the gate spacers GS can be removed from two side surfaces of each of the first active pattern AP1 and the second active pattern AP2. The gate spacers GS can be partially left on side surfaces of the recess RS. The exposed portions of the device isolation layer ST can be recessed during the etching process.

[0088] The first mask layer MP can be formed to selectively cover the second active pattern AP2. The first mask layer MP can selectively cover the second active region NR and can expose the first active region PR. The first mask layer MP can expose the first active pattern AP1.

[0089] Referring to FIG. 17 and FIGS. 18A-B A first semiconductor layer SL1 (e.g., a first portion P1) can be formed in the recess RS. The first portion P1 can be doped to contain a low concentration of impurities. In an implementation, the first portion P1 can be formed of or include boron-doped silicon germanium. The first portion P1 can be formed by a hydrogen (H2) bake process, which can be performed for a pre-cleaning process of a surface of the recess RS. In an implementation, the bake process can be performed at a temperature from about 700 °C to about 900 °C. The first portion P1 can be formed by a germanium migration phenomenon in which germanium atoms migrate toward a surface of the first channel pattern CH1 at a high temperature. In an implementation, the first portion P1 can be formed to a thickness from about 1 nm to about 5 nm. The germanium concentration of the first portion P1 can be in a range from about 30 at% to about 50 at%. The first portion P1 can be connected to the second portion P2 and the third portion P3. In an implementation, the bake process can be omitted, and the first portion P1 can not be provided.

[0090] Referring to FIG. 19 and FIGS. 20A-B The second semiconductor layer SL2 can be formed in the recess RS to cover the first portion P1 (of the first semiconductor layer SL1). The second semiconductor layer SL2 can be doped to have a low concentration of impurities. In an implementation, the second semiconductor layer SL2 can be formed of or include boron-doped silicon germanium.

[0091] Formation of the second semiconductor layer SL2 can include performing a first SEG process using the first portion Pl as a seed layer. In an implementation, the first SEG process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. In an implementation, the second semiconductor layer SL2 can have a convex cross-sectional shape, as shown in FIG. 20B . The second semiconductor layer SL2 can be formed to have a substantially conformal profile. The germanium concentration of the second semiconductor layer SL2 can be in a range from about 20 at% to about 30 at%. The second semiconductor layer SL2 can be formed to a thickness from about 3 nm to about 9 nm.

[0092] Referring to FIG. 21 , FIG. 22A and FIG. 22B , a main layer ML and a cap layer CL can be formed on the second semiconductor layer SL2. The main layer ML can be doped to have a higher impurity concentration than the impurity concentration of the buffer layer BL. In an implementation, the main layer ML can be formed of or include a silicon germanium (SiGe) layer doped with boron (B). In an implementation, a third semiconductor layer SL3, a fourth semiconductor layer SL4, and a fifth semiconductor layer SL5 can be formed in sequence on the second semiconductor layer SL2.

[0093] The main layer ML can be formed by a second SEG process in which the buffer layer BL is used as a seed layer. The cap layer CL can be formed by a third SEG process in which the main layer ML is used as a seed layer. In an implementation, the cap layer CL can include single crystalline silicon (Si). The concentration of silicon (Si) in the cap layer CL can be in a range from 95 at% to 100 at%. In an implementation, the third SEG process can be performed at a lower temperature than the temperatures used for the first SEG process and the second SEG process. The germanium concentration of the third semiconductor layer SL3 can be in a range from about 45 at% to about 60 at%. The germanium concentration of the fourth semiconductor layer SL4 can be in a range from about 50 at% to about 70 at%.

[0094] Referring to FIG. 23 and FIGS. 24A-D , the first mask layer MP can be removed. A second mask layer can be formed to selectively cover the first active pattern AP1. The second mask layer can selectively cover the first active region PR and can expose the second active region NR. The second mask layer can expose the second active pattern AP2.

[0095] The second source / drain pattern SD2 can be formed to fill the recesses RS of the second active pattern AP2 exposed by the second mask layer. For example, the formation of the second source / drain pattern SD2 can include performing a SEG process using the exposed inner side surfaces of the recesses RS as seed layers. The second source / drain pattern SD2 can contain the same semiconductor element (e.g., silicon (Si)) as the semiconductor element in the substrate 100. Thereafter, the second mask layer can be removed.

[0096] The first interlayer insulating layer 110 can be formed to cover the first source / drain pattern SD1 and the second source / drain pattern SD2, the gate spacers GS, and the hard mask pattern MA. The first interlayer insulating layer 110 can be formed of or include silicon oxide.

[0097] A planarization process can be performed on the first interlayer insulating layer 110 to expose the top surfaces of the sacrificial patterns PP. The planarization of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. Accordingly, the first interlayer insulating layer 110 can have a top surface that is coplanar with the top surfaces of the sacrificial patterns PP and the top surfaces of the gate spacers GS.

[0098] Each of the sacrificial patterns PP can be replaced with a gate electrode GE and a gate dielectric pattern GI. In an implementation, the exposed sacrificial patterns PP can be selectively removed to form empty spaces. The gate dielectric pattern GI can be formed in the empty spaces formed by the removal of the sacrificial patterns PP. The gate electrode GE can be formed on the gate dielectric pattern GI to fill the empty spaces.

[0099] The gate dielectric pattern GI can be conformally formed by an atomic layer deposition (ALD) and / or a chemical oxidation process. In an implementation, the gate dielectric pattern GI can be formed of or include a high-k dielectric material. In an implementation, the gate dielectric pattern GI can be formed of or include a ferroelectric material.

[0100] The formation of the gate electrode GE can include forming a gate electrode layer on the gate dielectric pattern GI and planarizing the gate electrode layer. In an implementation, the gate electrode layer can include a first gate electrode layer including a metal nitride and a second gate electrode layer including a low resistivity metal.

[0101] The upper portion of the gate electrode GE can be selectively etched to recess the gate electrode GE. The recessed top surface of the gate electrode GE can be lower than the top surface of the first ILD layer 110 and the top surface of the gate spacer GS. A gate cap pattern GP can be formed on the recessed gate electrode GE. The formation of the gate cap pattern GP can include forming a gate cap layer to cover the recessed gate electrode GE and planarizing the gate cap layer to expose the top surface of the first ILD layer 110. In an implementation, the gate cap layer can be formed of or include SiON, SiCN, SiCON, and / or SiN.

[0102] Referring back to FIG. 1 and FIGS. 2A-2D , a second ILD layer 120 can be formed on the first ILD layer 110. An active contact AC can be formed to penetrate the second ILD layer 120 and the first ILD layer 110 and electrically connect to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A gate contact GC can be formed to penetrate the second ILD layer 120 and the gate cap pattern GP and electrically connect to the gate electrode GE. The formation of the active contact AC and the gate contact GC can include forming a barrier pattern BM to fill the contact hole and forming a conductive pattern FM on the barrier pattern BM.

[0103] An interface pattern SC can be formed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. The formation of the interface pattern SC can include performing a silicidation process on the first source / drain pattern SD1 and the second source / drain pattern SD2. In an implementation, the interface pattern SC can be formed of or include titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and / or cobalt silicide.

[0104] A third ILD layer 130 can be formed on the second ILD layer 120. A first interconnect layer can be formed in the third ILD layer 130. The formation of the first interconnect layer can include forming an interconnect line IL and a via VI under the interconnect line IL. The interconnect line IL and the via VI can be formed by a damascene process or a dual damascene process.

[0105] FIGS. 25A-D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of FIG. 1 , respectively, to show a semiconductor device according to an embodiment. In the following description, for the sake of brevity, elements previously described with reference to FIG. 1 , FIGS. 2A-2D and FIG. 3 may be identified by the same reference numerals as those described previously without repeating their redundant description.

[0106] Referring to FIG. 1 and FIGS. 25A-D A substrate 100 including a first active region PR and a second active region NR can be provided. A device isolation layer ST can be on the substrate 100. The device isolation layer ST can define a first active pattern AP1 and a second active pattern AP2 in an upper portion of the substrate 100. The first active pattern AP1 and the second active pattern AP2 can be defined on the first active region PR and the second active region NR, respectively.

[0107] Each first active pattern AP1 can include a plurality of first channel patterns CH1 stacked vertically on the substrate 100. The stacked plurality of first channel patterns CH1 can be spaced apart from each other in a third direction D3. When viewed in a plan view, the stacked plurality of first channel patterns CH1 can overlap each other.

[0108] Each second active pattern AP2 can include a plurality of second channel patterns CH2 stacked vertically on the substrate 100. The stacked plurality of second channel patterns CH2 can be spaced apart from each other in the third direction D3. When viewed in a plan view, the stacked plurality of second channel patterns CH2 can overlap each other. The first channel pattern CH1 can be formed of or include a semiconductor material different from the substrate 100. For example, in a case where the substrate 100 is a silicon substrate, the first channel pattern CH1 can be formed of or include silicon germanium. The second channel pattern CH2 can be formed of or include a same material (e.g., silicon (Si)) as the substrate 100.

[0109] A first source / drain pattern SD1 can penetrate at least a portion of the first channel pattern CH1. A recess RS can penetrate at least a portion of the first channel pattern CH1, and the first source / drain pattern SD1 can fill the recess RS, respectively. The stacked plurality of first channel patterns CH1 can connect an adjacent pair of first source / drain patterns SD1 to each other. The first source / drain pattern SD1 according to the present embodiment can be configured to have substantially the same features as those in the previous embodiments.

[0110] A second source / drain pattern SD2 can penetrate at least a portion of the second channel pattern CH2. The stacked plurality of second channel patterns CH2 can connect an adjacent pair of second source / drain patterns SD2 to each other. The second source / drain pattern SD2 according to the present embodiment can be configured to have substantially the same features as those in the previous embodiments.

[0111] The gate electrode GE can cross the first and second channel patterns CH1 and CH2 and can extend in the first direction D1. When viewed in a plan view, the gate electrode GE can overlap the first and second channel patterns CH1 and CH2. A pair of gate spacers GS can be on two side surfaces of the gate electrode GE. A gate cap pattern GP can be provided on the gate electrode GE.

[0112] The gate electrode GE can surround each of the first and second channel patterns CH1 and CH2 (see, for example, FIG. 25D ). The gate electrode GE can be on the first top surface TS1, at least one side surface, and the first bottom surface BS1 of the first channel pattern CH1. The gate electrode GE can be on the second top surface TS2, at least one side surface, and the second bottom surface BS2 of the second channel pattern CH2. In an implementation, the gate electrode GE can surround the top surface, the bottom surface, and the opposite side surfaces of each of the first and second channel patterns CH1 and CH2. The transistor according to the present embodiment can be a three-dimensional field effect transistor (e.g., a multi-bridge channel field effect transistor (MBCFET)) in which the gate electrode GE is provided to surround the first and second channel patterns CH1 and CH2 three-dimensionally.

[0113] The gate dielectric pattern GI can be between each of the first and second channel patterns CH1 and CH2 and the gate electrode GE. The gate dielectric pattern GI can surround each of the first and second channel patterns CH1 and CH2.

[0114] The first source / drain pattern SD1 can include the first semiconductor layer SL1, and a first portion P1 of the first semiconductor layer SL1 can cover the first side surface SW1 (see, for example, FIG. 25A and FIG. 25C ). The first portion P1 can have substantially the same shape as in the previous embodiments. The first semiconductor layer SL1 can be between the gate dielectric pattern GI and the first channel pattern CH1. In an implementation, a second portion P2 of the first semiconductor layer SL1 can be between the gate dielectric pattern GI and the first channel pattern CH1. The second portion P2 of the first semiconductor layer SL1 can cover the second side surface SW2 of the first channel pattern CH1, as shown in FIG. 25D Unlike the previous embodiments, the second portion P2 can not be provided on the first top surface TS1 of the first channel pattern CH1. In an implementation, referring back to FIG. 7 , the second portion P2 according to the present embodiment can include two opposite side portions SP2 and can not have a top portion TP. The third portion P3 can have the same structure as in the previous embodiments. In an implementation, as in referring to FIG. 8 and FIG. 9As in the described embodiments, the second portion P2 and the third portion P3 can be omitted.

[0115] On the second active region NR, an insulating pattern IP can be between the gate dielectric pattern GI and the second source / drain pattern SD2. The gate electrode GE can be spaced apart from the second source / drain pattern SD2 by the gate dielectric pattern GI and the insulating pattern IP. In an implementation, the insulating pattern IP can be omitted on the first active region PR.

[0116] A first interlayer insulating layer 110 and a second interlayer insulating layer 120 can be on the substrate 100. An active contact AC can penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A gate contact GC can penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and be connected to the gate electrode GE.

[0117] A third interlayer insulating layer 130 can be on the second interlayer insulating layer 120. A first interconnect layer including interconnect lines IL and vias VI can be in the third interlayer insulating layer 130.

[0118] By summarizing and reviewing, it can be desirable for a semiconductor device to have high reliability, high performance, and / or multifunctionality. It can be considered to increase complexity and / or integration density of a semiconductor device.

[0119] One or more embodiments can provide a semiconductor device including a field effect transistor.

[0120] One or more embodiments can provide a semiconductor device having improved electrical characteristics.

[0121] According to an embodiment, it can be helpful to prevent impurities in a source / drain pattern from diffusing into a channel pattern, thereby improving operating characteristics of a semiconductor device.

[0122] Example embodiments have been disclosed herein and, although a particular terminology is employed, it is understood that the terminology is used in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, attributes and / or benefits from differing embodiments can be incorporated into an embodiment and / or method to form an additional embodiment that is not explicitly described herein. In addition, features, attributes and / or benefits from some embodiments can be incorporated into other embodiments as appropriate and desired. It will be appreciated that many modifications and variations of the examples described herein are possible, and the terms used herein have been selected for the purpose of clarity of description and example, and not for purposes of limitation of the example embodiments. Therefore, the examples are not limited to the specific examples described herein, but include any and all implementations falling within the scope of the appended claims.

[0123] Korean Patent Application No. 10-2019-0130171, filed on October 18, 2019, in the Korean Intellectual Property Office and entitled "Semiconductor Device," is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device comprising: a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including at least one first channel pattern; a first source / drain pattern in a recess in an upper portion of the at least one first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode on a top surface and at least one side surface of the at least one first channel pattern, wherein: each of the first source / drain pattern includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer provided in the recess in order, each of the at least one first channel pattern, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes silicon germanium (SiGe), and the first semiconductor layer has a higher germanium concentration than a germanium concentration of the at least one first channel pattern and a germanium concentration of the second semiconductor layer, wherein the at least one first channel pattern includes a pair of first surfaces opposite to each other in the first direction and facing the first source / drain pattern, and a pair of second surfaces opposite to each other in the second direction connecting the pair of first surfaces to each other and overlapping the gate electrode, the first semiconductor layer includes a first portion on the first surfaces and a second portion on the second surfaces, the at least one first channel pattern includes a plurality of first channel patterns spaced apart from each other in the second direction, the first portions of the first semiconductor layer are separately provided on the plurality of first channel patterns, and the third semiconductor layer is a single layer covering the first portions of the first semiconductor layer spaced apart from each other in the second direction.

2. The semiconductor device of claim 1, wherein the second semiconductor layer includes a plurality of portions separately provided on the first portions of the first semiconductor layer and spaced apart from each other.

3. The semiconductor device of claim 1, wherein the first semiconductor layer further includes a third portion extending to an area under the first portions of the first semiconductor layer to contact a bottom surface of the first portions of the first semiconductor layer.

4. The semiconductor device of claim 1, wherein the first portions of the first semiconductor layer have different thicknesses from the second portions of the first semiconductor layer.

5. The semiconductor device of claim 1, wherein the second portions of the first semiconductor layer cover a top surface of the at least one first channel pattern.

6. The semiconductor device of claim 1, wherein: the first semiconductor layer is thinner than the second semiconductor layer, and the second semiconductor layer is thinner than the third semiconductor layer.

7. The semiconductor device of claim 6, wherein a thickness of the second semiconductor layer is two to seven times a thickness of the first semiconductor layer.

8. The semiconductor device of claim 6, wherein: a thickness of the first semiconductor layer is in a range from 1 nm to 5 nm, and a thickness of the second semiconductor layer is in a range from 5 nm to 15 nm. The second semiconductor layer has a thickness in a range from 3 nm to 9 nm.

9. The semiconductor device of claim 1, wherein: each of the first source / drain patterns further includes a fourth semiconductor layer on the third semiconductor layer, and the fourth semiconductor layer has a germanium concentration higher than a germanium concentration of the third semiconductor layer.

10. The semiconductor device of claim 1, wherein: the first active pattern is on a first active region of the substrate, the semiconductor device further includes: a second active pattern on a second active region of the substrate and extending in the first direction; and a second source / drain pattern in a recess in an upper portion of the second active pattern, the first active region is a PMOSFET region, and the second active region is an NMOSFET region.

11. The semiconductor device of claim 1, wherein: the at least one first channel pattern includes a plurality of first channel patterns, the plurality of first channel patterns being sequentially stacked on the substrate, and the gate electrode surrounds a top surface, a bottom surface, and two side surfaces of each of the plurality of first channel patterns.

12. A semiconductor device, comprising: a substrate; a first active pattern on the substrate and extending in a first direction; a first source / drain pattern in a recess in an upper portion of the first active pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and at least one side surface of the first active pattern, wherein: each of the first source / drain patterns includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer provided in the recess in sequence, the first semiconductor layer has a germanium concentration higher than a germanium concentration of the second semiconductor layer, the first active pattern includes a first channel pattern in an upper portion thereof, the first channel pattern includes a pair of first surfaces opposite to each other in the first direction and facing the first source / drain pattern, and a pair of second surfaces opposite to each other in the second direction, connecting the pair of first surfaces to each other and overlapping the gate electrode, and the first semiconductor layer includes a first portion on the first surfaces and a second portion on the second surfaces, the first channel pattern includes a plurality of first channel patterns spaced apart from each other in the second direction, the first portions of the first semiconductor layer are provided separately on the plurality of first channel patterns, and the third semiconductor layer is a single layer covering the first portions of the first semiconductor layer spaced apart from each other in the second direction.

13. The semiconductor device of claim 12, wherein: the first channel pattern includes silicon germanium (SiGe), and the germanium concentration of the first semiconductor layer is higher than a germanium concentration of the first channel pattern.

14. The semiconductor device of claim 12, wherein: the first semiconductor layer is thinner than the second semiconductor layer, and the second semiconductor layer is thinner than the third semiconductor layer. ​ 15. The semiconductor device of claim 14, wherein: each of the first source / drain patterns further includes a fourth semiconductor layer on the third semiconductor layer, and the fourth semiconductor layer has a higher germanium concentration than the third semiconductor layer.

16. The semiconductor device of claim 12, wherein: the first active pattern is on a first active region of the substrate, the semiconductor device further includes: a second active pattern on a second active region of the substrate to extend in the first direction; and a second source / drain pattern in a recess in an upper portion of the second active pattern, the first active region is a PMOSFET region, and the second active region is an NMOSFET region.

17. A semiconductor device, comprising: a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; a first source / drain pattern in a recess in an upper portion of the first channel pattern; a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode on a top surface and at least one side surface of the first channel pattern; an active contact electrically connected to the first source / drain pattern; and an interface pattern between the active contact and the first source / drain pattern, wherein: each of the first source / drain patterns includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer provided in the recess in that order, each of the first channel pattern, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes silicon germanium (SiGe), the third semiconductor layer has a higher germanium concentration than the second semiconductor layer, the first semiconductor layer has a higher germanium concentration than the germanium concentration of the first channel pattern and the germanium concentration of the second semiconductor layer, the first channel pattern includes a pair of first surfaces opposite to each other in the first direction and facing the first source / drain pattern, and a pair of second surfaces opposite to each other in the second direction, connecting the pair of first surfaces to each other and overlapping the gate electrode, and the first semiconductor layer includes a first portion on the first surfaces and a second portion on the second surfaces, the first channel pattern includes a plurality of first channel patterns spaced apart from each other in the second direction, the first portions of the first semiconductor layer are provided separately and respectively on the plurality of first channel patterns, and the third semiconductor layer is a single layer covering the first portions of the first semiconductor layer spaced apart from each other in the second direction. ​

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