Debounce circuit with noise immunity and glitch event tracking

Abstract

A de-jitter circuit and method for masking or filtering glitches from an input signal are provided. The de-jitter circuit includes a reset synchronizer circuit and a logic circuit. The reset synchronizer circuit receives an input signal, detects glitches in the input signal, and outputs one or more reset synchronizer output signals, the one or more reset synchronizer output signals having a first reset synchronizer state indicating that a glitch has been detected. The logic circuit receives the one or more reset synchronizer output signals, determines that the one or more reset synchronizer output signals are in the first reset synchronizer state indicating that a glitch has been detected, and in response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer state, maintains the output signal of the de-jitter circuit in the current state of the output signal of the de-jitter circuit.

Description

Technical Field

[0001] The present application is directed to a de-bounce circuit that mitigates and masks glitch. Background Art

[0002] In microcontroller and system-on-chip (SoC) applications, as well as other applications, traces and wires and the signals passing through them are susceptible to external and ambient electrical noise. Noise can corrupt signals (which may be asynchronous control signals) and introduce errors into the signals. Noise can introduce errors into the signals intermittently.

[0003] In electronic devices, glitches may occur whereby an electronic signal changes its level due to noise or interference. For example, a signal that is a logic 1 (activated, asserted, or high) may temporarily change to a logic 0 (deactivated, deasserted, or low). Summary of the invention

[0004] A de-jitter circuit is provided herein for filtering, masking or mitigating glitches in an electronic signal. The de-jitter circuit receives a signal and outputs an output signal having glitches that have been filtered, masked or mitigated. The de-jitter circuit includes a reset synchronizer circuit that receives a signal and detects whether the signal has glitches. When the signal has glitches, the reset synchronizer circuit outputs a reset synchronizer output signal having a first state, the first state indicating that the glitches exist. The de-jitter circuit includes logic that receives the reset synchronizer output signal and determines that glitches exist in the signal based on the reset synchronizer output signal. In response, the logic maintains the output signal in its current state, thereby preventing the glitches from affecting the output signal.

[0005] When the signal does not have a glitch, the reset synchronizer circuit outputs a reset synchronizer output signal having a second state or a third state corresponding to the state of the signal. If the signal is a logic 0 and no glitch is detected, the reset synchronizer output signal has a second state, and the second state indicates that the signal is a logic 0 and no glitch is detected. If the signal is a logic 1 and no glitch is detected, the reset synchronizer output has a signal with a third state, and the third state indicates that the signal is a logic 1 and no glitch is detected.

[0006] The logic receives the reset synchronizer output signal. When the reset synchronizer output signal is in the second state or the third state, the logic determines that no glitch is detected. In addition, the state of the input signal can be collected from the state of the reset synchronizer output signal. That is, when the reset synchronizer output signal is in the second state, the logic determines that the signal is a logic 0 and the logic sets the output signal to a logic 0. When the reset synchronizer output signal is in the third state, the logic determines that the signal is a logic 1 and the logic sets the output signal to a logic 1.

[0007] Therefore, in the case where a glitch is detected, the debounce circuit is used to detect and mask the glitch. When the glitch is not detected, the debounce circuit passes the signal to the output without modification. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of a debounce circuit is shown.

[0009] Figure 2A A timing diagram of the signals of the debounce circuit is shown.

[0010] Figure 2B A timing diagram of the signals of the debounce circuit is shown.

[0011] Figure 3 A block diagram of a system including a debounce circuit is shown.

[0012] Figure 4 A flow chart of a method for mitigating glitch is shown. DETAILED DESCRIPTION

[0013] Figure 1 1 shows a schematic diagram of a de-bouncing circuit 100. The de-bouncing circuit 100 includes a reset synchronizer circuit 101 and a logic circuit 106. The reset synchronizer circuit 101 includes a first reset synchronizer 102 and a second reset synchronizer 104. The first reset synchronizer 102 includes a first latch 108 and a second latch 110. The first latch 108 and the second latch 110 can each be a set-reset (SR) flip-flop or a delay (D) flip-flop, etc. The second reset synchronizer 104 includes a third latch 112 and a fourth latch 114, and the third latch 112 and the fourth latch 114 can each be an SR flip-flop or a D flip-flop, etc.

[0014] Logic circuit 106 includes AND gate 116, OR gate 118, buffer 119, multiplexer 120, and output latch 122. AND gate 116 can be any type of logic and digital device, and OR gate 118 can be any type of logic or digital device. Buffer 119 can be any type of delay element operable to delay signal transmission. Multiplexer 120 can be any type of input selection device, and output latch 122 can be an SR flip-flop or a D flip-flop, etc.

[0015] In the first reset synchronizer 102, the first latch 108 and the second latch 110 each have a data input D, a clock input >, a data output Q and a reset input RST. The data output of the first latch 108 is coupled to the data input of the second latch 110. The data output of the first reset synchronizer 102 is taken from the data output of the second latch 110.

[0016] In the second reset synchronizer 104, the third latch 112 and the fourth latch 114 each have a data input D, a clock input >, a data output Q and a reset input RST. The data output of the first latch 112 is coupled to the data input of the second latch 114. The data output of the second reset synchronizer 104 is taken from the data output of the second latch 114.

[0017] The AND gate 116 has a first input (i.e., a non-inverting input) coupled to the output of the first synchronizer 102. The AND gate 116 has a second input (i.e., an inverting input) coupled to the output of the second reset synchronizer 104. The AND gate 116 also has an output. The OR gate 118 has a first input coupled to the output of the first reset synchronizer 102 and a second input coupled to the output of the second reset synchronizer 104. The OR gate 118 also has an output. The buffer 119 has an input coupled to the output of the AND gate 116, and the buffer 119 has an output.

[0018] The multiplexer 120 has a first data input, a second data input, a select input and an output. The second data input of the multiplexer 120 is coupled to the output of the buffer 119. The select input of the multiplexer 120 is coupled to the output of the OR gate 118.

[0019] The output latch 122 has a data input D, a clock input >, a reset input RST, and a data output Q. The data input of the output latch 122 is coupled to the data output of the multiplexer 120. The data output of the output latch 122 is coupled to the first data input of the multiplexer 120. The data output of the output latch 122 provides the output signal of the de-bounce circuit 100. The reset input of the output latch 122 (which is an inverting input) is configured to receive a system reset signal, which resets the de-bounce circuit 100 when deactivated (or logic 0). The system reset signal can be received from a controller of the de-bounce circuit 100, a device that provides an input to the de-bounce circuit 100, or a device that receives the output of the de-bounce circuit 100.

[0020] A clock signal (denoted as "CLK") is provided to the clock inputs of the latches 108, 110, 112, 114, 122. Thus, the clock signal sets the timing operation of the de-jitter circuit 100. The components of the de-jitter circuit 100 are driven by the same clock signal. The latches 108, 110, 112, 114 are clocked or synchronized and can be edge triggered. Although the latches 108, 110, 112, 114 are described herein as being triggered along the rising edge, the latches 108, 110, 112, 114 can be triggered in other ways (e.g., on the falling edge of the clock signal).

[0021] The data inputs of the first latch 108 and the third latch 112 are configured to receive statically configured data inputs, which may have a logic state of either logic 1 or logic 0 according to convention. Figure 1 In the debounce circuit 100, the data inputs of the first latch 108 and the third latch 112 are logic 1, but in alternative embodiments, the data inputs may be logic 0. The reset inputs of the latches 108, 110 are active low, while the reset inputs of the latches 112, 114 are active high.

[0022] The operation of the debounce circuit 100 is first described under a stable condition where the input signal does not experience glitches that cause the input signal to transition between states (e.g., instantaneously). During the stable condition, when the input signal is a logic 1, the first reset synchronizer 102 is not reset, while the second reset synchronizer 104 is reset by the input signal. Therefore, the first reset synchronizer 102 outputs a first signal (denoted as “S 1 At the same time, because the second reset synchronizer 104 is reset, the second reset synchronizer 104 outputs a second signal of logic 0 (represented as “S 2 ”). On the contrary, when the input signal is logic 0, the first reset synchronizer 102 is reset and the first signal is logic 0, while the second reset synchronizer 104 is not reset and the second signal is logic 1.

[0023] Therefore, during stable conditions, the first signal S 1 and the second signal S 2 Indicates input signals, one of which is logic 1 and the other is logic 0. When the first signal S 1 is logic 1 and the second signal S 2 When the first signal is a logic 0 and the second signal is a logic 1, the synchronizers 102 and 104 transmit the input signal as a logic 1. Conversely, when the first signal is a logic 0 and the second signal is a logic 1, the synchronizers 102 and 104 transmit the input signal as a logic 0.

[0024] AND gate 116 receives the first signal and the second signal and, during stable conditions, outputs a signal having a state that matches the state of the input signal. Due to the inversion of the second input of AND gate 116, when the first signal is a logic 1 and the second signal is a logic 0, the signal output by AND gate 116 is a logic 1. When the first signal is a logic 0 and the second signal is a logic 1, the signal output by AND gate 116 is a logic 0.

[0025] During stable conditions and in the absence of a glitch in the input signal, OR gate 118 outputs a logic 1 to the select input of multiplexer 120, thereby selecting the second data input of multiplexer 120. The glitch tracking signal employed at the output of OR gate 118 is a logic 1 and does not indicate the presence of a glitch.

[0026] The multiplexer 120 receives the output signal of the AND gate 116 at the second data input. The output signal of the AND gate 116 is delayed by the buffer 119 to allow the output signal of the AND gate 116 to reach the multiplexer 120 after the output signal of the OR gate. The multiplexer 120 receives the logic 1 of the glitch tracking signal at the select input, thereby commanding the multiplexer 120 to select the signal presented at the second data input. The multiplexer 120 outputs the output signal of the AND gate 116. As described herein, during stable conditions, the output signal of the AND gate 116 matches the input signal. The output latch 122 receives the signal output by the multiplexer 120 and provides an output signal matching the state of the received signal at the subsequent rising edge of the clock signal. Therefore, during stable conditions and in a steady state, the output signal of the de-jitter circuit 100 matches the input signal of the de-jitter circuit 100.

[0027] The operation of the debounce circuit 100 when the input signal experiences a glitch that causes it to transition between states is now described. When a glitch occurs in the input signal, the input signal instantaneously transitions to the opposite or complementary state. The synchronizers 102, 104 signal the occurrence of a glitch to the logic circuit 106. While during stable conditions, one of the synchronizers 102, 104 outputs a logic 1 and the other of the synchronizers 102, 104 outputs a logic 0, when a glitch occurs, both synchronizers 102, 104 output a logic 0.

[0028] When the input signal initially has a logic "1" state, the first synchronizer 102 outputs a logic 1, and the second synchronizer 104 is reset and outputs a logic 0. When a glitch occurs and the input signal transitions to a logic 0, the first synchronizer 102 is reset in response. The first synchronizer 102 outputs a logic 0. Due to the fact that the synchronizers 102, 104 each have two cascaded latches, the outputs of the synchronizers 102, 104 remain at a logic 0 for at least one clock cycle. In order for the first synchronizer 102 to transition from a logic 0 to a logic 1, two rising edges are required; namely, a first rising edge of the clock signal, a logic 1 is passed from the data input of the first latch 108 to the data input of the second latch 110; and a second rising edge, a logic 1 is passed from the data input of the second latch 110 to the output of the first synchronizer 102. The cascading of the latches 108 , 110 in the first synchronizer 102 and the latches 112 , 114 in the second synchronizer 104 ensures that the first synchronizer 102 and the second synchronizer 104 each output a logic 0 until at least two rising edges of the clock signal are observed when the glitch occurs.

[0029] When both the first synchronizer 102 and the second synchronizer 104 output a logic 0, the output of the OR gate 118 becomes a logic 0. Therefore, the multiplexer 120 no longer selects and outputs the output of the AND gate 116. Instead, the multiplexer 120 outputs the signal presented at the first data input of the multiplexer 120. As described herein, the signal presented at the first data input is the current output signal fed back from the output latch 122. Therefore, the multiplexer 120 recycles the output signal of the de-jitter circuit 100 and actually locks the output signal of the de-jitter circuit 100 to its current state, thereby masking the burr. Therefore, the burr in the input signal is not passed to the output signal.

[0030] When a glitch occurs, multiplexer 120 bypasses the output of AND gate 116. Multiplexer 120 no longer relies on the output of AND gate 116, and therefore no longer relies on the output signal of synchronizer 102 to determine or convey the state of the input signal. When a glitch is detected, debounce circuit 100 maintains the output signal in its current state.

[0031] When the input signal remains in the same state within two rising edges of the clock signal, the de-jitter circuit 100 exits the glitch detection operation. In response to the input signal remaining in the same state within two rising edges of the clock signal, the synchronizers 102 and 104 resume outputting complementary states. 1 , S 2) have complementary states, the output of AND gate 116 transmits the input signal. Note that due to the cascade of edge-triggered latches, the output of AND gate 116 transmits the state of the input signal with a delay of at least one clock cycle. In addition, the output of OR gate 118 is a logic 1. The logic 1 output causes multiplexer 120 to select and output the output of AND gate 116, which represents the state of the input signal. Output latch 122 receives the output of AND gate 116 and sets the state of the output signal to the state of the input signal after one rising edge of the clock signal (e.g., one clock cycle).

[0032] In the de-jitter circuit 100, when no glitch is detected, the synchronizers 102 and 104 operate to output a first signal and a second signal (S) having complementary states, respectively. 1 , S 2 When a glitch is detected, synchronizers 102, 104 output first and second signals (S) having the same state of logic 0 (or logic 1, depending on the use of the set inputs of conventional or latches 108, 110, 112, 114). 1 , S 2 ). When a glitch is detected, the synchronizers 102, 104 continue to output logic 0 for at least one clock cycle.

[0033] When the first signal and the second signal (S 1 , S 2 ) have complementary states, AND gate 116 receives the first signal and the second signal (S 1 , S 2 The AND gate 116 decodes the state of the input signal based on the first signal and the second signal (S 1 , S 2 ) state to output a signal with the same state as the input signal.

[0034] The OR gate 118 is based on the first signal and the second signal (S 1 , S 2 ) decodes whether the glitch has been detected by the synchronizer 102, 104. OR gate 118 outputs a signal indicating whether the glitch has been detected by the synchronizer 102, 104.

[0035] Buffer 119 delays the output signal of AND gate 116 and makes the path between OR gate 118 and multiplexer 120 faster than the path between AND gate 116 and multiplexer 120. Buffer 119 operates to ensure that the select signal provided by OR gate 118 reaches multiplexer 120 before the corresponding data signal provided by AND gate 116. It should be noted that in one embodiment, the use of buffer 119 may be abandoned in favor of a path between the output of OR gate 118 and multiplexer 120 that is faster than the path between AND gate 116 and multiplexer 120.

[0036] The multiplexer 120 receives the outputs of the AND gate 116 and the OR gate 118 and the output signal of the debounce circuit 100. When the multiplexer 120 receives an indication that a glitch has not been detected, the multiplexer 120 operates to pass the state of the input signal decoded from the outputs of the synchronizers 102, 104. When the multiplexer 120 receives an indication that a glitch has been detected, the multiplexer 120 operates to latch or recycle the current output signal of the latch 122. The output latch 122 operates to store the output signal within one clock cycle for use by the multiplexer 120 to latch or recycle the current output signal.

[0037] Figure 2A 2 shows a timing diagram 200a of the signals of the de-bounce circuit 100. A clock signal 202, an input signal 204, an output signal 206, a glitch tracking signal 208, a first signal S 1 210 and the second signal S 2 212 is shown in timing diagram 200a.

[0038] In the first timing diagram 200a, at the first time instance 222, the input signal 204 is a logic 1. Correspondingly, the first signal 210 is a logic 1 and the second signal 212 is a logic 0. The states of the first signal 210 and the second signal 212 convey the state of the input signal. At the second time instance 224, a glitch occurs, and the first signal 210 transitions to a logic 0 and fluctuates between states. As a result, the first signal 210 transitions to a logic 0. The glitch tracking signal also transitions to a logic 0, which indicates that a glitch has occurred. As described herein, in response to the glitch at the second time instance 224, the states of the first signal 210 and the second signal 212 (both logic 0) indicate that a glitch exists. The output signal 206 of the de-bounce circuit 100 is locked in its current state of logic 1. The glitch will be ignored and will not be passed from the input signal 204 to the output signal 206.

[0039] The first signal 210 remains at a logic 0 until a third time instance 226. At the third time instance 226, two rising edges (at least one clock cycle) of the clock signal 202 are observed from the occurrence of the glitch. At the third time instance 226, the first signal 210 transitions back to a logic 1.

[0040] Additionally, glitch tracking signal 208 transitions back to logic 1 at third time instance 226, indicating that the glitch in input signal 206 has ended. By counting the number of times glitch tracking signal 208 goes low or assumes logic state zero, the number of times a glitch occurs can be counted.

[0041] Figure 2B A timing diagram 200b is shown for signals of the debounce circuit 100. Initially at a first time instance 228, the input signal 204 is a logic 1. Correspondingly, the first signal 210 is a logic 1, and the second signal 212 is a logic 0. The output signal 206 is also a logic 1.

[0042] At a second time instance 230, the input signal 204 transitions from a logic 1 to a logic 0, and shortly thereafter a first glitch occurs, causing the input signal 204 to transition between two states. The transition causes the first signal 210 to transition to a logic 0, and the first glitch causes the second signal 210 to remain at a logic 0 for at least one clock cycle. The two states of the first signal 210 and the second signal 212 indicate that a glitch occurred. The glitch tracking signal 208 transitions to a logic 0. The debounce circuit output signal 206 remains at its previous state before the first glitch occurred.

[0043] Due to the fact that the latches 108, 110 of the first reset synchronizer 102 (whose reset input is active low) are reset by the input signal, the first signal 210 immediately transitions to logic 0 after the input signal 204 transitions from logic 1 to logic 0. At the same time, the latches 112, 114 of the second reset synchronizer 104 are no longer reset. However, due to the cascading of the latches 112, 114, two rising edges of the clock signal 202 are required so that the static signal provided at the data input of the third latch 112 propagates to the data output of the fourth latch 114 as the second signal 212.

[0044] Note that the use of two cascaded latches in each reset synchronizer 102, 104 ensures that when a glitch occurs, there is at least one clock cycle during which both the first signal 210 and the second signal 212 are low. In contrast, if one latch is used instead of two in each reset synchronizer 102, 104, a glitch coincident with the rising edge of the clock signal 202 may not be filtered out and may be mistaken for a signal transition. This glitch coincident with the rising edge of the clock signal 202 will then propagate to the output of the reset synchronizer 102, 104, and thus to the output signal 206 of the debounce circuit 100.

[0045] Similarly, using three cascaded latches results in the first output signal 210 and the second output signal 212 requiring three rising edges of the clock signal 202 instead of two (or at least two full clock cycles instead of one) to recover to complementary states after a glitch occurs.

[0046] After the transition with the first glitch, the input signal 204 stabilizes at a logic 0 state. For example, at the third time instance 232, the input signal 204 is at a logic 0 state. However, since the first glitch occurred previously, the output signal 206 is a logic 1.

[0047] After two rising edges of the clock signal 202 from the first glitch, at a fourth time instance 234, the second signal 212 transitions to a logic 1 and the first signal 210 remains at a logic 0. The states of the first signal 210 and the second signal 212 (complementary states of 0 and 1, respectively) indicate that no glitch was detected and the state of the input signal 204 is a logic 0.

[0048] In response, one clock cycle later, at a fifth time instance 236, the output signal 206 transitions to the corresponding state (logic 0) of the input signal 204. Due to the one clock cycle delay of the output latch 122, this transition occurs after one rising edge of the clock signal 202.

[0049] At a sixth time instance 238, a second glitch occurs in the input signal 204. In response, the second signal 212 transitions to a logic 0. Thus, the first signal 210 and the second signal 212 together indicate the presence of the second glitch. The glitch tracking signal 208 transitions to a logic 0 indicating that the second glitch was detected. The debounce circuit 100 maintains the output signal 204 in its logic 0 state prior to the occurrence of the second glitch, and the second glitch does not propagate in the output signal 206.

[0050] At the seventh time instance 240, when two rising edges of the clock signal 202 occur after the second glitch, both the second signal 212 and the glitch tracking signal 208 transition back to logic 1. The output signal 206 of the debounce circuit remains at logic 0 between the sixth time instance 238 and the seventh time instance 240. The second glitch does not affect the output signal 206.

[0051] Figure 3 A block diagram of a system 300 including a de-bounce circuit 100 is shown. The system 300 includes a first device 302 and a second device 304 and the de-bounce circuit 100. The output of the first device 302 is coupled to the input of the de-bounce circuit 100 (or its reset synchronizer circuit 101). The first device 302 sends an input signal to the de-bounce circuit 100. The input of the second device 304 is coupled to the output of the de-bounce circuit 100 (or its logic circuit 106). The second device 304 receives the output signal from the de-bounce circuit 100.

[0052] The de-bounce circuit 100 receives an input signal from a first device 302 and outputs an output signal to a second device 304. The input signal may include glitches as described herein. The de-bounce circuit 100 masks the glitches and outputs the output signal to the second device 304 as a glitch-free signal.

[0053] The first device 302 and the second device 304 may each be a processor, a controller, a microcontroller, a system on a chip, or a memory device (e.g., a random access memory (RAM), or an element, device, or component thereof). The de-bounce circuit 100 may be used to mitigate noise, glitches, or transient changes in the signals of the system 300, which may be caused by mechanical jitter that occurs when the signal state and ambient electrical noise of the system 300 change. The de-bounce circuit 100 performs robust electrical noise filtering while reducing the logic of the system 300 and minimizing overhead.

[0054] Figure 4 A flow chart of a method 400 for mitigating glitches is shown. In the method 400, a reset synchronizer circuit of a debounce circuit receives an input signal at 402. At 404, the reset synchronizer circuit detects a glitch in the input signal. In response to detecting the glitch in the input signal, the reset synchronizer circuit outputs one or more reset synchronizer output signals at 406, the one or more reset synchronizer output signals having a first reset synchronizer output state indicating that the glitch was detected.

[0055] At 408, the logic circuit determines that the one or more reset synchronizer output signals are in a first reset synchronizer output state indicating that a glitch is detected. In response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer output state, at 410, the logic circuit maintains the output signal of the debounce circuit at the current state of the output signal.

[0056] The various embodiments described above can be combined to provide further embodiments.

[0057] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents required for protection by such claims. Therefore, the claims are not limited by the disclosure.

Claims

1. A de-jitter circuit, comprising: The reset synchronizer circuit is configured as: receiving an input signal; detecting glitches in the input signal; as well as In response to detecting the glitch in the input signal, outputting one or more reset synchronizer signals, the one or more reset synchronizer signals having a first reset synchronizer state indicating that the glitch is detected; as well as The logic circuit is configured as: receiving the one or more reset synchronizer signals; determining that the one or more reset synchronizer signals are in the first reset synchronizer state indicating that the glitch is detected; as well as In response to determining that the one or more reset synchronizer signals are in the first reset synchronizer state, maintaining the output signal of the de-bounce circuit in a current state of the output signal of the de-bounce circuit.

2. The de-bounce circuit of claim 1 , wherein the reset synchronizer circuit is configured as: Determining that the input signal does not include the glitch; as well as In response to determining that the input signal does not include the glitch, outputting the one or more reset synchronizer output signals having a second reset synchronizer state when the input signal is in the first state, the second reset synchronizer state indicating that the glitch is not detected and the input signal is in the first state; as well as When the input signal is in the second state, the one or more reset synchronizer output signals are output with a third reset synchronizer state, the third reset synchronizer state indicating that the glitch is not detected and the input signal is in the second state.

3. The debounce circuit according to claim 2, wherein the logic circuit is configured to: determining that the one or more reset synchronizer output signals are in the second reset synchronizer state; and In response to determining that the one or more reset synchronizer output signals are in the second reset synchronizer state, outputting the output signal of the de-bounce circuit in the first state.

4. The debounce circuit according to claim 2, wherein the logic circuit is configured to: determining that the one or more reset synchronizer output signals are in the third reset synchronizer state; and In response to determining that the one or more reset synchronizer output signals are in the third reset synchronizer state, outputting the output signal of the de-bounce circuit in the second state.

5. The de-bouncing circuit of claim 1 , wherein the reset synchronizer circuit comprises: a first reset synchronizer having a reset input that is active low and configured to receive the input signal; as well as A second reset synchronizer has a reset input that is active high and configured to receive the input signal.

6. The de-bounce circuit according to claim 5, wherein: The first reset synchronizer includes a first latch and a second latch that are cascaded, wherein the first latch and the second latch each have a reset input that is active low and configured to receive the input signal; and The second reset synchronizer includes a third latch and a fourth latch that are cascaded, wherein the third latch and the fourth latch each have a reset input that is active high and configured to receive the input signal.

7. The de-bounce circuit according to claim 6, wherein: The first latch has a data input configured to receive a first state, a clock input configured to receive a clock signal, and a data output; and the second latch having a data input coupled to the data output of the first latch, a clock input configured to receive the clock signal, and a data output configured to provide a first reset synchronizer output signal of the one or more reset synchronizer output signals; The third latch has a data input configured to receive the first state, a clock input configured to receive the clock signal, and a data output; and The fourth latch has a data input coupled to the data output of the third latch, a clock input configured to receive the clock signal, and a data output configured to provide a second reset synchronizer output signal of the one or more reset synchronizer output signals.

8. The debounce circuit according to claim 1, wherein the logic circuit comprises: an AND gate having a first input configured to receive a first reset synchronizer output signal of the one or more reset synchronizer output signals, a second input configured to receive a second reset synchronizer output signal of the one or more reset synchronizer output signals and being an inverting input, and an output configured to provide a determined state of the input signal based on the first reset synchronizer output signal and the second reset synchronizer output signal when the glitch is not detected; as well as An OR gate has a first input configured to receive the first reset synchronizer output signal, a second input configured to receive the second reset synchronizer output signal, and an output configured to provide an indication of whether the glitch is detected based on the first reset synchronizer output signal and the second reset synchronizer output signal.

9. The debounce circuit according to claim 8, wherein the logic circuit comprises: a multiplexer having a first data input configured to receive the current state of the output signal, a second data input coupled to the output of the AND gate, a select input coupled to the output of the OR gate, and an output, wherein the multiplexer operates to: outputting the determined state of the input signal at the output of the multiplexer when the glitch is not detected; as well as When the glitch is detected, the current state of the output signal is output on the output of the multiplexer.

10. The debounce circuit according to claim 9, wherein the logic circuit comprises: an output latch having a data input coupled to the output of the multiplexer, a clock input configured to receive a clock signal, a data output configured to output the output signal, and a reset input configured to receive a system reset signal, the output latch operating to store the current state of the output signal for providing to the multiplexer.

11. A method for debounce circuit, comprising: Receiving an input signal from a reset synchronizer circuit in the de-jitter circuit; detecting glitches in the input signal by the reset synchronizer circuit; In response to detecting the glitch in the input signal, outputting, by the reset synchronizer circuit, one or more reset synchronizer output signals having a first reset synchronizer state among a plurality of reset synchronizer states, the first reset synchronizer state indicating that the glitch is detected; determining, by logic circuitry in the debounce circuit, that the one or more reset synchronizer output signals are in the first reset synchronizer state indicating that the glitch is detected; as well as In response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer state, the output signal of the de-bounce circuit is maintained by the logic circuit in a current state of the output signal.

12. The method according to claim 11, comprising: Determining, by the reset synchronizer circuit, that the input signal does not include the glitch; as well as In response to determining that the input signal does not include the glitch, When the input signal is in the first state, outputting, by the reset synchronizer circuit, the one or more reset synchronizer output signals having a second reset synchronizer state among the plurality of reset synchronizer states, the second reset synchronizer state indicating that the glitch is not detected and the input signal is in the first state; as well as When the input signal is in the second state, the one or more reset synchronizer output signals having a third reset synchronizer state among the plurality of reset synchronizer states are output by the reset synchronizer circuit, the third reset synchronizer state indicating that the glitch is not detected and the input signal is in the second state.

13. The method according to claim 12, comprising: determining, by the logic circuit, that the one or more reset synchronizer output signals are in the second reset synchronizer state; as well as In response to determining that the one or more reset synchronizer output signals are in the second reset synchronizer state, the output signal of the de-bounce circuit in the first state is output by the logic circuit.

14. The method according to claim 12, comprising: determining, by the logic circuit, that the one or more reset synchronizer output signals are in the third reset synchronizer state; as well as In response to determining that the one or more reset synchronizer output signals are in the third reset synchronizer state, the output signal of the de-bounce circuit in the second state is output by the logic circuit.

15. A system for a debounce circuit, comprising: A first device configured to send an input signal; The debounce circuit is coupled to the first device and includes: The reset synchronizer circuit is configured as: receiving the input signal; detecting glitches in the input signal; and In response to detecting the glitch in the input signal, outputting one or more reset synchronizer signals having a first reset synchronizer state, the first reset synchronizer state indicating that the glitch was detected; and The logic circuit is configured as: receiving the one or more reset synchronizer signals; determining that the one or more reset synchronizer signals are in the first reset synchronizer state indicating that the glitch is detected; and In response to determining that the one or more reset synchronizer signals are in the first reset synchronizer state, maintaining an output signal of the de-bounce circuit at a current state of the output signal of the de-bounce circuit; and A second device coupled to the de-bounce circuit is configured to receive the output signal.

16. The system of claim 15, wherein the reset synchronizer circuit is configured to: determining that the input signal does not include the glitch; and In response to determining that the input signal does not include the glitch, When the input signal is in the first state, outputting the one or more reset synchronizer output signals having a second reset synchronizer state, the second reset synchronizer state indicating that the glitch is not detected and the input signal is in the first state; and When the input signal is in the second state, the one or more reset synchronizer output signals are output with a third reset synchronizer state, the third reset synchronizer state indicating that the glitch is not detected and the input signal is in the second state.

17. The system of claim 16, wherein the logic circuit is configured to: determining that the one or more reset synchronizer output signals are in the second reset synchronizer state; and In response to determining that the one or more reset synchronizer output signals are in the second reset synchronizer state, outputting the output signal of the de-bounce circuit in the first state.

18. The system of claim 16, wherein the logic circuit is configured to: determining that the one or more reset synchronizer output signals are in the third reset synchronizer state; and In response to determining that the one or more reset synchronizer output signals are in the third reset synchronizer state, outputting the output signal of the de-bounce circuit in the second state.

19. The system of claim 15, wherein the reset synchronizer circuit comprises: The first reset synchronizer comprises: a first latch having a data input configured to receive a first state, a clock input configured to receive a clock signal, a data output, and an inverting reset input configured to receive the input signal; and a second latch having a data input coupled to the data output of the first latch, a clock input configured to receive the clock signal, a data output configured to provide a first reset synchronizer output signal of the one or more reset synchronizer output signals, and an inverted reset input configured to receive the input signal; and The second reset synchronizer comprises: a third latch having a data input configured to receive the first state, a clock input configured to receive the clock signal, and a non-inverting reset input configured to receive the input signal; and a fourth latch having a data input coupled to the data output of the third latch, a clock input configured to receive the clock signal, a data output configured to provide a second reset synchronizer output signal among the one or more reset synchronizer output signals, and a non-inverting reset input configured to receive the input signal.

20. The system of claim 15, wherein the logic circuit comprises: an AND gate having a first input configured to receive a first reset synchronizer output signal of the one or more reset synchronizer output signals, a second input configured to receive a second reset synchronizer output signal of the one or more reset synchronizer output signals and being an inverting input, and an output configured to provide a determined state of the input signal based on the first reset synchronizer output signal and the second reset synchronizer output signal when the glitch is not detected; as well as An OR gate has a first input configured to receive the first reset synchronizer output signal, a second input configured to receive the second reset synchronizer output signal, and an output configured to provide an indication of whether the glitch is detected based on the first reset synchronizer output signal and the second reset synchronizer output signal.

21. The system of claim 20, wherein the logic circuit comprises: a multiplexer having a first data input configured to receive the current state of the output signal, a second data input coupled to the output of the AND gate, a select input coupled to the output of the OR gate, and an output, wherein the multiplexer operates to: outputting the determined state of the input signal at the output of the multiplexer when the glitch is not detected; as well as When the glitch is detected, the current state of the output signal is output on the output of the multiplexer.

22. The system of claim 21, wherein the logic circuit comprises: an output latch having a data input coupled to the output of the multiplexer, a clock input configured to receive a clock signal, a data output configured to output the output signal, and a reset input configured to receive a system reset signal, the output latch operating to store the current state of the output signal for providing to the multiplexer.

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