Semiconductor device and method of forming the same

Abstract

An embodiment of the present invention provides a semiconductor device and a method for forming the same. The method includes forming a sensing pixel array in a substrate, forming a plurality of light-transmitting columns on the substrate, and forming a light-shielding layer on the substrate to cover the light-transmitting columns. The sensing pixel array includes a plurality of sensing pixels, and the light-transmitting columns are correspondingly arranged on the sensing pixels of the sensing pixel array. The light-shielding layer is a multi-layer film structure. The method further includes performing a planarization process to expose the top surface of the light-transmitting column. By forming the light-shielding layer filled between the light-transmitting columns into a multi-layer film structure, the light-transmitting columns may be prevented from tipping over due to the light-shielding layer being too soft or cracks may be prevented due to the light-shielding layer being too hard, thereby improving the reliability and process yield of the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly to an optical sensing structure and a method for forming the same. Background Art

[0002] Today's mobile electronic devices (such as mobile phones, tablet computers, notebook computers, etc.) are usually equipped with a user identification system to protect personal data security. Since everyone's fingerprint is different, the fingerprint sensor is a common and reliable user identification system.

[0003] Fingerprint sensors on the market often use optical technology to sense the user's fingerprint. The optical elements of such fingerprint sensors based on optical technology may include a light collimator, a beam splitter, a focusing lens, and a linear sensor, etc. The collimator is used to make the light incident on the sensor travel in parallel to reduce the energy loss caused by light divergence.

[0004] However, although existing optical fingerprint sensors generally meet their intended purpose, they are not completely satisfactory in all aspects and still need further improvement to enhance product yield and reliability. Summary of the invention

[0005] An embodiment of the present invention provides a method for forming a semiconductor device. The method includes forming a sensor pixel array in a substrate, forming a plurality of transparent pillars on the substrate, and forming a light shielding layer on the substrate to cover the transparent pillars. The sensor pixel array includes a plurality of sensor pixels, and the transparent pillars are correspondingly arranged on the sensor pixels of the sensor pixel array. The light shielding layer is a multi-layer structure. The method further includes performing a planarization process to expose the top surface of the transparent pillars.

[0006] The present invention also provides a semiconductor device. The device includes a sensing pixel array located in a substrate, a plurality of light-transmitting columns located on the substrate, and a light-shielding layer located on the substrate and filled between the light-transmitting columns. The sensing pixel array includes a plurality of sensing pixels, and the light-transmitting columns are correspondingly arranged on the sensing pixels of the sensing pixel array. The light-shielding layer is a multilayer film structure.

[0007] The following embodiments and the accompanying reference drawings will provide a detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Some embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention.

[0009] Figures 1A to 1C According to some embodiments, a method for forming Figure 1C Schematic cross-sectional views of various intermediate stages of an example method for fabricating a semiconductor device.

[0010] Figure 2A and Figure 2B According to some embodiments, a method for forming Figure 2B Schematic cross-sectional views of various intermediate stages of an example method for fabricating a semiconductor device.

[0011] Explanation of symbols:

[0012] 10, 20~Semiconductor devices

[0013] 100, 100'~Substrate

[0014] 200~Sensing pixel array

[0015] 202~Sensing Pixels

[0016] 300~Light-transmitting column

[0017] 400, 400'~Light-shielding layer

[0018] 402~Bottom shading layer

[0019] 403~Intermediate light shielding layer

[0020] 404~Top light shielding layer

[0021] 600~Light collimation layer

[0022] S1~Distance DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples to show different components of the embodiments of the present invention. The following will disclose specific examples of the components of this specification and their arrangement to simplify the description of the present invention. Of course, these specific examples are not intended to limit the present invention. For example, if the following invention content of this specification describes forming a first component on or above a second component, it means that it includes an embodiment in which the first and second components formed are in direct contact, and also includes an embodiment in which an additional component can be formed between the above-mentioned first and second components, and the first and second components are not in direct contact. In addition, the various examples in the description of the present invention may use repeated reference symbols and / or words. The purpose of these repeated symbols or words is to simplify and clarify, and is not used to limit the relationship between the various embodiments and / or the configurations.

[0024] Furthermore, in order to conveniently describe the relationship between one element or component and another element or component in the drawings, spatially relative terms may be used, such as "under", "below", "lower", "above", "upper" and the like. In addition to the orientations shown in the drawings, spatially relative terms also cover different orientations of the device in use or operation. When the device is turned to a different orientation (for example, rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the turning. It should be understood that additional operations may be provided before, during, and / or after the methods described in embodiments of the present invention, and in other embodiments of the methods, some of the operations described may be replaced or omitted.

[0025] Here, the terms "about", "approximately", and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meanings of "about", "approximately", and "generally" can still be implied.

[0026] Some variations of the example methods and structures are described herein. Those skilled in the art will readily appreciate that other modifications may be made within the scope of other embodiments. Although some of the method embodiments discussed are performed in a particular order, various other method embodiments may be performed in another logical order and may include fewer or more steps than discussed herein. In some illustrations, the element symbols of some of the components or parts shown therein may be omitted to avoid confusion with other components or parts; this is for the convenience of describing such illustrations.

[0027] Embodiments of the present invention provide a semiconductor device and a method for forming the same, which are particularly suitable for optical sensors including a light collimating layer. In some embodiments of the present invention, by forming a light shielding layer filled between light-transmitting pillars into a multi-layer film structure, the light-transmitting pillars can be prevented from collapsing due to the light shielding layer being too soft or from cracking due to the light shielding layer being too hard, thereby improving the reliability and process yield of the semiconductor device.

[0028] Figures 1A to 1C According to some embodiments, a method for forming Figure 1C Schematic cross-sectional views of various intermediate stages of an exemplary method of manufacturing a semiconductor device 10 .

[0029] Figure 1A The initial steps of a method for forming a semiconductor device 10 are shown according to an embodiment of the present invention. Figure 1A As shown, a substrate 100 is provided. In one embodiment, the substrate 100 may be a silicon substrate, a silicon germanium (SiGe) substrate, a compound semiconductor substrate, a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate or the like, which may be doped (e.g., using p-type or n-type dopants) or undoped. Generally speaking, a semiconductor-on-insulator substrate includes a film layer of semiconductor material formed on an insulator. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multi-layered or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate may include an elemental semiconductor containing silicon (Si) or germanium (Ge); a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination thereof.

[0030] In some embodiments, the substrate 100 may include various isolation features (not shown) to define an active region and electrically isolate active region devices in / on the substrate 100. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or combinations thereof.

[0031] In some embodiments, the substrate 100 may include various device elements. These device elements are not shown for simplicity and clarity. These device elements may include transistors, diodes, other suitable elements, or combinations thereof. For example, the transistor may be a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a high voltage transistor, a high frequency transistor, a p-channel and / or n-channel field effect transistor (PFETs / NFETs), and the like.

[0032] In some embodiments, the substrate 100 may include various conductive elements (e.g., conductive wires or vias) (not shown). For example, the conductive elements may be formed of aluminum, copper, tungsten, other appropriate conductive materials, alloys thereof, or combinations thereof.

[0033] Then, if Figure 1AAs shown, in some embodiments, a sensing pixel array 200 is formed in the substrate 100, and the sensing pixel array 200 has a plurality of sensing pixels 202. The sensing pixels 202 may be connected to a signal processing circuit (not shown). In some embodiments, the number of sensing pixels 202 of the sensing pixel array 200 depends on the area size of the optical sensing region. Each sensing pixel 202 may include one or more photodetectors. In some embodiments, the photodetector may include a photodiode, wherein the photodiode may include a photoelectric material having a three-layer structure of a P-type semiconductor layer, an intrinsic layer, and an N-type semiconductor layer, the intrinsic layer absorbs light to generate excitons, and the excitons are separated into electrons and holes at the junction of the P-type semiconductor layer and the N-type semiconductor layer, thereby generating a current signal. In other embodiments, the photodetector may also include a charged coupling device (CCD) sensor, a complementary metal-oxide-semiconductor (CMOS) image sensor, an active sensor, a passive sensor, other suitable sensors, or a combination thereof. In some embodiments, the sensing pixel 202 may convert the received light signal into an electronic signal through the photodetector, and process the electronic signal through a signal processing circuit. It is worth noting that in Figure 1A The number and arrangement of the sensing pixel array 200 shown are merely exemplary, and the present invention is not limited thereto. The sensing pixels 202 may be arrays with any number of rows and columns or in other arrangements.

[0034] Continue to refer Figure 1A , forming a plurality of light-transmitting pillars 300 disposed on the sensing pixel array 200 and corresponding to the sensing pixels 202. In some embodiments, a light-transmitting material layer (not shown) may be blanket-formed on the substrate 100 to cover the sensing pixel array 200. In some embodiments, the light-transmitting material layer may include a light-transmitting material having a light transmittance greater than about 90% in the wavelength range of 300 nanometers to 1200 nanometers, thereby allowing a portion of the incident light to pass through the light-transmitting material layer and reach the sensing pixels 202.

[0035] In some embodiments, the light-transmitting material layer may include a UV-curable material, a thermosetting material, or a combination thereof. For example, the light-transmitting material may include, for example, poly(methyl methacrylate, PMMA), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), perfluorocyclobutyl (PFCB) polymer, polyimide (PI), acrylic resin, epoxy resin, polypropylene (PP), polyethylene (PE), polystyrene (PS), polyvinyl chloride (PVC), other suitable materials, or combinations thereof. Spin coating, casting, bar coating, blade coating, roller coating, wire bar coating, dip coating, etc. may be used. The light-transmitting material layer is deposited on the substrate 100 by using a method such as coating, chemical vapor deposition (CVD), other suitable methods, or a combination thereof. In some embodiments, the thickness of the light-transmitting material layer formed by the above method is in a range of about 10 to about 300 microns, for example, 100 microns. In other embodiments, the thickness of the light-transmitting material layer is in a range of about 100 to about 500 microns, for example, 300 microns.

[0036] Next, the light-transmitting material layer formed on the substrate 100 is selectively removed to form the light-transmitting column 300. Figure 1A In some embodiments, since the light-transmitting pillars 300 are disposed on the sensing pixels 202, the light-transmitting pillars 300 disposed on the sensing pixels 202 can protect the sensing pixels 202 and reduce or prevent the sensing pixels 202 from being contaminated and / or damaged during the process, thereby affecting the sensitivity of the semiconductor device 10. In some embodiments, each light-transmitting pillar 300 is disposed on each sensing pixel 202. Figure 1AIn other embodiments, at least one light-transmitting rod 300 covers more than two sensing pixels 202 (not shown). In some embodiments, in the top view, the light-transmitting rods 300 may be circular, rectangular, polygonal, any shape, or a combination thereof, and are arranged in an array (not shown).

[0037] In some embodiments, a patterning process may be used to selectively remove the light-transmitting material layer to form the light-transmitting column 300. In some embodiments in which the light-transmitting material layer is a non-photoresist material, the patterning process may include a photolithography process and an etching process. The photolithography process may include, for example, photoresist coating (e.g., spin coating), soft baking, exposure patterning, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other appropriate processes, or combinations thereof. The etching process may include, for example, a wet etching process, a dry etching process (e.g., reactive ion etching (RIE), plasma etching, ion milling), other suitable processes, or combinations thereof.

[0038] In other embodiments, the light-transmitting material layer may be a photoresist material, in which case the light-transmitting material layer may be patterned by a photolithography process to directly form a patterned light-transmitting column 300 without an additional etching process. The photolithography process is similar to the above-mentioned photolithography process, so it will not be described in detail here.

[0039] In some embodiments, the thickness of the light-transmitting column 300 formed by the above method is in the range of about 5 to about 300 microns, for example, 100 microns. In other embodiments, the thickness of the light-transmitting column 300 is in the range of about 50 to about 500 microns, for example, 300 microns. In some embodiments, the top surfaces of the light-transmitting columns 300 are substantially aligned with each other. In some embodiments, the aspect ratio of the light-transmitting column 300 is in the range of about 2 to about 30, for example, about 5, about 10, about 15 or about 20. If the light-transmitting column 300 is too high (i.e., the aspect ratio is too large), the light-transmitting column 300 is easily deformed or collapsed, resulting in increased process difficulty and correspondingly increased process cost. If the light-transmitting column 300 is too wide (i.e., the aspect ratio is too small), it is easy to receive unnecessary incident light, making it difficult to achieve a collimation effect, thereby reducing the sensitivity of the semiconductor device 10.

[0040] Figure 1BThe formation of the light shielding layer 400 is depicted, wherein the light shielding layer 400 is a multi-layer structure. For example, the light shielding layer 400 includes a bottom light shielding layer 402 and a top light shielding layer 404. The light shielding layer 400 can be formed by forming the bottom light shielding layer 402 on the substrate 100 and forming the top light shielding layer 404 on the bottom light shielding layer 402. The bottom light shielding layer 402 and the top light shielding layer 404 are filled between the plurality of light-transmitting pillars 300, and the top light shielding layer 404 covers the top surface of the light-transmitting pillars 300. The top light shielding layer 404 can protect the light-transmitting pillars 300 from damage in the subsequent planarization process.

[0041] In some embodiments, the material of each film layer of the light shielding layer 400 (for example, the material of the bottom light shielding layer 402 and the top light shielding layer 404) has a light transmittance of less than about 1% in the wavelength range of 300 nanometers to 1200 nanometers, so that the light can accurately reach the sensing pixels 202 corresponding to each of the light-transmitting pillars 300. In some embodiments, the hardness of each film layer of the light shielding layer 400 (for example, the bottom light shielding layer 402 and the top light shielding layer 404) is greater than the hardness of the light-transmitting pillar 300 to protect the light-transmitting pillar 300 from damage in subsequent processes. In some embodiments, the Mohs' hardness of the light-transmitting pillar 300 can be in the range of about 1.5 to about 2.5, for example, about 2.0, and the Mohs' hardness of each film layer of the light shielding layer 400 (for example, the bottom light shielding layer 402 and the top light shielding layer 404) can be in the range of greater than about 1.5 to about 9.0, for example, about 2.5, for example, about 7.0.

[0042] In the subsequent process, the combination of the light-transmitting pillars 300 disposed on the sensing pixels 202 and the light-shielding layers 400 filled between the light-transmitting pillars 300 together constitutes a light-collimating layer 600 (to be described in detail later).

[0043] In some embodiments, the bottom light shielding layer 402 and the top light shielding layer 404 of the light shielding layer 400 are formed to have different hardnesses. Generally speaking, after the planarization process, if the light shielding layer is too soft, the light-transmitting column is easy to fall over, and if the light shielding layer is too hard, cracks are easily caused on the surface. In the embodiment of the present invention, the light shielding layer 400 is formed into a multi-layer structure with different hardnesses, so that the light shielding layer 400 includes a bottom light shielding layer 402 and a top light shielding layer 404 with different hardnesses, so as to eliminate the problem of light-transmitting column falling over or surface cracks that are easy to appear after the planarization process. According to some embodiments, the Mohs hardness difference between the bottom light shielding layer 402 and the top light shielding layer 404 may be in the range of about 2 to about 6, for example, about 4. In some embodiments, the hardness of the bottom light shielding layer 402 is less than that of the top light shielding layer 404, for example, the Mohs hardness of the bottom light shielding layer 402 is about 3, and the Mohs hardness of the top light shielding layer 404 is about 4. In some other embodiments, the hardness of the bottom light shielding layer 402 is greater than that of the top light shielding layer 404 . For example, the Mohs hardness of the bottom light shielding layer 402 is about 4, and the Mohs hardness of the top light shielding layer 404 is about 3.

[0044] In some embodiments, the bottom light shielding layer 402 and the top light shielding layer 404 may include different materials. For example, the bottom light shielding layer 402 and / or the top light shielding layer 404 may include a photoresist (e.g., a black photoresist or other suitable non-transparent photoresist), ink (e.g., a black ink or other suitable non-transparent ink), a molding compound (e.g., a black molding compound or other suitable non-transparent molding compound), a solder mask (e.g., a black solder mask or other suitable non-transparent solder mask), other suitable materials, or a combination thereof. In some embodiments, the bottom light shielding layer 402 and / or the top light shielding layer 404 may be a photocurable material, a thermally curable material, or a combination thereof. In the above embodiment, the light shielding material (not shown) for the bottom light shielding layer 402 and the top light shielding layer 404 can be coated or dispensed on the substrate 100 in sequence to completely cover the light-transmitting pillars 300 and fill the spaces between the plurality of light-transmitting pillars 300, and then a curing process is performed to cure the light shielding material to form the light shielding layer 400. For example, the curing process can be a photocuring process, a thermal curing process, or a combination thereof.

[0045] In other embodiments, the bottom light shielding layer 402 and the top light shielding layer 404 may include the same material, such as a thermal curing material. In the above embodiment, a first heat treatment process may be performed after the material of the bottom light shielding layer 402 is coated on the substrate 100 and before the material of the top light shielding layer 404 is coated, and a second heat treatment process may be performed after the material of the top light shielding layer 404 is coated on the substrate 100. In this way, since the material of the bottom light shielding layer 402 undergoes one more heat treatment process than the material of the top light shielding layer 404, the hardness of the bottom light shielding layer 402 is greater than the hardness of the top light shielding layer 404. In some embodiments, the first heat treatment process and / or the second heat treatment process may be performed at a temperature of about 100°C to about 200°C, for example, about 150°C. In some embodiments, the first heat treatment process and / or the second heat treatment process may be performed for a time of about 60 minutes to about 120 minutes, for example, about 90 minutes. For example, the heat treatment process may include a baking process.

[0046] In some embodiments, Figure 1B As shown, a distance S1 between the bottom surface of the top light shielding layer 404 and the top surface of the light-transmitting rod 300 is in a range from about 50 micrometers to about 250 micrometers.

[0047] Then, if Figure 1C As shown, the light shielding layer 400 is planarized to planarize the top light shielding layer 404, so that the top surface of the light-transmitting column 300 is exposed from the top light shielding layer 404. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process, a grinding process, other suitable processes, or a combination thereof. In some embodiments, after the planarization process, the top surface of the top light shielding layer 404 is flush with the top surface of the light-transmitting column 300, such as Figure 1CAs shown. In some embodiments, after the planarization process, the thickness of the top light shielding layer 404 is, for example, in a range of greater than 1 micron to about 200 microns. In some embodiments, after the planarization process and before the reliability test, the mask layer 400 may be subjected to a third heat treatment process to make the semiconductor device have better reliability. In an embodiment in which the bottom light shielding layer 402 and the top light shielding layer 404 include different materials, after the third heat treatment process, the bottom light shielding layer 402 and the top light shielding layer 404 still have different hardnesses. In an embodiment in which the bottom light shielding layer 402 and the top light shielding layer 404 include the same material, after the third heat treatment process, the bottom light shielding layer 402 and the top light shielding layer 404 have the same hardness. In some embodiments, the aforementioned third heat treatment process may be performed at a temperature of about 100°C to about 200°C, for example, about 150°C. In some embodiments, the aforementioned third heat treatment process may be performed for a time of about 60 minutes to about 120 minutes, for example, about 90 minutes. For example, the aforementioned third heat treatment process may include a baking process.

[0048] In some embodiments, Figure 1C As shown, a backside thinning process may be performed on the bottom surface of the substrate 100 to thin the substrate 100 , such as a chemical mechanical polishing (CMP) process, a grinding process, other suitable processes, or a combination thereof, to form a thinned substrate 100 ′.

[0049] As mentioned previously, the combination of the light-transmitting pillars 300 disposed on the sensing pixels 202 and the light-shielding layers 400 filled between the light-transmitting pillars 300 together constitute a light-collimating layer 600. The function of this light-collimating layer is to collimate the light to reduce the energy loss caused by light divergence. In some embodiments, other optical elements may be included above the light-collimating layer, such as: color filters, glass, lenses, etc. (not shown). In some embodiments, the incident light is guided to the sensing pixels 202 through the optical elements above the light-collimating layer 600 through the light-collimating layer 600.

[0050] In some embodiments, the light collimating layer 600 may include a cover layer (not shown) disposed on the light collimating layer 600. The cover layer may be a hard light-transmitting material, such as calcium aluminosilicate glass, soda lime glass, sapphire, transparent polymer, or other suitable materials, so that at least a portion of the incident light can pass through and reach the sensing pixel 202, and the hard cover can protect the semiconductor device 10 and other components thereunder.

[0051] In the above-mentioned embodiment, by forming the light-shielding layer filled between the light-transmitting columns into a multilayer film structure with different hardnesses, the light-transmitting columns can be prevented from collapsing due to the light-shielding layer being too soft or cracks can be prevented due to the light-shielding layer being too hard, thereby improving the reliability and process yield of the semiconductor device.

[0052] Figure 2A and Figure 2B According to some embodiments, a method for forming Figure 2B Schematic cross-sectional views of various intermediate stages of an exemplary method of a semiconductor device 20 of the present invention. For the sake of clarity, similar or identical components and processes will use the same reference symbols. For the purpose of simplicity, the description of these processes and devices will not be repeated here.

[0053] exist Figure 2A and Figure 2B In the embodiment described above, except that the light shielding layer 400 ′ further includes an intermediate light shielding layer 403 , the method for forming the semiconductor structure 20 is similar to the method for forming the semiconductor structure 10 .

[0054] Please refer to Figure 2A , first formed as Figure 1A Next, a bottom light shielding layer 402, a middle light shielding layer 403, and a top light shielding layer 404 are sequentially formed on the substrate 100 to form a light shielding layer 400'. The bottom light shielding layer 402, the middle light shielding layer 403, and the top light shielding layer 404 are filled between the plurality of light-transmitting columns 300, and the top light shielding layer 404 covers the top surface of the light-transmitting column 300. In this embodiment, since the light shielding layer 400' has a larger number of film layers, the mechanical properties of the light shielding layer 400' can be adjusted more flexibly.

[0055] In this embodiment, the middle light shielding layer 403 includes a material different from that of the bottom light shielding layer 402 and the top light shielding layer 404, so that each film layer of the light shielding layer 400' has a hardness that varies between soft and hard. For example, the hardness of the middle light shielding layer 403 is greater than the hardness of the bottom light shielding layer 402 and the top light shielding layer 404, so that the hardness of each film layer of the light shielding layer 400 has a soft-hard-soft variation. Alternatively, the hardness of the middle light shielding layer 403 is less than the hardness of the bottom light shielding layer 402 and the top light shielding layer 404, so that the hardness of each film layer of the light shielding layer 400 has a hard-soft-hard variation.

[0056] In some embodiments, the process and material for forming the intermediate light shielding layer 403 can be selected from the above Figure 1B The processes and materials used to form the bottom light shielding layer 402 and the top light shielding layer 404 are not described in detail here. Figure 2AIn the illustrated embodiment, the light shielding layer 400 ′ of the semiconductor device 20 has only one middle light shielding layer (eg, middle light shielding layer 403 ), but the present invention is not limited thereto, and the number of light shielding layer layers can be adjusted according to the characteristics required by actual products.

[0057] Then, if Figure 2B As shown, in some embodiments, the light shielding layer 400' may be subjected to a planarization process to planarize the top light shielding layer 404, so that the top surface of the light-transmitting column 300 is exposed from the top light shielding layer 404. In some embodiments, after the planarization process, the top surface of the top light shielding layer 404 is flush with the top surface of the light-transmitting column 300. As mentioned previously, the combination of the light-transmitting column 300 disposed on the sensing pixel 202 and the light shielding layer 400' filled between the light-transmitting column 300 together constitutes a light collimating layer 600. In some embodiments, a method similar to that described above regarding Figure 1C The light shielding layer 400' is planarized by the process for planarizing the light shielding layer 400, and thus will not be described in detail herein.

[0058] As mentioned previously, after the planarization process and before the reliability test, the light shielding layer 400' may be subjected to a heat treatment process to improve the reliability of the semiconductor device. This heat treatment process is similar to the third heat treatment process mentioned above, so it is not described here in detail. In this embodiment, since the middle light shielding layer 403 includes a material different from that of the bottom light shielding layer 402 and the top light shielding layer 404, after the heat treatment process, the film layers of the light shielding layer 400' still have a hardness that alternates between soft and hard.

[0059] In the above embodiment, an additional intermediate light-shielding layer may be formed in the light-shielding layer to more flexibly adjust the mechanical properties of the light-shielding layer.

[0060] like Figure 1C As shown, the semiconductor device 10 includes a substrate 100, a sensing pixel array 200 located in the substrate 100, and a plurality of light-transmitting pillars 300 located on the substrate 100. The sensing pixel array 200 includes a plurality of sensing pixels 202, and the light-transmitting pillars 300 are correspondingly disposed on the sensing pixels 202 of the sensing pixel array 200. The semiconductor device 10 further includes a light-shielding layer 400 located on the substrate 100 and filled between the light-transmitting pillars 300, wherein the light-shielding layer 400 is a multi-layer film structure. In some embodiments, the hardness of the light-shielding layer 400 is greater than the hardness of the light-transmitting pillars 300, so as to protect the light-transmitting pillars 300 from damage in subsequent processes.

[0061] In some embodiments, the light shielding layer 400 includes a bottom light shielding layer 402 and a top light shielding layer 404, wherein the bottom light shielding layer 402 and the top light shielding layer 404 have different hardnesses. In this embodiment, the light shielding layer filled between the light-transmitting pillars is formed into a multilayer film structure with different hardnesses, so that the light-transmitting pillars can be prevented from toppling due to the light shielding layer being too soft and the surface cracks can be prevented due to the light shielding layer being too hard after the planarization process, thereby improving the reliability and process yield of the semiconductor device.

[0062] In other embodiments, the light shielding layer of the semiconductor device may further include an intermediate light shielding layer 403 (e.g., the light shielding layer 400' of the semiconductor device 20) located between the bottom light shielding layer 402 and the top light shielding layer 404. In this embodiment, since the light shielding layer 400' has a larger number of film layers, the mechanical properties of the light shielding layer 400' can be adjusted more flexibly. In some embodiments, the hardness of the intermediate light shielding layer 403 is less than the hardness of the bottom light shielding layer 402 and the top light shielding layer 404, or the hardness of the intermediate light shielding layer 403 is greater than the hardness of the bottom light shielding layer 402 and the top light shielding layer 404.

[0063] In summary, the embodiments of the present invention form a multi-layer film structure with different hardnesses through forming the light-shielding layer filled between the light-transmitting layers, thereby avoiding the collapse of the light-transmitting column due to the light-shielding layer being too soft and the surface cracks caused by the light-shielding layer being too hard after the planarization process, thereby improving the reliability and process yield of the semiconductor device.

[0064] The above briefly describes the features of several embodiments of the present invention, so that those skilled in the art can more easily understand the present invention. Any person skilled in the art should understand that this specification can easily serve as a basis for the change or design of other structures or processes to achieve the same purpose and / or obtain the same advantages as the embodiments of the present invention. Any person skilled in the art can also understand that structures or processes equivalent to the above do not depart from the spirit and scope of protection of the present invention, and can be changed, replaced and modified without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that: include: forming a sensing pixel array in a substrate, wherein the sensing pixel array comprises a plurality of sensing pixels; Forming a plurality of light-transmitting columns on the substrate, which are correspondingly disposed on the sensing pixels of the sensing pixel array, and each of the light-transmitting columns has a continuous side surface; A light shielding layer is formed on the substrate to cover the light-transmitting column, wherein the light shielding layer is a multi-layer film structure, and the multi-layer film structure includes: a bottom light shielding layer, located on the substrate, wherein the bottom light shielding layer does not cover an upper portion of the continuous side surface of the light-transmitting column, and the bottom light shielding layer directly contacts a lower portion of the continuous side surface of the light-transmitting column and fills a space between the substrate and the lower portion of the continuous side surface of the light-transmitting column; a top light-shielding layer, located on the bottom light-shielding layer, and the top light-shielding layer directly contacts and covers the upper portion of the continuous side surface of the light-transmitting column, wherein the hardness of the top light-shielding layer is different from the hardness of the bottom light-shielding layer; and an intermediate light-shielding layer disposed between the top light-shielding layer and the bottom light-shielding layer, wherein the hardness of the intermediate light-shielding layer is different from the hardness of the top light-shielding layer and also different from the hardness of the bottom light-shielding layer; and A planarization process is performed to expose the top surface of the light-transmitting column.

2. The method for forming a semiconductor device according to claim 1, wherein: The hardness of the light shielding layer is greater than the hardness of the light-transmitting column.

3. The method for forming a semiconductor device according to claim 1, wherein: The step of forming the light shielding layer comprises: forming a bottom light shielding layer on the substrate; and A top light shielding layer is formed on the bottom light shielding layer, wherein the top light shielding layer covers the top surface of the light-transmitting column.

4. The method for forming a semiconductor device according to claim 3, wherein: Before the planarization process, the distance between the bottom surface of the top light-shielding layer and the top surface of the light-transmitting column is in the range of about 1 micron to about 200 microns, and after the planarization process, the top surface of the top light-shielding layer is flush with the top surface of the light-transmitting column.

5. The method for forming a semiconductor device according to claim 1, wherein: The top light shielding layer and the bottom light shielding layer are formed by using different materials.

6. The method for forming a semiconductor device according to claim 1, wherein: The top light shielding layer and the bottom light shielding layer are formed by using the same material.

7. The method for forming a semiconductor device according to claim 6, wherein: After forming the bottom light shielding layer and before forming the top light shielding layer, performing a first heat treatment process on the bottom light shielding layer; and After forming the top light shielding layer, a second heat treatment process is performed on the top light shielding layer and the bottom light shielding layer.

8. The method for forming a semiconductor device according to claim 7, wherein: The method further includes performing a third heat treatment process on the top light shielding layer and the bottom light shielding layer after the planarization process, so that the top light shielding layer and the bottom light shielding layer have the same hardness.

9. The method for forming a semiconductor device according to claim 1, wherein: The hardness of the middle light shielding layer is smaller than that of the bottom light shielding layer and the top light shielding layer.

10. The method for forming a semiconductor device according to claim 1, wherein: The hardness of the middle light shielding layer is greater than that of the bottom light shielding layer and the top light shielding layer.

11. The method for forming a semiconductor device according to claim 1, wherein: The middle light-shielding layer directly contacts the top light-shielding layer and the bottom light-shielding layer.

12. A semiconductor device, characterized in that: include: a sensing pixel array located in a substrate, wherein the sensing pixel array includes a plurality of sensing pixels; A plurality of light-transmitting columns are located on the substrate and are correspondingly disposed on the sensing pixels of the sensing pixel array, and each of the light-transmitting columns has a continuous side surface; as well as A light shielding layer is located on the substrate and filled between the light-transmitting columns, wherein the light shielding layer is a multi-layer film structure, and the multi-layer film structure includes: a bottom light shielding layer, located on the substrate, wherein the bottom light shielding layer does not cover an upper portion of the continuous side surface of the light-transmitting column, and the bottom light shielding layer directly contacts a lower portion of the continuous side surface of the light-transmitting column and fills a space between the substrate and the lower portion of the continuous side surface of the light-transmitting column; a top light-shielding layer, located on the bottom light-shielding layer, and the top light-shielding layer directly contacts and covers the upper portion of the continuous side surface of the light-transmitting column, wherein the hardness of the top light-shielding layer is different from the hardness of the bottom light-shielding layer; as well as A middle light-shielding layer is disposed between the top light-shielding layer and the bottom light-shielding layer, wherein the hardness of the middle light-shielding layer is different from the hardness of the top light-shielding layer and also different from the hardness of the bottom light-shielding layer.

13. The semiconductor device according to claim 12, wherein: The hardness of the light shielding layer is greater than the hardness of the light-transmitting column.

14. The semiconductor device according to claim 12, wherein: The thickness of the top light shielding layer is in a range from greater than 1 micron to about 200 microns.

15. The semiconductor device according to claim 12, wherein: The bottom light shielding layer and the top light shielding layer include different materials.

16. The semiconductor device according to claim 12, wherein: The hardness of the middle light shielding layer is smaller than that of the bottom light shielding layer and the top light shielding layer.

17. The semiconductor device according to claim 12, wherein: The hardness of the middle light shielding layer is greater than that of the bottom light shielding layer and the top light shielding layer.

18. The semiconductor device according to claim 12, wherein: The middle light-shielding layer directly contacts the top light-shielding layer and the bottom light-shielding layer.

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