Variable resistance memory devices

Abstract

A variable resistance memory device is provided, including a lower conductive line on a substrate, an upper conductive line on the lower conductive line to cross the lower conductive line, and a memory cell between the lower conductive line and the upper conductive line. The lower conductive lines extend in a first direction and are spaced apart from each other in a second direction crossing the first direction. Each of the lower conductive lines includes a first line portion extending in the first direction, a second line portion offset from the first line portion in the second direction and extending in the first direction, and a connection portion connecting the first line portion to the second line portion.

Description

[0001] This patent application claims priority from Korean Patent Application No. 10-2019-0132154 filed on October 23, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to semiconductor devices, and in particular, to variable resistance memory devices. Background Art

[0003] Semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices lose their stored data when their power supply is interrupted. Dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices are typical examples of volatile memory devices. In contrast, non-volatile memory devices retain their data even when their power supply is interrupted. Programmable read-only memory (PROM) devices, erasable programm ...

[0004] To meet the recent demand for semiconductor memory devices with high performance and low power consumption, next-generation semiconductor memory devices such as magnetic random access memory (MRAM) and phase change random access memory (PRAM) have been developed. The material or structure of such next-generation semiconductor memory devices has a resistance property that changes with current or voltage applied thereto and does not change even when the current supply or voltage supply is interrupted. Summary of the Invention

[0005] Example embodiments of the inventive concepts provide a variable resistance memory device having a reduced chip size.

[0006] Example embodiments of the inventive concepts provide a variable resistance memory device having a simple interconnection structure.

[0007] According to some example embodiments of the inventive concept, a variable resistance memory device may include: a substrate; lower conductive lines located on the substrate, the lower conductive lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; upper conductive lines located on the lower conductive lines to intersect the lower conductive lines; and memory cells located between the lower conductive lines and the upper conductive lines. Each of the lower conductive lines may include: a first line portion extending in the first direction; a second line portion offset from the first line portion in the second direction and extending in the first direction; and a connecting portion connecting the first line portion to the second line portion.

[0008] According to some example embodiments of the inventive concept, a variable resistance memory device may include: a substrate; a peripheral circuit portion located on the substrate; and a first unit stack and a second unit stack sequentially stacked on the peripheral circuit portion. The first unit stack may include: a first lower conductive line extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a first upper conductive line located on the first lower conductive line so as to intersect the first lower conductive line; and a first memory cell located between the first lower conductive line and the first upper conductive line. The second unit stack may include: a second lower conductive line extending in the first direction and spaced apart from each other in the second direction. The first lower conductive line and the second lower conductive line may be alternately arranged in the second direction.

[0009] According to some example embodiments of the inventive concept, a variable resistance memory device may include: a substrate; a peripheral circuit portion located on the substrate; and a first unit stack and a second unit stack sequentially stacked on the substrate. The second unit stack may include: a lower conductive line; an upper conductive line located on the lower conductive line so as to intersect the lower conductive line; a memory cell located between the lower conductive line and the upper conductive line; a lower contact connected to the lower conductive line; and an upper contact connected to the upper conductive line. Each of the lower contact and the upper contact penetrates the first unit stack and can be connected to the peripheral circuit portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0011] Figure 1 is a conceptual diagram illustrating a variable resistance memory device according to some example embodiments of the inventive concept.

[0012] Figure 2 yes Figure 1 Schematic plan view of a variable resistance memory device.

[0013] Figure 3 It is schematically shown Figure 1 A perspective view of each unit stack.

[0014] Figure 4 is a plan view illustrating a variable resistance memory device according to some example embodiments of the inventive concept.

[0015] Figure 5A 、 Figure 5B and Figure 5C Along the Figure 4 Cross-sectional views taken along line AA', line BB' and line CC'.

[0016] Figure 6 and Figure 7 are a plan view and a perspective view showing a portion of a first unit stack.

[0017] Figure 8 and Figure 9 are a plan view and a perspective view showing a portion of the second unit stack.

[0018] Figure 10 and Figure 11 are a plan view and a perspective view showing a portion of a third unit stack.

[0019] Figure 12 and Figure 13 Along the Figure 4 A cross-sectional view taken along line DD' and line EE'.

[0020] It should be noted that these drawings are intended to illustrate the general characteristics of the methods, structures and / or materials used in some example embodiments and are intended to supplement the written description provided below. However, these drawings are not to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment and should not be interpreted as defining or limiting the range or nature of the values ​​contained by the example embodiments. For example, the relative thickness and relative positioning of molecules, layers, regions and / or structural elements may be reduced or exaggerated for clarity. The use of similar reference numerals or identical reference numerals in different figures is intended to indicate the presence of similar elements or features or identical elements or features. DETAILED DESCRIPTION

[0021] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0022] Figure 1 is a conceptual diagram illustrating a variable resistance memory device according to some example embodiments of the inventive concept. Figure 2 yes Figure 1 A schematic plan view of a variable resistance memory device, Figure 3 It is schematically shown Figure 1 A perspective view of each unit stack.

[0023] Reference Figure 1 and Figure 2 , the variable resistance memory device 1000 may include a peripheral circuit portion PER located on a substrate 100 and a plurality of cell stacks CS sequentially stacked on the peripheral circuit portion PER. Figure 1An example including three cell stacks CS is shown, but the inventive concept is not limited to this example. The peripheral circuit portion PER may be disposed between the lowermost cell stack of the cell stacks CS and the substrate 100. The peripheral circuit portion PER may vertically overlap the cell stack CS and may be partially disposed below the cell stack CS.

[0024] Reference Figure 3 , each of the cell stacks CS may include a lower conductive line LCL, an upper conductive line UCL crossing the lower conductive line LCL, and a memory cell MC between the lower conductive line LCL and the upper conductive line UCL. The lower conductive lines LCL may extend in a first direction D1 and may be spaced apart from each other in a second direction D2 crossing the first direction D1. The upper conductive lines UCL may be spaced apart from the lower conductive lines LCL in a third direction D3 perpendicular to the first direction D1 and the second direction D2. The upper conductive lines UCL may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The first direction D1 and the second direction D2 may be parallel to Figure 1 The third direction D3 may be perpendicular to the top surface 100U of the substrate 100. The lower conductive lines LCL and the upper conductive lines UCL may be formed of or include at least one of a metal material (e.g., copper, tungsten, and / or aluminum) and / or a metal nitride (e.g., tantalum nitride, titanium nitride, and / or tungsten nitride).

[0025] Memory cells MC may be disposed at intersections of lower conductive lines LCL and upper conductive lines UCL. Memory cells MC may be arranged two-dimensionally in a first direction D1 and a second direction D2. Each memory cell MC may include a variable resistance pattern VR and a switch pattern SW. The variable resistance pattern VR and the switch pattern SW may be stacked in a third direction D3 between a pair of conductive lines LCL and UCL connected thereto. The variable resistance pattern VR and the switch pattern SW may be connected in series with each other. For example, the variable resistance pattern VR and the switch pattern SW included in each memory cell MC may be connected in series with each other between a corresponding lower conductive line LCL in the lower conductive lines LCL and a corresponding upper conductive line UCL in the upper conductive lines UCL. Figure 3 An example is shown in which the switch pattern SW is provided on the variable resistance pattern VR, but the inventive concept is not limited to this example. Figure 3 Unlike what is shown in FIG, the variable resistance pattern VR may be disposed on the switch pattern SW.

[0026] The variable resistance pattern VR may include a material having a variable resistance property, and this may enable the variable resistance pattern VR to be used as a data storage element. In some example embodiments, the variable resistance pattern VR may include a material whose phase changes to one of a crystalline structure and an amorphous structure according to the temperature of the material. The variable resistance pattern VR may include a compound containing at least one of chalcogenide elements (e.g., S, Te, and / or Se) and at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, Si, In, Ti, Ga, P, O, and C. For example, the variable resistance pattern VR may be formed of at least one of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe or include at least one of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe. In some example embodiments, the variable resistance pattern VR may have a superlattice structure in which a germanium-containing layer (e.g., a GeTe layer) and a germanium-free layer (e.g., an SbTe layer) are repeatedly stacked. In some example embodiments, the variable resistance pattern VR may be formed of or include at least one of a perovskite compound and / or a conductive metal oxide. For example, the variable resistance pattern VR may be formed of or include at least one of niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO ((Pr, Ca) MnO3), strontium titanium oxide, barium strontium titanium oxide, strontium zirconium oxide, barium zirconium oxide, and barium strontium zirconium oxide. In some example embodiments, the variable resistance pattern VR may have a double-layer structure including a conductive metal oxide layer and a tunnel insulating layer, or a triple-layer structure including a first conductive metal oxide layer, a tunnel insulating layer, and a second conductive metal oxide layer. In some example embodiments, the tunnel insulating layer may be formed of or include aluminum oxide, hafnium oxide, and / or silicon oxide.

[0027] In some example embodiments, the switch pattern SW may include a silicon diode or an oxide diode having a rectifying property. For example, the switch pattern SW may be composed of a silicon diode in which a p-type silicon layer and an n-type silicon layer are in contact with each other, or may be composed of a p-type NiO x layer and n-type TiO x layers are in contact with each other or p-type CuO xlayer and n-type TiO x In some example embodiments, the switch pattern SW may include an oxide material (eg, ZnO x MgO x and / or AlO x ), which has high resistance or current blocking properties under conditions below a specific voltage, and has low resistance or current conducting properties under conditions above a specific voltage. For example, in some example embodiments, the switch pattern SW may be a bidirectional threshold switch (OTS) device having bidirectional properties. In some example embodiments, the switch pattern SW may include a chalcogenide material in a substantially amorphous state. Here, the substantially amorphous state does not exclude a crystal structure of an object in which grains or partially crystallized portions exist. The chalcogenide material may include a compound containing at least one of chalcogen elements (such as S, Te, and / or Se) and at least one of Zn, Ge, Sb, Bi, Al, Pb, Sn, Ag, As, Si, In, Ti, Ga, and P. The chalcogenide material may, for example, include at least one of AsTe, AsSe, GeTe, SnTe, GeSe, SnSe, ZnTe, AsTeSe, AsTeGe, AsSeGe, AsTeGeSe, AsSeGeSi, AsTeGeSi, AsTeGeS, AsTeGeSiIn, AsTeGeSiP, AsTeGeSiSbS, AsTeGeSiSbP, AsTeGeSeSb, AsTeGeSeSi, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe and GeAsBiSe.

[0028] Each of the memory cells MC may further include an electrode layer EP disposed between the variable resistance pattern VR and the switch pattern SW. The electrode layer EP may electrically connect the variable resistance pattern VR to the switch pattern SW while preventing the variable resistance pattern VR from directly contacting the switch pattern SW. The electrode layer EP may be formed of or include, for example, at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

[0029] Return to reference Figure 1 and Figure 2The peripheral circuit portion PER may include a peripheral circuit for operating the memory cells MC of the cell stack CS. The peripheral circuit may include a first decoder circuit connected to the lower conductive line LCL of the cell stack CS, a second decoder circuit connected to the upper conductive line UCL of the cell stack CS, and an input / output (I / O) sense amplifier connected to the lower conductive line LCL or the upper conductive line UCL.

[0030] Figure 4 is a plan view illustrating a variable resistance memory device according to some example embodiments of the inventive concept, Figure 5A 、 Figure 5B and Figure 5C Along the Figure 4 For the sake of brevity, the following description will refer to an example of a variable resistance memory device 1000 in which three cell stacks CS are stacked.

[0031] Reference Figure 4 、 Figure 5A 、 Figure 5B and Figure 5C The peripheral circuit portion PER may be disposed on the substrate 100. The peripheral circuit portion PER may include a peripheral transistor PTR and a first interlayer insulating layer 110 covering the peripheral transistor PTR. The first interlayer insulating layer 110 may be formed of, or include, at least one of, for example, an oxide, a nitride, and / or an oxynitride. The first, second, and third cell stacks CS1, CS2, and CS3 may be sequentially stacked on the peripheral circuit portion PER. The peripheral transistor PTR may vertically overlap the first, second, and third cell stacks CS1, CS2, and CS3, and may be partially disposed below the first, second, and third cell stacks CS1, CS2, and CS3. The peripheral transistor PTR may constitute (or form) a peripheral circuit for operating the memory cells MC of the first, second, and third cell stacks CS1, CS2, and CS3.

[0032] The first cell stack CS1 may include a first lower conductive line LCL1, a first upper conductive line UCL1 intersecting the first lower conductive line LCL1, and a first memory cell MC1 between the first lower conductive line LCL1 and the first upper conductive line UCL1. The first lower conductive line LCL1 may be disposed on the first interlayer insulating layer 110. The first lower conductive lines LCL1 may extend in a first direction D1 and may be spaced apart from each other in a second direction D2. The first upper conductive line UCL1 may be vertically spaced apart from the first lower conductive line LCL1 in a third direction D3. The first upper conductive line UCL1 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. Each of the first lower conductive line LCL1 and the first upper conductive line UCL1 may be formed of or include at least one of a metal material (e.g., copper, tungsten, and / or aluminum) and / or a metal nitride (e.g., tantalum nitride, titanium nitride, and / or tungsten nitride). The first memory cell MC1 may be selectively disposed at an intersection of the first lower conductive line LCL1 and the first upper conductive line UCL1. Each of the first memory cells MC1 may include a reference Figure 3 The variable resistance pattern VR, the switch pattern SW and the electrode layer EP are described.

[0033] The first cell stack CS1 may include a second interlayer insulating layer 120 and a third interlayer insulating layer 130 sequentially stacked on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may cover the first lower conductive line LCL1 and may cover the side surface of the first memory cell MC1. The first upper conductive line UCL1 may be disposed on the second interlayer insulating layer 120. The third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120 to cover the first upper conductive line UCL1. The second interlayer insulating layer 120 and the third interlayer insulating layer 130 may be formed of or include, for example, at least one of an oxide, a nitride, and / or an oxynitride.

[0034] The first cell stack CS1 may include a first lower contact LCT1 selectively connected to the first lower conductive line LCL1 and a first upper contact UCT1 selectively connected to the first upper conductive line UCL1. Each of the first lower contacts LCT1 may extend vertically from the bottom surface of each of the first lower conductive lines LCL1 toward the substrate 100. Each of the first lower contacts LCT1 may be disposed to penetrate the first interlayer insulating layer 110 and may be connected to a terminal of a corresponding one of the peripheral transistors PTR. Each of the first upper contacts UCT1 may extend vertically from the bottom surface of each of the first upper conductive lines UCL1 to a region between adjacent ones of the first lower conductive lines LCL1. Each of the first upper contacts UCT1 may be disposed to penetrate the second interlayer insulating layer 120 between adjacent ones of the first memory cells MC1, penetrate the first interlayer insulating layer 110, and may be connected to a terminal of a corresponding one of the peripheral transistors PTR. Each of the first upper contacts UCT1 can penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120, so that the first upper contact UCT1 does not cross the first lower conductive line LCL1 and any of the first lower contacts LCT1, or alternatively, does not contact (e.g., directly contact, electrically contact) any of the first lower conductive line LCL1 and the first lower contact LCT1.

[0035] Figure 6 and Figure 7 1 and 2 are a plan view and a perspective view showing a portion of the first unit stack CS1.

[0036] Reference Figure 4 、 Figure 6 and Figure 7 , each of the first lower conductive lines LCL1 may include a first line portion LP1, a second line portion LP2, and a first connection portion CNP1, the first line portion LP1 extending in the first direction D1, the second line portion LP2 offset from the first line portion LP1 along the second direction D2 and extending in the first direction D1, and the first connection portion CNP1 connecting the first line portion LP1 to the second line portion LP2. Each of the first lower conductive lines LCL1 may have a meander line shape. The first lower conductive lines LCL1 may be arranged so that the first connection portions CNP1 of the first lower conductive lines LCL1 are aligned with each other in a fourth direction D4 intersecting the first direction D1 and the second direction D2. The fourth direction D4 may be parallel to Figure 1 The top surface 100U of the substrate 100 is formed.

[0037] The first line portion LP1 of each of the first lower conductive lines LCL1 may be disposed to intersect a corresponding first upper conductive line UCL1 of the first upper conductive lines UCL1. The second line portion LP2 of each of the first lower conductive lines LCL1 may be disposed to intersect a corresponding first upper conductive line UCL1 of the first upper conductive lines UCL1. The first memory cell MC1 may be selectively disposed at an intersection of the first line portion LP1 of each of the first lower conductive lines LCL1 and the first upper conductive line UCL1, and at an intersection of the second line portion LP2 of each of the first lower conductive lines LCL1 and the first upper conductive line UCL1.

[0038] Each of the first lower contacts LCT1 may extend vertically in the third direction D3. As an example, each of the first lower contacts LCT1 may be connected to the first line portion LP1 or the second line portion LP2 of each of the first lower conductive lines LCL1, but the inventive concept is not limited to this example. Each of the first lower contacts LCT1 may extend vertically from the bottom surface of each of the first lower conductive lines LCL1 toward the substrate 100 and may be connected to a corresponding peripheral transistor PTR of the peripheral transistors PTR.

[0039] Each of the first upper contacts UCT1 may be disposed between the first connection portions CNP1 of adjacent ones of the first lower conductive lines LCL1. Each of the first upper contacts UCT1 may be disposed closer to one of the adjacent ones of the first lower conductive lines LCL1. Each of the first upper contacts UCT1 may vertically extend from the bottom surface of each of the first upper conductive lines UCL1 to a region between the first connection portions CNP1 of adjacent ones of the first lower conductive lines LCL1 and may be connected to a corresponding one of the peripheral transistors PTR.

[0040] Return to reference Figure 4 、 Figure 5A 、 Figure 5B and Figure 5C The second cell stack CS2 may include a second lower conductive line LCL2, a second upper conductive line UCL2 intersecting the second lower conductive line LCL2, and a second memory cell MC2 between the second lower conductive line LCL2 and the second upper conductive line UCL2. The second lower conductive line LCL2 may be disposed on the third interlayer insulating layer 130. The second lower conductive lines LCL2 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. When viewed in a plan view, the first lower conductive lines LCL1 and the second lower conductive lines LCL2 may be alternately arranged in the second direction D2.

[0041] The second upper conductive lines UCL2 may be vertically spaced apart from the second lower conductive lines LCL2 in the third direction D3. The second upper conductive lines UCL2 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. When viewed in a plan view, the first upper conductive lines UCL1 and the second upper conductive lines UCL2 may be alternately arranged in the first direction D1.

[0042] The second lower conductive line LCL2 and the second upper conductive line UCL2 may be formed of or include at least one of a metal material (e.g., copper, tungsten, and / or aluminum) and / or a metal nitride (e.g., tantalum nitride, titanium nitride, and / or tungsten nitride). The second memory cell MC2 may be selectively disposed at an intersection of the second lower conductive line LCL2 and the second upper conductive line UCL2. Each of the second memory cells MC2 may include a reference Figure 3 The variable resistance pattern VR, the switch pattern SW and the electrode layer EP are described.

[0043] The second cell stack CS2 may include a fourth interlayer insulating layer 140 and a fifth interlayer insulating layer 150 sequentially stacked on the third interlayer insulating layer 130. The fourth interlayer insulating layer 140 may cover the second lower conductive line LCL2 and may cover the side surface of the second memory cell MC2. The second upper conductive line UCL2 may be disposed on the fourth interlayer insulating layer 140. The fifth interlayer insulating layer 150 may be disposed on the fourth interlayer insulating layer 140 to cover the second upper conductive line UCL2. The fourth interlayer insulating layer 140 and the fifth interlayer insulating layer 150 may be formed of or include, for example, at least one of an oxide, a nitride, and / or an oxynitride.

[0044] The second unit stack CS2 may include a second lower contact LCT2 and a second upper contact UCT2, the second lower contact LCT2 being selectively connected to the second lower conductive line LCL2, and the second upper contact UCT2 being selectively connected to the second upper conductive line UCL2. Each of the second lower contacts LCT2 may be configured to penetrate the first unit stack CS1 and may be connected to a terminal of a corresponding peripheral transistor PTR among the peripheral transistors PTR. Each of the second lower contacts LCT2 may extend vertically from the bottom surface of each of the second lower conductive lines LCL2 to a region between adjacent ones of the first lower conductive lines LCL1. Each of the second lower contacts LCT2 may be configured to penetrate the first interlayer insulating layer 110, the second interlayer insulating layer 120, and the third interlayer insulating layer 130 and may be connected to a corresponding one of the peripheral transistors PTR.

[0045] Each of the second upper contacts UCT2 may be configured to penetrate the first cell stack CS1 and may be connected to a terminal of a corresponding one of the peripheral transistors PTR. Each of the second upper contacts UCT2 may extend vertically from the bottom surface of each of the second upper conductive lines UCL2 to a region between adjacent ones of the second lower conductive lines LCL2, a region between adjacent ones of the first upper conductive lines UCL1, and a region between adjacent ones of the first lower conductive lines LCL1. Each of the second upper contacts UCT2 may penetrate not only the fourth interlayer insulating layer 140 between adjacent ones of the second memory cells MC2 but also the first interlayer insulating layer 110, the second interlayer insulating layer 120, and the third interlayer insulating layer 130, and may be connected to a corresponding one of the peripheral transistors PTR. Each of the second upper contacts UCT2 can penetrate the first unit stack CS1 and the second unit stack CS2 as described above, so that the second upper contact UCT2 does not cross any of the first lower conductive line LCL1, the first lower contact LCT1, the first upper conductive line UCL1, the first upper contact UCT1, the second lower conductive line LCL2, and the second lower contact LCT2, or alternatively, does not contact (e.g., directly contact, electrically contact) any of the first lower conductive line LCL1, the first lower contact LCT1, the first upper conductive line UCL1, the first upper contact UCT1, the second lower conductive line LCL2, and the second lower contact LCT2.

[0046] Figure 8 and Figure 9 1 and 2 are a plan view and a perspective view showing a portion of the second unit stack CS2.

[0047] Reference Figure 4 、 Figure 8 and Figure 9Each of the second lower conductive lines LCL2 may include a third line portion LP3, a fourth line portion LP4, and a second connection portion CNP2. The third line portion LP3 extends in the first direction D1, the fourth line portion LP4 is offset from the third line portion LP3 in the second direction D2 and extends in the first direction D1, and the second connection portion CNP2 is configured to connect the third line portion LP3 to the fourth line portion LP4. In some example embodiments, each of the second lower conductive lines LCL2 may have a meander line shape. The second lower conductive lines LCL2 may be arranged such that the second connection portions CNP2 of the second lower conductive lines LCL2 are aligned with each other in the fourth direction D4. When viewed in a plan view, the first lower conductive lines LCL1 and the second lower conductive lines LCL2 may be alternately arranged in the second direction D2. In some example embodiments, when viewed in a plan view, the first lower conductive lines LCL1 and the second lower conductive lines LCL2 may be arranged such that the first connection portions CNP1 and the second connection portions CNP2 are aligned with each other in the fourth direction D4.

[0048] The third line portion LP3 of each of the second lower conductive lines LCL2 may be disposed to intersect a corresponding second upper conductive line UCL2 of the second upper conductive lines UCL2. The fourth line portion LP4 of each of the second lower conductive lines LCL2 may be disposed to intersect a corresponding second upper conductive line UCL2 of the second upper conductive lines UCL2. The second memory cell MC2 may be selectively disposed at an intersection between the third line portion LP3 of each of the second lower conductive lines LCL2 and the second upper conductive line UCL2, and at an intersection between the fourth line portion LP4 of each of the second lower conductive lines LCL2 and the second upper conductive line UCL2.

[0049] Each of the second lower contacts LCT2 may extend vertically in the third direction D3. As an example, each of the second lower contacts LCT2 may be connected to the third line portion LP3 or the fourth line portion LP4 of each of the second lower conductive lines LCL2, but the inventive concept is not limited to this example. Each of the second lower contacts LCT2 may be arranged to penetrate the first unit stack CS1, and may be connected to a corresponding peripheral transistor PTR among the peripheral transistors PTR. In some example embodiments, each of the second lower contacts LCT2 may extend vertically from the bottom surface of each of the second lower conductive lines LCL2 to a region between adjacent ones of the first lower conductive lines LCL1, and may be connected to a corresponding peripheral transistor PTR among the peripheral transistors PTR. In some example embodiments, the first lower contacts LCT1 and the second lower contacts LCT2 may be arranged in a zigzag shape when viewed in a plan view, but the inventive concept is not limited to this example.

[0050] Each of the second upper contacts UCT2 may be disposed between the second connection portions CNP2 of adjacent ones of the second lower conductive lines LCL2. Each of the second upper contacts UCT2 may extend vertically from the bottom surface of each of the second upper conductive lines UCL2 to a region between the second connection portions CNP2 of adjacent ones of the second lower conductive lines LCL2. Each of the second upper contacts UCT2 may be disposed to penetrate the first cell stack CS1 and may be connected to a corresponding one of the peripheral transistors PTR. As an example, each of the second upper contacts UCT2 may extend into a region between adjacent ones of the first upper conductive lines UCL1 and into a region between the first connection portions CNP1 of adjacent ones of the first lower conductive lines LCL1 and may be connected to a corresponding one of the peripheral transistors PTR.

[0051] In some example embodiments, when viewed in a plan view, the first upper contact UCT1 and the second upper contact UCT2 may be disposed between the first connection portion CNP1 of the first lower conductive line LCL1 and the second connection portion CNP2 of the second lower conductive line LCL2, and may be aligned with the first connection portion CNP1 and the second connection portion CNP2 in the fourth direction D4.

[0052] Return to reference Figure 4 、 Figure 5A 、 Figure 5B and Figure 5C The third cell stack CS3 may include a third lower conductive line LCL3, a third upper conductive line UCL3 intersecting the third lower conductive line LCL3, and a third memory cell MC3 between the third lower conductive line LCL3 and the third upper conductive line UCL3. The third lower conductive line LCL3 may be disposed on the fifth interlayer insulating layer 150. The third lower conductive lines LCL3 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. When viewed in a plan view, the first lower conductive line LCL1, the second lower conductive line LCL2, and the third lower conductive line LCL3 may be alternately arranged in the second direction D2.

[0053] The third upper conductive lines UCL3 may be vertically spaced apart from the third lower conductive lines LCL3 in the third direction D3. The third upper conductive lines UCL3 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. When viewed in a plan view, the first upper conductive lines UCL1, the second upper conductive lines UCL2, and the third upper conductive lines UCL3 may be alternately arranged in the first direction D1.

[0054] The third lower conductive line LCL3 and the third upper conductive line UCL3 may be formed of or include at least one of a metal material (e.g., copper, tungsten, and / or aluminum) and / or a metal nitride (e.g., tantalum nitride, titanium nitride, and / or tungsten nitride). The third memory cell MC3 may be selectively disposed at an intersection of the third lower conductive line LCL3 and the third upper conductive line UCL3. Each of the third memory cells MC3 may include a reference Figure 3 The variable resistance pattern VR, the switch pattern SW and the electrode layer EP are described.

[0055] The third cell stack CS3 may include a sixth interlayer insulating layer 160 stacked on the fifth interlayer insulating layer 150. The sixth interlayer insulating layer 160 may cover the side surfaces of the third memory cells MC3 and the third lower conductive lines LCL3. The third upper conductive lines UCL3 may be disposed on the sixth interlayer insulating layer 160. The sixth interlayer insulating layer 160 may be formed of or include, for example, at least one of an oxide, a nitride, and / or an oxynitride.

[0056] The third cell stack CS3 may include a third lower contact LCT3 and a third upper contact UCT3. The third lower contact LCT3 is selectively connected to the third lower conductive line LCL3, and the third upper contact UCT3 is selectively connected to the third upper conductive line UCL3. Each of the third lower contacts LCT3 may be disposed to penetrate the first and second cell stacks CS1 and CS2 and may be connected to a terminal of a corresponding one of the peripheral transistors PTR. Each of the third lower contacts LCT3 may extend vertically from the bottom surface of each of the third lower conductive lines LCL3 to a region between adjacent ones of the second lower conductive lines LCL2 and a region between adjacent ones of the first lower conductive lines LCL1. Each of the third lower contacts LCT3 may be disposed to penetrate the first, second, third, fourth, and fifth interlayer insulating layers 110, 120, 130, 140, and 150 and may be connected to a corresponding one of the peripheral transistors PTR.

[0057] Each of the third upper contacts UCT3 can be configured to penetrate the first and second cell stacks CS1 and CS2 and can be connected to a terminal of a corresponding peripheral transistor PTR in the peripheral transistors PTR. Each of the third upper contacts UCT3 can vertically extend from the bottom surface of each of the third upper conductive lines UCL3 to a region between adjacent third lower conductive lines LCL3 in the third lower conductive lines LCL3. Each of the third upper contacts UCT3 can extend into a region between adjacent second upper conductive lines UCL2 in the second upper conductive lines UCL2, a region between adjacent second lower conductive lines LCL2 in the second lower conductive lines LCL2, a region between adjacent first upper conductive lines UCL1 in the first upper conductive lines UCL1, and a region between adjacent first lower conductive lines LCL1 in the first lower conductive lines LCL1, such that the third upper contact UCT3 does not cross any of the elements listed above, or alternatively, does not contact (e.g., directly contact, electrically contact) any of the elements listed above. Each of the third upper contacts UCT3 can be set to penetrate not only the sixth interlayer insulating layer 160 between adjacent third memory cells MC3 in the third memory cells MC3 but also the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, the fourth interlayer insulating layer 140 and the fifth interlayer insulating layer 150, and can be connected to the corresponding peripheral transistor PTR in the peripheral transistors PTR.

[0058] Figure 10 and Figure 11 1 and 2 are a plan view and a perspective view showing a portion of the third unit stack CS3.

[0059] Reference Figure 4 、 Figure 10 and Figure 11Each of the third lower conductive lines LCL3 may include a fifth line portion LP5 extending in the first direction D1, a sixth line portion LP6 offset from the fifth line portion LP5 in the second direction D2 and extending in the first direction D1, and a third connection portion CNP3 configured to connect the fifth line portion LP5 to the sixth line portion LP6. In some example embodiments, each of the third lower conductive lines LCL3 may have a meander line shape. The third lower conductive lines LCL3 may be arranged such that the third connection portions CNP3 of the third lower conductive lines LCL3 are aligned with each other in the fourth direction D4. When viewed in a plan view, the first lower conductive lines LCL1, the second lower conductive lines LCL2, and the third lower conductive lines LCL3 may be alternately arranged in the second direction D2. In some example embodiments, the first to third lower conductive lines LCL1, LCL2, and LCL3 may be disposed such that the first to third connection portions CNP1, CNP2, and CNP3 are aligned with each other in the fourth direction D4 when viewed in a plan view.

[0060] The fifth line portion LP5 of each of the third lower conductive lines LCL3 may be disposed to intersect a corresponding third upper conductive line UCL3 of the third upper conductive lines UCL3. The sixth line portion LP6 of each of the third lower conductive lines LCL3 may be disposed to intersect a corresponding third upper conductive line UCL3 of the third upper conductive lines UCL3. The third memory cell MC3 may be selectively disposed at an intersection between the fifth line portion LP5 of each of the third lower conductive lines LCL3 and the third upper conductive line UCL3, and at an intersection between the sixth line portion LP6 of each of the third lower conductive lines LCL3 and the third upper conductive line UCL3.

[0061] Each of the third lower contacts LCT3 may extend vertically in the third direction D3. For example, each of the third lower contacts LCT3 may be connected to the fifth line portion LP5 or the sixth line portion LP6 of each of the third lower conductive lines LCL3, however, the inventive concept is not limited to this example. Each of the third lower contacts LCT3 may be arranged to penetrate the first cell stack CS1 and the second cell stack CS2, and may be connected to a corresponding peripheral transistor PTR in the peripheral transistors PTR. In some example embodiments, each of the third lower contacts LCT3 may extend vertically from the bottom surface of each of the third lower conductive lines LCL3 to a region between adjacent second lower conductive lines LCL2 in the second lower conductive lines LCL2 and a region between adjacent first lower conductive lines LCL1 in the first lower conductive lines LCL1, and may be connected to a corresponding peripheral transistor PTR in the peripheral transistors PTR. In some example embodiments, when viewed in a plan view, the first lower contact LCT1, the second lower contact LCT2, and the third lower contact LCT3 may be arranged in a zigzag shape, however, the inventive concept is not limited to this example.

[0062] Each of the third upper contacts UCT3 may be disposed between the third connection portions CNP3 of adjacent ones of the third lower conductive lines LCL3. Each of the third upper contacts UCT3 may be disposed closer to one of the adjacent ones of the third lower conductive lines LCL3. Each of the third upper contacts UCT3 may extend vertically from the bottom surface of each of the third upper conductive lines UCL3 to a region between the third connection portions CNP3 of adjacent ones of the third lower conductive lines LCL3. Each of the third upper contacts UCT3 may be disposed to penetrate the first and second cell stacks CS1 and CS2 and may be connected to a corresponding one of the peripheral transistors PTR. As an example, each of the third upper contacts UCT3 may extend into a region between adjacent ones of the second upper conductive lines UCL2 and into a region between the second connection portions CNP2 of adjacent ones of the second lower conductive lines LCL2. Each of the third upper contacts UCT3 may extend into a region between adjacent ones of the first upper conductive lines UCL1 and a region between first connection portions CNP1 of adjacent ones of the first lower conductive lines LCL1 and may be connected to a corresponding one of the peripheral transistors PTR.

[0063] In some example embodiments, the first upper contact UCT1, the second upper contact UCT2, and the third upper contact UCT3 may be disposed between the first connection portion CNP1 of the first lower conductive line LCL1, the second connection portion CNP2 of the second lower conductive line LCL2, and the third connection portion CNP3 of the third lower conductive line LCL3 when viewed in a plan view, and may be aligned with the first connection portion CNP1, the second connection portion CNP2, and the third connection portion CNP3 in a fourth direction D4 when viewed in a plan view.

[0064] Figure 12 and Figure 13 Along the Figure 4 A cross-sectional view taken along line DD' and line EE'.

[0065] Reference Figure 4 and Figure 12When viewed in plan view, the first connection portion CNP1 of the first lower conductive line LCL1, the second connection portion CNP2 of the second lower conductive line LCL2, and the third connection portion CNP3 of the third lower conductive line LCL3 may be alternately arranged with the first upper contacts UCT1, the second upper contacts UCT2, and the third upper contacts UCT3 in a fourth direction D4. For example, each of the first upper contacts UCT1 may be offset from the first connection portion CNP1 of a corresponding one of the first lower conductive lines LCL1 along the fourth direction D4, may penetrate the first and second interlayer insulating layers 110 and 120, and may be connected to a corresponding one of the peripheral transistors PTR. The second connection portion CNP2 of each of the second lower conductive lines LCL2 may be offset from the corresponding one of the first upper contacts UCT1 along the fourth direction D4. Each of the third upper contacts UCT3 may be offset from the second connection portion CNP2 of a corresponding one of the second lower conductive lines LCL2 along the fourth direction D4, may penetrate the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, the fourth interlayer insulating layer 140, the fifth interlayer insulating layer 150, and the sixth interlayer insulating layer 160, and may be connected to the corresponding one of the peripheral transistors PTR. The third connection portion CNP3 of each of the third lower conductive lines LCL3 may be offset from the corresponding one of the third upper contacts UCT3 along the fourth direction D4. Each of the second upper contacts UCT2 may be offset from the third connection portion CNP3 of the corresponding one of the third lower conductive lines LCL3 along the fourth direction D4, may penetrate the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, and the fourth interlayer insulating layer 140, and may be connected to the corresponding one of the peripheral transistors PTR.

[0066] Reference Figure 4 and Figure 13The first lower conductive lines LCL1, the second lower conductive lines LCL2, and the third lower conductive lines LCL3 may be alternately arranged in the second direction D2. Each of the first lower contacts LCT1 may be connected to the first line portion LP1 or the second line portion LP2 of each of the first lower conductive lines LCL1, may penetrate the first interlayer insulating layer 110, and may be connected to a corresponding peripheral transistor PTR among the peripheral transistors PTR. Each of the second lower contacts LCT2 may be connected to the third line portion LP3 or the fourth line portion LP4 of each of the second lower conductive lines LCL2, may penetrate the first interlayer insulating layer 110, the second interlayer insulating layer 120, and the third interlayer insulating layer 130, and may be connected to a corresponding peripheral transistor PTR among the peripheral transistors PTR. Each of the third lower contacts LCT3 may be connected to the fifth line portion LP5 or the sixth line portion LP6 of each of the third lower conductive lines LCL3, may penetrate the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, the fourth interlayer insulating layer 140, and the fifth interlayer insulating layer 150, and may be connected to a corresponding one of the peripheral transistors PTR. In some example embodiments, the first lower contact LCT1, the second lower contact LCT2, and the third lower contact LCT3 may be arranged to form, for example, a zigzag arrangement in the second direction D2 when viewed in a plan view.

[0067] According to some example embodiments of the inventive concept, the first lower conductive line LCL1 and the first upper conductive line UCL1 may be connected to the peripheral transistor PTR for operating the first memory cell MC1 through the first lower contact LCT1 and the first upper contact UCT1. Each of the first lower contacts LCT1 may extend vertically from the bottom surface of each of the first lower conductive lines LCL1 toward the substrate 100 and may be connected to a corresponding one of the peripheral transistors PTR, and each of the first upper contacts UCT1 may extend vertically from the bottom surface of each of the first upper conductive lines UCL1 to a region between adjacent ones of the first lower conductive lines LCL1 and may be connected to a corresponding one of the peripheral transistors PTR. Therefore, the peripheral transistor PTR for operating the first memory cell MC1 may be locally disposed below the cell stacks CS1, CS2, and CS3.

[0068] The second lower conductive line LCL2 and the second upper conductive line UCL2 can be connected to the peripheral transistor PTR for operating the second memory cell MC2 through the second lower contact LCT2 and the second upper contact UCT2. Each of the second lower contact LCT2 and the second upper contact UCT2 can penetrate the first cell stack CS1 and can be connected to a corresponding peripheral transistor PTR among the peripheral transistors PTR. Therefore, the peripheral transistor PTR for operating the second memory cell MC2 can be locally disposed below the cell stacks CS1, CS2, and CS3.

[0069] Furthermore, the third lower conductive line LCL3 and the third upper conductive line UCL3 may be connected to the peripheral transistor PTR for operating the third memory cell MC3 through the third lower contact LCT3 and the third upper contact UCT3. Each of the third lower contact LCT3 and the third upper contact UCT3 may penetrate the first cell stack CS1 and the second cell stack CS2 and may be connected to a corresponding one of the peripheral transistors PTR. Thus, the peripheral transistor PTR for operating the third memory cell MC3 may be locally disposed below the cell stacks CS1, CS2, and CS3.

[0070] Since the peripheral transistors PTR for operating the memory cells MC1, MC2, and MC3 are locally disposed below the cell stacks CS1, CS2, and CS3, the chip size of the variable resistance memory device in which the plurality of cell stacks CS1, CS2, and CS3 are stacked can be reduced. Furthermore, since each of the first, second, and third lower contacts LCT1, LCT2, and LCT3, and the first, second, and third upper contacts UCT1, UCT2, and UCT3 are connected to a corresponding one of the peripheral transistors PTR via the following structure, the interconnect structure connecting the first, second, and third lower conductive lines LCL1, LCL2, and LCL3, and the first, second, and third upper conductive lines UCL1, UCL2, and UCL3, to the peripheral transistors PTR can be simplified.

[0071] Therefore, a variable resistance memory device having a reduced chip size and a simple interconnection structure can be provided.

[0072] In the following, reference will be made to Figure 4 and Figures 5A to 5C Methods for manufacturing a variable resistance memory device according to some example embodiments of the inventive concept are described. Figures 1 to 13 The described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0073] Reference Figure 4 、 Figure 5A 、 Figure 5B and Figure 5C A peripheral transistor PTR may be formed on the substrate 100. The peripheral transistor PTR may be, for example, a metal oxide semiconductor field effect transistor (MOSFET). A first interlayer insulating layer 110 may be formed on the substrate 100 to cover the peripheral transistor PTR.

[0074] A first lower contact LCT1 may be formed in the first interlayer insulating layer 110. In some example embodiments, forming the first lower contact LCT1 may include: forming a first lower contact hole in the first interlayer insulating layer 110; forming a conductive layer on the first interlayer insulating layer 110 to fill the first lower contact hole; and planarizing the conductive layer to expose a top surface of the first interlayer insulating layer 110. As a result of the planarization process, the first lower contact LCT1 may be partially formed in the first lower contact hole.

[0075] A first lower conductive line LCL1 may be formed on the first interlayer insulating layer 110. The first lower conductive line LCL1 may be formed to be selectively connected to the first lower contact LCT1. The step of forming the first lower conductive line LCL1 may include: forming a conductive layer on the first interlayer insulating layer 110; and patterning the conductive layer. As a result of the patterning process, the first lower conductive line LCL1 may be formed as shown in FIG. Figure 4 、 Figure 6 and Figure 7 The depicted embodiment has a meander line shape. A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110 to cover the first lower conductive line LCL1. A first memory cell MC1 may be formed in the second interlayer insulating layer 120. Forming the first memory cell MC1 may include: forming a plurality of holes in the second interlayer insulating layer 120 to define regions where the first memory cell MC1 will be formed; and locally forming the first memory cell MC1 in the holes.

[0076] First upper contacts UCT1 may be formed in the second interlayer insulating layer 120 and may extend into the first interlayer insulating layer 110. Each of the first upper contacts UCT1 may be formed to penetrate the first and second interlayer insulating layers 110 and 120. As an example, the step of forming the first upper contacts UCT1 may include: forming a first upper contact hole penetrating the first and second interlayer insulating layers 110 and 120; forming a conductive layer on the second interlayer insulating layer 120 to fill the first upper contact hole; and planarizing the conductive layer to expose the top surface of the second interlayer insulating layer 120. As a result of the planarization process, the first upper contacts UCT1 may be partially formed in the first upper contact holes.

[0077] A first upper conductive line UCL1 may be formed on the second interlayer insulating layer 120 to intersect the first lower conductive line LCL1. The first upper conductive line UCL1 may be selectively connected to the first upper contact UCT1. Forming the first upper conductive line UCL1 may include forming a conductive layer on the second interlayer insulating layer 120 and patterning the conductive layer. A third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120 to cover the first upper conductive line UCL1.

[0078] The second lower contacts LCT2 may be formed in the third interlayer insulating layer 130 and may extend into the first interlayer insulating layer 110 and the second interlayer insulating layer 120. Each of the second lower contacts LCT2 may be formed to penetrate the first interlayer insulating layer 110, the second interlayer insulating layer 120, and the third interlayer insulating layer 130. In some example embodiments, the step of forming the second lower contacts LCT2 may include: forming a second lower contact hole penetrating the first interlayer insulating layer 110, the second interlayer insulating layer 120, and the third interlayer insulating layer 130; forming a conductive layer on the third interlayer insulating layer 130 to fill the second lower contact hole; and planarizing the conductive layer to expose the top surface of the third interlayer insulating layer 130. As a result of the planarization process, the second lower contacts LCT2 may be locally formed in the second lower contact hole.

[0079] A second lower conductive line LCL2 may be formed on the third interlayer insulating layer 130. The second lower conductive line LCL2 may be selectively connected to the second lower contact LCT2. The step of forming the second lower conductive line LCL2 may include: forming a conductive layer on the third interlayer insulating layer 130; and patterning the conductive layer. As a result of the patterning process, the second lower conductive line LCL2 may be formed as shown in FIG. Figure 4 、 Figure 8 and Figure 9 The depicted memory cell MC2 has a meander line shape. A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130 to cover the second lower conductive line LCL2. A second memory cell MC2 may be formed in the fourth interlayer insulating layer 140. The second memory cell MC2 may be formed by substantially the same method as that used for the first memory cell MC1.

[0080] Second upper contacts UCT2 may be formed in the fourth interlayer insulating layer 140 and may extend into the first interlayer insulating layer 110, the second interlayer insulating layer 120, and the third interlayer insulating layer 130. Each of the second upper contacts UCT2 may be formed to penetrate the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, and the fourth interlayer insulating layer 140. In some example embodiments, forming the second upper contacts UCT2 may include: forming a second upper contact hole penetrating the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, and the fourth interlayer insulating layer 140; forming a conductive layer on the fourth interlayer insulating layer 140 to fill the second upper contact hole; and planarizing the conductive layer to expose the top surface of the fourth interlayer insulating layer 140. As a result of the planarization process, the second upper contacts UCT2 may be partially formed in the second upper contact holes.

[0081] A second upper conductive line UCL2 may be formed on the fourth interlayer insulating layer 140 to intersect the second lower conductive line LCL2. The second upper conductive line UCL2 may be selectively connected to the second upper contact UCT2. Forming the second upper conductive line UCL2 may include forming a conductive layer on the fourth interlayer insulating layer 140 and patterning the conductive layer. A fifth interlayer insulating layer 150 may be formed on the fourth interlayer insulating layer 140 to cover the second upper conductive line UCL2.

[0082] A third lower contact LCT3 may be formed in the fifth interlayer insulating layer 150 and may extend into the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, and the fourth interlayer insulating layer 140. Each of the third lower contacts LCT3 may penetrate the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, the fourth interlayer insulating layer 140, and the fifth interlayer insulating layer 150. The third lower contact LCT3 may be formed by substantially the same method as that for the second lower contact LCT2.

[0083] A third lower conductive line LCL3 may be formed on the fifth interlayer insulating layer 150. The third lower conductive line LCL3 may be selectively connected to the third lower contact LCT3. The step of forming the third lower conductive line LCL3 may include: forming a conductive layer on the fifth interlayer insulating layer 150; and patterning the conductive layer. As a result of the patterning process, the third lower conductive line LCL3 may be formed as shown in FIG. Figure 4 、 Figure 10 and Figure 11The depicted memory cell has a meander line shape. A sixth interlayer insulating layer 160 may be formed on the fifth interlayer insulating layer 150 to cover the third lower conductive line LCL3. A third memory cell MC3 may be formed in the sixth interlayer insulating layer 160. The third memory cell MC3 may be formed by substantially the same method as that used for the first and second memory cells MC1 and MC2.

[0084] A third upper contact UCT3 may be formed in the sixth interlayer insulating layer 160 and may extend into the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, the fourth interlayer insulating layer 140, and the fifth interlayer insulating layer 150. Each of the third upper contacts UCT3 may be provided to penetrate the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, the fourth interlayer insulating layer 140, the fifth interlayer insulating layer 150, and the sixth interlayer insulating layer 160. The third upper contact UCT3 may be formed by substantially the same method as that used for the second upper contact UCT2.

[0085] A third upper conductive line UCL3 may be formed on the sixth interlayer insulating layer 160 to cross the third lower conductive line LCL3. The third upper conductive line UCL3 may be selectively connected to the third upper contact UCT3. The third upper conductive line UCL3 may be formed by substantially the same method as that used for the second upper conductive line UCL2.

[0086] According to some example embodiments of the inventive concepts, it may be possible to implement a variable resistance memory device having a reduced chip size and a simple interconnection structure.

[0087] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A variable resistance memory device, comprising: lower conductive lines located on the substrate, the lower conductive lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; an upper conductive line positioned on the lower conductive line to cross the lower conductive line; as well as A memory cell is located between the lower conductive line and the upper conductive line. wherein each of the lower conductive lines includes: a first line portion extending in a first direction; a second line portion offset from the first line portion along a second direction and extending in the first direction; and a connecting portion connecting the first line portion to the second line portion, and The connection portions of the lower conductive lines are aligned with each other in a third direction crossing the first direction and the second direction.

2. The variable resistance memory device according to claim 1, wherein The memory cell is located at an intersection between the first line portion and the upper conductive line and at an intersection between the second line portion and the upper conductive line.

3. The variable resistance memory device according to claim 1 , further comprising: upper contacts, connected to the upper conductive wires, At least one of the upper contact members is located between connecting portions of adjacent lower conductive lines.

4. The variable resistance memory device according to claim 3, wherein: The at least one of the upper contacts extends from a bottom surface of a corresponding one of the upper conductive lines into a region between connection portions of adjacent ones of the lower conductive lines.

5. The variable resistance memory device according to claim 3 , further comprising: The peripheral transistor is located between the substrate and the lower conductive line. Wherein, the at least one upper contact among the upper contacts is connected to a terminal of a corresponding peripheral transistor among the peripheral transistors.

6. The variable resistance memory device according to claim 5, further comprising: The lower contact, connected to the lower conductive wire, At least one of the lower contacts extends from a bottom surface of a corresponding one of the lower conductive lines toward the substrate and is connected to a terminal of a corresponding one of the peripheral transistors.

7. The variable resistance memory device according to claim 1, wherein Each of the memory cells includes a variable resistance pattern and a switching pattern stacked in a direction perpendicular to a top surface of the substrate.

8. The variable resistance memory device according to claim 7, wherein: The variable resistance pattern includes a phase change material.

9. A variable resistance memory device, comprising: The peripheral circuit part is located on the substrate; as well as A first unit stack and a second unit stack are sequentially stacked on the peripheral circuit portion, The first unit stack includes: first lower conductive lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; first upper conductive lines located on the first lower conductive lines to intersect with the first lower conductive lines; and a first memory cell located between the first lower conductive lines and the first upper conductive lines. The second unit stack includes second lower conductive lines extending in the first direction and spaced apart from each other in the second direction, and The first lower conductive lines and the second lower conductive lines are alternately arranged in the second direction, Each of the first lower conductive lines comprises: a first line portion extending in a first direction; a second line portion offset from the first line portion in the second direction and extending in the first direction; and a first connecting portion connecting the first line portion to the second line portion, and The first connection portions of the first lower conductive lines are aligned with each other in a third direction crossing the first direction and the second direction.

10. The variable resistance memory device according to claim 9, wherein The second unit stack comprises: a second upper conductive line positioned on the second lower conductive line to cross the second lower conductive line; and a second memory cell located at an intersection between the second lower conductive line and the second upper conductive line, The first upper conductive lines and the second upper conductive lines extend in the second direction and are alternately arranged in the first direction.

11. The variable resistance memory device according to claim 9, wherein: The first unit stack further includes a first upper contact connected to the first upper conductive line, and At least one of the first upper contacts is located between first connection portions of adjacent ones of the first lower conductive lines and is connected to the peripheral circuit portion.

12. The variable resistance memory device according to claim 9, wherein Each of the second lower conductive lines comprises: a third line portion extending in the first direction; a fourth line portion offset from the third line portion in the second direction and extending in the first direction; and a second connecting portion, connecting the third line portion to the fourth line portion, The first connection portions of the first lower conductive lines and the second connection portions of the second lower conductive lines are alternately arranged in the third direction.

13. The variable resistance memory device according to claim 12, wherein: The second unit stack comprises: a second upper conductive line positioned on the second lower conductive line to cross the second lower conductive line; a second memory cell located at an intersection between the second lower conductive line and the second upper conductive line; and a second upper contact connected to a second upper conductive line, At least one of the second upper contacts is located between the second connection portions of adjacent second lower conductive lines and is connected to the peripheral circuit portion.

14. The variable resistance memory device according to claim 13, wherein: The first upper conductive lines and the second upper conductive lines extend in the second direction and are alternately arranged in the first direction, and The at least one of the second upper contacts penetrates the first unit stack and is connected to a peripheral circuit portion.

15. The variable resistance memory device according to claim 13, wherein: The at least one of the second upper contacts extends into a region between the first connection portions of adjacent ones of the first lower conductive lines.

16. The variable resistance memory device according to claim 9, wherein: The first unit stack includes: a first lower contact connected to the first lower conductive line, At least one of the first lower contacts extends from a bottom surface of a corresponding one of the first lower conductive lines toward the substrate and is connected to a peripheral circuit portion.

17. The variable resistance memory device according to claim 16, wherein: The second unit stack includes a second lower contact connected to the second lower conductive line, and At least one of the second lower contacts penetrates the first unit stack and is connected to a peripheral circuit portion.

18. A variable resistance memory device, comprising: The peripheral circuit part is located on the substrate; as well as A first unit stack and a second unit stack are sequentially stacked on a substrate, Wherein, the second unit stack includes: a lower conductive line; an upper conductive line positioned on the lower conductive line to cross the lower conductive line; a memory cell located between the lower conductive line and the upper conductive line; a lower contact connected to the lower conductive line; and upper contact, connected to the upper conductive wire, and wherein each of the lower contact and the upper contact penetrates the first unit stack and is connected to a peripheral circuit portion, Each of the first lower conductive lines comprises: a first line portion extending in a first direction; a second line portion offset from the first line portion in the second direction and extending in the first direction; and a first connecting portion connecting the first line portion to the second line portion, and The first connection portions of the first lower conductive lines are aligned with each other in a third direction crossing the first direction and the second direction.

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