Memory and semiconductor device including the same

Abstract

Embodiments of the present disclosure relate to a memory and a semiconductor device including the same. A TCAM (ternary content addressable memory) according to an embodiment includes a repeater in a delay path, the repeater being used to control timing in a replication circuit, which defines timing of a match. According to the above configuration, a TCAM that consumes low power and operates at high speed can be implemented.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a memory and a semiconductor device including the memory, and is particularly applicable to a content addressable memory which can be incorporated in a semiconductor device, and a semiconductor device incorporating the content addressable memory. BACKGROUND

[0002] Japanese Unexamined Patent Publication No. 2018-198104 discloses one exemplary configuration of a TCAM. SUMMARY

[0003] In a semiconductor device, a smaller area is achieved by miniaturizing the processing process, while the wiring resistance is increased by narrowing the width of the wiring. A TCAM (ternary content addressable memory) mounted on a semiconductor device to which a microfabrication process is applied can cause an increase in power consumption or a decrease in operation speed due to the amplitude of the meander resistor.

[0004] Other objects and novel features will become apparent from the description and drawings.

[0005] A typical aspect of the present disclosure will be briefly described below. That is, a TCAM according to an embodiment includes a repeater in a delay path for controlling timing in a replication circuit, which defines the timing of a match.

[0006] According to the above configuration, a TCAM that consumes low power and operates at high speed can be implemented. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram showing a main part of a TCAM according to a first embodiment.

[0008] Figure 2 is a diagram showing the relationship between the storage content of an SRAM cell and the data of a TCAM cell.

[0009] Figure 3 is a block diagram showing the configuration of a TCAM device according to the first embodiment.

[0010] Figure 4 is a diagram showing a main part related to timing control in a TCAM macro cell.

[0011] Figure 5 conceptually illustrates the planar layout of a TCAM macro cell.

[0012] Figure 6 is a timing diagram showing the operation timing of a TCAM search and match operation, and a replication circuit.

[0013] Figure 7is a schematic diagram illustrating a structure of a TCAM macro cell, the structure of the TCAM macro cell using cells arranged in a grid pattern.

[0014] Figure 8 is a timing chart showing a case where a potential of a match line rises due to a coupling effect with a search line.

[0015] Figure 9 is a diagram showing one exemplary cell layout of a replication path RPLP.

[0016] Figure 10 is a circuit diagram of a modification according to the first embodiment, showing one example of a configuration of an inverter having a test terminal in a TCAM cell array. DETAILED DESCRIPTION

[0017] Embodiments and examples will be described below with reference to the accompanying drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals, and repetitive description thereof can be omitted. In the drawings, configurations can be omitted or simplified for the convenience of description. Also, at least some of the embodiments and variations can be combined with each other arbitrarily.

[0018] [Embodiment 1]

[0019] (TCAM cell configuration)

[0020] Figure 1 is a circuit diagram showing a configuration of a main part of a TCAM cell according to the first embodiment. The TCAM 1 is a semiconductor integrated circuit, and includes a circuit formed on a semiconductor substrate (semiconductor chip) such as a single-crystal silicon substrate (semiconductor chip) using a known CMOS manufacturing process.

[0021] The TCAM cell MC (also referred to as a memory cell or a bit cell) includes two SRAM cells (static random access memory cells) 11 and 12, and a data comparator 13. The SRAM cell 11 is also referred to as an X cell, and the SRAM cell 12 is also referred to as a Y cell. The X cell 11 stores one-bit data complementary to each other (when one node is “1”, the data of the other bit becomes “0”) in an internal storage node pair ND1 and ND1_n. The Y cell 12 stores one-bit data complementary to each other in a storage node pair ND2 and ND2_n.

[0022] The TCAM cell is connected to a bit line pair BT and BB, a search line pair ST and SB, a match line ML, and word lines WLA and WLB. The bit line pair BT, BB is described later in detail. The search line pair ST, SB is described later in detail. The match line ML is described later in detail. The word lines WLA and WLB are described later in detail. Figure 3The search line pair ST and SB extends in the column direction (Y direction) of the TCAM cell array 20, and is shared by a plurality of TCAM cells arranged in the column direction. The match line ML extends in the row direction (X direction) of the TCAM cell array 20, and is shared by a plurality of TCAM cells arranged in the row direction. The word lines WLA and WLB extend in the row direction (X direction) of the TCAM cell array 20, and are shared by a plurality of TCAM cells arranged in the row direction. The word lines WLA and WLB can be referred to as a first word line and a second word line.

[0023] The match line ML extends in the row direction (X direction) of the TCAM cell array 20, and is shared by a plurality of TCAM cells arranged in the row direction. The word lines WLA and WLB extend in the row direction (X direction) of the TCAM cell array 20, and are shared by a plurality of TCAM cells arranged in the row direction. The word lines WLA and WLB can be referred to as a first word line and a second word line.

[0024] The X cell 11 includes inverters INV1, INV2, N-channel MOS (Metal Oxide Semiconductor) transistors Q1 and Q2. The inverter INV1 is connected between the storage node ND1 and the storage node ND1_n, such that the direction from the storage node ND1_n to the storage node ND1 is the forward direction. The inverter INV2 is connected in parallel with INV1, and is in the opposite direction to INV1. The MOS transistor Q1 is connected between the storage node ND1 and the bit line BT. The MOS transistor Q2 is connected between the storage node ND1_n and the bit line BB. The gates of the MOS transistors Q1 and Q2 are connected to the word line WLA.

[0025] The Y cell 12 includes inverters INV3, INV4, MOS (Metal Oxide Semiconductor) transistors Q3 and Q4. The inverter INV3 is connected between the storage node ND2 and the storage node ND2_n, such that the direction from the storage node ND2_n to the storage node ND2 is the forward direction. The inverter INV4 is connected in parallel with INV3, and is in the opposite direction to INV3. The MOS transistor Q3 is connected between the storage node ND2 and the bit line BT. The MOS transistor Q4 is connected between the storage node ND2_n and the bit line BB. The gates of the MOS transistors Q3 and Q4 are connected to the word line WLB.

[0026] The data comparator 13 includes N-channel MOS transistors Q6 to Q9. The MOS transistors Q6 and Q7 are connected in series between a node ND3 and a ground node GND, the node ND3 being a node at which the MOS transistors Q6 and Q7 are connected to the match line ML. The MOS transistors Q8 and Q9 are connected in series between the node ND3 and the ground node GND, and in parallel with the entirety of the series-connected MOS transistors Q6 and Q7. The gates of the MOS transistors Q6 and Q8 are connected to the storage nodes ND1, ND2, respectively. The gates of the MOS transistors Q7 and Q9 are connected to the search lines ST and SB, respectively.

[0027] When the memory cell is a BCAM (for example, in Figure 1 ), the word line WLB and the word line Y cell are deleted, and the gate of the MOS transistor Q8 is connected to the storage node ND1-n of the X cell.

[0028] Figure 2 is a table showing the correspondence between the storage contents of the X cell and the Y cell of Figure 1 and the data of the TCAM cell.

[0029] Referring to Figure 1 and Figure 2 , the TCAM cell can store three values "0", "1", and "x" (don't care) using a 2-bit SRAM cell. More specifically, when "1" is stored in the storage node ND1 of the X cell 11, and "0" is stored in the storage node ND2 of the Y cell 12, it is assumed that "0" is stored in the TCAM cell. When "0" is stored in the storage node ND1 of the X cell 11, and "1" is stored in the storage node ND2 of the Y cell 12, it is assumed that "1" is stored in the TCAM cell. When "0" is stored in the storage node ND1 of the X cell 11, and "0" is stored in the storage node ND2 of the Y cell 12, it is assumed that "x" (don't care) is stored in the TCAM cell. The case where "1" is stored in the storage node ND1 of the X cell 11, and "1" is stored in the storage node ND2 of the Y cell 12 is not used.

[0030] According to the configuration of the TCAM cell described above, when the search data is "1" (i.e., the search line ST is "1" and the search line SB is "0") and the TCAM data is "0" (the storage node ND1 is "1" and the storage node ND2 is "0"), the MOS transistors Q6 and Q7 are turned on so that the potential of the pre-charged match line ML is pulled to the ground potential. When the search data is "0" (i.e., the search line SL is "0" and the search line SL-n is "1") and the TCAM data is "1" (the storage node ND1 is "0" and the storage node ND2 is "1"), the MOS transistors Q8 and Q9 are turned on so that the potential of the pre-charged match line ML is pulled to the ground potential. That is, when the search data and the TCAM data do not coincide with each other, the potential of the match line ML is pulled to the ground potential.

[0031] On the contrary, when the input search data is "1" and the TCAM data is "1" or "x", or when the search data is "0" and the TCAM data is "0" or "X" (i.e., both coincide), the potential (power supply potential VDD level) of the pre-charged match line ML is maintained.

[0032] As described above, in the TCAM, as long as the data of all the TCAM cells to which the match line ML corresponding to at least one entry (row) is connected does not coincide with the input search data, the charge stored in the match line ML is extracted.

[0033] (array configuration)

[0034] Figure 3 is a diagram showing the configuration of a TCAM device according to the present embodiment. The TCAM device 1 includes a TCAM macro cell 10 and a priority encoder (PREN) 30. The TCAM macro cell 10 includes a TCAM cell array (CARY) 20 (also simply referred to as a cell array), an input / output (I / O) circuit 21, a match amplifier circuit (MA) 22, a control logic circuit (CNT) 23, a word line driver (WLD) 24, and a replication circuit (RPL) 25.

[0035] The cell array 20 includes TCAM cells arranged in a matrix (M+1 rows; n+1 columns). In the cell array 20, the number of rows (the number of entries) is M+1 (M is a positive integer), and the number of columns (the number of bits of the entries) is n+1 (n is a positive integer).

[0036] For each column of the cell array 20, n+1 bit line pairs (BT[0], BB[0] to BT[n], BB[n]) and n+1 search line pairs (ST[0], SB[0] to ST[n], SB[n]) are provided. Corresponding to each row of the cell array 20, M+1 match lines (ML[0] to ML[M]), M+1 word lines for X cells (WLA[0] to WLA[M]), and M+1 word lines for Y cells (WLB[0] to WLB[M]) are provided. The word lines WLA[0]-WLA[M] are first word lines, and the word lines WLB[0] to WLB[M] are second word lines.

[0037] The I / O circuit 21 includes a write driver WRD, a read sense amplifier SA, a search line driver SLD, and a copy circuit RPL. At the time of writing, the write driver WRD supplies write data to the corresponding TCAM cells via the bit line pairs BT and BB. The read sense amplifier SA amplifies data read from the TCAM cells via the bit line pairs BT and BB, and outputs the amplified data.

[0038] The search line driver SLD is also referred to as a selection circuit, and at the time of searching, supplies search data to the corresponding TCAM cells via the search line pairs ST[0], SB[0] to ST[n], SB[n]. As a result, when TCAM cell data coinciding with the input search data exists, the TCAM cell data along at least one of the word lines WLA and WLB is selected. That is, the search circuit includes the search line driver SLD and the search line pairs (ST[0], SB[0]-ST[n], SB[n]).

[0039] The control logic circuit (CNT) 23 controls the operation of the entire TCAM macro unit 10. For example, at the time of searching, the control logic circuit 23 receives a search command and outputs control signals to the search line driver SLD and the match amplifier circuit MA to control the operation of the search line driver SLD, the match amplifier circuit MA, and the precharge circuit PRCS. At the time of writing, the control logic circuit 23 outputs control signals to the write driver WRD and the word line driver WLD 24 to control the operation of the write driver WRD and the word line driver 24. The control logic circuit 23 outputs control signals to the word line driver 24 and the sense amplifier SA for reading to control the operation of the word line driver 24 and the sense amplifier SA for reading.

[0040] The match amplifier circuit MA 22 includes a plurality of match amplifiers MA0 to MAm corresponding to the rows of the cell array, respectively. The inputs of the match amplifiers MA0 to MAm are connected to the corresponding match lines ML (ML[0] to ML[M]), respectively, and the outputs of the match amplifiers MA0 to MAm are connected to the corresponding match signal output lines MLo (MLo0 to MLoM), respectively. At the time of search, the match amplifiers MA0 to MAm generate detection signals indicating whether or not the corresponding TCAM cell data matches the corresponding portion of the input search data based on the potentials of the corresponding match lines ML (ML[0] to ML[M]), and the match amplifiers MA0 to MAm output the detected signals to the corresponding match signal output lines MLo (MLo0 to MLoM). In this embodiment, the match amplifiers MA0 to MAm include a precharge circuit PRCS (not shown) for precharging the match lines ML[0] to ML[M] corresponding to the search. That is, the detection circuit includes the match amplifier circuit (MA) and the match lines ML (ML[0] to ML[M]).

[0041] The match amplifiers MA0 to MAm are connected to the control logic circuit 23 via a match line enable signal line MAE. As will be described later, the control logic circuit 23 is configured to activate (high level) or deactivate (low level) the match line enable signal line MAE. When the match output enable signal line MAE is not activated, the match amplifiers MA0 to MAm do not output the detection signals, and the match amplifiers MA0 to MAm output the detection signals in response to activation of the match output enable signal line MAE.

[0042] The copy circuit 25 defines a timing at which the control logic circuit 23 activates the match line enable signal line MAE by a delay circuit provided therein, which will be described later.

[0043] When the plurality of match signal output lines MLo0 to MLoM are set to indicate coincident signal levels at the time of search in the normal operation, a priority encoder (PREN) 30 is provided to select one match signal output line in accordance with a predetermined priority.

[0044] (Configuration example of clock generation circuit and copy circuit)

[0045] Figure 4 is a circuit diagram showing the main part relating to the timing control in the TCAM macro cell 10 of Figure 3 is a circuit diagram showing the main part relating to the timing control in the TCAM macro cell 10 of

[0046] The control logic circuit 23 includes a clock generation circuit 110 that generates an internal clock signal intclk from a main clock signal CLK. The replica circuit 25 includes a first forward wiring RPLML1, a repeater RP1, a second forward wiring RPLML2, a repeater RP2, a folding wiring RPLTN, a first return wiring BACKML1, a repeater RP3, and a second return wiring BACKML2. These elements are connected in series and to the control logic circuit 23. This series of paths is referred to as a replica path RPLP.

[0047] The clock generation circuit 110 includes inverters IV10 to IV13 or circuits OR10 to OR11, a delay circuit DLY, a set / reset latch circuit RSLT, and buffer amplifiers BA10 to BA11.

[0048] The main clock signal CLK is a clock signal that periodically transitions between two states of LOW (low potential state) and HIGH (high potential state). The internal clock signal intclk generated based on the main clock signal CLK is connected to the I / O circuit 21 via the buffer amplifier BA10, and to the match amplifier 22 via the buffer BA11. In response to the HIGH assertion of the internal clock signal intclk, the search line driver SLD in the I / O circuit 21 operates, and the match amplifier 22 turns off the pre-charge of the match line ML.

[0049] On the other hand, with respect to the replica circuit 25, the first forward direction line RPLML is shifted to the low level by the inverter IV12. Depending on whether the input signal is in the LOW state or the HIGH state, the repeaters RP1 to RP3 perform a regeneration operation, or a repetition operation, for outputting a LOW or HIGH signal. For example, the repeater RP1 that has detected that the first forward wiring RPLML has become LOW converts the second forward wiring RPLML to LOW.

[0050] The wirings and repeaters that constitute the replica path RPLP operate such that the first forward wiring ML1 and the second return wiring BACKML2 are at the same potential through the above-described voltage conversion interlocking. When both the first forward wiring RPLML and the second return wiring BACKML2 become LOW, the OR circuit OR11 outputs LOW. In response to this, the reset latch circuit RSLT in the clock generation circuit 110 is reset, and the internal clock signal intclk is deasserted low. When the OR circuit OR11 outputs LOW, the match line enable signal line MAE is asserted HIGH by means of IV13.

[0051] Here, since the plurality of capacitors C are connected to the replica path RPLP as a capacitive load, a delay depending on the wiring capacitance occurs in the voltage transition of the corresponding wiring in the replica path RPLP. Thus, by the signal passing through the replica path RSLT, a predetermined delay occurs by the set / reset latch circuit from the time when the internal clock signal intclk is asserted HIGH to the time when the internal clock signal intclk is de-asserted to the low level. The main function of the replica circuit 25 is to set the delay time longer than the time from the start of the operation of the search line driver SLD to the time when the state of the match line ML is determined, i.e., the timing of the state change of the replica match line. Since the match line enable signal line MAE is activated after the state of the match line ML is determined by the operation of the replica circuit 25, the match amplifier 22 can accept the result of the match operation at the desired timing.

[0052] In the design of the replica circuit as described above, the inventors have found the following problems. That is, in the front-end processing, the resistance of the wiring increases by the wiring miniaturization. Although the search operation of the TCAM is rate-limited by the operation of the match line, the resistor of the match line increases with the miniaturization of the interconnection, so that the speed of the state transition of the match line becomes slow. Then, the replica circuit needs to be designed to have a larger delay time to follow the delay time. The problems identified here are the following three. The first is that the transistors constituting the replica path RPLP flow through the replica path during the state transition, and the operating current increases. The second is that the hot carrier degradation of the transistors is significant due to the through current. The third is that the slow transition appears as a large variation in the delay time due to the variation in the threshold voltage of the transistor, which affects the slower TCAM operation speed and the poor timing margin. The present invention solves these problems, which are described in more detail below.

[0053] (TCAM macro cell layout example)

[0054] Figure 5 is a diagram conceptually showing Figure 4 the planar layout of the TCAM macro cell 10 of . Within the TCAM of the macro cell 10, regions in which the following items are formed are arranged sequentially along the Y direction: the word line driver (WLD) 24, the TCAM cell array (CARY) 20, and the match amplifier circuit (MA) 22. On the other hand, in the X direction, the formation region of the control logic circuit 23 is provided below the word line driver WLD 24. In the Y direction, on the right side of the control logic circuit 23, the formation regions of the replica circuit 25 and the I / O circuit 21 are arranged to be arranged side by side in the X direction. The wiring region TP is arranged on the right side of the replica circuit 25 and the I / O circuit 21 in the Y direction.

[0055] In the TCAM cell array 20, as one example, one match line ML is drawn, and the match line ML is arranged along the Y direction. In the TCAM cell array 20, further, a pair of word lines WLA and WLB arranged along the Y direction, a pair of bit lines BT and BB arranged along the X direction, and a pair of search lines ST and SB arranged along the X direction are drawn. In the replication circuit 25, a first forward wiring RPLML1, a second forward wiring RPLML2, a first return wiring BACKML1, a second return wiring BACKML2, and relays RP1, RP3 are drawn. The first forward wiring RPLML1, the second forward wiring RPLML2, the first return wiring BACKML1, and the second return wiring BACKML2 are arranged along the Y direction in parallel with the match line ML, respectively.

[0056] Since the length of the formation region of the TCAM cell array 20 in the Y direction is substantially the same as the length of the formation region of the replication circuit 25 in the Y direction, the wiring length of the outgoing path in the replication path RPLP (i.e., the wiring length obtained by adding the first outgoing path wiring RPLML1 and the second outgoing path wiring RPLML2) is designed to be substantially the same length as the wiring length of the match line ML. Similarly, the wiring length of the return path in the replication path RPLP (i.e., the wiring length obtained by adding the first return path wiring BACKML1 and the second return path wiring BACKML) is also designed to be substantially the same length as the wiring length of the match line ML. The length of the match line ML is determined to correspond to the width of the TCAM (i.e., the number of bits of one entry). That is, the replication circuit RPL can be considered to include a line (replication line) for replicating the match line ML.

[0057] Here, a capacitance is provided in the replication path RPLP by a parasitic capacitance, a capacitor, or the like, which has a value substantially equal to the value of the wiring capacitance of the parasitic capacitance including the match line ML.

[0058] In the replication path RPLP, the signal of the second forward path wiring RPLML2 is input to the return wiring RPLTN including the relay RP2, and the relay RP2 outputs a regenerated signal to the first return path wiring BACKML1. Here, the folding wiring RPLTN, the relay RP2, and the wiring of the input / output portion thereof are formed in the wiring region TP. In other words, a part of the replication circuit 25 is also formed over the wiring region TP.

[0059] Figure 6is a timing chart showing the operation timing of the TCAM search and match operation, and the operation of the replica circuit. In response to the transition of the main clock signal CLK from LOW to HIGH, the internal clock signal intclk changes from LOW to HIGH. In response to the change of the internal clock signal intclk to HIGH, the search lines ST and SB corresponding to the data to be searched change to HIGH, and the discharge of the corresponding match line ML begins when the data exists in the TCAM cell. At the same time, the discharge of the first forward direction line RPLMLl including the load capacitor C begins. When the potential of the first forward direction line RPLMLl falls below the threshold of the relay RP1 due to the discharge, the relay RP1 begins the discharge of the second forward direction line RPLML2 including the load capacitor C. When the potential of the second forward direction line RPLML2 falls below the threshold of the relay RP2, the relay RP2 begins the discharge of the first return line BACKMLl including the load capacitor C. When the potential of the first return line BACKMLl falls below the threshold of the relay RP3, the relay RP3 begins the discharge of the second return line BACKML2 including the load capacitor C. When the second return line BACKML2 changes to LOW by the voltage conversion of the replica path RPLP as described above, the match line enable signal line MAE becomes HIGH according to the circuit shown in Figure 4 In response to the assertion of the match line enable signal line MAE, the match amplifier circuit operates to output the search result from the match signal output line ML0. Similarly, in response to the change of the second return line BACKML2 to LOW, the reset latch circuit RST is reset, and the internal clock signal intclk changes from HIGH to LOW.

[0060] Here, by adjusting the capacitance of the load capacitor C to be applied to the replica path RPLP at the time of design, the delay timing of the voltage conversion is defined so that the timing te at which the match line enable signal line MAE is asserted becomes later than the timing tm at which the potential of the match line ML is determined to be a low potential as the search result. As a result, it is possible to prevent the match amplifier 22 from accepting data in a state in which the voltage of the match line ML is not determined, and to prevent the output of an incorrect search result.

[0061] The advantages of the replication path RPLP including the repeaters RP1 to RP3 will be described below. As described above, the replication path RPLP defines timing by using the timing of the transition of the potential of the replication path from HIGH to LOW. However, the signal whose potential is not in HIGH and not in the state in the middle of the transition causes a pass-through current to flow through the gates of the transistors included in the circuit. Therefore, the TCAM macro unit 10 requires a larger operating current, which prevents the TCAM macro unit 10 from consuming less power. Additionally, the pass-through current causes a large amount of hot carriers in the transistors included in the circuit, which deteriorates the characteristics of the transistors. Additionally, since the variation of the threshold value in the circuit is greatly affected, it is necessary to increase the time and voltage margin in the operation of the circuit, which also hinders the improvement of the operation speed. By providing the repeaters RP1 to RP3 in the replication path RPLP as in the present embodiment, the transition time of the potential of each wiring constituting the replication path RPLP can be shortened. In other words, the desired timing can be defined by the transition of the potential having a large slope and a large swing, so that a TCAM macro unit 10 having low power dissipation, high-speed operation, and high reliability can be provided.

[0062] Figure 7 is a conceptual diagram of the cell layout of the TCAM macro unit 10 according to the present embodiment. Figure 7 The positional relationship of each circuit or element is illustrated by regarding each circuit or element constituting the TCAM macro unit 10 as one cell, and arranging each cell in a grid pattern. Figure 7 It is shown that each of the word line driver WLD, the search line driver SLD, and the sense amplifier SA includes a plurality of cells. The width of the cells of the source line driver SLD, the word line driver WLD, and the sense amplifier SA in the Y direction corresponds to the width of one column of the TCAM cell array 20. That is, one cell corresponds to the bit line pair BT and BB, and the search line pair ST and SB. The width of the load capacitor C of each cell in the Y direction also corresponds to the width of one column of the TCAM cell array 20. As seen in the Y axis direction, the repeaters RP1 and RP3 are arranged near the center of the width of the TCAM cell array 20. In the present embodiment, the repeaters RP1 and RP3 are formed in regions corresponding to two cells of the load capacitor C. The control logic circuit 23 is distributed at positions not only along the positions of the word line driver 24 in the X direction, but also along the positions of the match amplifier circuit 22 and the repeater RP2 in the X direction. This is because, in some cases, among the circuit elements constituting the control logic circuit, the circuit elements related to the control of the match amplifier circuit 22 are expected to be arranged around the match amplifier circuit 22.

[0063] Additionally, according to Figure 7The load capacitance C and the repeaters RP1 to RP3 in the replica path RPLP are arranged between the TCAM cell array 20 and the search line driver SLD. As a result, when the search lines ST and SB are activated and the potential of the match line ML rises together with a coupling effect, the potential of the RPLP line (e.g., RPLML1) in the replica path also rises by the coupling effect, so that the potential of the replica path RPLP can follow the change in the potential of the match line ML.

[0064] Figure 8 is a timing chart showing a case where the potential of the match line ML rises due to the influence of coupling with the search lines ST and SB. When the potentials of the search lines ST and SB change from LOW to HIGH, the match line ML in the HIGH state becomes a high potential state. Therefore, the time until the match line ML is discharged in the matching operation and the potential becomes a LOW state becomes long. Since the potential of the RPLP line (e.g., RPLML1) in the replica path rises due to the same coupling effect, the time required for the potential to become a low state becomes long together with the coupling effect. The timing of asserting the match line enable signal line MAE can be delayed.

[0065] (load capacitance and repeater details)

[0066] Figure 9 is a diagram illustrating an exemplary cell layout of the replica path RPLP. Figure 9 is Figure 7 a conceptual diagram of the cell layout of Figure 7 The I / O circuit 21, the control logic circuit 23, and the replica circuit 25 have been described in detail. In Figure 9 In the embodiment shown in the drawing, the load capacitance C is implemented by the gate capacitance of a PMOS transistor. The gate voltage of the PMOS transistor can be controlled by the potentials of the gate control lines GC1 to GC4, which are connected to the control logic circuit 23. Therefore, the load capacitance C can be changed by changing the voltage applied to the gate of the PMOS transistor. In this embodiment mode, the load capacitor C is implemented by a PMOS transistor, but the load capacitor C can also be implemented by an NMOS transistor. Each of the repeaters RP1 and RP3 is formed in a cell having the same area as that of the load capacitor C.

[0067] The main effects of the TCAM macro cell 10 according to the present embodiment are as follows. In other words, a TCAM that consumes low power and operates at high speed can be implemented by strict timing design and high operation reliability.

[0068] [Modification of inverters of Embodiment 1]

[0069] Referring back to Figure 4, the TCAM macro cell 10 according to the first embodiment includes a plurality of inverters defining a predetermined timing in the circuit. Specifically, it is the inverters IV 12 and the inverters IV 13 that constitute the repeaters RP 1 to RP 3. Figure 10 A configuration example of an inverter INV T with test terminals is shown, the inverter INV T being a modified example of these inverters. Figure 10 The inverter INV T with test terminals is a circuit that is used to discharge the output node OUT when the potential of the input node IN is HIGH, and to charge the output node OUT when the potential of the input node IN is LOW.

[0070] Here, the test terminal inverter INV T is a circuit that can variably control the drivability, i.e., the ability to charge and discharge the output node OUT (in other words, the output current) through the test terminals TE 1 and TE 2. During normal operation, both TE 1 and TE 2 are low. In the TCAM search operation, where the state of the match line ML being high impedance needs to be read, but when current leakage occurs in the match line ML, the match line ML becomes low regardless of the search result, and a false search result can be output. This modification makes it possible to test for the presence or absence of this current leakage. More specifically, when the test terminal TE 1 is LOW, and the test terminal TE 2 is HIGH, the speed at which the output node is discharged is reduced, i.e., the drivability of the inverter is reduced, and the timing delay of the replica path RP LP is made longer. As a result, the timing at which the match line enable signal line MAE is asserted can be arbitrarily delayed, and it can be determined whether an abnormality such as current leakage occurs in the match line ML by comparing the output result with that at the time of normal operation.

[0071] On the other hand, when the test terminal TE 1 is set to HIGH, and the test terminal TE 2 is set to LOW, the speed at which the output node is discharged is improved, i.e., the drivability of the inverter node is increased, and the timing delay of the replica path RP LP is further increased. As a result, the timing at which the match line enable signal line MAE is asserted can be determined to be arbitrarily fast, and the operating margin of the TCAM macro cell 10 can be determined by comparing the output result with that at the time of normal operation.

[0072] According to this modification, it is possible to test whether an abnormality occurs in the operation of the match line ML. Additionally, the operating margin of the TCAM macro cell 10 can be tested.

[0073] Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the embodiments that have been described, and of course, various modifications can be made without departing from the spirit of the invention.

Claims

1. A content-addressable memory, comprising: Multiple content-addressable memory units; Multiple word lines are respectively coupled to the multiple content-addressable memory units; Multiple bit lines are respectively coupled to the multiple content-addressable memory cells; Multiple search lines are respectively coupled to the multiple content-addressable memory units; Multiple matching lines are respectively coupled to the multiple content-addressable memory units; A matching amplifier is coupled to the plurality of matching lines; An output selection circuit is configured to select and output at least one output of the matched amplifier; The replication circuit is configured to specify the timing of the output performed by the output selection circuit. The replication circuit includes: The copied wiring is formed parallel to the plurality of matching lines; Multiple delay elements, coupled to the replicated wiring; and Multiple repeater elements are disposed in the path of the replication wiring, wherein the replication circuit further includes output terminals and input terminals, the output terminals being configured to supply an output voltage to the replication wiring, and the input terminals being configured to input an input voltage. The replicated wiring includes: The first region is coupled to the output terminal; The second region is coupled to the input terminal; and The third region is neither coupled to the output terminal nor coupled to the input terminal. The plurality of repeater elements include: A first repeater circuit is disposed between the first region and the third region; and The second repeater circuit is located between the third zone and the second zone.

2. The content-addressable memory of claim 1, further comprising a search line driver configured to selectively supply voltage to the matching line. The copy wiring is disposed between the plurality of content-addressable memory cells and the search line driver.

3. The content-addressable memory according to claim 1, The timing of the output performed by the output selection circuit is specified based on the voltage transition timing of the low and high levels of the input voltage.

4. The content-addressable memory according to claim 1, The plurality of delay elements include: A first delay element is disposed in the first region; A second delay element is disposed in the second region; as well as A third delay element is disposed in the third region.

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