Semiconductor device including stacked data lines

Abstract

The present application relates to semiconductor devices including stacked data lines. Some embodiments include devices and methods of forming the devices. One of the devices includes a first conductive contact; a second conductive contact; multiple layers of conductive material stacked one above the other and located above the first and second conductive contacts; multiple layers of dielectric material interleaved with the multiple layers of conductive material, the multiple layers of conductive material and the multiple layers of dielectric material forming a material stack; a first conductive structure located on a first side of the material stack and contacting the first conductive contact and a first layer of conductive material in the multiple layers of conductive material; and a second conductive structure located on a second side of the material stack and contacting the second conductive contact and a second layer of conductive material in the multiple layers of conductive material.

Description

Technical Field

[0001] The present application relates to a semiconductor device, and in particular to a semiconductor device including stacked data lines. Background Art

[0002] Semiconductor devices such as memory devices are widely used in computers and many other electronic products to store information. Memory devices typically include memory cells and data lines to carry information (in the form of signals) to and from the memory cells. As the demand for memory cell density for a given device area increases, the number of data lines may also increase to keep pace with the increased memory cell density. However, due to area limitations in some conventional memory devices, increasing the number of data lines in such conventional memory devices may present challenges. Summary of the invention

[0003] On the one hand, the present application provides a device comprising: a first conductive contact; a second conductive contact; multiple layers of conductive material, which are stacked on top of each other and are located above the first and second conductive contacts; multiple layers of dielectric material, which are interlaced with the multiple layers of conductive material, and the multiple layers of conductive material and the multiple layers of dielectric material form a material stack; a first conductive structure, which is located on a first side of the material stack and contacts the first conductive contact and a first layer of conductive material in the multiple layers of conductive material; and a second conductive structure, which is located on a second side of the material stack and contacts the second conductive contact and a second layer of conductive material in the multiple layers of conductive material.

[0004] On the other hand, the present application provides a device comprising: a memory cell string; a data line located above the memory cell string, the data lines being stacked one above the other in different layers of the device; a conductive line coupled to the memory cell string and the data line, so that each of the conductive lines is coupled to a corresponding data line in the data lines and a corresponding memory cell string in the memory cell string; a selection transistor, each of the selection transistors being coupled between a memory cell of a corresponding memory cell string in the memory cell string and a corresponding conductive line in the conductive line; a selection gate shared by the selection transistors; and an access line shared by the memory cell string.

[0005] On the other hand, the present application provides a method comprising: forming multiple layers of conductive material stacked on top of each other and located above conductive contacts; forming multiple layers of dielectric material interlaced with the multiple layers of conductive material; forming a conductive structure contacting the conductive contacts and contacting a layer of conductive material in the multiple layers of conductive material; and forming a dielectric structure electrically separating the conductive structure from the multiple layers of conductive material except for the layer of conductive material.

[0006] On the other hand, the present application provides a method, which includes: forming a multi-layer first dielectric material and a multi-layer second dielectric material interlaced with the multi-layer first dielectric material, the multi-layer first dielectric material and the multi-layer second dielectric material are formed above the conductive contacts of the pillars of the memory cell string; forming a hard mask on the multi-layer first dielectric material and the multi-layer second dielectric material; removing a first portion of the multi-layer first dielectric material and a first portion of the multi-layer second dielectric material to form a first stepped structure and a second stepped structure in the remaining portion of the multi-layer first dielectric material and the remaining portion of the multi-layer second dielectric material, wherein when forming the first and second stepped structures, the second portion of the multi-layer first dielectric material under the hard mask and the multi-layer second dielectric material under the hard mask are not removed; The invention relates to a method for forming a conductive layer in a first material stack, wherein the conductive layer is formed by first and second stepped structures, wherein the conductive layer is provided with a conductive film having a first conductive surface and a second conductive film having a first conductive surface. The method comprises: removing the conductive layer from the first material stack and the conductive film having a second conductive surface. The method comprises: removing the conductive layer from the first material stack and the conductive film having a second conductive surface. The method comprises: removing the conductive layer from the first material stack and the conductive film having a second conductive surface. The method comprises: removing the conductive layer from the first material stack and the conductive film having a second conductive surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A portion of a schematic diagram of an apparatus in the form of a memory device having multiple sets of data lines according to one embodiment of the invention is shown.

[0008] Figure 2 An example is shown according to an embodiment of the present invention. Figure 1 Schematic diagram of a portion of a memory device of FIG. 1 , in which example the memory device includes nine data lines in each group of data lines.

[0009] Figure 3A According to some embodiments described herein Figure 2 A side view (eg, a cross section relative to the ZY direction) of a structure of a portion of a memory device including Figure 2 A structure of a set of data lines and a structure of a memory cell string of a memory device.

[0010] Figure 3B According to some embodiments described herein Figure 3AA top view (eg, a cross section relative to the XY plane) of a portion of a pillar of a memory cell string.

[0011] Figure 3C According to some embodiments described herein Figure 3A A top view (eg, a cross section relative to the XY plane) of conductive contacts of a pillar of a memory cell string.

[0012] Figure 4 A top view of a structure of a memory device according to some embodiments described herein is shown, which includes Figure 2 A data line of a memory device and a conductive contact (eg, a drain contact) of a corresponding memory cell string.

[0013] Figure 5 According to some embodiments described herein Figure 4 An isometric view of a portion of the structure of a memory device including a memory cell region and a data line stack of the memory device.

[0014] Figure 6 According to some embodiments described herein Figure 1 and Figure 2 A top view of the structure of a memory device including a memory cell block and a data line stack of the memory device.

[0015] Figures 7 to 31 Different views of elements during a process of forming a memory device, including forming a data line stack of the memory device, are shown according to some embodiments described herein. DETAILED DESCRIPTION

[0016] The technology described herein is a memory device with stacked data lines, where the data lines are stacked on top of each other in different layers (vertical layers) of the memory device. The stacked structure of the data lines described herein can increase the density of data lines in a given area. This can allow more memory cells to be coupled to the data lines. This can increase the density of memory cells in a given area of ​​the described memory device. Figures 1 to 31 Other improvements and benefits of the described techniques are discussed.

[0017] Figure 1 1 shows a portion of a schematic diagram of an apparatus in the form of a memory device 100 having multiple sets of data lines according to one embodiment of the present invention. The memory device 100 may include a non-volatile (e.g., a NAND flash memory device) or other type of memory device. Figure 1As shown in FIG. 1 , the memory device 100 may include a memory cell region (eg, a memory array region) 101 (which has memory cells 110, 111, 112, and 113) and a data line (a group of data lines) 170. 1 Up to 170 N , data line (a group of data lines) 171 1 To 171 N and data line (a group of data lines) 172 1 Up to 172 N Data line 170 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 172 9 The bit lines (eg, local bit lines) of the memory device 100 may be included (or may be a part thereof).

[0018] Memory device 100 may include an equal number of data lines in multiple groups of data lines (eg, stacks). Figure 1 In the figures, the reference "N" (the number of data lines in each group of data lines) can be any integer that is at least equal to two (N can be equal to two (N=2) or N can be greater than two (N>2)).

[0019] like Figure 1 As shown in FIG. 1 , the data line 170 1 Up to 170 N can respectively carry a signal (eg, a bit line signal) BL0 1 To BL0 N Data line 171 1 To 171 N can respectively carry a signal (eg, a bit line signal) BL1 1 To BL1 N . Data line 172 1 Up to 172 N can respectively carry a signal (eg, a bit line signal) BL2 1 To BL2 N .

[0020] Figure 1 Directions X, Y, and Z are shown that may be relative to physical directions (e.g., dimensions) of the structure of the memory device 100. For example, the Z direction may be a direction perpendicular to a substrate (e.g., a semiconductor substrate) of the memory device 100 (e.g., a vertical direction relative to the substrate). The Z direction is perpendicular to the X direction and the Y direction (e.g., the Z direction is perpendicular to the XY plane of the memory device 100).

[0021] In the physical structure of the memory device 100, the data line 1701 Up to 170 N 、Data line 171 1 To 171 N And data line 172 1 Up to 172 N The data lines of the same group (eg, data line 170) may be configured as conductive lines and have corresponding lengths extending in the Y direction. 1 Up to 170 N ) within a data line (eg, data line 170 1 Up to 170 N ) may be formed in a stacked structure. In the stacked structure, data lines in the same group may be positioned (e.g., stacked) on top of each other in different layers (e.g., layers) in the Z direction above the memory cell region 101 of the memory device 100. For example, in the physical structure of the memory device 100, the data lines 170 1 Up to 170 N 、Data line 171 1 To 171 N And data line 172 1 Up to 172 N The data lines 170 may be formed in a corresponding stack (eg, a side-by-side stack in the X direction) above the memory cell region 101. 1 Up to 170 N The data line 171 may be formed in a stack (eg, a first data line stack). 1 To 171 N may be formed in another stack (eg, a second data line stack adjacent to the first stack), and the data line 172 1 Up to 172 N It may be formed in a stack (eg, a third data line stack adjacent to the second stack).

[0022] Figure 1 The diagram shows a system including three groups of data lines (eg, the group of data lines 170 1 Up to 170 9 , the group of data lines 171 1 To 171 9 and the group of data lines 172 1 Up to 172 9 ) is an example of a memory device 100. However, the memory device 100 may include a plurality of groups of data lines.

[0023] like Figure 1 As shown in , memory cells 110 , 111 , 112 , and 113 may be organized into blocks (memory cell blocks). Figure 1The memory device 100 including two blocks 191 and 192 is shown as an example. However, the memory device 100 may include a plurality of blocks. The blocks (eg, blocks 191 and 192) of the memory device 100 may share a data line (eg, data line 170). 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 172 9 ) to carry information read from a memory cell of a selected memory cell of the memory device 100 (e.g., a selected memory cell in block 191 or 192) or information to be stored in the memory cell (in the form of a signal).

[0024] like Figure 1 As shown in FIG. 1 , memory cells 110, 111, 112, and 113 may be included in (e.g., may be formed into) corresponding memory cell strings in each block (e.g., blocks 191 and 192) of the memory device 100. For example, in block 191, the memory device 100 may include memory cell string 130. 1 Up to 130 N 、Memory cell string 131 1 To 131 N and memory cell string 132 1 Up to 132 N In another example, in block 192, the memory device 100 may include a memory cell string 130' 1 Up to 130' N , memory cell string 131' 1 To 131' N and memory cell string 132' 1 Up to 132' N .

[0025] In each block (eg, block 191 or 192 ) of the memory device 100 , the number of memory strings in the X direction coupled to a set of data lines may be equal to the number of data lines (eg, N) of the set of data lines.

[0026] like Figure 1 As shown in FIG. 1 , each memory cell string (eg, memory cell string 130 ) of the memory device 100 1) may have memory cells connected in series (e.g., four memory cells connected in series), wherein the memory cells connected in series may include one of the memory cells 110, one of the memory cells 111, one of the memory cells 112, and one of the memory cells 113. In the physical structure of the memory device 100, the memory cells 110, 111, 112, and 113 may be formed (e.g., vertically formed) in different layers (e.g., four different layers) in the Z direction of the memory device 100 and the data line 170. 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 172 9 below the stacked structure). Figure 1 Four memory cells in each memory cell string are shown (eg, memory cell string 130 1 However, the number of memory cells in each memory cell string of the memory device 100 may be different.

[0027] like Figure 1 As shown in , memory device 100 can include control gates 150, 151, 152, and 153, which can carry corresponding signals WL0, WL1, WL2, and WL3. Control gates 150, 151, 152, and 153 can include (or can be a portion of) access lines (e.g., word lines) of memory device 100. Each of control gates 150, 151, 152, and 153 can be part of a structure (e.g., a layer) of conductive material (e.g., a layer of conductive material) located in a single layer of memory device 100. Memory device 100 can use signals WL0, WL1, WL2, and WL3 during operation (e.g., read, write, or erase operation) to control access to memory cells 110, 111, 112, and 113 of block 191, respectively. For example, during a read operation, the memory device 100 may use the signals WL0, WL1, WL2, and WL3 to control access to the memory cells 110, 111, 112, and 113 of the block 191 to read (e.g., sense) information (e.g., previously stored information) from the memory cells 110, 111, 112, and 113 of the block 191. In another example, during a write operation, the memory device 100 may use the signals WL0, WL1, WL2, and WL3 to control access to the memory cells 110, 111, 112, and 113 of the block 191 to store information in the memory cells 110, 111, 112, and 113 of the block 191.

[0028] In block 192, memory device 100 may include similar control gates. For example, the memory device may include control gates 150', 151', 152', and 153', which may carry corresponding signals WL0', WL1', WL2', and WL3'. Each of control gates 150', 151', 152', and 153' may be part of a structure (e.g., a layer) of conductive material (e.g., a layer of conductive material) located in a single layer of memory device 100. Control gates 150', 151', 152', and 153' may be located in the same layer as control gates 150, 151, 152, and 153, respectively. Figure 1 As shown in , control gates 150', 151', 152' and 153' can be electrically separated from control gates 150, 151, 152 and 153. Therefore, the access line including control gates 150, 151, 152 and 153 can be electrically separated from the access line including control gates 150', 151', 152' and 153'.

[0029] During an operation (e.g., a read, write, or erase operation), the memory device 100 may use signals WL0′, WL1′, WL2′, and WL3′ to respectively control access to the memory cells 110, 111, 112, and 113 of the block 192. For example, during a read operation, the memory device 100 may use signals WL0′, WL1′, WL2′, and WL3′ to control access to the memory cells 110, 111, 112, and 113 of the block 192 to read (e.g., sense) information (e.g., previously stored information) from the memory cells 110, 111, 112, and 113 of the block 192. In another example, during a write operation, memory device 100 may control access to memory cells 110 , 111 , 112 , and 113 of block 192 using signals WL0 ′, WL1 ′, WL2 ′, and WL3 ′ to store information in memory cells 110 , 111 , 112 , and 113 of block 192 .

[0030] like Figure 1 As shown in , memory cells in different memory cell strings in the same block can share the same control gate (e.g., share the same physical control gate) in the block. For example, in block 191, memory cells 110 can share control gate 150, memory cells 111 can share control gate 151, memory cells 112 can share control gate 152, and memory cells 113 can share control gate 153. In block 192, memory cells 110 can share control gate 150', memory cells 111 can share control gate 151', memory cells 112 can share control gate 152', and memory cells 113 can share control gate 153'.

[0031] Figure 1 Four control gates in each block of memory device 100 (eg, control gates 150, 151, 152, and 153 in block 191) are shown as an example. The number of control gates in each block of memory device 100 may vary (eg, may be more than four).

[0032] like Figure 1 As shown in , memory device 100 may include a line (e.g., a source line or source plate) 198 that may carry a signal (e.g., a source line signal) SRC. Line 198 may be configured as a conductive line or conductive plate of memory device 100. Line 198 may be a common conductive line (e.g., a common source line or a common source plate) of blocks 191 and 192. Line 198 may be coupled to a ground connection of memory device 100.

[0033] The memory device 100 may include a select gate (eg, a drain select gate) 181. 1 To 181 N and a transistor (eg, a drain selection transistor) 161 1 To 161 N . Transistor 161 1 can share the same select gate 181 1 . Transistor 161 N can share the same select gate 181 N . Select gate 181 1 To 181 N Can carry signal SGD respectively 1 to SGD N .

[0034] Transistor 161 1 To 161 N The signal SGD 1 to SGD N During a memory operation (eg, a read or write operation) of the memory device 100, the transistor 161 may be turned on. 1 To 161 N (For example, by activating the corresponding signal SGD 1 to SGD N ) to couple the memory cell strings of block 191 to the corresponding set of data lines 170 1 Up to 170 N , 171 1 To 171 N and 172 1 Up to 172 N . Transistor 161 can be turned off1 To 161 N (For example, by deactivating the corresponding signal SGD 1 to SGD N ) to connect the memory cell strings of block 191 to the corresponding set of data lines 170 1 Up to 170 N , 171 1 To 171 N and 172 1 Up to 172 N Decoupling.

[0035] The memory device 100 may include transistors (e.g., source select transistors) 160, each of which may be coupled between the line 198 and the memory cells in the corresponding memory cell string of the block 191. The transistors 160 may share the same select gate (e.g., source select gate) 180 of the memory device 100. The transistors 160 may be controlled (e.g., turned on or off) by the same signal, such as an SGS signal (e.g., source select gate signal) provided on the select gate 180. During a memory operation (e.g., a read or write operation) of the memory device 100, the transistors 160 may be turned on (e.g., by activating the SGS signal) to couple the memory cell string of the block 191 to the line 198. The transistors 160 may be turned off (e.g., by deactivating the SGS signal) to decouple the memory cell string of the block 191 from the line 198.

[0036] In block 192, the memory device 100 may include similar select gates and transistors. For example, the memory device 100 may include a select gate (eg, drain select gate) 181′. 1 Up to 181' N and a transistor (eg, a drain select transistor) 161' 1 Up to 161' N . Transistor 161' 1 can share the same select gate 181' 1 . Transistor 161' N can share the same select gate 181' N . Select gate 181' 1 Up to 181' N Can carry signal SGD' 1 to SGD' N .

[0037] Transistor 161' 1 Up to 161' N can be represented by the signal SGD' 1 to SGD' NDuring a memory operation (eg, a read or write operation) of the memory device 100, the transistor 161' may be turned on. 1 Up to 161' N (For example, by activating the corresponding signal SGD' 1 to SGD' N ) to couple the memory cell strings of block 192 to the corresponding set of data lines 170 1 Up to 170 N , 171 1 To 171 N and 172 1 Up to 172 N . Transistor 161' can be turned off 1 Up to 161' N (For example, by deactivating the corresponding signal SGD' 1 to SGD' N ) to connect the memory cell strings of block 192 to the corresponding set of data lines 170 1 Up to 170 N , 171 1 To 171 N and 172 1 Up to 172 N Decoupling.

[0038] The memory device 100 may include transistors (e.g., source select transistors) 160', each of which may be coupled between the line 198' and the memory cells in the corresponding memory cell string of the block 192. The transistors 160' may share the same select gate (e.g., source select gate) 180' of the memory device 100. The transistors 160' may be controlled (e.g., turned on or off) by the same signal, such as the SGS' signal (e.g., source select gate signal) provided on the select gate 180'. During a memory operation (e.g., a read or write operation) of the memory device 100, the transistors 160' may be turned on (e.g., by activating the SGS' signal) to couple the memory cell string of the block 192 to the line 198. The transistors 160' may be turned off (e.g., by deactivating the SGS' signal) to decouple the memory cell string of the block 192 from the line 198.

[0039] The memory device 100 includes other components not shown in Figure 1 In order not to obscure the exemplary embodiments described herein, the following reference is made to Figures 2 to 6 Some structures of the memory device 100 are described. At least a portion of the memory device 100 (eg, the memory cell region 101 and the set of data lines 170) 1 Up to 170 9 , 1711 To 171 9 and 172 1 Up to 172 9 part of ) can contain references that can be used with Figures 7 to 31 Any memory device described may have a structure similar to (or identical to) that of the memory device.

[0040] Figure 2 An example is shown according to an embodiment of the present invention. Figure 1 Schematic diagram of a portion of a memory device 100 of FIG. 1 , in which the memory device 100 includes nine data lines in each group of data lines (eg, N=9). Figure 1 and Figure 2 In the present invention, similar or identical elements are given the same reference numerals. Figure 2 As shown in FIG. 1 , the memory device 100 may include a set of nine data lines 170 1 Up to 170 9 (170 1 , 170 2 , 170 3 , 170 4 , 170 5 , 170 6 , 170 7 , 170 8 and 170 9 ), a group of nine data lines 171 1 To 171 9 And a set of nine data lines 172 1 Up to 172 9 .

[0041] As described above, the number of memory strings in the X direction coupled to a set of data lines may be equal to the number of data lines (eg, N) of the set of data lines. Figure 2 In the example of FIG. 1 , each of blocks 191 and 192 may include nine memory strings in the X direction, which are coupled to corresponding sets of data lines. For example, in block 191, memory device 100 may include nine memory strings coupled to data lines 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 20 1 Up to 170 9 Nine memory cell strings 130 1 Up to 130 9 (130 1 , 130 2 , 130 3 , 130 4 , 130 5 , 130 6 , 130 7 , 130 8 and 130 9); respectively coupled to the data line 171 1 To 171 9 Nine memory cell strings 131 1 To 131 9 ; and are coupled to the data line 172 1 Up to 172 9 Nine memory cell strings 132 1 Up to 132 9 .

[0042] In a similar manner at block 192, the memory device 100 may include a plurality of memory cells coupled to the data lines 170, respectively. 1 Up to 170 9 Nine memory cell strings 130' 1 Up to 130' 9 ; respectively coupled to the data line 171 1 To 171 9 Nine memory cell strings 131' 1 To 131' 9 ; and are coupled to the data line 172 1 Up to 172 9 Nine memory cell strings 132' 1 Up to 132' 9 .

[0043] like Figure 2 As shown in FIG. 1 , the memory cell string 130 1 Up to 130 9 can be connected by conductive connection 140 1 Up to 140 9 Coupled to data line 170 1 Up to 170 9 Memory cell string 130' 1 Up to 130' 9 can be connected via conductive connections 140' 1 Up to 140' 9 Coupled to data line 170 1 Up to 170 9 .

[0044] In similar connection, the memory cell string 131 1 To 131 9 can be connected through conductive connection 141 1 Up to 141 9 Coupled to data line 171 1 To 171 9 Memory cell string 131' 1 To 131' 9 can be connected through conductive connection 141 ' 1Up to 141' 9 Coupled to data line 171 1 To 171 9 .

[0045] Memory cell string 132 1 Up to 132 9 can be connected through conductive connection 142 1 Up to 142 9 Coupled to data line 172 1 Up to 172 9 Memory cell string 132' 1 Up to 132' 9 can be connected through conductive connection 142' 1 Up to 142' 9 Coupled to data line 172 1 Up to 172 9 .

[0046] The manner in which the memory cell strings in the X direction in one block (e.g., block 191) are coupled to a particular set of data lines may be the same as the manner in which the memory cell strings in the X direction in another block (e.g., block 191) are coupled to the particular set of data lines. Figure 2 As shown in FIG. 1 , the memory cell string 130 in block 191 1 Up to 130 9 coupled (eg, coupled in a sequential manner) to the data line 170 1 Up to 170 9 The manner can be similar to the memory cell string 130' in block 192 1 Up to 130' 9 coupled (eg, coupled in a sequential manner) to the data line 170 1 Up to 170 9 Therefore, in the physical structure of the memory device 100, the conductive connection 140 1 Up to 140 9 may have a conductive connection 141 1 Up to 141 9 Similar (or identical) structures.

[0047] Figure 2 The memory cell string (eg, memory cell string 131′) in the X direction is shown. 1 To 131' 9 ) and the corresponding group of data lines (data lines 171 1 To 171 9 ) are exemplary connections (e.g., sequential connections) between the memory cell strings in the X direction and the corresponding groups of data lines. However, the connections between the memory cell strings in the X direction and the corresponding groups of data lines may be the same as Figure 2Different from the exemplary connection shown in FIG. 1 , as long as one memory cell string in the X direction can be coupled to a corresponding data line of a group of data lines. For example, Figure 2 The memory cell string 130 is shown 1 , 130 2 , 130 3 , 130 4 , 130 5 , 130 6 , 130 7 , 130 8 and 130 9 are coupled to the data lines 170 1 , 170 2 , 170 3 , 170 4 , 170 5 , 170 6 , 170 7 , 170 8 and 170 9 However, as long as the memory cell string 130 1 Up to 130 9 and data line 170 1 Up to 170 9 can be coupled to each other in a one-to-one connection (eg, memory cell string 130 1 Up to 130 9 Does not have data line 170 1 Up to 170 9 ), memory cell string 130 1 Up to 130 9 can be done in different ways (e.g., instead of Figure 2 ) is coupled to the data line 170 1 Up to 170 9 .

[0048] Figure 3A FIG. 1 shows a schematic diagram of some embodiments described herein. Figure 2 1 is a side view (eg, a cross section with respect to the ZY direction) of a portion of the structure of the memory device 100, which includes a data line 170 of the memory device 100. 1 Up to 170 9The structure of the memory cell string 130 and the structure of the memory cell string 130 are shown in the drawings. For simplicity, detailed descriptions of the same elements are not repeated in the drawings. Also for simplicity, cross-section lines (e.g., hatching) are omitted from most elements shown in the drawings described herein. Some elements of the memory device 100 and other memory devices (e.g., memory device 700) described herein may be omitted from specific figures in the drawings to avoid obscuring the description of one or more elements described in the specific figures. The dimensions (e.g., physical structures) of the elements shown in the drawings described herein are not drawn to scale.

[0049] exist Figure 3A , the structure of the memory cell string 130 may be the memory cell string 130 of the block 191 of the memory device 100. 1 Up to 130 9 The other memory cell strings ( Figure 1 and Figure 2 ) may have a structure similar to (or the same as) that of the memory cell string 130.

[0050] like Figure 3A As shown in FIG. 1 , the data line 170 1 Up to 170 9 The data line 170 may have a corresponding length extending in the Y direction. 1 Up to 170 9 Each of the data lines 170 may have a thickness in the Z direction (which is smaller than the length). 1 Up to 170 9 The memory devices 100 may be located in different layers (eg, layers) 301 to 309, respectively (eg, stacked on top of each other). Figure 3A As shown in FIG. 1 , layers 301 to 309 are located in a portion of the memory device 100 that is located above the memory cell region 101 (with respect to the Z direction). The memory cell region 101 is located above the substrate 390 of the memory device 100. As described above with reference to Figure 1 As described, the memory cell region 101 is where memory cell strings (one of which is shown as memory cell string 130 ) of the memory device 100 may be formed.

[0051] exist Figure 3A , the conductive structure 314 may be a conductive connection 140 of the memory device 100. 1 Up to 140 9 ( Figure 2). Conductive structure 314 may include (e.g., may be formed of) a conductive material (e.g., metal, conductively doped polysilicon, or other conductive material). Conductive structure 314 may have a structure (e.g., a vertical structure) extending through the material of layers 301 to 309 in the Z direction. Conductive structure 314 may be electrically coupled to (e.g., may contact) data line 170. 1 Up to 170 9 and the remaining data lines 170 1 Up to 170 9 Electrically separate from (e.g., not in contact with) Figure 3A As shown in FIG. 3 , the conductive structure 314 may be formed on the data line 170 7 A portion (eg, landing pad) 307 is electrically coupled to the data line 170 7 . Figure 3A The conductive structure 314 and the data line 170 are shown. 1 Up to 170 6 And data line 170 8 and 170 9 (Data line 170 7 ) to indicate the spacing (eg, gap) between the conductive structure 314 and the data line 170. 1 Up to 170 6 And data line 170 8 and 170 9 Separate electrically.

[0052] Figure 3A The conductive structure 314 is shown coupled to the data line 170 7 As an example. However, the conductive structure 314 may be coupled to the data line 170 8 and 170 9 As long as the conductive structure 314 is electrically coupled to at most one (only one) data line of a group of data lines (e.g., coupled to data line 170 1 Up to 170 9 Only one of

[0053] like Figure 3A As shown in FIG. 1 , the memory cell string 130 may include a pillar (eg, a vertical pillar) 330. The pillar 330 may include (eg, may be formed of) a conductive material (eg, conductively doped polysilicon). Figure 3A As shown in , pillar 300 may have a length extending in the Z direction (eg, extending vertically relative to substrate 390). Figure 1 The memory cell string 130 in 1 Up to 130 9) may include corresponding columns, and each of which may be similar to (or the same as) column 330.

[0054] The memory cell string 130 may include a conductive contact 340, which may be a portion of a pillar 330 of the memory cell string 130. The conductive contact 340 may be formed of a metal or other conductive material. The pillar 330 may include a portion 344. The conductive contact 340 and the pillar portion 344 may include the same conductive material or different conductive materials.

[0055] The conductive structure 314 and the pillar 330 may be a data line 170 7 and a portion of a circuit path (eg, a conductive channel of memory cell string 130) between conductive region 398 (associated with signal SRC). Conductive region 398 may be Figure 1 A portion of a line (e.g., a source line or source plate) 198 in the. Figure 3A In the memory device 100, during a memory operation (eg, a read or write operation), the conductive structure 340 and the pillar 330 may be connected to the data line 170. 7 A circuit path (eg, a current path) is formed between the conductive region 398 and the conductive region 398 .

[0056] like Figure 3A As shown in FIG. 1 , the conductive contact 340 may be located closer to the data line 170. 8 and 170 9 of the memory cell string 130 (eg, the drain side) (compared to the conductive region 398 (which may be Figure 1 The line in (e.g., a portion of the source line or source plate) 198) is adjacent to the other side (e.g., the source side). Therefore, Figure 3A The conductive contact 340 in may be referred to as a drain contact of the memory cell string 130 .

[0057] The substrate 390 of the memory device 100 may include a semiconductor substrate (eg, a silicon-based substrate). For example, the substrate 390 may include a p-type silicon substrate or an n-type silicon substrate. Figure 3A As shown in FIG, memory cells 110, 111, 112, and 113 of memory cell string 130 may be positioned in the Z direction along corresponding portions of pillars 330 in different layers of memory device 100. For example, memory cells 110, 111, 112, and 113 may be positioned (e.g., vertically formed) on top of one another in layers 350, 351, 352, and 353, respectively.

[0058] Control gates 150, 151, 152, and 153 may be positioned along corresponding portions (in the Z direction) of pillar 330 in the same layer (e.g., layers 350, 351, 352, and 353, respectively) as memory cells 110, 111, 112, and 113. Control gates 150, 151, 152, and 153 may include (e.g., may be formed of) a conductive material (e.g., metal, doped polysilicon, other conductive materials).

[0059] exist Figure 3A In the embodiment, the select gate 180 and Figure 1 The select gate 180 shown in FIG. Figure 3A The selection gate 181 in the embodiment may be the selection gate 181 1 To 181 N ( Figure 1 ) is one of the transistors 161. The transistor 161 may be a transistor 161 1 To 161 N One of the Figure 3A As shown in , transistors 160 and 161 may be positioned along corresponding portions of pillar 330 in the Z direction. The material of select gates 180 and 181 may include a conductive material (eg, conductively doped polysilicon, metal, other conductive materials).

[0060] Memory cell string 130 may include material 303, 304, 305 between portion 344 of pillar 330 and corresponding ones of control gates 150, 151, 152, and 153. Material 303 may also be between pillar 330 and each of select gates 180 and 181. Figure 3A As shown in FIG. 1 , materials 303, 304, and 305 may be split between memory cells 110, 111, 112, and 113. Materials 303, 304, and 305 located at a particular memory cell (in memory cells 110, 111, 112, and 113) may be a portion of that particular memory cell (e.g., a memory element).

[0061] Material 303 may include one or more charge blocking materials, such as a dielectric material (eg, silicon nitride) that is capable of blocking the tunneling of charges.

[0062] Material 304 may include one or more charge storage materials that can provide a charge storage function to represent the value of the information stored in memory cells 310, 311, 312, and 313. For example, material 304 may include polysilicon (e.g., conductively doped polysilicon), which may be p-type polysilicon or n-type polysilicon. The polysilicon may be configured to function as a floating gate (e.g., to store charge) in a memory cell (e.g., memory cell 310, 311, 312, or 313). In another example, material 304 may include a dielectric material (e.g., a silicon nitride-based material or other dielectric material) that can trap charge in a memory cell (e.g., memory cell 310, 311, 312, or 313).

[0063] Material 305 may include one or more tunneling dielectric materials capable of allowing tunneling of electric charges (eg, electrons), such as silicon dioxide.

[0064] like Figure 3A As shown in FIG. 1 , the memory device 100 may include a circuit system 395 located (e.g., formed) below the memory cell region 101 (e.g., directly below the memory cell string 130). The circuit system 395 may include other circuit elements coupled to the memory device 100 (e.g., coupled to the data line 170). 1 Up to 170 9 ) of the circuit system 395 (e.g., transistor T). The circuit elements (e.g., transistor T) of the circuit system 395 may be configured to perform a portion of the function of a memory device (e.g., memory device 100). For example, the circuit system 395 may include decoder circuits, driver circuits, buffers, sense amplifiers, charge pumps, and other circuit systems of the memory device 100.

[0065] Different views of column 330 along lines 3B-3B and 3C-3C are shown in FIG. Figure 3B and Figure 3C Shown in. Figure 3B Shown along Figure 3A 3B-3B is a top view (eg, a cross section relative to the XY plane) of portion 344 of column 330 . Figure 3C Shown along Figure 3A 3C-3C of the conductive contact 340 of the column 330 is a top view (eg, a cross section relative to the XY plane).

[0066] like Figure 3BAs shown in , portion 344 may include material 344A and material 344B surrounded by material 344A. Material 344A may be (or may include) part of a conductive structure (e.g., a conductive path) of pillar 330. Material 334B may include a dielectric material. In an alternative structure of pillar 330, material 344B may be omitted from pillar 330, such that the entire portion 344 of pillar 330 may include material 344 (without material 344B).

[0067] Figure 3B Shown along Figure 3A A top view (eg, a cross section relative to the XY plane) of portion 344 of column 330 along line 3C-3C. Figure 3C Shown along Figure 3A 3B-3B of the conductive contact 340 of the pillar 330. FIG.

[0068] like Figure 3C As shown in , the shape of the conductive contact 340 (eg, in top view) can be relatively circular. Figure 3C , the shape of portion 344 (eg, in top view) may be relatively circular. Figure 1 and Figure 2 Other conductive contacts (eg, drain contacts) shown in FIG. 3A and 3B may have shapes similar to those of conductive contact 340 (as viewed from a top view).

[0069] Figure 4 FIG. 1 shows a top view of the structure of a memory device 100 according to some embodiments described herein, including a data line 170 of the memory device 100. 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 172 9 and corresponding memory cell string 130 1 Up to 130 9 A conductive contact (eg, drain contact) 340 1 Up to 340 9 .

[0070] Figure 4 Also shown are conductive contacts (eg, drain contacts) 341 of other corresponding memory cell strings (not labeled) of the memory device 100. 1 To 341 9 (Only the conductive contacts 341 are marked 1 and 341 9 ) and a conductive contact (eg, drain contact) 342 1To 342 9 (Only the conductive contacts 342 are marked 1 and 342 9 ).like Figure 4 As shown in FIG. , the conductive contact 340 1 Up to 340 9 ,341 1 To 341 9 and 342 1 To 342 9 Each of them can have Figure 3A , Figure 3B and Figure 3C The conductive contact 340 may be shaped similarly to the shape of the (eg, circular) conductive contact 340 of the pillar 330 of the memory cell string 130 in FIG. 1 Up to 340 9 ,341 1 To 341 9 and 342 1 To 342 9 Located (in the Z direction) on data line 170 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 172 9 . Figure 4 As shown in FIG. 1 , the data line 170 1 Up to 170 9 、Data line 171 1 To 171 9 And data line 172 1 Up to 172 9 May have a length extending in the Y direction.

[0071] Conductive contact 340 1 Up to 340 9 Can be along the data line 170 1 Up to 170 9 The length of the stack (in the Y direction) and is positioned on both sides thereof (in the X direction). In a similar manner, the conductive contacts 341 1 To 341 9 Can be along data line 171 1 To 171 9 The conductive contacts 342 are located along the length of the stack (in the Y direction) and on both sides thereof (in the X direction). 1 To 342 9 Can be along data line 172 1 Up to 172 9The length of the stack (in the Y direction) and are positioned on both sides thereof (in the X direction).

[0072] Figure 4 Also shown is a conductive structure 314 of the memory device 100. 1 To 314 9 and other conductive structures (not labeled). Figure 4 As shown in FIG. , the conductive structure may alternatively be formed on the data line 171 1 To 171 9 On the sides of the stack (e.g., the left and right sides in the X direction).

[0073] Conductive structures (eg, conductive structures 314 1 To 314 9 ) can overlap (relative to the top view) and contact (eg, be electrically coupled to) a corresponding conductive contact. For example, conductive structure 314 1 May overlap and contact the conductive contact 340 1 , conductive structure 314 2 May overlap and contact the conductive contact 340 2 , and so on.

[0074] like Figure 4 As shown in FIG. , the conductive structure (eg, conductive structure 314 1 To 314 9 ) can also contact (e.g., electrically couple to) a corresponding data line of the data line stack at a portion of the corresponding data line that can be a protruding portion of the corresponding data line (e.g., a landing pad directly below a portion of the corresponding conductive structure, as viewed from a top view). For example, conductive structure 314 1 Can be data line 170 1 The protruding portion (eg, integral portion) of the portion 501 (in Figure 5 ) contacting the data line 170 9 , and the conductive structure 314 3 Can be data line 170 5 The protruding portion (eg, integral portion) of the portion 503 (in Figure 5 ) contacting the data line 170 5 .

[0075] As mentioned above Figure 2 3, the memory device 100 may have an example of nine data lines (eg, N=9) in each group of data lines. Figure 4 As shown in FIG. 1 , the group of data lines 170 1 Up to 170 9 (The associated signal BL01 To BL0 9 ) can be formed in a stack of nine data lines that are stacked one above the other in the Z direction. Figure 4 As shown in FIG. 1 , the data line 170 9 It can be the top data line, and data line 170 1 Up to 170 8 (It is hidden in the data line 170 9 Below) can be on data line 170 9 Downward (below in the Z direction).

[0076] In a similar manner, the group of data lines 171 1 To 171 9 (The associated signal BL1 1 To BL1 9 ) can be formed in a stack of nine data lines that are stacked one above the other in the Z direction. Figure 4 As shown in FIG. 1 , data line 171 9 It can be the top data line, and data line 171 1 To 171 8 (It is hidden in the data line 171 9 Below) can be on data line 170 9 Downward (below in the Z direction).

[0077] The group of data lines 172 1 Up to 172 9 (The associated signal BL2 1 To BL2 9 ) can be formed in a stack of nine data lines that are stacked one above the other in the Z direction. Figure 4 As shown in FIG. 1 , data line 172 9 It can be the top data line, and data line 172 1 Up to 172 8 (It is hidden in the data line 172 9 Below) can be on data line 172 9 Downward (below in the Z direction).

[0078] Figure 5 According to some embodiments described herein Figure 4 An isometric view of a portion of the structure of a memory device 100 including a memory cell region 101 and a data line 170 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 1729 Stacking. Figure 5 As shown in FIG. 1 , the group of data lines 170 1 Up to 170 9 The group of data lines 170 may be formed in a stack of nine data lines. 1 To 171 9 can be formed in another stack of nine data lines (eg, with data line 170 1 Up to 170 9 The group of data lines 172 1 Up to 172 9 It may be formed in another stack of nine data lines (eg, with data line 171 1 To 171 9 Data line 170 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 172 9 The stacks of may be positioned side by side with each other (in the X-direction) and on the same layer of the memory device 100 .

[0079] like Figure 5 As shown in FIG. 1 , the data line 170 1 Up to 170 9 Each of the data lines 170 may include (eg, may be formed of) a structure (eg, a member (eg, a layer)) of a conductive material. 1 Up to 170 9 The memory cell region 101 may include nine separate material structures (eg, fabrications) stacked one above the other. In a similar fashion, the set of data lines 170 1 To 171 9 Another stack (eg, with the data line 170) of nine conductive material structures (eg, articles (eg, layers)) may be formed. 1 Up to 170 9 The group of data lines 172 1 Up to 172 9 Another stack (eg, with the data line 171) of nine conductive material structures (eg, members (eg, layers)) may be formed. 1 To 171 9 Data line 170 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 172 9Exemplary materials include metal, conductively doped polysilicon, or other conductive materials.

[0080] Figure 5 Also shown are some conductive contacts of the memory device 100 (eg, conductive contacts 340 1 ,340 3 ,340 5 ,340 7 and 340 9 ) and corresponding conductive structures (eg, conductive structures 314 1 ,314 3 ,314 5 ,314 7 and 314 9 ). Conductive structure 314 1 ,314 3 ,314 5 ,314 7 and 314 9 The conductive connections 140 of the memory device 100 may be 1 , 140 3 , 140 5 , 140 7 and 140 9 ( Figure 2 ). For simplicity, Figure 5 Other conductive contacts (e.g. Figure 4 The conductive contacts 340 shown in 2 ,340 4 ,340 6 ,340 8 and 341 1 To 341 9 and 342 1 To 342 9 ) and corresponding conductive structures coupled to conductive contacts of the memory device 100.

[0081] like Figure 5 As shown in FIG. , the conductive structure 314 1 ,314 3 ,314 5 ,314 7 and 314 9 The portions (eg, landing pads) 501, 503, 505, 507, and 509 may be coupled to the corresponding data lines 170, respectively. 9 , 170 5 , 170 1 , 170 4 and 170 8 . Portions 501, 503, 505, 507 and 509 may be data lines 170,9 , 170 5 , 170 1 , 170 4 and 170 8 Therefore, the materials of the portions 501, 503, 505, 507, and 509 may be respectively connected to the data line 170. 9 , 170 5 , 170 1 , 170 4 and 170 8 The same materials. Figure 5 , each of the portions 501, 503, 505, 507, and 509 may be a protruding portion of a corresponding data line, wherein the protruding portion may protrude from one side of the corresponding data line in a direction (eg, an X direction) perpendicular to the length of the corresponding data line.

[0082] like Figure 5 As shown in FIG. 1 , the memory device 100 may include a spacer (eg, a vertical dielectric spacer) 345. The spacer 345 may form a conductive structure 314. 1 ,314 3 ,314 5 ,314 7 and 314 9 The corresponding conductive structure and the data line 170 1 Up to 170 9 The stack is electrically separated by a dielectric structure.

[0083] As mentioned above Figures 1 to 5 The above can be done in blocks (e.g., Figure 1 and Figure 2 The data lines (eg, data lines 170) are shared between blocks 191 and 192 in FIG. 1 Up to 170 9 ).therefore, Figure 5 Data line 170 1 Up to 170 9 The stack of can extend across (eg, be formed over) the blocks of memory device 100 and can be coupled to respective conductive contacts (eg, drain contacts) of respective memory cell strings in each block.

[0084] Figure 6 1 shows a top view of the structure of a memory device 100 according to some embodiments described herein, which includes blocks 191 and 192 and data line 170. 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 1729 of stacking. Figure 6 Also shown is data line 670 1 to 670 9 The stack and along the data line 670 1 to 670 9 For simplicity, Figure 6 The other data line stacks and data line 172 are omitted. 1 Up to 172 9 Stacking and data lines 670 1 to 670 9 Conductive contacts between stacks. Figure 6 As shown in FIG. 1 , the data line 170 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 172 9 The stack of memory cells 130 may extend across blocks 191 and 192 in the Y direction. 1 Up to 130 9 , 131 1 To 131 9 and 132 1 Up to 132 9 Conductive contacts (not in Figure 6 The middle mark) may be located on the data line 170 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 172 9 of the corresponding stack.

[0085] The memory device 100 and other memory devices (eg, referenced below) Figures 7 to 31 The stacked structure of the data lines of the memory device 700 described herein allows the memory devices described herein to have improvements and benefits over some conventional memory devices. For example, the stacked data lines described (e.g., data lines 170 1 Up to 170 9 , 171 1 To 171 9 and 172 1 Up to 172 9 ( Figures 1 to 6 ) and Figures 7 to 31The stacking of data lines in a memory device (e.g., memory devices 100 and 700) can increase the density of data lines for a given device area of ​​a memory device (e.g., memory devices 100 and 700). This can allow more memory cells (e.g., more memory cell strings) of a given device area to be coupled to the stacked data lines, thereby increasing the memory cell density of the memory device for a given area.

[0086] In addition, some conventional memory devices may have spacing (e.g., horizontal spacing) constraints that limit the number of columns of memory cell strings to be coupled to data lines in such conventional memory devices. Therefore, some memory cell strings in such conventional memory devices may not be used (e.g., wasted). The stacked data lines described herein can eliminate such constraints and allow a relatively high number of memory cell strings to be coupled to the stacked data lines. This can also increase the memory cell density of a given area of ​​the described memory device compared to some conventional memory devices.

[0087] Moreover, some applications may have a requirement that a particular device area contain a relatively high number of memory cells. To accommodate such a requirement, the column density (e.g., memory cell string density) of a particular device area of ​​a memory device may be increased. As a result, the number of data lines may also be increased. The stacked data lines described herein may allow the data line density to keep pace with such column density (e.g., memory cell string density), thereby making the memory devices described herein suitable for such applications.

[0088] Figures 7 to 31 Different views of elements during a process of forming a memory device 700 according to some embodiments described herein are shown. Some or all of the processes for forming the memory device 700 may be used to form the above referenced Figures 1 to 6 A memory device 100 is described.

[0089] Figure 7 The conductive contacts 740 are shown 1 to 740 9 A top view of a memory device 700. Conductive contacts 740 1 to 740 9 The conductive contacts 340 of the memory device 100 may correspond to 1 Up to 340 9 ( Figure 4 ). Conductive contact 740 1 to 740 9 It can be a memory cell string (from Figure 7 Top view of the pillar (hidden) (at the conductive contact 740 1 to 740 9A memory cell string of the memory device 700 and a corresponding column (which includes a conductive contact 740 1 to 740 9 ) is already forming and Figure 7 The associated memory device 700 is formed in a process prior to the process (not described herein). Figure 7 Other conductive contacts (of other pillars and corresponding memory cell strings) of the memory device 700 are also shown. Figure 7 Only some of the other conductive contacts of memory device 700 are labeled, such as conductive contacts 722, 723, 724, 728, 731, 732, 733, 735-739, 742, 747, 748, 752, 758, and 759).

[0090] Figure 7 Also shown are hard masks 701 to 712 formed over other materials (described in detail below) and over conductive contacts of the memory device 700. Each of the hard masks 701 to 712 may be formed to have a length extending in the Y direction and a width in the X direction. The material of the hard masks 701 to 712 may include tungsten or other materials that may not be affected by processes (e.g., trimming and etching processes) performed on other materials (e.g., silicon dioxide, silicon nitride, and materials of the photoresist structure) during formation of the data line stack of the memory device 700.

[0091] Formation and Figure 7 The associated memory device 700 process also forms other materials (in the Figure 8 ). Figure 7 Lines 792, 793, 791, and 794 in illustrative examples illustrate the locations of memory device 700 in subsequent figures showing different views (eg, cross-sections) of memory device 700.

[0092] Figure 7 Also shown is a location 717 (eg, the area indicated by the dashed rectangle) that may span a portion of the memory device 700. As described below (eg, with reference to Fig.17 , Fig.18 and Fig.19 ), the process of forming the data line stack of the memory device 700 may include forming a resist structure at position 717 (eg, Fig.17 , Fig.18 and Fig.19 The resist structure 1717 in the semiconductor device 700 is formed to cover the material in a portion of the semiconductor device 700 (eg, the portion at the position 717). Fig.19The described process can selectively remove a portion of the material not covered by the resist structure, such as the resist structure 1717. This process is a portion of forming a staircase structure in the material used to form the data line stack of the memory device 700.

[0093] Figure 8 The conductive contacts (eg, conductive contacts 740) of the memory device 700 are shown. 2 , 722, 732, 742, and 752) after forming a material of a different layer (eg, layer) in a corresponding layer (eg, layer) of memory device 700 above memory device 700 (eg, 722, 732, 742, and 752). Figure 7 The cross section at line 791 in FIG. 1 ). The materials of different layers (at the Figure 8 The conductive contacts 740 may be formed in a sequential manner. 2 , 722, 732, 742 and 752. For example, Figure 8 The process used may include conductive contacts 740 2 , 722 , 732 , 742 , and 752 , material 881 is formed (e.g., deposited) above material 881 , material 871 is formed (e.g., deposited) above material 881 , material 882 is formed (e.g., deposited) above material 871 , and so on, until material 890 is formed.

[0094] Materials 871-879 and materials 881-890 are also formed on other conductive contacts of memory device 700 (eg, Figure 7 However, for simplicity, Figure 8 Only a portion of the memory device 700 is shown (e.g., along Figure 7 portion of line 791 in).

[0095] like Figure 8 As shown in FIG. 8 , hard masks 701 to 705 may be formed over materials 871 to 879 and materials 881 to 890. Although not shown in FIG. Figure 8 , but other hard masks (e.g., Figure 7 706 to 712 in the hard mask).

[0096] Fig. 9 Another portion of the memory device 700 is also shown (eg, Figure 7As shown in FIG. 1 , the material 871 to 879 at the portion of the cross section at line 792 of FIG. 1 and the material 881 to 890 at the portion of the cross section at line 792 of FIG. Fig. 9 As shown in FIG. 7 , the conductive contacts 740 are also 8 , 728, 738, 748 and 758 (which are Figure 7 Conductive contacts 740 8 , 728, 738, 748 and 758 are the same) to form materials 871 to 879 and materials 881 to 890.

[0097] Fig.10 Another portion of the memory device 700 is also shown (eg, Figure 7 As shown in FIG. 1 , the material 871 to 879 at the portion of the cross section at line 793 of FIG. 1 and the material 881 to 890 at the portion of the cross section at line 793 of FIG. Fig.10 As shown in FIG. 1 , conductive contacts 731, 733, 735, 737 and 739 (which are Figure 7 Materials 871 to 879 and materials 881 to 890 are formed over the conductive contacts 731, 733, 735, 737 and 739 (the same).

[0098] In with Figures 11 to 31 In the associated following processes, different portions of materials 871 to 879 and materials 881 to 890 may be removed (e.g., removed using an etching process) in different steps (e.g., different etching processes). When other portions of materials 871 to 879 and materials 881 to 890 (e.g., portions not under hard masks 701 to 712) are removed, portions under hard masks 701 to 712 (from the hard masks 701 to 712) are not removed. Figure 7 Materials 871 to 879 and materials 881 to 890 (for example, remain unchanged) as seen in the view in FIG.

[0099] Fig.11 A portion of a memory device 700 is shown (eg, Figure 7 ), which includes the remaining portion (e.g., the first remaining portion) of materials 872 to 879 and materials 882 to 890 after removing (e.g., by using an etching process) a portion of materials 872 to 879 and materials 882 to 890 at location 1101. Fig.11 The associated process does not remove material (eg, silicon nitride) 871. Therefore, Fig.11 The rest of the material in 871 is related to Fig.10 The same material as in 871. Fig.11 , the process of removing portions of materials 872 - 879 and materials 882 - 890 at location 1101 may include using a resist structure 1111 having an opening at location 1101 .

[0100] Fig.12 A portion of a memory device 700 is shown (eg, Figure 7 1202A and 1202B), which includes materials 872 to 879 and remaining portions (e.g., second remaining portions) of materials 882 to 890 after removing (e.g., removing using an etching process) a portion of materials (e.g., silicon nitride) 874 and 875 and materials (e.g., silicon dioxide) 884 and 885 at each of locations 1202A and 1202B. The process of removing portions of materials 872 to 879 and materials 882 to 890 at each of locations 1202A and 1202B may include using a resist structure 1212 having openings at locations 1101, 1202A, and 1202B. The resist structure 1212 may be formed by removing (e.g., trimming) locations 1202A and 1202B ( Fig.12 ) at the resist structure 1111( Fig.11 ) portion to form a resist structure 1212.

[0101] Fig.13 A portion of a memory device 700 is shown (eg, Figure 7 1303A and 1303B) after removing (e.g., removing using an etching process) a portion of material (e.g., silicon nitride) 876 and 877 and material (e.g., silicon dioxide) 886 and 887 at each of locations 1303A and 1303B. The process of removing a portion of material 872 to 879 and material 882 to 890 at each of locations 1303A and 1303B may include using a resist structure 1313 having openings at locations 1101, 1202, and 1303A and 1303B. The resist structure 1313 may be formed by removing (e.g., trimming) locations 1303A and 1303B ( Fig.13 ) at the resist structure 1212 ( Fig.12 ) to form a portion of the resist structure 1313.

[0102] Fig.14 A portion of a memory device 700 is shown (eg, Figure 71404B) after removing (e.g., removing using an etching process) a portion of material (e.g., silicon nitride) 878 and 879 and material (e.g., silicon dioxide) 888, 889, and 890 at each of locations 1404A and 1404B. The process of removing the portion of material 872 to 879 and material 882 to 890 at each of locations 1404A and 1404B may include using a resist structure 1414 having openings at locations 1101, 1202, 1303A and 1303B, and 1404A and 1404B. The resist structure 1414 may be formed by removing (e.g., trimming) locations 1404A and 1404B ( Fig.14 ) at the resist structure 1313 ( Fig.13 ) to form a portion of the resist structure 1414.

[0103] Fig.15 Another portion of the memory device 700 is shown (eg, Figure 7 791 ), which includes different views of material 872 to 879 at position 1404A and the remainder of material 882 to 890 (e.g., a fourth remainder). Fig.15 Position 1404A in Fig.14 The same as position 1404A in FIG. 1404A. However, Fig.15 The position 1404A in the XZ direction (e.g., from along Figure 7 791 in the cross section), and Fig.14 The position 1404A in the YZ direction (e.g., relative to the Figure 7 793 in the cross section). Fig.15 As shown in Fig.14 During the associated process, portions of materials 871 to 879 and materials 881 to 890 under the hard mask (eg, hard mask 701 to 705) are not removed. Fig.15 As shown in FIG. 14 , materials 878 and 879 and portions of materials 888, 889, and 890 (at locations 1404A and not under hard masks (eg, hard masks 701 to 705)) are removed. Fig.14 associated process).

[0104] Fig.16 Another portion of the memory device 700 is shown (eg, Figure 7 792 of the cross section), which includes different views of materials 872-879 at position 1404B and the remainder of materials 882-890 (e.g., a fourth remainder). Fig.16Position 1404B in Fig.14 The same as position 1404B in FIG. 1404B. However, Fig.16 The position 1404B in the XZ direction (e.g., from along Figure 7 ), and Fig.14 The position 1404B in the YZ direction (e.g., relative to the Figure 7 793 in the cross section). Fig.16 As shown in Fig.14 During the associated process, portions of materials 871 to 879 and materials 881 to 890 under the hard mask (eg, hard mask 701 to 705) are not removed. Fig.16 As shown in FIG. 14 , materials 878 and 879 and portions of materials 888, 889, and 890 (at locations 1404B and not under hard masks (eg, hard masks 701 to 705)) are removed. Fig.14 associated process).

[0105] Fig.17 and Fig.18 17. A portion of the memory device 700 is shown after forming the resist structure 1717 (eg, at Figure 7 Different views of the cross section at lines 792 and 793 of FIG. Fig.17 As shown in , a resist structure 1717 may be formed over a hard mask (eg, hard masks 701 to 705) of the memory device 700. Fig.18 In the embodiment, the resist structure 1717 can be formed on a portion of the memory device 700 from the location of the conductive contact 735 to the rest of the memory device 700 in the Y direction relative to the direction from the conductive contact 735 to the conductive contact 737. Figure 7 As described above, a resist structure 1717 may be formed at location 717 to cover the material in a portion of the memory device 700 (eg, the portion at location 717). Fig.17 and Fig.18 , the portion of memory device 700 beneath resist structure 1717 is Figure 7 A portion of the portion of the memory device 700 at location 717 in FIG. Fig.18 In the embodiment, portions 1802, 1803, 1804 and 1805 (which are not covered by the resist structure 1717) will be in contact with Fig.19 The associated process is removed. Fig.18As shown in , each of portions 1802, 1803, 1804, and 1805 may include one of materials 873 to 879 and one of materials 883 to 889. Portion 1805 may include a portion of the remainder of material 890.

[0106] Fig.19 Shows Fig.18 700, which includes removing (e.g., by using an etching process) portions 1802, 1803, 1804, and 1805 ( Fig.18 ) after materials 872 to 879 and the remainder of materials 882 to 890 (e.g., the fifth remainder).

[0107] Fig. 20 and Fig.21 shows that in the removal (with Fig.19 associated process) sections 1802, 1803, 1804 and 1805 ( Fig.18 ) after the portion of the memory device 700 (for example, respectively at Figure 7 Different views of the cross section at lines 793 and 791 of FIG. Fig. 20 As shown in Fig.19 The associated processes may form step structures 2001 and 2002 that are opposite to each other (e.g., the steps of step structure 2001 face the steps of step structure 2002 in the Y direction). The steps of step structure 2001 are at uneven levels with the steps of step structure 2001, so that the top exposed portions of step structure 2001 (e.g., the tops of the steps) of the remaining portions of materials 872, 874, 876, and 878 are at uneven levels with the top exposed portions of step structure 2002 (e.g., the tops of the steps) of the remaining portions of materials 871, 873, and 875.

[0108] Fig. 22 A portion of memory device 700 (eg, a dielectric material) is shown after forming material (eg, dielectric material) 2208. Figure 7 The material 2208 may include silicon dioxide. The material 2208 may be included in the hard masks 701 to 705 and Fig. 22 An initial material (eg, silicon dioxide) is deposited over the other materials of the memory device 700 shown in FIG. Fig. 20In the view of FIG. 8 , the initial material may also be deposited (filled) in the space at the stepped structure of materials 871 to 879 and materials 881 to 890. After the initial material is deposited (filled), a material removal process (e.g., a chemical mechanical planarization (CMP) process) may be used to remove a portion (e.g., a top portion) of the initial material and stop at hard masks 701 to 705 (e.g., stop at the top of hard masks 701 to 705). Thus, hard masks 701 to 705 may be used as a stopper (e.g., a stop layer) in the material removal process. The remainder of the initial material (after its top portion is removed) is Fig. 22 and Fig.23 Material 2208 is shown.

[0109] Fig.23 A portion of a memory device 700 is shown (eg, Figure 7 A cross section at line 794 of FIG. 1 ) comprising Fig. 22 Different view materials 2208 are shown in FIG. Figure 7 As shown in FIG. 7 , line 794 may be at an angle relative to the X and Y directions (eg, extending in a diagonal direction) such that a view of memory device 700 may include conductive contacts 740. 1 ,740 2 , 723, 724, 735, 736, 747, 748 and 759.

[0110] Fig.24 A portion of memory device 700 is shown after forming openings (e.g., trenches) 2401, 2402, 2403, 2404, 2405, and 2406. Forming openings 2401, 2402, 2403, 2404, 2405, and 2406 may include removing (e.g., by using an etching process) material (e.g., silicon oxide) 2208, materials 871-879, and portions of materials 881-890 at the locations of openings 2401, 2402, 2403, 2404, 2405, and 2406 down to conductive contacts 740. 1 ,740 2 , 723, 724, 735, 736, 747, 748 and 759 (e.g., to the top thereof). Fig.24 The associated process may include exposing the conductive contacts 740 at the corresponding openings 2401, 2402, 2403, 2404, 2405, and 2406. 1 ,740 2 , 723, 724, 735, 736, 747, 748 and a portion of each of 759.

[0111] Fig.25A portion of memory device 700 is shown after forming material (e.g., dielectric material) 2508. Material 2508 may include silicon dioxide. Forming material 2508 may include depositing (e.g., filling) material (e.g., silicon dioxide) in openings 2401, 2402, 2403, 2404, 2405, and 2406. Material 2508 may also be formed over hard masks 701-705.

[0112] Fig.26 A portion of memory device 700 is shown after forming openings (e.g., contact openings) 2611-2619. Forming openings 2611-2619 may include removing (e.g., by using an etching process) a portion of material (e.g., silicon oxide) 2208 and 2508 at the locations of openings 2611-2619 down to conductive contacts 740. 1 ,740 2 , 723, 724, 735, 736, 747, 748 and 759 (e.g., to the top thereof). Fig.26 The associated process may include exposing the conductive contacts 740 at the corresponding openings 2611, 2612, 2613, 2614, and 2615. 1 ,740 2 , 723, 724, 735, 736, 747, 748 and a portion of each of 759.

[0113] and Fig.26 The associated process may include a selective etching process so that the material 881 to 889 at the layers 2601 to 2609 located at the locations of the openings 2611 to 2619 is not removed. Fig.26 An associated process may include exposing portions (eg, landing pads) 2671 - 2679 of materials 881 - 889 , respectively, at the locations of openings 2611 - 2619 , respectively.

[0114] and Fig.26 The associated process may include forming isolation structures 2635 so that one of isolation structures 2635 may be located at conductive contact 740. 1 ,740 2 , between two adjacent conductive contacts among 723, 724, 735, 736, 747, 748 and 759.

[0115] Fig. 27A portion of the memory device 700 is shown after forming spacers (e.g., vertical dielectric spacers) 2745 on the sidewalls of the respective openings 2611-2619. Forming the spacers 2745 can include depositing a dielectric material (e.g., silicon dioxide) in the openings 2611-2619 and then removing (e.g., by using an etching process) a portion of the dielectric material. The remaining portion of the dielectric material is formed Fig. 27 2745 shown in FIG. 2745. Some of the remainder of the dielectric material may also be formed on each isolation structure 2635 (eg, on the sidewalls). Fig. 27 The dielectric material formed on the isolation structure 2635 is omitted. Fig.30 As described above, the spacer 2745 may form a dielectric structure that electrically separates the corresponding conductive structure from the corresponding stack of data lines. For example, the spacer 2745 may correspond to Figure 5 spacers (eg, vertical dielectric spacers) 345 that separate the conductive structures 314 1 ,314 3 ,314 5 ,314 7 and 314 9 ( Figure 5 ) and the corresponding conductive structure in the data line 170 1 Up to 170 9 ( Figure 5 ) are electrically separated from the corresponding stacks of data lines.

[0116] Fig.28 A portion of memory device 700 is shown after removing (eg, digging out) materials 871-879. Fig. 27 An associated process may include forming empty spaces at locations occupied by materials 871 - 879 .

[0117] Fig.29 A portion of memory device 700 is shown after forming conductive material 2970. Conductive material 2970 may include metal, conductive doped polysilicon, or other conductive material. As an example, conductive material 2970 may include tungsten or a combination of tungsten and nitride. Forming conductive material 2970 may include depositing conductive material 2970 in openings 2611-2619 and in empty spaces at locations occupied by materials 871-879.

[0118] Fig.30 A portion of the memory device 700 is shown after removing a portion (eg, a top portion) of the conductive material 2970 and the hard masks 701 to 705. Fig.30The associated process may include a material removal process (eg, a CMP process) that may remove the top portion of the conductive material 2970 and the hard masks 701 to 705 and stop at the layer of material (eg, material 2508 ) directly below the hard masks 701 to 705 .

[0119] like Fig.30 As shown in Fig.30 Associated processes may form data lines 3071-3079 and conductive structures 3041-3049. Data lines 3071-3079 may be located in layers 2601-2609 of memory device 700, respectively.

[0120] Fig.30 Shown along Figure 7 794. Thus, data lines 3071 to 3079 may be in Figure 7 700 and are located side by side in the X direction and on the same layer of the memory device 700. For example, data lines 3076 and 3078 may be located at Figure 7 The data lines 3072 and 3074 may be two data lines of the stack of nine data lines located below (eg, directly below) the location of the hard mask 701 in FIG. Figure 7 The data lines 3071 and 3073 may be two data lines of the stack of nine data lines located below (eg, directly below) the location of the hard mask 702 in FIG. Figure 7 The data lines 3075 and 3077 may be two data lines of the stack of nine data lines located below (eg, directly below) the location of the hard mask 703 in FIG. Figure 7 The data line 3079 may be two data lines of the stack of nine data lines located below (eg, directly below) the location of the hard mask 704 in FIG. Figure 7 The hard mask 705 is positioned below (eg, directly below) one data line of the stack of nine data lines.

[0121] As an example, Fig.30 The data lines 3076 and 3078 can be Figure 1 The set of data lines 170 of the memory device 100 1 Up to 170 9 The two data lines in; Fig.30 The data lines 3072 and 3074 can be Figure 1 The group of data lines 171 of the memory device 100 1 To 171 9 The two data lines in the data line 3071 and 3073 can be located at Figure 7The hard mask 703 is positioned directly beneath two data lines of the stack of nine data lines.

[0122] like Fig.30 As shown in FIG. , the data lines in the data line stack can be connected to Figure 8 Respective ones of materials 882 to 889 formed in associated processes are electrically separated from one another. Fig.30 The data lines in the data line stack can be formed by including spacers 2745 (in the same Fig. 27 The data line stacks including data lines 3076 and 3078 may be electrically separated from each other by dielectric structures including at least one spacer 2745 formed in an associated process. For example, the data line stacks including data lines 3076 and 3078 may be electrically separated from each other by dielectric structures including spacers 2745 adjacent to respective sides (e.g., left and right sides) of the data line stacks including data lines 3076 and 3078.

[0123] Will Fig.30 A dielectric structure that electrically separates data lines (material of data lines) in a data line stack in the embodiment of the present invention may also electrically separate a conductive structure from data lines other than data lines coupled to the conductive structure. For example, a dielectric structure (which includes spacers 2745 adjacent to data lines 3076 and 3078) may electrically separate conductive structure 3041 from data lines in a data line stack including data lines 3076 and 3078 in addition to data line 3078. In another example, a dielectric structure (which includes spacers 2745 adjacent to data lines 3076 and 3078) may electrically separate conductive structure 3042 from data lines in a data line stack including data lines 3076 and 3078 in addition to data line 3076.

[0124] Therefore, with Fig.30 The associated process may form a stack of data lines (e.g., data lines 3071-3079) from the material 881 of the memory device 700 and the conductive structures (e.g., conductive structures 3041-3049). The conductive structures may be connected to the data line stack of the memory device 700 and the corresponding conductive contacts (e.g., conductive contacts 740 1 ,740 2 , 723, 724, 735, 736, 747, 748, and 759) are in electrical contact with (electrically coupled to) each data line stack. The conductive structure can be located on a respective side of each data line stack. For example, conductive structures 3041 and 3042 can be located on respective sides (e.g., left and right sides) of a data line stack including data lines 3076 and 3078. In another example, conductive structures 3043 and 3044 can be located on respective sides (e.g., left and right sides) of a data line stack including data lines 3072 and 3074.

[0125] As mentioned above, because Fig.30 Shown along Figure 7 794, so the data lines 3071 to 3079 can be part of five data line stacks. However, one data line stack of the memory device 700 can also have a structure of a combination of the data lines 3071 to 3079. For example, the hard mask 701 ( Figure 7 ) may include data lines 3071, 3072, 3073, 3074, 3075, 3076, 3077, 3078 and 3079 in sequence, wherein data line 3071 may be the bottom data line of the stack and data line 3079 may be the top data line of the stack.

[0126] Fig.31 A portion of memory device 700 is shown after forming material 3108. Material 3108 may include silicon dioxide.

[0127] The process of forming the memory device 700 may include additional processes that are omitted from the description herein. For example, additional processes may be performed to form interconnects and form conductive paths between data lines and other components of the memory device 700.

[0128] The illustrations of devices (e.g., memory devices 100 and 700) and methods (e.g., methods of forming memory device 700) are intended to provide a general understanding of the structure of various embodiments, and are not intended to provide a complete description of all elements and features of devices that can utilize the structures described herein. The device herein refers to, for example, a device (e.g., memory devices 100 and 700) or a system including the device (e.g., memory devices 100 and 700). Although the stacked structure of the data lines described herein can be included in a memory device (e.g., memory devices 100 and 700). However, the stacked structure of the data lines described herein can also be included in other semiconductor devices. Examples of semiconductor devices include processors (e.g., general-purpose processors), application-specific integrated circuits (ASICs), memory controllers, and other semiconductor devices.

[0129] Reference above Figures 1 to 31Any of the components described may be implemented in a variety of ways, including simulation via software. Thus, the above-described devices (e.g., memory devices 100 and 700) or a portion of each memory device and system may be characterized herein as one or more "modules". Such modules may include hardware circuit systems, single processor and / or multi-processor circuits, memory circuits, software program modules and objects and / or firmware and combinations thereof, as needed and / or depending on the specific implementation of each embodiment. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitance-inductance simulation package, a power / heat dissipation simulation package, a signal transmission-reception simulation package and / or a combination of software and hardware for operating each potential embodiment or simulating its operation.

[0130] The memory devices described herein (e.g., memory devices 100 and 700) can be included in devices (e.g., electronic circuit systems), such as high-speed computers, communication and signal processing circuit systems, single or multi-processor modules, single or multiple embedded processors, multi-core processors, message information switches, and dedicated modules (including multi-layer, multi-chip modules). Such devices can be further included as subcomponents in various other devices (e.g., electronic systems), such as televisions, cellular phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Moving Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, etc.

[0131] Reference above Figures 1 to 31 Embodiments described include devices and methods of forming the devices. One of the devices includes a first conductive contact; a second conductive contact; multiple layers of conductive material stacked one above the other and located above the first and second conductive contacts; multiple layers of dielectric material interleaved with the multiple layers of conductive material, the multiple layers of conductive material and the multiple layers of dielectric material forming a material stack; a first conductive structure located on a first side of the material stack and contacting the first conductive contact and a first layer of conductive material in the multiple layers of conductive material; and a second conductive structure located on a second side of the material stack and contacting the second conductive contact and a second layer of conductive material in the multiple layers of conductive material. Other embodiments are described that include additional devices and methods.

[0132] In the detailed description and claims, the term "on..." used with respect to two or more elements (e.g., materials), one "on" another refers to at least some contact between the elements (e.g., between the materials). The term "above" refers to the elements (e.g., materials) being in close proximity, but may have one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Unless so stated, "on..." or "over..." do not imply any directionality as used herein.

[0133] In the detailed description and claims, a list of items joined by the term "at least one" may refer to any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" refers to only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" refers to only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0134] In the detailed description and claims, a list of items joined by the term "one of..." may refer to only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" refers to only A (not including B) or only B (not including A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" refers to only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0135] The above description and accompanying drawings illustrate some embodiments of the subject matter of the present invention so that those skilled in the art can practice the embodiments of the subject matter of the present invention. Other embodiments may incorporate structural, logical, electrical, process and other changes. Examples represent possible variations only. The parts and features of some embodiments may be included in the parts and features of other embodiments, or may be replaced by them. After reading and understanding the above description, many other embodiments will be apparent to those skilled in the art.

Claims

1. A memory device, comprising: a first conductive contact; a second conductive contact; multiple layers of conductive material stacked one above the other to implement a data line of the memory device and located above the first and second conductive contacts; multiple layers of dielectric material interleaved with the multiple layers of conductive material, the multiple layers of conductive material and the multiple layers of dielectric material forming a material stack; a first conductive structure located on a first side of the material stack and contacting the first conductive contact and a first layer of conductive material in the multi-layer conductive material, wherein the first layer of conductive material includes a first protruding portion and the first conductive structure contacts the first layer of conductive material at the first protruding portion; a second conductive structure located on a second side of the material stack and contacting the second conductive contact and a second layer of conductive material in the multi-layer conductive material, wherein the second layer of conductive material includes a second protruding portion, and the second conductive structure contacts the second layer of conductive material at the second protruding portion; and A dielectric structure separates the first conductive structure from the multiple layers of conductive material except the first layer of conductive material.

2. The memory device of claim 1 , further comprising: a first conductive pillar located below the first conductive contact and contacting the first conductive contact; and A second conductive pillar is located below the second conductive contact and contacts the second conductive contact. 3 . The memory device of claim 1 , wherein one of the multiple layers of conductive material is between the first layer of conductive material and the second layer of conductive material.

4. The memory device of claim 1, further comprising an additional dielectric structure separating the second conductive structure from the multiple layers of conductive material other than the second layer of conductive material.

5. A memory device comprising: a memory cell string; data lines located above the memory cell strings, the data lines stacked on top of each other in different layers of the device; conductive lines coupled to the memory cell strings and the data lines such that each of the conductive lines is coupled to a corresponding one of the data lines and a corresponding one of the memory cell strings; select transistors, each of the select transistors coupled between a memory cell of a corresponding one of the memory cell strings and a corresponding one of the conductive lines; a select gate shared by the select transistors; an access line shared by the memory cell string; and A conductive structure includes a protruding portion contacting the conductive line.

6. The memory device of claim 5, further comprising: an additional string of memory cells; additional conductive lines coupled to the additional memory cell strings and the data lines such that each of the additional conductive lines is coupled to a respective one of the data lines and a respective one of the memory cell strings; and An additional access line is shared by the additional memory cell strings and is electrically separate from the access line.

7. The memory device of claim 5, further comprising: an additional string of memory cells; additional data lines located above the additional memory cell strings, the additional data lines being stacked one above the other in different layers of the device; and and an additional conductive line coupled to the additional memory cell strings and the additional data lines such that each of the additional conductive lines is coupled to a corresponding one of the additional data lines and a corresponding one of the additional memory cell strings, wherein the access line is shared by the memory cell string and the additional memory cell strings.

8. The memory device of claim 7, wherein the data line is comprised in a first data line stack and the further data line is comprised in a second data line stack, and the first and second data line stacks are positioned side by side with each other on a same layer of the device.

9. A method for forming a memory device, comprising: forming multiple layers of conductive material stacked one above the other to implement data lines of the memory device and over the conductive contacts; forming multiple layers of dielectric material interleaved with the multiple layers of conductive material; forming a conductive structure that contacts the conductive contact and contacts a layer of conductive material in the multiple layers of conductive material; and A dielectric structure is formed that electrically separates the conductive structure from the multiple layers of conductive material except for the one layer of conductive material.

10. The method of claim 9, wherein the dielectric structure is formed before forming the conductive structure.

11. The method of claim 9, wherein the conductive contact contacts a conductive pillar of a memory cell string of a memory device, and the memory cell string is formed before forming the multiple layers of conductive material and the multiple layers of dielectric material.

12. The method according to claim 11, further comprising: forming an additional conductive structure contacting an additional conductive contact of an additional conductive pillar of an additional string of memory cells of the memory device and contacting an additional layer of conductive material of the multiple layers of conductive material; and A further dielectric structure is formed that electrically separates the further conductive structure from the multiple layers of conductive material other than the further layer of conductive material.

13. The method of claim 12, wherein the multiple layers of conductive material and the multiple layers of dielectric material form a material stack, the conductive structure is formed on a first side of the material stack, and the further conductive structure is formed on a second side of the material stack.

14. The method according to claim 11, further comprising: forming additional conductive structures contacting respective additional conductive pillars of additional strings of memory cells of the memory device and contacting additional ones of the multiple layers of conductive material; and A dielectric structure is formed that electrically separates the conductive structure and the further conductive structure from the multiple layers of conductive material. 15 . The method of claim 14 , wherein the multiple layers of conductive material and the multiple layers of dielectric material form a material stack, and the conductive structures and the further conductive structures are formed alternately on sides of the material stack.

16. A method for forming a memory device, comprising: forming multiple layers of a first dielectric material and multiple layers of a second dielectric material interleaved with the multiple layers of the first dielectric material, the multiple layers of the first dielectric material and the multiple layers of the second dielectric material being formed over conductive contacts of pillars of a string of memory cells; forming a hard mask over the multiple layers of first dielectric material and the multiple layers of second dielectric material; removing a first portion of the multi-layer first dielectric material and a first portion of the multi-layer second dielectric material to form a first stepped structure and a second stepped structure in a remaining portion of the multi-layer first dielectric material and a remaining portion of the multi-layer second dielectric material, wherein a second portion of the multi-layer first dielectric material under the hard mask and a second portion of the multi-layer second dielectric material under the hard mask are not removed when forming the first and second stepped structures; forming material stacks such that each of the material stacks includes a portion of the first stepped structure, a portion of the second stepped structure, and one of the second portion of the multi-layer first dielectric material and the second portion of the multi-layer second dielectric material; removing the remaining portions of the multi-layer second dielectric material in the first and second stepped structures and the second portion of the multi-layer second dielectric material under the hard mask; forming a conductive material in a space where the remaining portion of the multi-layer second dielectric material in the first and second stepped structures and the second portion of the multi-layer second dielectric material under the hard mask are removed to form a data line of the memory device; and Conductive structures are formed such that respective ones of the conductive structures contact respective conductive materials in one of the material stacks.

17. The method of claim 16, wherein the multiple layers of first dielectric material comprise silicon dioxide and the multiple layers of second dielectric material comprise silicon nitride. The method according to claim 16 , wherein the second stepped structure is opposite to the first stepped structure.

19. The method of claim 16, further comprising: A dielectric spacer is formed between the conductive structure and the material stack to separate the conductive structure from the conductive material.

20. The method of claim 16, wherein the top exposed portions of the first remaining portions of the multi-layer second dielectric material of the first stepped structure are at a non-level with the top exposed portions of the first remaining portions of the multi-layer second dielectric material of the second stepped structure.

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