Integrated chip and method for forming isolation structure

Abstract

In some embodiments, the present invention relates to an integrated chip, which includes a semiconductor device, a polysilicon isolation structure, and a first insulator pad and a second insulator pad. The semiconductor device is arranged on the front side of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the front side of the substrate toward the back side of the substrate. The first insulator pad and the second insulator pad surround the first outermost wall and the second outermost wall of the polysilicon isolation structure, respectively. The substrate includes a single crystalline facet arranged between the first insulator pad and the second insulator pad. The top of the single crystalline facet is located above the bottommost surface of the polysilicon isolation structure, the bottommost surface of the first insulator pad, and the bottommost surface of the second insulator pad. The present invention also relates to a method for forming an isolation structure. The present invention provides reliable electrical isolation between various semiconductor devices integrated onto the same substrate.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an integrated chip and a method for forming an isolation structure. Background Art

[0002] Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). An integrated chip (IC) may use many different types of semiconductor devices depending on the application of the integrated chip. To reduce the area of ​​the integrated chip, semiconductor devices may be formed close to each other. To prevent interference between semiconductor devices, techniques and / or features for device isolation in an integrated chip are being studied. Among other things, deep trench isolation (DTI) structures are promising candidate features for providing electrical isolation between semiconductor devices to improve device performance without occupying a large area on the integrated chip. Summary of the invention

[0003] An integrated chip according to an embodiment of the present disclosure includes: a semiconductor device, which is arranged on the front side of a substrate; a polysilicon isolation structure, which continuously surrounds the semiconductor device and extends from the front side of the substrate toward the back side of the substrate; and a first insulator pad and a second insulator pad, which respectively surround the first outermost wall of the polysilicon isolation structure and the second outermost wall of the polysilicon isolation structure, wherein the substrate includes a single crystalline small plane arranged between the first insulator pad and the second insulator pad, wherein the top of the single crystalline small plane is located above the bottommost surface of the polysilicon isolation structure, the bottommost surface of the first insulator pad, and the bottommost surface of the second insulator pad.

[0004] An integrated chip according to an embodiment of the present disclosure includes: a single crystalline base layer; an active layer arranged on the single crystalline base layer; an insulator layer separating the active layer from the single crystalline base layer; a polycrystalline silicon isolation structure continuously separating an inner region of the active layer from an outer region of the active layer, wherein the polycrystalline silicon isolation structure extends through the active layer and extends into the single crystalline base layer; and an insulator pad covering the outermost wall of the polycrystalline silicon isolation structure and arranged on a horizontally extending surface of the single crystalline base layer, wherein the single crystalline base layer includes a protrusion extending outward from the horizontally extending surface of the single crystalline base layer and arranged between the insulator pads, and the protrusion has a top portion located above the bottommost surface of the insulator pad and the bottommost surface of the polycrystalline silicon isolation structure.

[0005] A method for forming an isolation structure in a substrate according to an embodiment of the present disclosure comprises: patterning the substrate to form a groove continuously surrounding a central portion of the substrate, wherein the groove extends from the top surface of the substrate toward the bottom surface of the substrate in a first direction orthogonal to the top surface of the substrate; depositing an insulator layer along the groove; removing the insulator layer from a horizontally extending surface of the substrate defining the bottom of the groove so that an insulator pad covers an outer surface of the groove defined by a side wall of the substrate; and growing polysilicon in the groove and between the insulator pads, wherein the polysilicon grows from the horizontally extending surface of the substrate toward the top surface of the substrate in a second direction orthogonal to the top surface of the substrate and opposite to the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present invention can be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A , Figure 1B and Figure 1C Various views of some embodiments of an integrated chip with a deep trench isolation (DTI) structure that is substantially defect-free and surrounds a semiconductor device are illustrated.

[0008] Figure 2A and Figure 2B Cross-sectional views illustrating some additional embodiments of integrated chips having deep trench isolation structures with polysilicon filling recessed below insulator liners.

[0009] Figure 3 Cross-sectional views of some additional embodiments of integrated chips having deep trench isolation structures in a base semiconductor substrate are illustrated.

[0010] Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Figure 7 , Fig. 8A , Figure 8B , Fig. 9 , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 11C , Fig.11D as well as Figure 12 to Figure 15Various cross-sectional and top views illustrating some embodiments of methods of forming deep trench isolation structures formed using a selective growth process to mitigate the formation of voids during the growth of polysilicon.

[0011] Fig.16 Description Figures 4 to 15 Flowcharts of some embodiments of the method.

[0012] [Explanation of Symbols]

[0013] 100A, 100C, 200A, 300, 400, 500, 600A, 700, 800A, 900, 1000A, 1100A, 1100B, 1100C, 1100D, 1200, 1300, 1500: Cross-sectional view

[0014] 100B, 600B, 800B, 1000B, 1400: Top view

[0015] 101: Substrate

[0016] 101b, 302b: bottom surface

[0017] 101c: Central Section

[0018] 101o: Outer part

[0019] 101t, 112t, 302t: Top surface

[0020] 102: Base layer

[0021] 102b: Horizontally extended surface

[0022] 104: Insulator layer

[0023] 106: Active layer

[0024] 108: Deep Trench Isolation Structure

[0025] 108i: Deep trench isolation structure inside

[0026] 108o: Outer deep trench isolation structure

[0027] 110: Polysilicon isolation structure

[0028] 110b: Grain boundary

[0029] 110g: Die

[0030] 110t: Top surface

[0031] 112: Insulator gasket

[0032] 112a: first insulator pad / insulator pad

[0033] 112b: Second insulator pad / insulator pad

[0034] 112u: Upper side wall

[0035] 114: Facet

[0036] 114p: Vertex

[0037] 120: Semiconductor devices

[0038] 200B: Schematic diagram

[0039] 204: Dielectric Structure

[0040] 206: Isolation contact

[0041] 302: Single substrate

[0042] 508: Mask structure

[0043] 510: First oxide layer

[0044] 512: First nitride layer

[0045] 514: Second oxide layer

[0046] 602: Photoresist layer

[0047] 604a: First opening

[0048] 604b: Second opening

[0049] 702: First etching process

[0050] 802: Second etching process

[0051] 804a: First groove

[0052] 804b: Second groove

[0053] 806: Dashed line

[0054] 902: Conformal oxide layer

[0055] 1002: The third etching process

[0056] 1101: Polysilicon Growth Process

[0057] 1102: Rift

[0058] 1103: Bottom-up direction

[0059] 1104: Polysilicon

[0060] 1600: Methods

[0061] 1602, 1604, 1606, 1608, 1610, 1612: Steps

[0062] AA', CC': Section line

[0063] B: Area

[0064] d1: non-zero distance

[0065] h1: first maximum height / first height

[0066] s1: average particle size

[0067] t1: first thickness

[0068] V1: First voltage terminal

[0069] V2: Second voltage terminal

[0070] V D : Drain voltage terminal

[0071] V G : Gate voltage terminal

[0072] V S : Source voltage terminal

[0073] w1: first maximum width

[0074] w2: second largest width DETAILED DESCRIPTION

[0075] The following disclosure provides many different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to make the present invention concise. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature formed on or formed on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature cannot be directly contacted. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not essentially specify the relationship between the various embodiments and / or configurations described.

[0076] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0077] In some applications, more than one semiconductor device may be integrated onto the same substrate. However, as device size decreases and voltage operating conditions increase (e.g., greater than 50 volts), it may be difficult to prevent current leakage, crosstalk between semiconductor devices, and / or eventual device performance degradation. To mitigate current leakage and device performance degradation, in some embodiments, for example, multiple semiconductor devices may be integrated onto a silicon-on-insulator (SOI) substrate including an insulator layer between an active layer and a base layer. In other embodiments, to arrange semiconductor devices closer to each other and provide more reliable device isolation, an isolation structure may be formed to electrically isolate the semiconductor devices from each other. For example, a deep trench isolation (DTI) structure filled with polysilicon may be formed to continuously surround each of the semiconductor devices. The polysilicon may be doped, and an isolation bias may be applied to the polysilicon during operation to achieve electrical isolation and improve device performance.

[0078] To form a deep trench isolation structure in, for example, a silicon-on-insulator substrate, a trench may be formed extending from the top surface of the top substrate to the insulator layer. An oxide layer is grown to line the trench, and polysilicon may be grown to fill the trench between the oxide layers. The polysilicon may be grown in a furnace and / or an epitaxial chamber. However, typically, the polysilicon may grow outward from the opposite sidewalls of the trench toward the middle of the trench, and the polysilicon eventually intersects in the middle of the trench to form a void in the polysilicon. The void may compromise the mechanical properties (e.g., yield stress) and electrical properties (e.g., resistance) of the deep trench isolation structure. In addition, the polysilicon may have an uneven top surface, and a planarization process (e.g., chemical mechanical planarization (CMP)) is required to planarize the top surface of the deep trench isolation structure in accordance with the top surface of the top substrate. In addition to increasing manufacturing time and cost, the chemical mechanical planarization process may also damage the polysilicon, especially when there is a void at a height close to the top surface of the top substrate.

[0079] Various embodiments of the present invention relate to a selective polysilicon growth process for reducing voids in polysilicon and thereby producing a reliable deep trench isolation structure. In some embodiments, a trench is formed, for example, in a silicon-on-insulator substrate having an active layer and a base layer separated by an insulator layer. The trench passes through the active layer and extends into the base layer, such that a horizontally extending surface of the base layer defines the bottom of the trench. An oxide layer is deposited along the inner surface defining the trench, and an etching process is performed to remove the oxide layer from the horizontally extending surface of the base layer. A selective growth process is performed to grow polysilicon in a bottom-up direction, such that the polysilicon grows from the horizontally extending surface of the base layer to the top surface of the active layer without starting to grow on the oxide layer. In addition, the selective growth process is performed under conditions that achieve a high polysilicon growth rate (e.g., greater than 2 microns per minute) to efficiently fill the trench, thereby forming a deep trench isolation structure. The selective growth process can reduce voids trapped in the deep trench isolation structure, and in some embodiments, since the top surface of the polysilicon is substantially smooth due to bottom-up growth, no chemical mechanical planarization step is required. Therefore, the selective growth process provides an efficient and reliable method to produce deep trench isolation structures that effectively electrically isolate semiconductor devices on a substrate.

[0080] Figure 1A A cross-sectional view 100A of some embodiments of an integrated chip is illustrated having a deep trench isolation (DTI) structure extending into a base layer of a silicon-on-insulator (SOI) substrate.

[0081] The integrated chip includes a deep trench isolation structure 108 embedded in a substrate 101. In some embodiments, the substrate 101 may be a silicon-on-insulator substrate and include a base layer 102, an insulator layer 104 disposed on the base layer 102, and an active layer 106 disposed on the insulator layer 104. In some such embodiments, the insulator layer 104 is an oxide (e.g., silicon dioxide, germanium oxide). In other embodiments, the substrate may be a base substrate comprising a semiconductor material (e.g., silicon, germanium, etc.).

[0082] In some embodiments, the deep trench isolation structure 108 includes a first insulator liner 112a and a second insulator liner 112b. The polysilicon isolation structure 110 is arranged between the first insulator liner 112a and the second insulator liner 112b. The deep trench isolation structure 108 extends from a top surface 101t of the substrate 101 (e.g., a front side of the substrate 101) toward a bottom surface 101b of the substrate 101 (e.g., a back side of the substrate 101). In some embodiments, the topmost surface 110t of the polysilicon isolation structure 110, the top surface 112t of the first insulator liner 112a and the top surface 112t of the second insulator liner 112b, and the top surface 101t of the substrate 101 are substantially coplanar. In some embodiments, the deep trench isolation structure 108 may have a first maximum height h1 greater than about 7 microns. The deep trench isolation structure 108 may also have a first maximum width w1, which in some embodiments is in a range between about 1.5 microns and about 3 microns. In some embodiments, there are two deep trench isolation structures 108 spaced apart from each other by the substrate 101, such as an inner deep trench isolation structure 108i and an outer deep trench isolation structure 108o. In other embodiments (not shown), there may be one or more deep trench isolation structures 108 in the substrate 101. The deep trench isolation structure 108 extends completely through the active layer 106 and the insulator layer 104, so that the bottom surface of the deep trench isolation structure 108 directly contacts the base layer 102.

[0083] In addition, in some embodiments, the base layer 102 may include a facet 114 that protrudes toward the topmost surface 110t of the polysilicon isolation structure 110. In some embodiments, the base layer 102 including the facet 114 is a single crystalline semiconductor material. For example, the base layer 102 may include single crystalline silicon or single crystalline germanium. In some embodiments, from the cross-sectional view 100A, the facet 114 may include a triangular profile. The vertex 114p of the facet 114 may be located above the bottommost surface of the deep trench isolation structure 108. For example, in some embodiments, the vertex 114p of the facet 114 may be located above the bottommost surface of the first insulator liner 112a and the bottommost surface of the second insulator liner 112b and / or the bottommost surface of the polysilicon isolation structure 110. In addition, in some embodiments, the vertex 114p of the facet 114 may also be located above the bottommost surface of the insulator layer 104. The polysilicon isolation structure 110 may separate the vertex 114p of the facet 114 and the sidewalls of the facet 114 that meet at the vertex 114p from the first insulator liner 112a and the second insulator liner 112b. The surface of the base layer 102 surrounding the facet 114 may directly contact the bottom surface of the polysilicon isolation structure 110. Therefore, the polysilicon isolation structure 110 may include, for example, polysilicon of a single crystalline silicon material that directly contacts the facet 114. In some other embodiments, the polysilicon isolation structure 110 may include, for example, doped polysilicon.

[0084] In some embodiments, the inner deep trench isolation structure 108i may be coupled to a first voltage terminal V1, and the outer deep trench isolation structure 108o may be coupled to a second voltage terminal V2. In some embodiments, the first voltage terminal V1 and the second voltage terminal V2 may be the same voltage terminal, so that the inner deep trench isolation structure 108i and the outer deep trench isolation structure 108o have the same bias voltage. Therefore, the polysilicon isolation structure 110 in each of the deep trench isolation structures 108 may be biased to provide sufficient electrical isolation between various semiconductor devices located on the substrate 101.

[0085] Figure 1B A top view 100B is shown illustrating some embodiments of a DTI structure surrounding a semiconductor device.

[0086] The top view 100B illustrates the cross-sectional line AA', which may correspond to the cross-sectional view 100A of 1A. In some embodiments, the outer deep trench isolation structure 108o with the insulator liner 112 may continuously surround the inner deep trench isolation structure 108i, and the inner deep trench isolation structure 108i with the insulator liner 112 may continuously surround the semiconductor device 120. The deep trench isolation structures 108 may each exhibit some type of "ring-like" shape, which may mean that the deep trench isolation structure 108 is a continuously connected structure. For example, in some embodiments of the top view 100B, the deep trench isolation structures 108 each have a rectangular ring-like shape, while in other embodiments, the deep trench isolation structures 108 exhibit, for example, a circular ring-like shape, an elliptical ring-like shape, or some other ring-like geometric shape. It should be understood that in some embodiments, the outer deep trench isolation structure 108 o may be omitted to save space on the substrate 101 , while in other embodiments, more than two deep trench isolation structures 108 may be used to improve electrical isolation of the semiconductor device 120 .

[0087] Figure 1C A cross-sectional view 100C illustrating some embodiments of an integrated chip, the cross-sectional view 100C corresponding to Figure 1B Section line CC'.

[0088] In some embodiments, the semiconductor device 120 may be, for example, a transistor device, such as a metal oxide semiconductor field effect transistor (MOSFET). In such embodiments, the semiconductor device 120 (e.g., a metal oxide semiconductor field effect transistor) may be disposed on the front side of the active layer 106 of the substrate 101 and include a gate voltage terminal V G The gate structure is coupled to the source voltage terminal V S The source region and coupled to the drain voltage terminal V D In some embodiments, the inner deep trench isolation structure 108i may be spaced apart from the semiconductor device 120. However, the semiconductor device 120 may be disposed in a portion of the active layer 106, surrounded by an insulating material (insulator layer 104, first insulator liner 112a of the inner deep trench isolation structure 108i) to assist in electrically isolating the semiconductor device 120. In addition, the inner deep trench isolation structure 108i and the outer deep trench isolation structure 108o may be sufficiently biased to mitigate leakage of the semiconductor device 120, thereby reducing power loss of other devices integrated on the substrate 101 and cross-talk between the other devices.

[0089] Figure 2AA cross-sectional view 200A illustrating some additional embodiments of an integrated chip including a deep trench isolation structure in a silicon-on-insulator substrate.

[0090] In some embodiments, the dielectric structure 204 overlies the deep trench isolation structure 108. The isolation contact 206 is disposed within the dielectric structure 204 and coupled to the polysilicon isolation structure 110 of the deep trench isolation structure 108. The isolation contact 206 may be one or more conductive materials coupled to the first voltage terminal V1 and the second voltage terminal V2 so that the polysilicon isolation structure may be biased to isolate the semiconductor device ( Figure 1B 120) is electrically isolated from the polysilicon isolation structure 110. In some embodiments, the topmost surface 110t of the polysilicon isolation structure 110 may be located below the top surface 112t of the first insulator liner 112a and the top surface 112t of the second insulator liner 112b and the top surface 101t of the substrate 101. For example, in some embodiments, the topmost surface 110t of the polysilicon isolation structure 110 may be located at a non-zero distance d1 below the top surfaces of the insulator liners 112a, 112b. In some such embodiments, the top surface 112t of the first insulator liner 112a and the top surface 112t of the second insulator liner 112b and the top surface 101t of the substrate 101 may still be substantially coplanar. In addition, in some embodiments, from the cross-sectional view 200A, the polysilicon isolation structure 110 may have non-coplanar outer sidewalls, which may be due to, for example, residual effects of manufacturing the first insulator liner 112a and the second insulator liner 112b.

[0091] Figure 2B illustrate Figure 2A Some embodiments of a schematic diagram 200B of a die structure in region B of a polysilicon isolation structure 110 are shown.

[0092] Figure 2B Schematic diagram 200B microscopically shows Figure 2B The polysilicon isolation structure 110 has polysilicon dies 110g, for example, the dies 110g are separated by grain boundaries 110b. In some embodiments, the average grain size s1 is used to quantify the average size of the dies 110g in a certain area. For example, various techniques (e.g., linear intercept method, grain size per area method, and other software methods) can be used to calculate the average grain size from the microstructure image, however, the average grain size can be quantified as an average grain diameter (e.g., length, width, height). In addition, many factors affect the average grain size of the material, such as processing methods, processing conditions (e.g., temperature, pressure, etc.) and composition. In some embodiments, the polysilicon isolation structure 110 may have an average grain size s1 greater than about 300 nanometers, which in some embodiments may indicate that the growth rate of polysilicon during manufacturing is high.

[0093] Figure 3 A cross-sectional view 300 of some embodiments of an integrated chip including a deep trench isolation structure in a substrate is illustrated.

[0094] In some embodiments, the deep trench isolation structure 108 may be embedded within a single substrate 302 that includes the same semiconductor material extending between a top surface and a bottom surface of the single substrate 302. In some such embodiments, when a single substrate 302 is used instead of a silicon-on-insulator substrate (SOI) Figure 1A 101), to compensate for the insulator layer ( Figure 1A 104), more deep trench isolation structures 108 can be arranged around the semiconductor device under the same conditions. In other embodiments, one deep trench isolation structure 108 may still be sufficient to isolate the semiconductor device on a single substrate 302.

[0095] In some embodiments, the first insulator liner 112a and the second insulator liner 112b may have rounded bottom surfaces, which may be due in part to processing conditions. In some embodiments, the single substrate 302 may be a single crystalline semiconductor material (e.g., single crystalline silicon). In some embodiments, the single substrate 302 includes a facet 114. Therefore, in such embodiments, the facet 114 is also the same single crystalline semiconductor material as the single substrate 302. In some embodiments, from the cross-sectional view 300, the facet 114 may exhibit an overall triangular shape, but with rough or non-coplanar edges. The deep trench isolation structure 108 may extend from the top surface 302t of the single substrate 302 toward the bottom surface 302b of the single substrate 302, but may not extend completely through the single substrate 302. However, in some embodiments, the facet 114 may have a top portion disposed above the bottommost surface of the first insulator liner 112a and the bottommost surface of the second insulator liner 112b. The deep trench isolation structure 108 may extend close to the bottom surface 302b of the single substrate 302 to provide as much electrical isolation as possible without sacrificing the mechanical strength of the single substrate 302. For example, in some embodiments, the lower surface of the deep trench isolation structure 108 may be spaced apart from the bottom surface 302b of the single substrate 302 by a distance in a range between 10 nanometers and 100 nanometers.

[0096] Figures 4 to 15 Cross-sectional and top view diagrams 400 to 1400 illustrate some embodiments of methods of forming deep trench isolation (DTI) structures having substantially defect-free polysilicon isolation structures for reliable electrical isolation. Figures 4 to 15 , but it should be understood that Figures 4 to 15The structure disclosed in is not limited to this method, but can be used as a separate structure independently of the method.

[0097] like Figure 4 As shown in the cross-sectional view 400 of , a substrate 101 is provided. The substrate 101 may be a silicon-on-insulator substrate, and the silicon-on-insulator substrate includes a base layer 102, an insulator layer 104 located on the base layer 102, and an active layer 106 located on the insulator layer 104. In some embodiments, the base layer 102 includes a single crystalline semiconductor material (e.g., silicon, germanium, etc.). Similarly, the active layer 106 may also include a semiconductor material, such as silicon, germanium, etc. In some embodiments, the active layer 106 may include, for example, p-type silicon doped with boron. In such embodiments, the doping concentration of the active layer 106 may be, for example, 10 per cubic centimeter. 15 In some embodiments, the active layer 106 has a thickness in a range of, for example, about 6.5 microns and about 7.5 microns. In other embodiments, the active layer 106 has a thickness equal to about 7 microns. In some embodiments, the insulator layer 104 can be a matrix oxide, which includes, for example, silicon oxide. In other embodiments, the insulator layer 104 can include, for example, nitrides, carbides, or some other dielectric materials. The insulator layer 104 can have a thickness in a range of, for example, about 0.2 microns and about 0.4 microns. In other embodiments, the insulator layer 104 can have a thickness equal to about 0.3 microns.

[0098] like Figure 5As shown in the cross-sectional view 500 of , a mask structure 508 is formed over the top surface 101t of the substrate 101. The mask structure 508 can be used, for example, to pattern the substrate 101 and also protect the substrate 101. In some embodiments, the mask structure 508 includes one or more hard mask layers (e.g., a silicon nitride layer, a silicon carbide layer, etc.). For example, in the cross-sectional view 500, the mask structure 508 may include a stack of a first oxide layer 510 including silicon oxide, a first nitride layer 512 including silicon nitride, and a second oxide layer 514 including silicon oxide. In some embodiments, the first oxide layer 510 may be a native oxide grown on the top surface 101t of the substrate 101. The mask structure 508 may be formed by one or more deposition techniques (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), sputtering, etc.).

[0099] like Fig. 6A As shown in the cross-sectional view 600A of , a photoresist layer 602 may be deposited over the mask structure 508 and patterned to define a first opening 604a and a second opening 604b. The photoresist layer 602 may be deposited via a spin coating process. The photoresist layer 602 may then be selectively exposed to electromagnetic radiation according to a photomask. The electromagnetic radiation modifies the solubility of the exposed areas within the photoresist layer 602 to define soluble areas. Subsequently, the photoresist layer 602 is developed to define a first opening 604a and a second opening 604b after removing the soluble areas.

[0100] In some embodiments, cross-sectional view 600A corresponds to Figure 6B An embodiment of the section line AA' in the top view 600B.

[0101] From the top view 600B, the first opening 604a and the second opening 604b in the photoresist layer 602 are continuously connected openings. The first opening 604a and the second opening 604b expose the mask structure ( Fig. 6A The first opening 604a and the second opening 604b will define the inner deep trench isolation (DTI) structure and the outer deep trench isolation structure ( Figure 1AHowever, in other embodiments, for example, each semiconductor device of the integrated chip includes only one deep trench isolation structure, and therefore, either the first opening 604a or the second opening 604b is formed in the photoresist layer 602. However, the substrate ( Fig. 6A In some embodiments, the first opening 604a and the second opening 604b may each have a first maximum width w1 in a range between about 1.5 microns and about 3 microns, for example.

[0102] like Figure 7 As shown in the cross-sectional view 700 of FIG. 1 , a first etching process 702 (e.g., wet etching, dry etching) may be performed to remove portions of the mask structure 508 that are not covered by the photoresist layer 602. After the first etching process 702, the first opening 604a and the second opening 604b extend through the mask structure 508 to expose portions of the substrate 101.

[0103] like Fig. 8A As shown in the cross-sectional view 800A of FIG. 8 , the photoresist layer ( Figure 7 602), and a second etching process 802 is performed to form a first trench 804a and a second trench 804b in the substrate 101. The first trench 804a and the second trench 804b are formed by the first opening and the second opening ( Figure 7 604a, 604b). In some embodiments, the second etching process 802 utilizes a dry etchant rather than a wet etchant to achieve substantially coplanar sidewalls of the first trench 804a and the second trench 804b. The sidewalls of the first trench 804a and the sidewalls of the second trench 804b are defined by the inner surface of the substrate 101. In some embodiments, the first trench 804a and the second trench 804b have substantially vertical sidewalls, while in other embodiments, the first trench 804a and the second trench 804b may have angled sidewalls as illustrated by dashed lines 806. In an embodiment where the substrate 101 is a silicon-on-insulator substrate, the first trench 804a and the second trench 804b extend into the base layer 102 such that a horizontally extending surface 102b of the base layer 102 defines the bottom of the first trench 804a and the bottom of the second trench 804b. In some embodiments, the first trench and the second trench may have a first maximum height h1 measured from the top surface 101 t of the substrate 101 , the first maximum height h1 being greater than about 7 micrometers.

[0104] In some embodiments, cross-sectional view 800A corresponds to Figure 8B An embodiment of the section line AA' in the top view 800B.

[0105] From the top view 800B, the base layer 102 is not covered by the mask structure ( Fig. 8A The first trench 804a and the second trench 804b are covered with a second oxide layer 514 of the substrate 108. It should be understood that in some embodiments, the first trench 804a and the second trench 804b each have a rectangular ring shape, while in other embodiments, the first trench 804a and the second trench 804b each exhibit, for example, a circular ring shape, an elliptical ring shape, or some other ring-shaped (e.g., continuously connected) geometric shape. The first trench 804a can continuously surround the central portion 101c of the substrate 101 and separate the central portion 101c of the substrate 101 from the outer portion 101o of the substrate 101.

[0106] like Fig. 9 As shown in the cross-sectional view 900 of , a conformal oxide layer 902 is grown on the substrate 101. In some embodiments, the conformal oxide layer 902 is formed by a thermal growth process in a furnace chamber. In some embodiments, the conformal oxide layer 902 may be formed by a deposition process (e.g., chemical vapor deposition, plasma enhanced chemical vapor deposition, etc.). In some embodiments, the conformal oxide layer 902 may include an oxide, such as silicon oxide. In other embodiments, the conformal oxide layer 902 may include some other dielectric material, such as silicon carbide, silicon oxide, or silicon oxynitride. In addition, in some embodiments, the conformal oxide layer 902 may have a first thickness t1 in a range of, for example, between about 300 nanometers and about 500 nanometers. In some embodiments, the first trench 804a and the second trench 804b are not completely filled with the conformal oxide layer 902, and there is still a cavity with a second maximum width w2 between the conformal oxide layer 902. In some embodiments, the second maximum width w2 is in a range of, for example, between about 400 nanometers and about 500 nanometers.

[0107] like Fig. 10A As shown in the cross-sectional view 1000A of FIG. 1 , a third etching process 1002 is performed to remove the conformal oxide layer ( Fig. 9 The third etching process 1002 removes the conformal oxide layer ( 902 ) from the bottom of the first trench 804a and the bottom of the second trench 804b. Fig. 9902), so that the horizontal extension surface 102b of the base layer 102 is exposed after the third etching process 1002. In some embodiments, the third etching process 1002 utilizes a vertical dry etchant, so no masking layer is required. Due to the third etching process 1002, the upper sidewall 112u of the first insulator pad 112a and the upper sidewall 112u of the second insulator pad 112b may have rounded edges. In other words, in some embodiments, the thickness of the upper portion of the first insulator pad 112a and the upper portion of the second insulator pad 112b may be less than the thickness of the lower portion of the first insulator pad 112a and the lower portion of the second insulator pad 112b. In some embodiments, due to the residual effect of the third etching process 1002, the height of the mask structure 508 may be reduced. However, the mask structure 508 may still cover the top surface 101t of the substrate 101.

[0108] In some embodiments, cross-sectional view 1000A corresponds to Fig. 10B An embodiment of the section line AA' in the top view 1000B.

[0109] From the top view 1000B, the horizontally extending surface 102b of the base layer 102 is not covered by oxide. It should be understood that the base layer 102 is a wafer, and in some embodiments, the wafer has a generally circular shape. In some embodiments, at this point in the manufacturing process, at least 50% of the top surface area of ​​the substrate 101 (e.g., wafer) is covered with oxide. Therefore, less than 50% of the top surface area of ​​the wafer constituting the substrate 101 is the horizontally extending surface 102b of the base layer 102, and the less than 50% top surface area is exposed semiconductor material (e.g., silicon). The polysilicon (see FIG. 11A to FIG. 11D ) from the horizontally extending surface 102b of the base layer 102. In addition, in some other embodiments, at this point in the manufacturing process, at least 98% of the top surface area of ​​the substrate 101 (e.g., wafer) is covered with oxide. Thus, in such other embodiments, less than 2% of the top surface area of ​​the wafer making up the substrate 101 is the horizontally extending surface 102b of the base layer 102, and the less than 2% of the top surface area is exposed semiconductor material (e.g., silicon). By having at least 98% of the top surface area of ​​the wafer covered with oxide, the polysilicon (see FIG. 11A to FIG. 11D) The growth rate from the horizontally extending surface 102b of the base layer may be 2 to 3 times greater than when approximately 50% of the top surface area of ​​the wafer is covered with oxide. In yet other embodiments, the horizontally extending surface 102b of the base layer 102 exposed in the top view 1000B is equal to approximately 1.29% of the top surface area of ​​the wafer constituting the substrate 101. In other words, from the top view 1000B, in some embodiments, the second oxide layer 514 has a first total surface area on the wafer, the first insulator liner 112a and the second insulator liner 112b have a second total surface area on the wafer, and the horizontally extending surface 102b of the base layer 102 exposed on the wafer has a third total surface area. The sum of the first total surface area, the second total surface area, and the third total surface area may be equal to, for example, the fourth total surface area. In some embodiments, the ratio of the third total surface area to the fourth total surface area may be less than approximately 50%. In other embodiments, the ratio of the third total surface area to the fourth total surface area may be, for example, less than or equal to approximately 1.3%.

[0110] FIG. 11A to FIG. 11D Cross-sectional view 1100A of some embodiments illustrating polysilicon growth process 1101 at different times. For example, Fig.11A 1100A illustrates a cross-sectional view of a time period immediately after the polysilicon growth process has begun. Fig.11D Cross-sectional view 1100D is illustrated near the time of the end of the polysilicon growth process.

[0111] A polysilicon growth process 1101 is performed to fill the first trench 804a and the second trench 804b with polysilicon. The substrate 101 may be loaded into a chamber for a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process. In some embodiments, the substrate 101 is loaded into a low pressure chemical vapor deposition (LPCVD) chamber. The chamber conditions are adjusted so that the polysilicon growth process 1101 has a fast growth rate to fill the first trench 804a and the second trench 804b, and has a high selectivity to the base layer 102 (e.g., silicon) and no selectivity to the oxide (first insulator liner 112a, second insulator liner 112b, second oxide layer 514). Considering that the first trench 804a and the second trench 804b may have a first height greater than 7 microns ( Fig. 8Ah1), and the first height greater than 7 microns is large for a typical polysilicon growth process, so a fast growth rate is desired to increase throughput. In addition, it is desired to have a high selectivity to the base layer 102 so that polysilicon grows in a bottom-up direction. For example, the first trench 804a and the second trench 804b extend into the substrate 101 in a first direction orthogonal to the top surface 101t of the substrate 101, and the polysilicon growth process 1101 is controlled to grow in a second direction also orthogonal to the top surface 101t of the substrate 101 and opposite to the first direction.

[0112] In some embodiments, to facilitate high growth rates, the temperature of the chamber is set to be in a range of, for example, between about 850 degrees Celsius and about 1100 degrees Celsius, and the pressure of the chamber may be set to be in a range of, for example, between about 10 Torr and about 300 Torr. In addition, high oxide surface area coverage may facilitate high growth rates of polysilicon. Thus, as described above with respect to Fig. 10B As shown, at least 50% of the top surface area of ​​the substrate 101 (e.g., wafer) is covered by oxide (first insulator liner 112a, second insulator liner 112b, second oxide layer 514). Therefore, less than 50% of the top surface area of ​​the substrate 101 (e.g., wafer) is the horizontally extending surface 102b of the base layer 102 to facilitate a high growth rate of polysilicon, and less than 50% of the top surface area is exposed semiconductor material (e.g., silicon).

[0113] In addition, the above temperature and pressure parameters and the composition and concentration of the first precursor can assist in the highly selective growth of polysilicon onto the exposed semiconductor material (e.g., silicon) of the base layer 102. For example, in some embodiments, the first precursor may include dichlorosilane gas (DCS) for silicon growth, hydrogen chloride gas (HCl) for removing defects during growth, and boron gas (B2H6) for doping silicon during growth. In some embodiments, the ratio of HCl to DCS in the chamber during the polysilicon growth process 1101 is in the range of about 2 and about 8. In other embodiments, the ratio of HCl to DCS in the chamber is higher than 5 to mitigate particle formation defects in the oxide, and lower than 10 to prevent the etching effect of HCl from being too large and causing the polysilicon to grow too slowly. As the ratio of HCl to DCS increases, the polysilicon growth process 1101 becomes more selective to silicon. In some embodiments, HCl flows into the chamber at a rate of about 400 standard cubic centimeters per minute, and DCS flows into the chamber at a rate in a range between about 70 standard cubic centimeters per minute and about 200 standard cubic centimeters per minute. In some embodiments, B2H6 flows into the chamber at a rate of about 200 standard cubic centimeters per minute. In some embodiments, the boron concentration of polysilicon 1104 may be about 2 x 10 18dopant atoms (e.g., boron) and approximately 2 x 10 19 Therefore, in some embodiments, the polysilicon 1104 can have a higher dopant concentration than the active layer 106. In addition, in some embodiments, the active layer 106 and the polysilicon 1104 can have the same doping type.

[0114] like Fig.11A As illustrated in the cross-sectional view 1100A of , in some embodiments, during the first time in the polysilicon growth process 1101, a facet 114 is formed, which is part of the base layer 102. Therefore, in some embodiments, the facet 114 and the base layer 102 are part of the same single crystalline silicon. The facet 114 is formed due to the high selectivity of the polysilicon growth process 1101. DCS causes the exposed base layer 102 to grow with the single crystalline silicon, but HCl etches away some parts of the growing single crystalline silicon. The facet 114 is the single crystalline silicon that remains. The facet 114 includes the main plane 111 of silicon, because the plane 111 has the highest packing density compared to other lattice planes in the silicon structure, and therefore has the highest surface energy. Therefore, the plane 111 of silicon can prevent etching by HCl, and the facet 114 is similar to the triangular protrusion of the base layer 102. Since the facet 114 is a result of the polysilicon growth process 1101, the facet 114 is located above the bottommost surface of the first insulator liner 112a and the bottommost surface of the second insulator liner 112b, and therefore, the facet 114 is grown after forming the first trench 804a and the second trench 804b.

[0115] In some embodiments, polysilicon 1104 starts growing at the crack 1102 between the facet 114 and one of the first insulator liner 112a or the second insulator liner 112b. Thus, the polysilicon growth process 1101 is selective to single crystalline silicon, and the growth changes from single crystalline silicon to polysilicon near the crack 1102 and in contact with one of the first insulator liner 112a or the second insulator liner 112b.

[0116] like Fig. 11B110B, illustrating a polysilicon growth process 1101 during a second time period greater than the first time period. Polysilicon 1104 continues to grow in the first trench 804a and the second trench 804b in the bottom-up direction 1103. Due to the conditions of the furnace and the composition and concentration of the first precursor, the polysilicon 1104 continues to selectively grow from itself in the bottom-up direction 1103, and the growth of the polysilicon 1104 does not originate from the first insulator liner 112a and the second insulator liner 112b nor from the mask structure 508. In some embodiments, the selective conditions of the furnace may be as follows: the temperature is about 1040 degrees Celsius, the pressure is about 80 Torr, about 1.29% of the surface area of ​​the substrate 101 is not covered by oxide, and the ratio of HCl to DCS is 5.7, wherein the HCl has a flow rate of about 400 standard cubic centimeters per minute, and wherein the DCS has a flow rate of about 70 standard cubic centimeters per minute. In addition, in some embodiments, the polysilicon 1104 is doped during the deposition of the polysilicon 1104. For example, in some embodiments, the polysilicon 1104 can be doped using boron mixed with hydrogen (B2H6) at a flow rate of about 200 standard cubic centimeters per minute, so that the polysilicon 1104 can be more effectively biased to achieve electrical isolation. This selective condition can allow the growth rate of the polysilicon 1104 to be equal to about 2 microns per minute. Due to the high growth rate, the polysilicon 1104 can have an average grain size greater than 300 nanometers. In addition, since the polysilicon growth process 1101 is selective, the polysilicon 1104 can grow in the bottom-up direction 1103, thereby reducing the retention of voids.

[0117] like Fig. 11C As shown in the cross-sectional view 1100C of , at a predetermined time after the second time in the polysilicon growth process 1101, the polysilicon 1104 may have a top surface located at the same level or approximately the same level as the top surface 101t of the substrate 101. Therefore, in some embodiments, since the polysilicon growth process 1101 is performed in the bottom-up direction 1103, the polysilicon 1104 has minimal voids and may have a top surface at or below the top surface 101t of the substrate 101. In addition, in some embodiments, the polysilicon 1104 may have a substantially smooth or flat top surface. In some embodiments, the polysilicon growth process 1101 may be stopped at a predetermined time so that the top surface of the polysilicon 1104 is located at the same or approximately the same level as the top surface 101t of the substrate 101. In some embodiments, the top surface of the polysilicon 1104 may be slightly lower than the top surface 101t of the substrate 101 (see Figure 2A ), in such embodiments where the polysilicon growth process 1101 stops at a predetermined time, the method may continue to Fig.13 , and therefore, skip Fig.11D and Fig.12 Steps in .

[0118] like Fig.11D As shown in the cross-sectional view 1100D of FIG. 1 , in some embodiments, the polysilicon growth process 1101 may continue to a fourth time after the predetermined time, so that the polysilicon 1104 may be grown above the top surface 101t of the substrate 101. Fig. 11C The cross-sectional view 1100C shows more polysilicon 1104, but because the polysilicon growth process 1101 is performed in a bottom-up direction 1103, the polysilicon 1104 still has no or mostly no voids.

[0119] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , if the polysilicon growth process ( Fig.11D 1101) is grown above the top surface 101t of the substrate 101 (e.g., Fig.11D ), a planarization process is performed on the polysilicon 1104. The planarization process (eg, chemical mechanical planarization) may be performed so that the polysilicon 1104, the first insulator liner 112a, the second insulator liner 112b, and the mask structure 508 have substantially coplanar upper surfaces.

[0120] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , the mask structure ( Fig.12 In some embodiments, the mask structure ( Fig.12 508). In some embodiments, Fig.12 Planarization process and Fig.13 The planarization process can be a single and identical planarization process. Fig.12 After that, deep trench isolation (DTI) structures 108 each including a polysilicon isolation structure 110 are embedded in the substrate 101, and the deep trench isolation structure 108 has an upper surface substantially coplanar with the top surface 101t of the substrate 101.

[0121] In some embodiments, if the polysilicon growth process 1101 makes the polysilicon ( Fig.12 1104) is higher than the top surface 101t of the substrate 101 (see Fig.11D ), then remove the mask structure ( Fig.12 508) will also remove polysilicon ( Fig.12 Some parts of 1104).

[0122] In other embodiments, the mask structure ( Fig.12 508) removal from Fig. 11C The example continues, skipping Fig.11D and Fig.12 Therefore, before removing the mask structure ( Fig.12 During the planarization process of 508), the polysilicon ( Fig. 11C 1104). Therefore, by stopping the polysilicon growth process at a predetermined time ( Fig. 11C 1101), can be omitted Fig.12 The planarization process illustrated in the cross-sectional view 1200 of can be used to save material and improve throughput.

[0123] like Fig.14 As shown in the top view 1400 of FIG. 1 , the semiconductor device 120 may be formed such that the deep trench isolation structure 108 continuously surrounds the semiconductor device 120. In some embodiments, the semiconductor device 120 may be a transistor device, such as a metal oxide semiconductor field effect transistor (MOSFET). The semiconductor device 120 may be manufactured using common manufacturing methods (e.g., layer deposition, photolithography, and etching processes).

[0124] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 15 , in some embodiments, a dielectric structure 204 may be formed on the substrate 101, and an isolation contact 206 may be formed in the dielectric structure 204, and the isolation contact 206 is coupled to each polysilicon isolation structure 110 of the deep trench isolation structure 108. In some embodiments, the dielectric structure 204 may include, for example, nitride (e.g., silicon nitride, silicon oxynitride), carbide (e.g., silicon carbide), oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant (low-k) value oxide (e.g., carbon-doped oxide, SiCOH), etc. The dielectric structure 204 may be formed in a semiconductor device (e.g., a semiconductor device) surrounded by the deep trench isolation structure 108. Fig.14 The dielectric structure 204 and the isolation contact 206 are then formed. The isolation contact 206 can supply a bias voltage to the polysilicon isolation structure 110 without a gap, so that the deep trench isolation structure 108 is a semiconductor device ( Fig.14 120) provides adequate electrical isolation.

[0125] Fig.16 illustrate Figures 4 to 15 Flowchart of some embodiments of a method 1600 of forming a deep trench isolation structure as described in .

[0126] Although method 1600 is described and illustrated below as a series of steps (acts) or events, it should be understood that the illustrated ordering of these steps or events should not be interpreted in a limiting sense. For example, in addition to the order illustrated and / or described herein, some steps may also occur in a different order and / or occur simultaneously with other steps or events. In addition, all of the steps illustrated may not be required to implement one or more aspects or embodiments of the description herein. In addition, one or more of the steps illustrated herein may be implemented in one or more separate steps and / or stages.

[0127] At step 1602, the substrate is patterned to form a trench that continuously surrounds a central portion of the substrate. Fig. 8A Cross-sectional view 800A of some embodiments corresponding to step 1602 is illustrated.

[0128] At step 1604, an oxide layer is deposited along the trenches. Fig. 9 Cross-sectional view 900 of some embodiments corresponding to step 1604 is illustrated.

[0129] At step 1606, the oxide layer is removed from the bottom of the trench defined by the horizontally extending surface of the substrate to form an insulator liner. Fig. 10A Cross-sectional view 1000A of some embodiments corresponding to step 1606 is illustrated.

[0130] At step 1608, polysilicon is grown in the trenches and between the insulator liners such that the polysilicon grows in a bottom-up direction. FIG. 11A to FIG. 11D Cross-sectional views 1100A to 1100D illustrate some embodiments corresponding to step 1608 .

[0131] At step 1610, a semiconductor device is formed on a substrate such that polysilicon surrounds the semiconductor device. Fig.14 Top view 1400 of some embodiments corresponding to step 1610 is illustrated.

[0132] At step 1612, a first contact is formed on the semiconductor device and a second contact is formed on the polysilicon, wherein the contacts are embedded in a dielectric structure. Fig.15 Cross-sectional view 1500 of some embodiments corresponding to step 1612 is illustrated.

[0133] Therefore, the present invention relates to a method of forming a deep trench isolation structure by growing substantially defect-free polysilicon in a bottom-up direction to fill the deep trench isolation structure with the polysilicon, thereby providing reliable electrical isolation between various semiconductor devices integrated on the same substrate.

[0134] Therefore, in some embodiments, the present invention relates to an integrated chip, which includes: a semiconductor device, which is arranged on the front side of a substrate; a polysilicon isolation structure, which continuously surrounds the semiconductor device and extends from the front side of the substrate toward the back side of the substrate; and a first insulator pad and a second insulator pad, which respectively surround the first outermost wall of the polysilicon isolation structure and the second outermost wall of the polysilicon isolation structure, wherein the substrate includes a single crystalline small plane arranged between the first insulator pad and the second insulator pad, wherein the top of the single crystalline small plane is located above the bottommost surface of the polysilicon isolation structure, the bottommost surface of the first insulator pad and the bottommost surface of the second insulator pad.

[0135] In some embodiments, the substrate is single crystalline. In some embodiments, the single crystalline facet has a triangular profile when viewed in cross-section. In some embodiments, the substrate comprises: a semiconductor base layer; an insulator layer located above the semiconductor base layer; and a semiconductor active layer located above the insulator layer, and in some embodiments, the semiconductor base layer comprises the single crystalline facet. In some embodiments, the polysilicon isolation structure comprises an average grain size greater than 300 nanometers. In some embodiments, the polysilicon isolation structure has a topmost surface located below a topmost surface of the substrate.

[0136] In other embodiments, the present invention relates to an integrated chip, which includes: a single crystalline base layer; an active layer arranged on the single crystalline base layer; an insulator layer separating the active layer from the single crystalline base layer; a polycrystalline silicon isolation structure continuously separating an inner region of the active layer from an outer region of the active layer, wherein the polycrystalline silicon isolation structure extends through the active layer and extends into the single crystalline base layer; and an insulator pad covering the outermost wall of the polycrystalline silicon isolation structure and arranged on a horizontally extending surface of the single crystalline base layer, wherein the single crystalline base layer includes a protrusion extending outward from the horizontally extending surface of the single crystalline base layer and arranged between the insulator pads, the protrusion having a top located above the bottommost surface of the insulator pad and the bottommost surface of the polycrystalline silicon isolation structure.

[0137] In some embodiments, the polysilicon isolation structure has a height greater than or equal to about 7 microns. In some embodiments, the protrusion includes sidewalls that meet at a vertex, and wherein the sidewalls are separated from the insulator liner by the polysilicon isolation structure. In some embodiments, the polysilicon isolation structure comprises p-type doped polysilicon. In some embodiments, an additional polysilicon isolation structure is further included, which continuously surrounds the polysilicon isolation structure and is separated from the polysilicon isolation structure by the outer region of the active layer. In some embodiments, the polysilicon isolation structure has a topmost surface located below a topmost surface of the insulator liner.

[0138] In another embodiment, the present invention relates to a method for forming an isolation structure in a substrate, the method comprising: patterning the substrate to form a groove continuously surrounding a central portion of the substrate, wherein the groove extends from the top surface of the substrate toward the bottom surface of the substrate in a first direction orthogonal to the top surface of the substrate; depositing an insulator layer along the groove; removing the insulator layer from a horizontally extending surface of the substrate defining the bottom of the groove so that an insulator pad covers an outer surface of the groove defined by the sidewalls of the substrate; and growing polycrystalline silicon in the trench and between the insulator pads, wherein the polycrystalline silicon grows from the horizontally extending surface of the substrate toward the top surface of the substrate in a second direction orthogonal to the top surface of the substrate and opposite to the first direction.

[0139] In some embodiments, the polysilicon is grown in a chamber using a first precursor comprising a ratio of hydrogen chloride gas to dichlorosilane gas between about 5 and about 8. In some embodiments, the first precursor further comprises boron gas to dope the polysilicon. In some embodiments, the polysilicon is grown at a temperature between about 850 degrees Celsius and about 1100 degrees Celsius and a pressure between about 10 torr and about 300 torr. In some embodiments, the growth of the polysilicon has a growth rate greater than 2 microns per minute. In some embodiments, the growth of the polysilicon stops at a predetermined time before the polysilicon grows beyond the top surface of the substrate. In some embodiments, at the predetermined time, the polysilicon has a substantially flat topmost surface. In some embodiments, the substrate is a wafer having a circular shape, and in some embodiments, less than 50% of the substrate is exposed after removing the insulator layer and before growing the polysilicon.

[0140] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated chip, comprising: A single crystalline base layer; An active layer disposed on the single crystalline base layer; an insulator layer separating the active layer from the single crystalline base layer; a semiconductor device disposed on the front side of the active layer; a polysilicon isolation structure continuously surrounding the semiconductor device and extending through the active layer and the insulator layer and into the single crystalline base layer; as well as A first insulator liner and a second insulator liner surround the first outermost wall of the polysilicon isolation structure and the second outermost wall of the polysilicon isolation structure respectively and extend into the single crystalline base layer, The single crystalline base layer includes a single crystalline facet arranged between the first insulator pad and the second insulator pad, wherein the top of the single crystalline facet is located above the bottommost surface of the polysilicon isolation structure, the bottommost surface of the first insulator pad and the bottommost surface of the second insulator pad.

2. The integrated chip of claim 1, wherein the single crystalline facet has a triangular profile when viewed in cross-section. 3 . The integrated chip of claim 1 , wherein the polysilicon isolation structure comprises an average grain size greater than 300 nanometers. 4 . The integrated chip of claim 1 , wherein the polysilicon isolation structure has a topmost surface located below a topmost surface of the active layer.

5. An integrated chip comprising: A single crystalline base layer; An active layer disposed on the single crystalline base layer; an insulator layer separating the active layer from the single crystalline base layer; a polysilicon isolation structure that continuously separates an inner region of the active layer from an outer region of the active layer, wherein the polysilicon isolation structure extends through the active layer and into the single crystalline base layer; as well as an insulator liner covering the outermost sidewall of the polysilicon isolation structure and disposed on a horizontally extending surface of the single crystalline base layer, The single crystalline base layer includes a protrusion extending outward from the horizontally extending surface of the single crystalline base layer and arranged between the insulator pads, wherein the protrusion has a top located above the bottommost surface of the insulator pad and the bottommost surface of the polysilicon isolation structure. 6 . The integrated chip according to claim 5 , wherein the polysilicon isolation structure has a height greater than or equal to 7 microns. 7 . The integrated chip of claim 5 , wherein the protrusion comprises sidewalls meeting at an apex, and wherein the sidewalls are separated from the insulator liner by the polysilicon isolation structure.

8. The integrated chip according to claim 5, wherein the polysilicon isolation structure comprises p-type doped polysilicon.

9. The integrated chip according to claim 5, further comprising: An additional polysilicon isolation structure continuously surrounds the polysilicon isolation structure and is separated from the polysilicon isolation structure by the outer region of the active layer.

10. The integrated chip of claim 9, wherein the polysilicon isolation structure has a topmost surface located below a topmost surface of the insulator liner.

11. A method for forming an isolation structure in a substrate, the method comprising: patterning the substrate to form a trench continuously surrounding a central portion of the substrate, wherein the trench extends from the top surface of the substrate toward a bottom surface of the substrate in a first direction orthogonal to the top surface of the substrate; depositing an insulator layer along the trench; removing the insulator layer from a horizontally extending surface of the substrate defining a bottom of the trench so that an insulator liner covers an outer surface of the trench defined by sidewalls of the substrate; as well as Polysilicon is grown in the trenches and between the insulator liners, wherein the polysilicon grows from the horizontally extending surface of the substrate toward the top surface of the substrate in a second direction that is orthogonal to the top surface of the substrate and opposite to the first direction.

12. The method of claim 11, wherein the polysilicon is grown in a chamber using a first precursor comprising a ratio of hydrogen chloride gas to dichlorosilane gas of between 5 and 8. 13 . The method according to claim 12 , wherein the first precursor further comprises boron gas to dope the polysilicon.

14. The method of claim 11, wherein the polysilicon is grown at a temperature between 850 degrees Celsius and 1100 degrees Celsius and a pressure between 10 Torr and 300 Torr.

15. The method of claim 11, wherein the growth of the polysilicon has a growth rate greater than 2 microns per minute. 16 . The method of claim 11 , wherein the growth of the polysilicon stops a predetermined time before the polysilicon grows beyond the top surface of the substrate.

17. The method of claim 16, wherein at the predetermined time, the polysilicon has a planar topmost surface.

18. The method of claim 11, wherein the substrate is a wafer having a circular shape, and wherein less than 50% of the substrate is exposed after removing the insulator layer and before growing the polysilicon.

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