Driver inverter circuit

Abstract

The present invention discloses an inverting circuit of a driver, comprising: a first switching element; a second switching element; a clamping circuit, which is connected in series between the first switching element and the second switching element, and has a first node between the first switching element and the clamping circuit, and a second node between the second switching element and the clamping circuit; and a capacitor element, which is coupled between the first node and the second node; the first switching element is a first type switching element, and the second switching element is a second type switching element.

Description

Technical Field

[0001] The present invention relates to a driver, and more particularly, to an inverter circuit of the driver. Background Art

[0002] In the field of traditional switching power converters, the driving circuit generates a driving voltage to drive the power switch to perform power conversion. In high-voltage applications, the driving circuit operates in a high-voltage environment, and the components need to be manufactured using a high-voltage process, resulting in a large circuit area and high production costs. On the other hand, as shown in FIG1 , the traditional high-voltage driving circuit includes a plurality of inverter circuits, each of which includes a group of symmetrical high-voltage metal oxide semiconductor transistors connected in series. However, the above-mentioned symmetrical high-voltage metal oxide semiconductor transistors have a large area and a large gate-source parasitic capacitance, which causes control signal delays and affects the power conversion efficiency. Summary of the invention

[0003] In view of this, the present invention proposes an inverter circuit of a driver to effectively solve the above problems encountered in the prior art.

[0004] According to a specific embodiment of the present invention, an inverter circuit of a driver is provided. In this embodiment, the inverter circuit of the driver includes a first switch element, a second switch element, a clamp circuit and a capacitor element. The clamp circuit is connected in series between the first switch element and the second switch element, and there is a first node between the first switch element and the clamp circuit, and there is a second node between the second switch element and the clamp circuit. The capacitor element is coupled between the first node and the second node. The first switch element is a first type switch element, and the second switch element is a second type switch element.

[0005] In one embodiment, the control terminals of the first switch and the second switch are respectively used as the first input terminal and the second input terminal to receive a set of in-phase input signals; and provide a set of output signals inverted from the input signals at the first node and the second node respectively.

[0006] In one embodiment, the clamping circuit includes a third switch element and a fourth switch element. The third switch element is connected in series to the first switch element, and the fourth switch element is connected in series between the third switch element and the second switch element.

[0007] In one embodiment, the clamping circuit receives a first clamping voltage and a second clamping voltage at control terminals of the third switch element and the fourth switch element, respectively, to limit the upper and lower limits of the output signal generated from the output terminal.

[0008] In one embodiment, the third switch element is a first type switch element, and the fourth switch element is a second type switch element.

[0009] In one embodiment, the first switch element, the second switch element, the third switch element and the fourth switch element are asymmetric high-voltage elements.

[0010] In one embodiment, the clamping circuit further includes a fifth switch element and a sixth switch element, and the fifth switch element and the sixth switch element are connected in series between the third switch element and the fourth switch element.

[0011] In one embodiment, the area of ​​the third switch element is smaller than that of the first switch element; the area of ​​the fourth switch element is smaller than that of the second switch element; the areas of the third switch element and the fourth switch element are related to the delay time between the input signal received by the inverter circuit and the output signal provided by the inverter circuit.

[0012] In one embodiment, the area of ​​the capacitor element is proportional to the area of ​​the input switch element of the subsequent inverter circuit.

[0013] In one embodiment, the inverting circuit further includes a protection circuit, which includes a first resistor and a second resistor, wherein the first resistor is coupled between the first node and the second node, and the second resistor is coupled between the first node and the first reference voltage or between the second node and the second reference voltage.

[0014] In one embodiment, the inverter circuit further includes a first diode and a second diode, the first diode is coupled between the first node and a first reference voltage (VHH), and the second diode is coupled between the second node and a second reference voltage (VS).

[0015] Compared with the prior art, the present invention uses asymmetric high voltage components to reduce the parasitic capacitance of the components, and utilizes a clamping circuit and coupling capacitor components to provide coupling current to improve the signal delay of the driver and reduce the area of ​​the clamping circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1A and Figure 1B They are the traditional driver and its circuit schematic diagram respectively.

[0017] Figure 2 FIG. 4 is a circuit diagram of an inverter circuit of a driver according to a first embodiment of the present invention.

[0018] Figure 3 FIG. 1 is a waveform diagram according to the first embodiment of the present invention.

[0019] Figure 4 FIG. 4 is a circuit diagram of an inverter circuit of a driver according to a second embodiment of the present invention.

[0020] Figure 5 FIG. 4 is a circuit diagram of an inverter circuit of a driver according to a third embodiment of the present invention.

[0021] Figure 6 FIG. 4 is a circuit diagram of a driver of the present invention.

[0022] Description of main component symbols:

[0023] 1 Inverter circuit

[0024] 11 First switching element

[0025] 12 Second switching element

[0026] 13 Clamping circuit

[0027] 14 Capacitor element

[0028] 15 First Node

[0029] 16 Second Node

[0030] 17 First output terminal

[0031] 18 Second output terminal

[0032] 19 Third switching element

[0033] 20 Fourth switch element

[0034] 21. Protection circuit

[0035] 22 Multiple transistors

[0036] 221 Fifth switch element

[0037] 222 Sixth switch element

[0038] 191, 201 control terminal

[0039] 30 Post-stage inverter circuit

[0040] R1, R2 resistors

[0041] D1, D2 diodes

[0042] M1, M2 transistors

[0043] PWMI_H, PWMI_L, PWMO_H, PWMO_L signals

[0044] VHH First reference voltage

[0045] VS Second reference voltage

[0046] Icc Current

[0047] C LH , C LL capacitance

[0048] P1, N1 Input switch element DETAILED DESCRIPTION

[0049] Figure 2 FIG. 1 is a circuit diagram of an inverter circuit of a driver according to a first embodiment of the present invention. Figure 2 As shown, the inverter circuit 1 of the driver includes: a first switch element 11, a second switch element 12, a clamp circuit 13 and a capacitor element 14. The clamp circuit 13 is connected in series between the first switch element 11 and the second switch element 12, and there is a first node 15 between the first switch element 11 and the clamp circuit 13, and there is a second node 16 between the second switch element 11 and the clamp circuit 13. The capacitor element 14 is coupled between the first node 15 and the second node 16. In this embodiment, the first switch element 11 is a first type switch element (for example, PMOS), and the second switch element 12 is a second type switch element different from the first type (for example, NMOS).

[0050] The inverter circuit 1 uses the control terminal of the first switch element 11 as the first input terminal and the control terminal of the second switch element 12 as the second input terminal to receive a set of in-phase input signals PWMI_H / PWMI_L, and generates a set of output signals PWMO_H / PWMO_L inverted from the input signals PWMI_H / PWMI_L at the first node and the second node, respectively. In other words, the inverter circuit further includes a first output terminal 17 coupled to the first node 15 and a second output terminal 18 coupled to the second node 16, for outputting the aforementioned output signals PWMO_H / PWMO_L.

[0051] The clamp circuit 13 includes a third switch element 19 and a fourth switch element 20, and the fourth switch element 20 is connected in series with the third switch element 19 and the second switch element 12. The clamp circuit 13 receives a first clamp voltage and a second clamp voltage at a control terminal 191 of the third switch element 19 and a control terminal 201 of the fourth switch element 20, respectively, to limit the upper and lower limits of the output signals (PWMO_H and PWMO_L) generated from the first output terminal 17 and the second output terminal 18. The first switch element 11, the second switch element 12, the third switch element 19 and the fourth switch element 20 are asymmetric high-voltage metal oxide semiconductor transistor elements. The element area of ​​the third switch element 19 is smaller than the element area of ​​the first switch element 11. The element area of ​​the fourth switch element 20 is smaller than the element area of ​​the second switch element 12. The third switch element 19 is a first type switch element (e.g., PMOS), and the fourth switch element 20 is a second type switch element (e.g., NMOS). The areas of the third switch element 19 and the fourth switch element 20 of the clamp circuit 13 are determined according to the signal delay requirement. The shorter the required delay is, the greater the coupling current is, and the larger the switch element area in the clamp circuit 13 is. In this embodiment, the area ratio used is first switch element: third switch element = second switch element: fourth switch element = 4:1.

[0052] The capacitor 14 is coupled between the first node 15 and the second node 16 , and is charged and discharged when the output signal PWMO_H / PWMO_L transitions to generate a current Icc to help the output signal PWMO_H / PWMO_L accelerate the transition.

[0053] In this embodiment, the inverter circuit 1 further includes a protection circuit 21, and the protection circuit 21 includes a first resistor R1 and a second resistor R2. The first resistor R1 is coupled between the first node 15 and the second node 16, and the second resistor R2 is coupled between the first node 15 and the first reference voltage VHH (eg, Figure 6 as shown) or between the second node 16 and the second reference voltage VS (as shown Figure 2 The resistors in the protection circuit 21 are used to control the preset level of the inverter circuit output (the resistor string is coupled to the second reference voltage VS, and the preset output is low; the resistor string is coupled to the first reference voltage VHH, and the preset output is high, to prevent the input signals PWM1_H and PWM1_L from being erroneously output when the input is floating).

[0054] In this embodiment, the inverter circuit 1 further includes a first diode D1 and a second diode D2. The first diode D1 is coupled between the first node 15 and the first reference voltage VHH, and the second diode D2 is coupled between the second node 16 and the second reference voltage VS. The first diode D1 and the second diode D2 are used to prevent the output signal level from exceeding the reference voltage. In one embodiment, the diodes D1 and D2 can be Zener diodes. In another embodiment, a diode string composed of a plurality of diodes connected in series can also be used.

[0055] The aforementioned capacitor element 14 includes but is not limited to a single capacitor, and the element parameters can be adjusted as required to generate the required coupling current. For example, it can be a capacitive impedance network composed of multiple small capacitors in parallel, series, or resistors, as long as it can store and release charges.

[0056] Figure 3 Schematic diagram of circuit waveforms according to the first embodiment of the present invention. Figure 3 As shown, the first switch element 11 and the second switch element 12 receive input signals PWMI_H / PWMI_L respectively. At the first time T1, the input signals PWMI_H / PWMI_L turn high, the first switch element 11 is turned off, and the second switch element 12 is turned on, so the output signal PWMO_L of the node 16 is quickly pulled to the second reference voltage VS (i.e., low level). In the period from the first time T1 to the second time T2, since the node 16 is coupled to the node 15 through the clamp circuit 13, the output signal PWMO_H of the node 15 is pulled down accordingly. Since the speeds at which the potentials of the nodes 15 and 16 are pulled down are different, that is, the voltage change rates of the output signals PWMO_H and PWMO_L at both ends of the capacitor element 14 are inconsistent, the charge of the node 15 flows into the capacitor element 14 to charge it, so that the current Icc is generated on the capacitor element 14 to quickly eliminate the difference in the change rate at both ends of the capacitor element 14. In the second period T2, the output signals PWMO_H and PWMO_L of the nodes 15 and 16 are both pulled down to the target potential. The charge flow on the node 15 accelerates the pull-down of the output signal PWMO_H on the node 15 to reduce the pull-down delay of the output signal PWMO_H / PWMO_L.

[0057] At the third time T3, when the input signal PWMI_H / PWMIL turns to a low level, the first switch element 11 is turned on, and the second switch element 12 is turned off, so that the output signal PWMO_H of the node 15 is quickly pulled to the first reference voltage VHH (i.e., a high level). Since the node 15 is coupled to the node 16 through the clamp circuit 13, the output signal PWMO_L of the node 16 is pulled high accordingly. Similarly, during the period from the third time T3 to the fourth time T4, since the voltage change rates of the output signals PWMO_H and PWMO_L at both ends of the capacitor element 14 are different, the capacitor element 14 releases charges to the node 16 to generate a current Icc to quickly eliminate the voltage change rate difference at both ends of the capacitor element 14. Through the flow of charges on the node 16, the output signal PWMO_L on the node 16 is quickly pulled high, thereby reducing the pull-up delay of the output signal PWMO_H / PWMO_L. And at the fourth time T4, the output signals PWMO_H and PWMO_L of the nodes 15 and 16 reach the target potential.

[0058] Figure 4 1 is a circuit diagram of an inverter circuit of a driver according to a second embodiment of the present invention. The difference between the inverter circuit of the second embodiment and the inverter circuit of the first embodiment is that the first resistor R1 and the second resistor R2 in the protection circuit 20 of the second embodiment are resistor elements M1 and M2 composed of metal oxide semiconductor transistor elements to provide a high resistance (about Mohm level). The operation of the inverter circuit of the driver of the second embodiment is the same as the operation of the inverter circuit of the driver of the first embodiment, and will not be repeated here.

[0059] Figure 5 : is a circuit diagram of the inverter circuit of the driver according to the third embodiment of the present invention. The difference between the third embodiment and the first embodiment is that the clamping circuit of the third embodiment further includes a plurality of low-voltage metal oxide semiconductor transistor (MOS) elements 22, and a plurality of clamping voltages are respectively input to the control terminals of these low-voltage MOS elements to achieve the effect of multi-stage clamping. In this embodiment, only the fifth switch element 221 and the sixth switch element 222 are connected in series between the third switch element 19 and the fourth switch element 20 in the clamping circuit, and the fifth switch element 221 and the sixth switch element 222 are low-voltage MOS elements, but the present invention is not limited thereto. The operation of the inverter circuit of the driver of the third embodiment is the same as that of the inverter circuit of the driver of the first embodiment, and will not be repeated here.

[0060] Figure 6 FIG. 1 is a circuit diagram of a single-stage inverter circuit and a subsequent-stage inverter circuit of the present invention. Figure 6As shown, the post-stage inverter circuit 30 is a traditional inverter structure, and the capacitance area of ​​the capacitor element 14 is determined by the element area of ​​the input switch element of the post-stage inverter circuit. In a specific embodiment, the area ratio of the capacitor element 14 to the input switch element of the post-stage inverter circuit 30 is approximately 10:1. Figure 6 Middle C LH , C LL are the parasitic capacitances of the input switch elements P1 and N1 of the subsequent inverter circuit 30. In addition, the inverter circuit of the present invention can be used as a multi-stage dual-input dual-output inverter for receiving and transmitting PWM signals.

[0061] The clamping circuit in the inverter circuit of the driver of the present invention comprises a third switch element 19 (PMOS) matched with the first switch element 11 (PMOS), and a fourth switch element 20 (NMOS) matched with the second switch element 12 (NMOS). The third switch element 19 and the fourth switch element 20 are also asymmetric high-voltage transistors (MOSFET). The third switch element 19 and the fourth switch element 20 can input a clamping voltage to limit the upper and lower limits of the output signal to prevent the output signal voltage from varying too much. The capacitor element of the present invention is connected in series to the output ends of the PMOS pair and the NMOS pair, and provides a coupling current to reduce delay when the signal transitions. Compared with the circuit structure of the prior art, the present invention has a smaller area (about 6% area reduction) and lower delay (reduced from 20ns to 5-7ns).

[0062] The present invention has been described by the above-mentioned relevant embodiments, however, the above-mentioned embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent settings included in the spirit and scope of the claims are included in the scope of the present invention.

Claims

1. An inverting circuit of a driver, characterized in that: include: a first switching element; a second switching element; a clamping circuit connected in series between the first switching element and the second switching element, wherein a first node is provided between the first switching element and the clamping circuit, and a second node is provided between the second switching element and the clamping circuit, wherein the clamping circuit comprises a third switching element and a fourth switching element, wherein the third switching element is connected in series with the first switching element, and the fourth switching element is connected in series with the third switching element and the second switching element; as well as a capacitor element coupled between the first node and the second node; The first switch element is a first type switch element, and the second switch element is a second type switch element.

2. The inverter circuit according to claim 1, characterized in that: The control ends of the first switch element and the second switch element are respectively used as a first input end and a second input end for receiving a set of in-phase input signals, and the first node and the second node provide a set of output signals inverted with the input signals.

3. The inverter circuit according to claim 1, characterized in that: The clamping circuit receives a first clamping voltage and a second clamping voltage at control terminals of the third switch element and the fourth switch element respectively.

4. The inverter circuit according to claim 1, characterized in that: The third switch element is the first type switch element, and the fourth switch element is the second type switch element.

5. The inverter circuit according to claim 1, characterized in that: The first switch element, the second switch element, the third switch element and the fourth switch element are asymmetric high-voltage elements.

6. The inverter circuit according to claim 1, characterized in that: The clamp circuit further includes a fifth switch element and a sixth switch element, and the fifth switch element and the sixth switch element are connected in series between the third switch element and the fourth switch element.

7. The inverter circuit according to claim 1, characterized in that: The area of ​​the third switch element is smaller than that of the first switch element; the area of ​​the fourth switch element is smaller than that of the second switch element; wherein the areas of the third switch element and the fourth switch element are related to the delay time between the input signal received by the inverter circuit and the output signal provided by the inverter circuit.

8. The inverter circuit according to claim 1, characterized in that: The area of ​​the capacitor element is proportional to the area of ​​the input switch element of the subsequent inverter circuit.

9. The inverter circuit according to claim 1, characterized in that: It also includes a protection circuit, which includes a first resistor and a second resistor, the first resistor is coupled between the first node and the second node, and the second resistor is coupled between the first node and a first reference voltage or between the second node and a second reference voltage.

10. The inverter circuit of the driver according to claim 1, characterized in that: The invention also includes a first diode and a second diode. The first diode is coupled between the first node and a first reference voltage, and the second diode is coupled between the second node and a second reference voltage.

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