A transient response enhanced LDO
By introducing a transient response enhancement circuit in LDO, using hysteresis comparator and ONE_SHOT to eliminate glitches, adjusting the gate voltage of the adjustment tube through NMOS tube, solving the problem of slow response speed of traditional LDO during load transient changes, and achieving more Good transient response effect.
Patent Information
- Application Number
- CN202110102480.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-01-26
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2041-01-26
AI Technical Summary
Traditional LDOs are difficult to improve the response speed when load transients change, and the bandwidth is limited under limited power consumption, so transient response is difficult to further improve.
A transient response enhancement LDO is designed to utilize hysteresis by introducing a transient response enhancement circuit TRANSIENT ENHANGCE between the error amplifier EA and the gate of the adjustment tube MP, including a hysteresis comparator, ONE_SHOT and two NMOS tubes MN1 and MN2. The comparator compares the input differential of the error amplifier to the drain voltage of the tube, eliminates the burr by ONE_SHOT, and adjusts the gate voltage of the adjustment tube through the NMOS tube to enhance the load transient response.
It improves the transient response and anti-noise performance of LDO, enhances the transient response capability of load, and effectively improves the stability of the output voltage.
Smart Images
Figure CN112732000B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of circuit design, and in particular to a transient response enhanced LDO. Background Art
[0002] LDO is a DC step-down linear regulator that can maintain a stable output voltage even when the input voltage or load current changes. Figure 1 As shown, its working principle is: VOUT=(R1+R2) / R2*VREF. When the load changes, for example, the load current increases and VOUT decreases, VFB decreases. Through the error amplifier EA, VEA is reduced, thereby adjusting the adjustment tube MPASS, increasing the current and increasing the VOUT voltage. Through this negative feedback loop, the VOUT voltage is finally restored. The load transient response of conventional LDO is adjusted through a negative feedback loop, and the larger the bandwidth of the LDO, the better the transient response. However, increasing the bandwidth will also increase power consumption. In the case of limited power consumption, the bandwidth is limited, and the transient response is difficult to further improve. Therefore, a separate transient response enhancement circuit is required to improve its response speed. Summary of the invention
[0003] In view of the above technical problems, the present invention provides a transient response enhanced LDO.
[0004] A transient response enhanced LDO comprises an error amplifier EA, an adjustment tube MP, feedback resistor networks RA and RB, a feedback capacitor CA, a load capacitor CL and a load resistor Rout; a transient response enhancement circuit TRANSIENT ENHANGCE for enhancing the transient response of the load is connected between the gates of the error amplifier EA and the adjustment tube MP, and the TRANSIENT ENHANGCE comprises a hysteresis comparator, ONE_SHOT and two NMOS tubes MN1 and MN2; input terminals VP and VN of the hysteresis comparator collect and compare the drain voltage of the input differential pair tube of the error amplifier EA, and after the comparison result is eliminated by ONE_SHOT, the gate voltage of the adjustment tube MP is adjusted by the NMOS tube.
[0005] Preferably, the error amplifier EA includes M1-M10, wherein the substrates of M1-M4 and the sources of M1-M3 are connected to the input voltage VIN; the source of M4 is connected to the drain of M2, and the gate and drain of M1 are connected to the gate of M3 and the drain of M7; the gates of M2 and M4 are respectively connected to the externally supplied bias BIAS1 and BIAS2; the drain of M4 is connected to the source and substrate of M5 and M6, and the gates of M5 and M6 are respectively connected to the two inputs INP and INN; the drain of M5, the drain and gate of M8 are connected to the gate of M7 and connected to the VP terminal of the hysteresis comparator; the drain of M6, The drain and gate of M9 are connected to the gate of M10 and to the VN terminal of the hysteresis comparator; the drains of M3 and M10 are connected and are connected to the gate of the adjustment tube MP and the output of TRANSIENTENHANGCE as the output of the error amplifier EA; the source and substrate of M7-M10 are grounded; the source and substrate of the adjustment tube MP are connected to the input voltage VIN, and the drain is connected to one end of RA, CA, CL, and Rout and serves as the output end to output the voltage VOUT; RA and CA are connected in parallel to RB and connected to INN as the FB terminal; the other ends of RB, CL, and Rout are all grounded.
[0006] Preferably, the power supply voltages of the hysteresis comparator and ONE_SHOT are both the input voltage VIN, the output of the hysteresis comparator is connected to the input of ONE_SHOT, and the output of ONE_SHOT is connected to the gate of MN1; the drain of MN1 is connected to the gate of the adjustment tube MP as the output of TRANSIENT ENHANGCE, and the source of MN1 is connected to the drain of MN2; the gate of MN2 is connected to the externally supplied bias BIAS, and the substrates of MN1 and MN2 and the source of MN2 are all grounded.
[0007] The beneficial effects of the present invention are as follows: a transient response enhancement circuit TRANSIENT ENHANGCE is connected between the error amplifier EA and the gate of the adjustment tube MP; a hysteresis comparator is used to collect and compare the drain voltage of the input differential pair of the error amplifier EA, and the obtained comparison result is used to eliminate burrs through ONE_SHOT, thereby improving the anti-noise performance of transient enhancement; and the gate voltage of the adjustment tube MP is adjusted through the NMOS tube, thereby achieving the effect of enhancing the transient response of the load. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The present invention will be further described below in conjunction with the accompanying drawings.
[0009] Figure 1 This is the circuit structure diagram of the traditional LDO;
[0010] Figure 2 is an overall circuit structure diagram of an embodiment of the present invention;
[0011] Figure 3 4 is a circuit structure diagram of a TRANSIENT ENHANGCE in an embodiment of the present invention. DETAILED DESCRIPTION
[0012] The technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0013] The present invention provides a transient response enhanced LDO, the overall circuit structure of which is as follows Figure 2 As shown, it mainly includes an error amplifier EA, an adjustment tube MP, a feedback resistor network RA and RB, a feedback capacitor CA, a load capacitor CL and a load resistor Rout. A transient response enhancement circuit TRANSIENT ENHANGCE for enhancing the load transient response is connected between the gates of the error amplifier EA and the adjustment tube MP.
[0014] The error amplifier EA includes M1-M10, wherein the substrates of M1-M4 and the sources of M1-M3 are connected to the input voltage VIN. The source of M4 is connected to the drain of M2, and the gate and drain of M1 are connected to the gate of M3 and the drain of M7. The gates of M2 and M4 are connected to the externally supplied bias BIAS1 and BIAS2 respectively. The drain of M4 is connected to the sources and substrate of M5 and M6, and the gates of M5 and M6 are connected to the two inputs INP and INN respectively. The drain of M5, the drain and gate of M8 are connected to the gate of M7 and to the VP terminal of TRANSIENTENHANGCE; the drain of M6, the drain and gate of M9 are connected to the gate of M10 and to the VN terminal of TRANSIENTENHANGCE. The drains of M3 and M10 are connected and connected to the gate of the adjustment tube MP and the output of TRANSIENT ENHANGCE as the output of the error amplifier EA. The sources and substrates of M7-M10 are grounded. The source and substrate of the adjustment tube MP are connected to the input voltage VIN, and the drain is connected to one end of RA, CA, CL, and Rout and serves as the output end to output the voltage VOUT. RA and CA are connected in parallel to RB and connected to INN as the FB end (not shown in the figure); the other ends of RB, CL, and Rout are all grounded.
[0015] The specific structure of TRANSIENT ENHANGCE is as follows Figure 3As shown, it includes a hysteresis comparator, ONE_SHOT and two NMOS tubes MN1 and MN2. Among them, the power supply voltages of the hysteresis comparator and ONE_SHOT are both input voltage VIN, the input terminals VP and VN of the hysteresis comparator respectively collect and compare the drain voltages of the input differential pair tubes M5 and M6 of the error amplifier EA, the output terminal of the hysteresis comparator is connected to the input terminal of ONE_SHOT, and the output terminal of ONE_SHOT is connected to the gate of MN1. The drain of MN1 is connected to the gate of the adjustment tube MP as the output of TRANSIENT ENHANGCE, and the source of MN1 is connected to the drain of MN2. The gate of MN2 is connected to the external bias BIAS, and the substrates of MN1 and MN2 and the source of MN2 are all grounded.
[0016] Working principle: When the load current increases, the output voltage VOUT decreases, the FB voltage decreases, and the INN voltage connected to FB decreases accordingly. The drain VN voltage of the differential pair tube M6 increases, exceeding the threshold voltage of the hysteresis comparator, and the output flips to a high level. After filtering out the noise through the ONE_SHOT single pulse trigger circuit, it is transmitted to the gate of MN1; at this time, the potential is high, MN1 is turned on, and under the bias of the MN2 gate BIAS, the gate voltage of the adjustment tube MP is pulled down, thereby increasing the current of the adjustment tube MP and increasing the drain voltage, that is, the VOUT level is restored, thereby enhancing the transient response. In normal operation, the VN voltage of the hysteresis comparator is lower than its threshold voltage, the output is low, the gate of MN1 is low, and the MN1 branch is turned off.
[0017] Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention.
Claims
1. A transient response enhanced LDO, comprising an error amplifier EA, a regulating tube MP, feedback resistor networks RA and RB, a feedback capacitor CA, a load capacitor CL and a load resistor Rout, characterized in that: A transient response enhancement circuit TRANSIENT ENHANGCE for enhancing the transient response of the load is connected between the error amplifier EA and the gate of the adjustment tube MP. The TRANSIENT ENHANGCE includes a hysteresis comparator, a single pulse trigger circuit ONE_SHOT, and two NMOS tubes MN1 and MN2. The input terminals VP and VN of the hysteresis comparator collect and compare the drain voltage of the input differential pair of the error amplifier EA. After the comparison result is eliminated by ONE_SHOT, the gate voltage of the adjustment tube MP is adjusted by the NMOS tube. The power supply voltages of the hysteresis comparator and ONE_SHOT are both the input voltage VIN, the output of the hysteresis comparator is connected to the input of ONE_SHOT, and the output of ONE_SHOT is connected to the gate of MN1; the drain of MN1 is connected to the gate of the adjustment tube MP as the output of TRANSIENTENHANGCE, and the source of MN1 is connected to the drain of MN2; the gate of MN2 is connected to the external bias BIAS, and the substrates of MN1 and MN2 and the source of MN2 are all grounded; The error amplifier EA includes M1-M10, wherein the substrates of M1-M4 and the sources of M1-M3 are connected to the input voltage VIN; the source of M4 is connected to the drain of M2, the gate and drain of M1 are connected to the gate of M3 and the drain of M7; the gates of M2 and M4 are respectively connected to the externally supplied biases BIAS1 and BIAS2; the drain of M4 is connected to the sources and substrates of M5 and M6, and the gates of M5 and M6 are respectively connected to the two inputs INP and INN; the drain of M5, the drain and gate of M8 are connected to the gate of M7 and to the VP terminal of the hysteresis comparator; the drain of M6, the drain and gate of M9 are connected to the gate of M10 and to the VN terminal of the hysteresis comparator; the drains of M3 and M10 are connected and are connected as the output of the error amplifier EA to the gate of the adjustment tube MP and the TRANSIENT terminal. The output of ENHANGCE is connected; the source and substrate of M7-M10 are grounded; the source and substrate of the adjustment tube MP are connected to the input voltage VIN, and the drain is connected to one end of RA, CA, CL, and Rout and serves as the output end to output the voltage VOUT; RA and CA are connected in parallel to RB and connected to INN as the FB end; the other ends of RB, CL, and Rout are all grounded.