Multiplier, method, integrated circuit chip and computing device for floating point operations

Abstract

This invention relates to a multiplier, method, integrated circuit chip, and computing device for floating-point operations. The computing device may be included in a combined processing unit, which may further include a general-purpose interconnect interface and other processing units. The computing device interacts with the other processing units to jointly perform user-specified computational operations. The combined processing unit may also include a storage device connected to both the computing device and the other processing units, for storing data from these devices. The solution of this invention can be widely applied to various floating-point data operations.

Description

Technical Field

[0001] This disclosure generally relates to the field of floating-point arithmetic. More specifically, this disclosure relates to methods for floating-point arithmetic, multipliers, integrated circuit chips, and computing devices. Background Technology

[0002] In current signal processing algorithms, such as inner product operations between vectors and convolution operations of matrices, a large number of multiply-accumulate operations are used, and the efficiency of these operations often depends on the execution speed of the multiplier. Although current multipliers have achieved significant improvements in execution efficiency, there is still room for improvement in processing floating-point data. Therefore, how to obtain a high-efficiency, low-power, and low-cost multiplier to perform multiplication operations on floating-point data has become a problem that needs to be solved in the existing technology. Summary of the Invention

[0003] In order to at least partially solve the technical problems mentioned in the background art, the present disclosure provides a multiplier for floating-point operations, a method, an integrated circuit chip including the multiplier, and a computing device.

[0004] In one aspect, this disclosure provides a multiplier for performing floating-point multiplication according to an operation mode, wherein the floating-point number includes at least an exponent and a mantissa. The multiplier includes: an exponent processing unit for obtaining the exponent after the multiplication operation according to the operation mode, the exponent of a first floating-point number, and the exponent of a second floating-point number; and a mantissa processing unit for obtaining the mantissa after the multiplication operation according to the operation mode, the mantissa of the first floating-point number, and the mantissa of the second floating-point number, wherein the operation mode is used to indicate the data format of the first floating-point number and the data format of the second floating-point number.

[0005] In another aspect, this disclosure provides a method for performing floating-point multiplication using a multiplier, wherein the floating-point number includes at least an exponent and a mantissa, the multiplier performing the multiplication operation based on an operation mode, the method comprising: using the exponent processing unit of the multiplier to obtain the exponent after the multiplication operation according to the operation mode, the exponent of a first floating-point number, and the exponent of a second floating-point number; and using the mantissa processing unit of the multiplier to obtain the mantissa after the multiplication operation according to the operation mode, the mantissa of the first floating-point number, and the mantissa of the second floating-point number, wherein the operation mode is used to indicate the data format of the first floating-point number and the data format of the second floating-point number.

[0006] In another aspect, this disclosure provides an integrated circuit chip including the aforementioned multiplier. In one or more embodiments, the multiplier of this disclosure can be configured as a standalone integrated circuit chip or disposed on an integrated circuit chip or computing device to perform operations on floating-point numbers of various data formats.

[0007] By utilizing the multiplier, corresponding arithmetic method, integrated circuit chip, and computing device disclosed herein, operations on various floating-point data types can be supported without requiring multiple separate multipliers for different floating-point data types. Therefore, the multiplier disclosed herein is flexible and can be widely applied to various floating-point data operations. Furthermore, when processing input data with a large bit width, the multiplier disclosed herein supports cyclic multiplexing operations, thereby eliminating the need for additional processing chips and reducing the integrated circuit footprint. Attached Figure Description

[0008] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding portions wherein:

[0009] Figure 1 This is a schematic diagram illustrating a floating-point data format according to an embodiment of this disclosure;

[0010] Figure 2 This is a schematic structural block diagram illustrating a multiplier according to an embodiment of this disclosure;

[0011] Figure 3 This is a structural block diagram illustrating further details of a multiplier according to an embodiment of this disclosure;

[0012] Figure 4 This is a schematic block diagram illustrating a mantissa processing unit according to an embodiment of the present disclosure;

[0013] Figure 5 This is a schematic diagram illustrating a partial product operation according to an embodiment of this disclosure;

[0014] Figure 6 This is a schematic block diagram illustrating the operation flow and schematic block diagram of the Wallace tree compressor according to an embodiment of this disclosure;

[0015] Figure 7 This is a schematic block diagram showing the overall structure of a multiplier according to an embodiment of this disclosure;

[0016] Figure 8 This is a flowchart illustrating a method for performing floating-point multiplication using a multiplier according to an embodiment of this disclosure;

[0017] Figure 9This is a structural diagram illustrating a combined processing apparatus according to an embodiment of the present disclosure; and

[0018] Figure 10 This is a schematic diagram illustrating the structure of a circuit board according to an embodiment of the present disclosure. Detailed Implementation

[0019] The technical solution disclosed herein provides a multiplier, method, integrated circuit chip, and computing device for floating-point arithmetic. Unlike existing floating-point multipliers, this disclosure provides a multiplier that supports multiple operation modes, thus overcoming the limitation of existing multipliers that can only support one type of floating-point arithmetic. Specifically, this disclosure utilizes multiple operation modes to indicate different floating-point data types, and during floating-point multiplication, various data operations are performed based on one of the operation modes, including, for example, encoding, compression, summation, normalization, and rounding operations, thereby realizing operations associated with one of the multiple floating-point data types. Therefore, the multiplier disclosed herein can support multi-mode operations, further improving the flexibility of floating-point arithmetic and reducing computational costs.

[0020] The technical solutions and multiple embodiments thereof disclosed herein will now be described in detail with reference to the accompanying drawings. It should be understood that many specific details regarding floating-point operations will be set forth in order to provide a thorough understanding of the multiple embodiments described herein. However, those skilled in the art can practice the multiple embodiments described herein without these specific details, guided by the teachings of this disclosure. In other instances, this disclosure does not describe well-known methods, processes, and components in detail to avoid unnecessarily obscuring the embodiments described herein. Furthermore, this description should not be construed as limiting the scope of the multiple embodiments disclosed herein.

[0021] Figure 1 This is a schematic diagram illustrating a floating-point data format 100 according to an embodiment of this disclosure. Figure 1As shown, the floating-point number to which the present disclosure can be applied may include three parts, such as a sign (or sign bit) 102, an exponent (or exponent bit) 104, and a mantissa (or mantissa bit) 106, wherein for unsigned floating-point numbers, the sign or sign bit may be absent. In some embodiments, the floating-point number applicable to the multiplier of the present disclosure may include at least one of half-precision floating-point number, single-precision floating-point number, double-precision floating-point number, and custom floating-point number. Specifically, in some embodiments, the floating-point number format to which the present disclosure can be applied may be a floating-point format conforming to the IEEE 754 standard, such as a double-precision floating-point number (float64, abbreviated as "FP64"), a single-precision floating-point number (float32, abbreviated as "FP32"), or a half-precision floating-point number (float16, abbreviated as "FP16"). In other embodiments, the floating-point format can be an existing 16-bit floating-point number (bfloat16, abbreviated "BF16"), or a custom floating-point format, such as an 8-bit floating-point number (bfloat8, abbreviated "BF8"), an unsigned half-precision floating-point number (unsigned float16, abbreviated "UFP16"), or an unsigned 16-bit floating-point number (unsigned bfloat16, abbreviated "UBF16"). For ease of understanding, Table 1 below shows some of the above data formats, where the sign bit width, exponent bit width, and mantissa bit width are for illustrative purposes only.

[0022] Table 1

[0023] Data types Sign bit width Exponent width Mantissa width FP16 1 5 10 BF16 1 8 7 FP32 1 8 23 BF8 1 5 3 UFP16 0 5 (or 6) 11 (or 10) UBF16 0 8 8

[0024] For the various floating-point number formats mentioned above, the multiplier disclosed herein can support multiplication operations between at least two floating-point numbers having any of the above formats, wherein the two floating-point numbers can have the same or different floating-point data formats. For example, the multiplication operation between two floating-point numbers can be FP16*FP16, BF16*BF16, FP32*FP32, FP32*BF16, FP16*BF16, FP32*FP16, BF8*BF16, UBF16*UFP16, or UBF16*FP16, etc.

[0025] Figure 2 This is a schematic structural block diagram illustrating a multiplier 200 according to an embodiment of the present disclosure. As previously described, the multiplier of the present disclosure supports multiplication of floating-point numbers in various data formats, which can be indicated by the operation modes of the present disclosure, so that the multiplier operates in one of multiple operation modes.

[0026] like Figure 2As shown, the multiplier disclosed herein generally includes an exponent processing unit 202 and a mantissa processing unit 204, wherein the exponent processing unit is used to process the exponent bits of the floating-point number, and the mantissa processing unit is used to process the mantissa bits of the floating-point number. Optionally or additionally, in some embodiments, when the floating-point number processed by the multiplier has a sign bit, the multiplier may further include a sign processing unit 206, which can be used to process floating-point numbers including a sign bit.

[0027] In operation, the multiplier can perform floating-point operations on a first and a second floating-point number received, input, or buffered, according to one of the operation modes. These first and second floating-point numbers have one of the floating-point data formats discussed earlier. For example, when the multiplier is in the first operation mode, it can support multiplication of two floating-point numbers FP16*FP16, while in the second operation mode, it can support multiplication of two floating-point numbers BF16*BF16. Similarly, when the multiplier is in the third operation mode, it can support multiplication of two floating-point numbers FP32*FP32, and in the fourth operation mode, it can support multiplication of two floating-point numbers FP32*BF16. The correspondence between the example operation modes and floating-point numbers is shown in Table 2 below.

[0028] Table 2

[0029] Operation mode number Floating-point type 1 FP16*FP16 2 BF16*BF16 3 FP32*FP32 4 FP32*BF16

[0030] In one embodiment, Table 2 described above can be stored in a memory of the multiplier, and the multiplier selects one of the operation modes in the table according to instructions received from an external device, such as... Figure 10 The external device 1012 is shown in the figure. In another embodiment, the input to this operation mode can also be via, as shown in the figure. Figure 3 The mode selection unit 308 shown automatically implements this. For example, when two FP16 floating-point numbers are input to the multiplier disclosed herein, the mode selection unit can select the multiplier to operate in the first operation mode according to the data format of the two floating-point numbers. As another example, when an FP32 floating-point number and a BF16 floating-point number are input to the multiplier disclosed herein, the mode selection unit can select the multiplier to operate in the fourth operation mode according to the data format of the two floating-point numbers.

[0031] It can be seen that the different operation modes disclosed herein are associated with the corresponding floating-point data. That is, the operation modes disclosed herein can be used to indicate the data format of the first floating-point number and the data format of the second floating-point number. In another embodiment, the operation modes disclosed herein can not only indicate the data format of the first floating-point number and the data format of the second floating-point number, but also the data format after a multiplication operation. The extended operation modes, combined with Table 2, are shown in Table 3 below.

[0032] Table 3

[0033]

[0034] Unlike the operation mode numbers shown in Table 2, the operation modes in Table 3 are extended by one bit to indicate the data format after floating-point multiplication. For example, when the multiplier is operating in operation mode 21, it performs floating-point operations on the input two floating-point numbers BF16*BF16 and outputs the result of the floating-point multiplication in FP16 data format.

[0035] The above-described numbered operation patterns indicating floating-point data formats are merely exemplary and not limiting. Based on the teachings of this disclosure, it is also conceivable to establish indexes based on the operation patterns to determine the formats of the multipliers and multiplicands. For example, an operation pattern may include two indices: a first index indicating the type of a first floating-point number and a second index indicating the type of a second floating-point number. For instance, in operation pattern 13, the first index "1" indicates that the first floating-point number (or multiplicand) is in the first floating-point format, i.e., FP16, while the second index "3" indicates that the second floating-point number (or multiplier) is in the second floating-point format, i.e., FP32. Furthermore, a third index can be added to the operation pattern, indicating the data format of the output result. For example, for operation pattern 131, the third index "1" could indicate that the data format of the output result is the first floating-point format, i.e., FP16. As the number of operation patterns increases, corresponding indices or index levels can be added as needed to facilitate the establishment of the relationship between operation patterns and data formats.

[0036] Furthermore, although numerical designations are used here as an example to represent the operation mode, in other examples, other symbols or codes can be used to represent the operation mode as needed by the application, such as letters, symbols, or numbers and combinations thereof. Such expressions using letters, numbers, symbols, or combinations thereof can then represent the operation mode and identify the data format of the first floating-point number, the second floating-point number, and the output result. Additionally, when these expressions are formed in the form of instructions, the instructions can include three fields: a first field indicating the data format of the first floating-point number, a second field indicating the data format of the second floating-point number, and a third field indicating the data format of the output result. Of course, these fields can also be combined into one field, or new fields can be added to indicate more content related to the floating-point data format. It can be seen that the operation mode disclosed herein can not only be associated with the input floating-point data format but can also be used to normalize the output result to obtain a product result with the desired data format.

[0037] Figure 3 This is a more detailed structural block diagram illustrating a multiplier 300 according to an embodiment of this disclosure. From Figure 3 As can be seen from the content shown, it includes not only Figure 2 The exponent processing unit 202, mantissa processing unit 204, and optional sign processing unit 206 shown also illustrate the internal components these units may include and the units related to their operation, which will be discussed below. Figure 3 The exemplary operation of these units will be described in detail below.

[0038] To perform floating-point multiplication, the exponent processing unit can be used to obtain the exponent after multiplication based on the aforementioned operation mode, the exponent of the first floating-point number, and the exponent of the second floating-point number. In one embodiment, the exponent processing unit can be implemented using addition and subtraction circuitry. For example, the exponent processing unit here can be used to add the exponent of the first floating-point number, the exponent of the second floating-point number, and the offset values ​​of their respective input floating-point data formats, and then subtract the offset values ​​of the output floating-point data formats to obtain the exponent after multiplication of the first and second floating-point numbers.

[0039] Furthermore, the mantissa processing unit of the multiplier can be used to obtain the mantissa after multiplication based on the aforementioned operation mode, the first floating-point number, and the second floating-point number. In one embodiment, the mantissa processing unit may include a partial product operation unit 312 and a partial product summation unit 314, wherein the partial product operation unit is used to obtain an intermediate result based on the mantissa of the first floating-point number and the mantissa of the second floating-point number. In some embodiments, the intermediate result may be multiple partial products (e.g., ...) obtained during the multiplication operation of the first floating-point number and the second floating-point number. Figure 5 and Figure 6(Illustrated schematically). The partial product summation unit is used to sum the intermediate results to obtain a summed result, and uses the summed result as the mantissa after the multiplication operation.

[0040] To obtain the intermediate result, in one embodiment, this disclosure utilizes a Booth encoding circuit to pad the mantissa of the second floating-point number (e.g., acting as a multiplier in floating-point arithmetic) with leading and trailing zeros (where padding with leading zeros converts the mantissa from an unsigned number to a signed number), in order to obtain the intermediate result. It should be understood that, depending on the encoding method, the mantissa of the first floating-point number (e.g., acting as a multiplicand in floating-point arithmetic) may also be encoded (e.g., padded with leading and trailing zeros), or both, to obtain multiple partial products. Further description of the partial products will be provided later with reference to the accompanying drawings.

[0041] In another embodiment, the partial product summation unit may include an adder for summing the intermediate results to obtain the summed result. In yet another embodiment, the partial product summation unit includes a Wallace tree and an adder, wherein the Wallace tree is used to sum the intermediate results to obtain a second intermediate result, and the adder is used to sum the second intermediate result to obtain the summed result. In these embodiments, the adder may include at least one of a full adder, a serial adder, and a carry-lookahead adder.

[0042] In one embodiment, the mantissa processing unit may further include a control circuit 316, configured to call the mantissa processing unit multiple times according to the operation mode when the operation mode indicates that the mantissa bit width of at least one of the first floating-point number or the second floating-point number is greater than the data bit width that the mantissa processing unit can process at one time. In one embodiment, this control circuit may be implemented as a control signal, such as a counter or a control flag. To achieve multiple calls, the partial product summation unit may further include a shifter. When the control circuit calls the mantissa processing unit multiple times according to the operation mode, the shifter shifts the existing summation result in each call and adds it to the summation result obtained in the current call to obtain a new summation result. The new summation result obtained in the last call is used as the mantissa after the multiplication operation.

[0043] In one embodiment, the multiplier disclosed herein further includes a regularization unit 318 and a rounding unit 320. The regularization unit can be used to perform floating-point number regularization processing on the mantissa and exponent after multiplication to obtain a regularized exponent result and a regularized mantissa result, and use the regularized exponent result and the regularized mantissa result as the exponent and mantissa after multiplication. For example, according to the data format indicated by the operation mode, the regularization unit can adjust the bit width of the exponent and mantissa to conform to the requirements of the aforementioned indicated data format. In addition, the regularization unit can also make other adjustments to the exponent or mantissa. For example, in some application scenarios, when the mantissa value is not 0, the most significant bit of the mantissa should be 1; otherwise, the exponent bit can be modified and the mantissa bit shifted simultaneously to make it a normalized number. In another embodiment, the regularization unit can also adjust the exponent after multiplication based on the mantissa after multiplication. For example, when the most significant bit of the mantissa after multiplication is 1, the exponent obtained after multiplication can be incremented by 1. Correspondingly, the rounding unit can be used to perform rounding operations on the regularized mantissa result according to the rounding mode, and use the mantissa after the rounding operation as the mantissa after the multiplication operation. Depending on the application scenario, the rounding unit can perform rounding operations such as rounding down, rounding up, and rounding to the nearest significant number. In some application scenarios, the rounding unit can also round the 1 shifted out during the right shift of the mantissa.

[0044] In addition to the exponent processing unit and the mantissa processing unit, the multiplier disclosed herein may optionally include a sign processing unit. When the input floating-point number is a floating-point number with a sign bit, the sign processing unit can be used to obtain the sign of the multiplication operation based on the sign of the first floating-point number and the sign of the second floating-point number. For example, in one embodiment, the sign processing unit may include an XOR logic circuit 322, which is used to perform an XOR operation based on the sign of the first floating-point number and the sign of the second floating-point number to obtain the sign of the multiplication operation. In another embodiment, the sign processing unit can also be implemented using a truth table or logical judgment.

[0045] In addition, to ensure that the input or received first and second floating-point numbers conform to a specified format, in one embodiment, the multiplier disclosed herein may further include a normalization processing unit 324, used to normalize the first or second floating-point number according to the operation mode when the first or second floating-point number is a denormalized non-zero floating-point number, to obtain the corresponding exponent and mantissa. For example, when the selected operation mode is the second operation mode shown in Table 2, and the input first and second floating-point numbers are FP16 type data, the normalization processing unit can be used to normalize the FP16 type data to BF16 type data so that the multiplier can operate in the second operation mode. In one or more embodiments, the normalization processing unit may also be used to preprocess (e.g., mantissa expansion) the mantissa of normalized floating-point numbers with implicit 1s and denormalized floating-point numbers without implicit 1s, to facilitate the operation of the subsequent mantissa processing unit. Based on the above description, it can be understood that the normalization processing unit 324 and the aforementioned regularization unit 318 may perform the same or similar operations in some embodiments. The difference is that the normalization processing unit 324 performs normalization processing on the input floating-point data, while the regularization unit 318 performs regularization processing on the mantissa and exponent to be output.

[0046] The above combination Figure 3 The multiplier disclosed herein and several embodiments thereof have been described. Based on the above description, those skilled in the art will understand that the solution disclosed herein obtains the result of a multiplication operation (including the exponent, mantissa, and optional sign) through the execution of the multiplier. Depending on the application scenario, for example, when the aforementioned regularization and rounding processes are not required, the result obtained by the mantissa processing unit and the exponent processing unit can be regarded as the final operation result. Furthermore, when the aforementioned regularization and rounding processes are required, the exponent and mantissa obtained after the regularization and rounding processes can be regarded as the final operation result, or a part of the final operation result (when considering the final sign). Furthermore, the solution disclosed herein enables the multiplier to support operations on floating-point numbers of different types or data formats through multiple operation modes, thereby achieving multiplier reuse, thus saving chip design overhead and computational costs. In addition, through a multiple-call mechanism, the multiplier disclosed herein also supports the calculation of high-bit-width floating-point numbers. Given that the multiplication of the mantissa (or mantissa digits or mantissa portion) is crucial to the overall performance of floating-point arithmetic, the following will combine... Figure 4 To describe the tails operation disclosed herein.

[0047] Figure 4 This is a schematic block diagram illustrating the operation of the mantissa processing unit 400 according to an embodiment of this disclosure. Figure 4As shown, the mantissa processing operation disclosed herein can mainly involve two units, namely, the combination of the aforementioned... Figure 3 The partial product operation unit and the partial product summation unit are discussed. From the perspective of operation timing, the mantissa processing operation can be roughly divided into a first stage and a second stage. In the first stage, the mantissa processing operation will obtain an intermediate result, while in the second stage, the mantissa processing operation will obtain the mantissa result output from adder 408.

[0048] In an exemplary specific operation, the first and second floating-point numbers received by the multiplier can be divided into multiple parts, namely the aforementioned sign (optional), exponent, and mantissa. Optionally, after normalization, the mantissa portions of the two floating-point numbers will be input into the mantissa processing unit (e.g., ...). Figure 2 or Figure 3 The mantissa processing unit in the middle, and specifically enters the partial product operation unit. For example Figure 4 As shown, this disclosure utilizes the Booth encoding circuit 402 to pad the mantissa of the second floating-point number (i.e., the multiplier in floating-point arithmetic) with 0s at both high and low bits, and performs Booth encoding processing to obtain the intermediate result in the partial product generation circuit 404. Of course, the first and second floating-point numbers here are for illustrative and not limiting purposes only; therefore, in some application scenarios, the first floating-point number can be the multiplier and the second floating-point number can be the multiplicand. Accordingly, in some encoding processes, the encoding operation can also be performed on the floating-point number acting as the multiplicand.

[0049] To better understand the technical solution disclosed herein, a brief introduction to Booth encoding is provided below. Generally, when two binary numbers are multiplied, the multiplication operation produces a large number of intermediate results called partial products. These partial products are then accumulated to obtain the final result of multiplying the two binary numbers. The more partial products there are, the larger the area and power consumption of the array multiplier will be, the slower the execution speed will be, and the more difficult its implementation circuit will be. The purpose of Booth encoding is to effectively reduce the number of summation terms in the partial products, thereby reducing the circuit area. Its algorithm involves first encoding the input multipliers according to corresponding rules. In one embodiment, the encoding rules can be, for example, as shown in Table 4 below:

[0050] Table 4

[0051]

[0052] y in Table 4 2i+1 y 2i and y 2i-1X can represent the numerical value corresponding to each group of sub-data to be encoded (i.e., the multiplier), and X can represent the mantissa of the first floating-point number (i.e., the multiplicand). After performing Booth encoding on each group of corresponding sub-data to be encoded, the corresponding encoded signal PPi (i = 0, 1, 2, ..., n) is obtained. As illustrated in Table 4, the encoded signal obtained after Booth encoding can include five categories, namely -2X, 2X, -X, X, and 0. For example, based on the above encoding rules, if the received multiplicand is an 8-bit data "X7X6X5X4X3X2X1X0", the following partial product can be obtained:

[0053] 1) When the multiplier includes three consecutive data "001" in the table above, the partial product is X, which can be represented as "X7X6X5X4X3X2X1X0". The 9th bit is the sign bit, i.e. PPi = {X[7], X};

[0054] 2) When the multiplier includes three consecutive digits “011” from the table above, the partial product is 2X, which can be represented as X shifted left by one digit, resulting in “X7X6X5X4X3X2X1X00”, i.e., PPi = {X, 0}.

[0055] 3) When the multiplier includes three consecutive digits "101" from the table above, the partial product is -X, which can be expressed as: This means that “X7X6X5X4X3X2X1X0” is inverted bitwise and then 1 is added, i.e., PPi = ~{X[7],X}+1;

[0056] 4) When the multiplier includes three consecutive digits "100" from the table above, the partial product is -2X, which can be expressed as: This means shifting "X7X6X5X4X3X2X1X0" one bit to the left, inverting the result, and then adding 1, i.e., PPi = ~{X, 0} + 1;

[0057] 5) When the multiplier includes three consecutive digits “111” or “000” from the table above, the partial product is 0, i.e., PPi = {9′b0}.

[0058] It should be understood that the above description of the process for obtaining partial products in conjunction with Table 4 is merely exemplary and not restrictive. Those skilled in the art, under the teachings of this disclosure, can modify the rules in Table 4 to obtain partial products different from those shown in Table 4. For example, when there are multiple consecutive digits (e.g., 3 or more) of a specific number in the multiplier, the obtained partial product can be the two's complement of the multiplicand, or, for example, the "add 1" operation in items 3) and 4) above can be performed after summing the partial products.

[0059] As can be understood from the above introductory description, by encoding the mantissa of the second floating-point number using a Booth encoding circuit and using the mantissa of the first floating-point number, multiple partial products can be generated from the partial product generation circuit as intermediate results, and these intermediate results are fed into the Wallace Tree compressor 406 in the partial product summation unit. It should be understood that obtaining partial products using Booth encoding is only one preferred method of obtaining partial products in this disclosure, and those skilled in the art can obtain such partial products in other ways. For example, it can also be obtained through a shift operation, i.e., selecting whether to shift and add the multiplicand or add 0 based on whether the multiplier's bit value is 1 or 0 to obtain the corresponding partial product. Similarly, using a Wallace Tree compressor to implement the partial product addition operation is merely exemplary and not limiting; those skilled in the art can also conceive of using other types of adders to implement such partial product addition operations. This adder can, for example, be one or more full adders, half adders, or various combinations thereof.

[0060] The Wallace tree compressor (or simply Wallace tree) is primarily used to sum the intermediate results (i.e., multiple partial products) mentioned above, reducing the number of accumulations of partial products (i.e., compression). Typically, the Wallace tree compressor employs a carry-save (CAS) architecture and the Wallace tree algorithm, which utilizes a Wallace tree array for computationally faster than traditional carry-pass addition.

[0061] Specifically, the Wallace tree compressor can compute the sum of partial products of each row in parallel. For example, it can reduce the number of times to accumulate N partial products from N-1 times to Log2N times, thereby improving the speed of the multiplier and having significant implications for the efficient use of resources. Depending on different application needs, the Wallace tree compressor can be designed in various types, such as 7-2 Wallace trees, 4-2 Wallace trees, and 3-2 Wallace trees. In one or more embodiments, this disclosure uses a 7-2 Wallace tree as an example to implement various floating-point operations of this disclosure, which will be discussed later in conjunction with... Figure 5 and Figure 6 It is described in detail.

[0062] In some embodiments, the Wallace tree compression operation disclosed herein can be arranged to have M inputs and N outputs, the number of which can be no less than K, where N is a preset positive integer less than M, and K is a positive integer no less than the maximum bit width of the intermediate results. For example, M can be 7, and N can be 2, i.e., a 7-2 Wallace tree as described in detail below. When the maximum bit width of the intermediate results is 48, K can be a positive integer of 48, meaning the number of Wallace trees can be 48.

[0063] In some embodiments, depending on the operation mode, one or more groups of Wallace trees can be selected to sum the intermediate results, wherein each group has X Wallace trees, and X is the number of bits in the intermediate result. Furthermore, there can be a carry relationship between Wallace trees within each group, but no carry relationship between groups. In an exemplary connection, Wallace tree compressors can be connected via carry, for example, from the carry output of a lower-order Wallace tree compressor (e.g., ...). Figure 6 C in The carry output (C) of the high-order Wallace tree compressor is sent to the high-order Wallace tree compressor. out It can also become a higher-order Wallace tree compressor that receives carry input from a lower-order Wallace tree compressor. Furthermore, when selecting one or more Wallace tree compressors from multiple Wallace tree compressors, any selection is possible; for example, they can be selected in the order of 0, 1, 2, and 3, or connected in the order of 0, 2, 4, and 6, as long as the selected Wallace tree compressors are selected according to the aforementioned carry relationship.

[0064] The Wallace tree and its operations described above will be illustrated with an illustrative example below. Assume the first and second floating-point numbers are 16-bit data (e.g., FP16*FP16), the multiplier supports a data width of 32 bits (thus supporting parallel multiplication of two sets of 16-bit data), and the Wallace tree is a 7-2 Wallace tree compressor with 7 inputs (i.e., an example value of M above) and 2 outputs (i.e., an example value of N above). In this example scenario, 48 Wallace trees (i.e., an example value of K above) can be used to perform the multiplication of the two sets of data in parallel.

[0065] Of the 48 Wallace trees mentioned above, trees 0 through 23 (i.e., the 24 trees in the first group) can perform partial product summation of the first group of multiplications, and the Wallace trees within this group can be connected sequentially via carry. Furthermore, trees 24 through 47 (i.e., the 24 trees in the second group) can perform partial product summation of the second group of multiplications, where the Wallace trees within this group are connected sequentially via carry. Additionally, there is no carry relationship between the 23rd Wallace tree in the first group and the 24th Wallace tree in the second group; that is, there is no carry relationship between Wallace trees in different groups.

[0066] Return to Figure 4After the partial products are compressed and summed using a Wallace tree compressor, the compressed partial products are summed using an adder to obtain the result of the mantissa multiplication operation. Regarding the adder, in one or more embodiments disclosed herein, it may include one of a full adder, a serial adder, and a carry-lookahead adder, used to sum the last two rows of partial products obtained by the Wallace tree compressor to obtain the result of the mantissa multiplication operation.

[0067] Understandable, through Figure 4 The mantissa multiplication operation illustrated, particularly using Booth coding and Wallace trees, can efficiently obtain the result of the mantissa multiplication operation. Specifically, Booth coding effectively reduces the number of partial product summation terms, thereby reducing the circuit area, while Wallace compressed trees can compute the sum of partial products of each row in parallel, thus improving the speed of the multiplier.

[0068] The following will combine Figure 5 and Figure 6 The example operations for partial product sums and 7-2 Wallace trees are described in detail. It is understood that the descriptions herein are merely illustrative and not restrictive, and are intended only to provide a better understanding of this disclosure.

[0069] Figure 5 This shows that after the aforementioned combination Figures 2-4 The partial product 500 obtained after the partial product generation circuit in the described mantissa processing unit is represented by four rows of white dots between the two dashed lines in the figure, where each row of white dots identifies a partial product. To facilitate the subsequent execution of the Wallace tree compressor, the bit depth can be pre-expanded. For example, Figure 5 The black dots represent the highest bit value of each 9-bit partial product that has been copied. It can be seen that the partial product is expanded and aligned to 16 (8+8) bits (i.e., the mantissa of the multiplicand is 8 bits wide + the mantissa of the multiplier is 8 bits wide). In another embodiment, for example, for the partial product of a 25*13 binary multiplication, the partial product is expanded to 38 (25+13) bits (i.e., the mantissa of the multiplicand is 25 bits wide + the mantissa of the multiplier is 13 bits wide).

[0070] Figure 6 This is a schematic block diagram 600 illustrating the operation flow and schematic block diagram of the Wallace tree compressor according to an embodiment of this disclosure.

[0071] like Figure 6 As shown, after performing a multiplication operation on the mantissas of two floating-point numbers, for example as previously described, the result can be obtained by encoding the multiplier with Booth code and using the multiplicand. Figure 6The diagram shows seven partial products. The number of partial products generated is reduced due to the use of the Booth coding algorithm. For ease of understanding, a Wallace tree with seven elements is marked with a dashed box in the partial product section of the diagram, and the process of compressing it from seven elements to two elements is further illustrated with arrows. In one embodiment, this compression process (or summation process) can be implemented using a full adder, i.e., inputting three elements and outputting two elements (i.e., a sum and a carry to the higher bit). A schematic block diagram of the Wallace tree compressor is shown in Figure 7-2. Figure 6 As shown on the right, it can be understood that the Wallace tree compressor includes 7 inputs from a column of partial products (such as...). Figure 6 (The seven elements are marked in the dashed box on the left). In operation, the carry input of the 0th column of the Wallace tree is 0, and the carry output Cout of each column of the Wallace tree serves as the carry input Cin of the next column of the Wallace tree.

[0072] from Figure 6 As can be seen in the left-hand section, after four compressions, the Wallace tree containing 7 elements can be compressed into a tree containing 2 elements. As mentioned earlier, this disclosure uses a 7-2 Wallace tree compressor to finally compress the partial product of 7 rows into a partial product with two rows (i.e., the second intermediate result of this disclosure), and uses an adder (e.g., a carry-lookahead adder) to obtain the mantissa result.

[0073] To further illustrate the principles of this disclosure, the following will exemplarily describe how the multiplier of this disclosure performs the first-stage operation under the four operation modes of FP16*FP16, FP16*FP16, FP32*FP32, and FP32*BF16, that is, until the Wallace tree compressor completes the summation of intermediate results to obtain the second intermediate result:

[0074] (1)FP16*FP16

[0075] In this operation mode of the multiplier, the mantissa of the floating-point number is 10 bits. Considering the denormalized non-zero number under the IEEE 754 standard, it can be extended by 1 bit, resulting in a mantissa of 11 bits. Furthermore, since the mantissa is unsigned, when using the Booth encoding algorithm, 1 bit of 0 can be added to the high-order bits, thus the total mantissa is 12 bits. When Booth encoding is applied to the second floating-point number (i.e., the multiplier), and the first floating-point number is referenced, seven partial products can be obtained in both the high and low parts through the partial product generation circuit. The seventh partial product is 0, and each partial product has a bit width of 24 bits. This can be compressed using 48 7-2 Wallace trees, with the carry from the 23rd to 24th Wallace trees being 0.

[0076] (2)BF16*BF16

[0077] In this operation mode of the multiplier, the mantissa of the floating-point number is 7 bits. Considering the denormalized non-zero number and the extension to a signed number under the IEEE 754 standard, the mantissa can be extended to 9 bits. When the second floating-point number, i.e. the multiplier, is encoded using Booz and referenced to the first floating-point number, seven valid partial products can be obtained in the high and low parts respectively through the partial product generation circuit. The 6th and 7th partial products are 0. Each partial product has a bit width of 18 bits. Compression is performed using two groups of 7-2 Wallace trees, 0-17 and 24-41, where the carry of the 23rd to 24th Wallace trees is 0.

[0078] (3)FP32*FP32

[0079] In this operation mode of the multiplier, the mantissa of the floating-point number can be 23 bits. Considering the denormalized non-zero number under the IEEE 754 standard, the mantissa can be extended to 24 bits. To save the area of ​​the multiplication unit, the multiplier disclosed herein can be called twice in this operation mode to complete one operation. Therefore, each mantissa multiplication is 25 bits * 13 bits, that is, the first floating-point number ina is extended by 1 bit 0 to become a 25-bit signed number, and the 24-bit mantissa of the second floating-point number inb is divided into two 12-bit parts, high and low, and extended by 1 bit 0 to obtain two 13-bit multipliers, represented as inb_high13 and inb_low13. In specific operation, the multiplier disclosed herein is called for the first time to calculate ina * inb_low13, and the multiplier is called for the second time to calculate ina * inb_high13. In each calculation, seven valid partial products are generated through Booth encoding, each with a bit width of 38 bits, and compressed using a 7-2 Wallace tree from the 0th to the 37th product.

[0080] (4)FP32*BF16

[0081] In this operation mode of the multiplier, the mantissa of the first floating-point number ina is 23 bits, and the mantissa of the second floating-point number inb is 7 bits. Considering the denormalized non-zero number and the extended signed number under the IEEE 754 standard, the mantissa can be extended to 25 bits and 9 bits respectively. A 25-bit × 9-bit multiplication is performed to obtain 7 valid partial products, of which the 6th and 7th partial products are 0. The bit width of each partial product is 34 bits, which is compressed through the 0th to 33rd Wallace trees.

[0082] The above examples illustrate how the multiplier disclosed herein performs the first-stage operation in four operational modes, with Booth coding and a 7-2 Wallace tree being preferred. Based on the above description, those skilled in the art will understand that this disclosure uses seven partial products, allowing the 7-2 Wallace tree to be reused in different operational modes.

[0083] In some operation modes, the aforementioned mantissa processing unit may further include a control circuit, which can be used to call the mantissa processing unit multiple times according to the operation mode when the mantissa bit width of the first floating-point number indicated by the operation mode and / or the mantissa bit width of the first floating-point number is greater than the data bit width that the mantissa processing unit can process at one time. Further, for the case of multiple calls, the partial product summation circuit may further include a shifter, which is used to shift the existing summation result when the mantissa processing unit is called multiple times according to the operation mode, and add it to the summation result obtained in the current call to obtain a new summation result, and use the new summation result as the mantissa after the multiplication operation.

[0084] For example, as mentioned earlier, the mantissa processing unit can be called twice in FP32*FP32 operation mode. Specifically, in the first call to the mantissa processing unit, the mantissa bits (i.e., ina*inb_low13) are added in the second stage using a carry-lookahead adder to obtain the second low-order intermediate result. In the second call to the mantissa processing unit, the mantissa bits (i.e., ina*inb_high13) are added in the second stage using a carry-lookahead adder to obtain the second high-order intermediate result. Subsequently, in one embodiment, the second low-order intermediate result and the second high-order intermediate result can be accumulated using a shift operation to obtain the mantissa after the multiplication operation. This shift operation can be expressed as follows:

[0085] r fp32xfp32 =sum h [37:0] << 12+sum l [37:0]

[0086] The second highest intermediate result sum h [37:0] Shift left by 12 bits and sum with the middle result of the second least significant bit. l [37:0]Accumulate.

[0087] The above text combined Figures 4-6 The multiplier disclosed herein describes in detail the operations performed when multiplying the mantissas of a first floating-point number and a second floating-point number during floating-point arithmetic. Of course, Figure 4 To focus on describing the operation of the mantissa processing unit of this multiplier, other units, such as the exponent processing unit and the sign processing unit, are not shown or described. The following will combine... Figure 7 The overall description of the multiplier disclosed herein, as well as the description of the mantissa processing unit given above, also applies. Figure 7 The scene depicted.

[0088] Figure 7This is a general schematic block diagram illustrating a multiplier 700 according to an embodiment of this disclosure. It should be understood that the positions, presence, and connections of the various units depicted in the figure are merely exemplary and not limiting. For example, some units may be integrated, while others may be separated or omitted or replaced depending on the application scenario.

[0089] The multiplier disclosed herein can be exemplarily divided into a first stage and a second stage according to the operation flow in each operation mode, as shown by the dotted lines in the figure. In summary, in the first stage: the calculation result of the sign bit is output, the intermediate calculation result of the exponent bit is output, and the intermediate calculation result of the mantissa bit is output (e.g., including the aforementioned encoding process of the fixed-point multiplication Booth algorithm for the input mantissa bit and the Wallace tree compression process). In the second stage: regularization and rounding operations are performed on the exponent and mantissa to output the calculation result of the exponent and the calculation result of the mantissa.

[0090] like Figure 7 As shown, the multiplier disclosed herein may include a mode selection unit 702 and a normalization processing unit 704, wherein the mode selection unit can select an operation mode based on an input mode signal (in_mode). In one embodiment, the input mode signal may correspond to the operation mode number in Table 2. For example, when the input mode signal indicates operation mode number "1" in Table 2, the multiplier can be set to operate in FP16*FP16 operation mode, and when the input mode signal indicates operation mode number "3" in Table 2, the multiplier can be set to operate in FP32*FP32 operation mode. For illustrative purposes, Figure 7 Only four exemplary operation modes are shown: FP16*FP16, BF16*BF16, FP32*FP32, and FP32*BP16. However, as previously stated, the multiplier disclosed herein also supports many other different operation modes.

[0091] The normalization processing unit can be configured to normalize the first floating-point number or the second floating-point number according to the operation mode when the first floating-point number or the second floating-point number is a non-normalized non-zero floating-point number, in order to obtain the corresponding exponent and mantissa, for example, to normalize the floating-point number in the data format indicated by the operation mode according to the IEEE 754 standard.

[0092] Furthermore, the multiplier includes a mantissa processing unit to perform the multiplication operation of the first floating-point mantissa and the second floating-point mantissa. For this purpose, in one or more embodiments, the mantissa processing unit may include a bit-length expansion circuit 706, a Booth encoder 708, a partial product generation circuit 710, a Wallace tree compressor 712, and an adder 714, wherein the bit-length expansion circuit can be used to expand the mantissa to accommodate denormalized non-zero numbers under the IEEE 754 standard, to suit the operation of the Booth encoder. Since the Booth encoder, partial product generation circuit, Wallace tree compressor, and adder have already been combined... Figures 4-6 The same description has been provided in detail, so it applies here as well and will not be repeated here.

[0093] In some embodiments, the multiplier disclosed herein further includes a regularization unit 716 and a rounding unit 718, the regularization unit and the rounding unit having the same characteristics as... Figure 3 The units shown have the same function. Specifically, for a regularized unit, it can be based on, for example... Figure 7 The output mode signal "out_mode" indicates the data format used to perform floating-point regularization processing on the summation result and the exponent data from the exponent processing unit to obtain a regularized exponent result and a regularized mantissa result. For example, according to the data format indicated by the output mode signal, the regularization unit can adjust the bit width of the exponent and mantissa to conform to the requirements of the aforementioned indicated data format. For another example, when the highest bit of the mantissa is 0, and the mantissa is not 0, the regularization unit can repeatedly shift the mantissa left by 1 bit and decrement the exponent by 1 until the highest bit value is 1. For the rounding unit, in one embodiment, it can be used to perform a rounding operation on the regularized mantissa result according to the rounding mode to obtain a rounded mantissa, and use the rounded mantissa as the mantissa after the multiplication operation.

[0094] In one or more embodiments, the aforementioned output mode signal may be part of an operation mode, used to indicate the data format after the multiplication operation. For example, as described in Table 3 above, when the operation mode number is "12", the number "1" can be equivalent to the aforementioned "in_mode" signal, used to indicate the execution of an FP16*FP16 multiplication operation, while the number "2" can be equivalent to the "out_mode" signal, used to indicate that the data type of the output result is BF16. Therefore, it is understood that in some application scenarios, the output mode signal can be combined with the aforementioned input mode signal to provide it to the mode selection unit. Based on this combined mode signal, the mode selection unit can determine the data format of the input data and the output result at the initial stage of the multiplier operation without having to provide a separate output mode signal to the regularization, thereby further simplifying the operation.

[0095] In one or more embodiments, the aforementioned rounding operation may include, for example, the following five rounding modes.

[0096] (1) Round to the nearest value: In this mode, when two values ​​are equally close, the even number takes precedence. The result will be rounded to the nearest representable value. However, when two numbers are equally close, the even number (which is the number ending in 0 in binary) will be used as the rounding result.

[0097] (2) Rounding: See the example below for a demonstration operation;

[0098] (3) Rounding towards +∞: Under this rule, the result will be rounded towards positive infinity;

[0099] (4) Rounding towards -∞: Under this rule, the result will be rounded towards negative infinity; and

[0100] (5) Rounding to 0: Under this rule, the result will be rounded to 0.

[0101] For example, in the "rounding" mode, the mantissa rounding is as follows: Multiplying the 24-bit mantissas of two normalized floating-point numbers results in a 48-bit (47-0) mantissa. After normalization (if the highest bit of the mantissa is 0, shift the mantissa left by 1 bit; if the highest bit of the mantissa is 1, leave the mantissa unchanged and increment the temporary exponent obtained earlier by 1), only bits 46 to 24 are output. When the 23rd bit of the mantissa is 0, the (23-0)th bit is discarded; when the 23rd bit of the mantissa is 1, carry over 1 to the 24th bit and discard the (23-0)th bit.

[0102] Return to Figure 7 The multiplier disclosed herein also includes an exponent processing unit 720 and a sign processing unit 722. The exponent processing unit can be used to obtain the exponent after the multiplication operation based on the operation mode, the exponent of the first floating-point number, and the exponent of the second floating-point number. For example, the exponent processing circuit can add the exponent data of the first floating-point number, the exponent data of the second floating-point number, and the offset values ​​of their respective input floating-point data types, and subtract the offset values ​​of the output floating-point data types to obtain the exponent data of the product of the first and second floating-point numbers. In one or more embodiments, the exponent processing unit can be implemented as or include an addition / subtraction circuit, which is used to obtain the exponent after the multiplication operation based on the operation mode, the exponent of the first floating-point number, the exponent of the second floating-point number, and the operation mode.

[0103] In one embodiment, the sign processing unit can be implemented as an XOR circuit, which performs an XOR operation on the sign bit data of the first floating-point number and the second floating-point number to obtain the sign bit data of the product of the first floating-point number and the second floating-point number.

[0104] The above text combined Figure 7 The multiplier disclosed herein is described in detail. Through this description, those skilled in the art will understand that the multiplier supports operation under multiple arithmetic modes, thereby overcoming the shortcomings of existing multipliers that only support single floating-point operations. Furthermore, since the multiplier disclosed herein is reusable, it also supports high-bit-width floating-point data, reducing computational costs and overhead. In one or more embodiments, the multiplier disclosed herein may also be arranged in or included in an integrated circuit chip or computing device to perform multiplication operations on floating-point numbers under multiple arithmetic modes.

[0105] On the other hand, the multiplier disclosed herein can support parallel multiplication of multiple sets of floating-point numbers, each set of floating-point numbers including a first floating-point number and a second floating-point number. The first floating-point numbers in each set can be concatenated together and input into the multiplier, or input into the multiplier in parallel without concatenation. Similarly, the second floating-point numbers in each set can be concatenated together and input into the multiplier, or input into the multiplier in parallel without concatenation. Each set of input floating-point numbers can be multiplied using a sign processing unit, a mantissa processing unit, and an exponent processing unit, respectively. Furthermore, the multiplier may also include multiple sign processing units, mantissa processing units, and exponent processing units as described above, with each set of input floating-point numbers processed by different sign processing units, mantissa processing units, and exponent processing units. Of course, a multiplier may include one or more sign processing units, one or more exponent processing units, and one or more mantissa processing units. The number of these three processing units can be arbitrarily combined. For example, a multiplier may include multiple sign processing units, multiple exponent processing units, and one mantissa processing unit. Each set of floating-point numbers is processed using different sign processing units and different exponent processing units, and is processed sequentially using the same mantissa processing unit. Further, for example, the mantissa processing unit may include multiple Wallace trees. These multiple Wallace trees can be divided into one or more sets of Wallace trees according to actual conditions (e.g., operation mode). Each set of Wallace trees is responsible for processing the mantissa of a set of floating-point numbers. For example, it may be divided into two sets of Wallace trees, each supporting the operation of two 16-bit mantissas. For example, the first and second floating-point numbers in each set of floating-point numbers may both have 16-bit mantissas. Thus, the Wallace trees in this multiplier support parallel operations of these two sets of 16-bit mantissas. The mantissa processing unit can also include multiple other components (such as Booth encoding circuits), each of which is responsible for processing the mantissa of a set of floating-point numbers. Of course, the components in the mantissa processing unit can be called multiple times, without needing to set up multiple units. Furthermore, the first and second floating-point numbers in each set of floating-point numbers can be concatenated together and input into the multiplier.

[0106] Figure 8 This is a flowchart illustrating a method 800 for performing floating-point multiplication using a multiplier according to an embodiment of this disclosure. It will be understood that the multiplier mentioned herein is the one described above in conjunction with... Figures 1-7 The multiplier is described in detail, and therefore the previous description of the multiplier and its internal components, functions and operations also applies to the description here.

[0107] like Figure 8As shown, method 800 may include, at step S802, using the exponent processing unit of the multiplier to obtain the exponent after the multiplication operation based on the operation mode, the exponent of the first floating-point number, and the exponent of the second floating-point number. As previously mentioned, the operation mode may be one of several operation modes and may be used to indicate the data format of the floating-point number. In one or more embodiments, the operation mode may also be used to determine the data format of the floating-point number of the output result.

[0108] Next, in step S804, the method 800 can utilize the mantissa processing unit of the multiplier to obtain the mantissa after the multiplication operation based on the operation mode, the first floating-point number, and the second floating-point number. Regarding exemplary mantissa operations, this disclosure uses a Booth coding algorithm and a Wallace tree compressor in some preferred embodiments to improve the efficiency of mantissa processing. Additionally, when the first floating-point number and the second floating-point number are signed numbers, the method 800 can also obtain the sign after the multiplication operation based on the sign of the first floating-point number and the sign of the second floating-point number in step S806.

[0109] Although the above method illustrates the use of the multiplier disclosed herein to perform floating-point multiplication in steps, the order of these steps does not imply that the steps of this method must be performed in the stated order, but can be processed in other orders or in parallel. Furthermore, other steps of method 800 are not described herein for the sake of brevity, but those skilled in the art will understand from the content of this disclosure that this method can also perform the aforementioned combinations using a multiplier. Figures 1-7 The various operations described.

[0110] In the above embodiments disclosed herein, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant descriptions in other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as these combinations of technical features do not contradict each other, they should be considered within the scope of this specification.

[0111] Figure 9 This is a structural diagram illustrating a combined processing apparatus 900 according to an embodiment of the present disclosure. As shown, the combined processing apparatus 900 includes a computing device 902, which may include the multiplier of the present disclosure as described above in conjunction with the accompanying drawings. Additionally, the combined processing apparatus includes a general interconnect interface 904 and other processing devices 906. The computing device according to the present disclosure interacts with other processing devices to jointly complete user-specified operations.

[0112] According to the scheme disclosed herein, the other processing device may include one or more types of processors such as a central processing unit (“CPU”), a graphics processing unit (“GPU”), and a neural network processor, and the number of such processors is not limited but determined according to actual needs. In one or more embodiments, the other processing device may serve as an interface between the computing device disclosed herein (which may be specifically embodied as a machine learning computing device) and external data and control, performing tasks including but not limited to data transfer, and completing basic control such as starting and stopping the machine learning computing device; the other processing device may also cooperate with the machine learning computing device to jointly complete computing tasks.

[0113] According to the disclosed scheme, the universal interconnect interface can be used to transfer data and control commands between a computing device and other processing devices. For example, the computing device can obtain required input data from other processing devices via the universal interconnect interface and write it to the on-chip storage device of the computing device. Furthermore, the computing device can obtain control commands from other processing devices via the universal interconnect interface and write them to the on-chip control cache of the computing device. Alternatively or optionally, the universal interconnect interface can also read data from the storage module of the computing device and transmit it to other processing devices.

[0114] Optionally, the combined processing apparatus may further include a storage device 908, which may be connected to the computing device and the other processing device respectively. In one or more embodiments, the storage device may be used to store data from the computing device and the other processing device, particularly suitable for data that cannot be fully stored in the internal storage of the computing device or other processing device, requiring computation.

[0115] Depending on the application scenario, the combined processing device disclosed herein can serve as a System-on-a-Chip (SoC) for devices such as mobile phones, robots, drones, video capture equipment, and video surveillance equipment. This effectively reduces the core area of ​​the control unit, increases processing speed, and lowers overall power consumption. In this case, the general-purpose interconnect interface of the combined processing device connects to certain components of the device. These components may include, for example, a camera, monitor, mouse, keyboard, network card, or Wi-Fi interface.

[0116] In some embodiments, this disclosure also discloses a chip or integrated circuit chip that includes the aforementioned computing device, combined processing device, and multiplier. In other embodiments, this disclosure also discloses a chip package structure that includes the aforementioned chip.

[0117] In some embodiments, this disclosure also discloses a circuit board that includes the above-described chip packaging structure. See also... Figure 10It provides the aforementioned exemplary board, which, in addition to the chip 1002, may also include other supporting components, including but not limited to: storage device 1004, interface device 1006, and controller 1008.

[0118] The storage device is connected to the chip within the chip package structure via a bus and is used to store data. The storage device may include multiple sets of storage cells 1010. Each set of storage cells is connected to the chip via a bus. It can be understood that each set of storage cells may be DDR SDRAM (“Double Data Rate SDRAM”).

[0119] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the memory device may include four groups of memory cells. Each group of memory cells may include multiple DDR4 chips. In one embodiment, the chip may internally include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification.

[0120] In one embodiment, each group of memory cells may include multiple Double Data Rate (DDR) synchronous dynamic random access memories (DRAMs) arranged in parallel. DDR can transfer data twice within one clock cycle. A controller for controlling the DDR is provided in the chip for controlling the data transfer and data storage of each memory cell.

[0121] The interface device is electrically connected to the chip within the chip package structure. The interface device is used to realize data transmission between the chip and an external device 1012 (e.g., a server or computer). For example, in one embodiment, the interface device can be a standard PCIe interface. For instance, data to be processed is transferred from the server to the chip via a standard PCIe interface, realizing data transfer. In another embodiment, the interface device can also be other interfaces; this disclosure does not limit the specific form of the other interfaces mentioned above, as long as the interface unit can realize the switching function. Furthermore, the calculation results of the chip are still transmitted back to the external device (e.g., the server) by the interface device.

[0122] The controller is electrically connected to the chip to monitor its status. Specifically, the chip and the controller can be electrically connected via an SPI interface. The controller may include a microcontroller ("MCU"). The chip may include multiple processing chips, multiple processing cores, or multiple processing circuits, and can drive multiple loads. Thus, the chip can operate in different states, such as high load and low load. The controller can regulate the operating states of multiple processing chips, multiple processing cores, and / or multiple processing circuits within the chip.

[0123] In some embodiments, this disclosure also discloses an electronic device or apparatus that includes the aforementioned circuit board. Depending on the application scenario, the electronic device or apparatus may include a data processing device, robot, computer, printer, scanner, tablet computer, smart terminal, mobile phone, dashcam, navigator, sensor, camera, server, cloud server, camera, camcorder, projector, watch, earphone, mobile storage, wearable device, vehicle, home appliance, and / or medical device. The vehicle includes airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs.

[0124] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this disclosure. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0125] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0126] In the embodiments provided in this disclosure, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, optical, acoustic, magnetic, or other forms.

[0127] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0128] Furthermore, the functional units in the various embodiments disclosed herein can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software program module.

[0129] If the integrated unit is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, when the technical solution disclosed herein can be embodied in the form of a software product, the computer software product is stored in a storage device and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage device includes various media capable of storing program code, such as a USB flash drive, read-only memory ("ROM"), random access memory ("RAM"), portable hard drive, magnetic disk, or optical disk.

[0130] The foregoing can be better understood in accordance with the following terms:

[0131] Item A1, a multiplier for performing floating-point multiplication according to an operation mode, wherein the floating-point number includes at least an exponent and a mantissa, the multiplier comprising:

[0132] An exponent processing unit is configured to obtain the exponent after the multiplication operation based on the operation mode, the exponent of the first floating-point number, and the exponent of the second floating-point number; and

[0133] The mantissa processing unit is used to obtain the mantissa after the multiplication operation based on the operation mode, the mantissa of the first floating-point number, and the mantissa of the second floating-point number.

[0134] The operation mode is used to indicate the data format of the first floating-point number and the data format of the second floating-point number.

[0135] Clause A2, the multiplier as described in Clause A1, wherein the operation mode is further used to indicate the data format after the multiplication operation.

[0136] Clause A3, the multiplier as described in Clause A1 or Clause A2, wherein the data format includes at least one of half-precision floating-point, single-precision floating-point, double-precision floating-point, and custom floating-point.

[0137] Clause A4, a multiplier according to any one of clauses A1-A3, wherein the floating-point number further includes a sign, the multiplier further comprising:

[0138] The sign processing unit is used to obtain the sign of the multiplication operation based on the sign of the first floating-point number and the sign of the second floating-point number.

[0139] Clause A5, a multiplier according to any one of clauses A1-A4, wherein the sign processing unit includes an XOR logic circuit for performing an XOR operation on the sign of the first floating-point number and the sign of the second floating-point number to obtain the sign after the multiplication operation.

[0140] Clause A6, the multiplier according to any one of clauses A1-A5, further includes:

[0141] The normalization processing unit is used to normalize the first floating-point number or the second floating-point number according to the operation mode when the first floating-point number or the second floating-point number is a non-normalized non-zero floating-point number, so as to obtain the corresponding exponent and mantissa.

[0142] Clause A7, the multiplier according to any one of Clauses A1-A7, wherein the mantissa processing unit includes a partial product operation unit and a partial product summation unit, wherein the partial product operation unit is used to obtain an intermediate result based on the mantissa of the first floating-point number and the mantissa of the second floating-point number, and the partial product summation unit is used to perform a summation operation on the intermediate result to obtain a summation result, and use the summation result as the mantissa after the multiplication operation.

[0143] Clause A8, the multiplier according to any one of clauses A1-A7, wherein the partial product operation unit includes a Booth encoding circuit for padding the high and low bits of the mantissa of the first floating-point number or the second floating-point number with 0 and performing Booth encoding processing to obtain the intermediate result.

[0144] Clause A9, a multiplier according to any one of clauses A1-A8, wherein the partial product summation unit includes an adder for summing the intermediate results to obtain the summed result.

[0145] Clause A10, a multiplier according to any one of clauses A1-A9, wherein the partial product summation unit comprises a Wallace tree and an adder, wherein the Wallace tree is used to sum the intermediate results to obtain a second intermediate result, and the adder is used to sum the second intermediate results to obtain the summed result.

[0146] Clause A11, a multiplier according to any one of clauses A1-A10, wherein the adder includes at least one of a full adder, a serial adder, and a carry-lookahead adder.

[0147] Clause A12, a multiplier according to any one of clauses A1-A11, wherein when the number of intermediate results is less than M, zero values ​​are added as intermediate results, such that the number of intermediate results is equal to M, where M is a preset positive integer.

[0148] Clause A13, a multiplier according to any one of clauses A1-A12, wherein each of the Wallace trees has M inputs and N outputs, and the number of the Wallace trees is not less than K, where N is a preset positive integer less than M, and K is a positive integer not less than the maximum bit width of the intermediate result.

[0149] Clause A14, a multiplier according to any one of clauses A1-A13, wherein the partial product summing unit is used to select one or more groups of Wallace trees to sum the intermediate result according to the operation mode, wherein each group has X Wallace trees, where X is the number of bits in the intermediate result, wherein there is a carry relationship between the Wallace trees within each group, and no carry relationship between the Wallace trees between groups.

[0150] Clause A15, the multiplier according to any one of clauses A1-A14, wherein the mantissa processing unit further includes control circuitry for calling the mantissa processing unit multiple times according to the operation mode when the operation mode indicates that the mantissa bit width of at least one of the first floating-point number or the second floating-point number is greater than the data bit width that the mantissa processing unit can process at one time.

[0151] Clause A16, the multiplier according to any one of clauses A1-A15, wherein the partial product summation unit further includes a shifter, wherein when the control circuit calls the mantissa processing unit multiple times according to the operation mode, the shifter is used in each call to shift the existing summation result and add it to the summation result obtained in the current call to obtain a new summation result, and the new summation result obtained in the last call is used as the mantissa after the multiplication operation.

[0152] Clause A17, the multiplier according to any one of Clauses A1-A16, further includes a regularization unit for performing floating-point regularization processing on the mantissa and exponent after the multiplication operation to obtain a regularized exponent result and a regularized mantissa result, and using the regularized exponent result and the regularized mantissa result as the exponent and mantissa after the multiplication operation.

[0153] Clause A18, the multiplier according to any one of clauses A1-A17, further includes a rounding unit for performing a rounding operation on the regularized mantissa result according to a rounding mode to obtain a rounded mantissa, and using the rounded mantissa as the mantissa after the multiplication operation.

[0154] Clause A19, the multiplier described in any one of Clauses A1-A18, further includes:

[0155] The mode selection unit is used to select, from a variety of operation modes supported by the multiplier, an operation mode that indicates the data format of the first floating-point number and the second floating-point number.

[0156] Item A20, a method for performing floating-point multiplication using a multiplier, wherein the floating-point number includes at least an exponent and a mantissa, the multiplier performing the multiplication based on an operation mode, the method comprising:

[0157] The exponent processing unit of the multiplier is used to obtain the exponent after the multiplication operation according to the operation mode, the exponent of the first floating-point number, and the exponent of the second floating-point number.

[0158] The mantissa processing unit of the multiplier is used to obtain the mantissa after the multiplication operation based on the operation mode, the mantissa of the first floating-point number, and the mantissa of the second floating-point number.

[0159] The operation mode is used to indicate the data format of the first floating-point number and the data format of the second floating-point number.

[0160] Clause A21, an integrated circuit chip including a multiplier as described in any one of Clauses A1-A19.

[0161] Clause A22, a computing device comprising a multiplier as described in any one of Clauses A1-A19 or an integrated circuit chip as described in Clause A21.

[0162] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0163] It should be understood that the terms "first," "second," "third," and "fourth," etc., in the claims, specification, and drawings of this disclosure are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0164] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0165] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0166] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this disclosure. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this disclosure, and on the specific implementation methods and application scope of this disclosure, are all within the scope of protection of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A multiplier for floating-point multiplication according to an operation mode, wherein the floating-point number comprises at least an exponent and a mantissa, the multiplier comprising: an exponent processing unit for obtaining an exponent after the multiplication according to the operation mode, an exponent of a first floating-point number and an exponent of a second floating-point number; and a mantissa processing unit for obtaining a mantissa after the multiplication according to the operation mode, a mantissa of the first floating-point number and a mantissa of the second floating-point number, wherein the operation mode is used to indicate a data format of the first floating-point number and a data format of the second floating-point number, and the data format of the first floating-point number is different from the data format of the second floating-point number; wherein the mantissa processing unit comprises a partial product operation unit and a partial product summation unit, wherein the partial product operation unit is used to obtain an intermediate result according to the mantissa of the first floating-point number and the mantissa of the second floating-point number, and the partial product summation unit is used to sum the intermediate result to obtain a summation result, and the summation result is used as the mantissa after the multiplication; wherein the mantissa processing unit further comprises a control circuit, which is used to call the mantissa processing unit multiple times according to the operation mode when the operation mode indicates that a mantissa bit width of at least one of the first floating-point number or the second floating-point number is greater than a data bit width that can be processed by the mantissa processing unit at one time. 2.The multiplier according to claim 1, wherein the operation mode is further used to indicate a data format after the multiplication. 3.The multiplier according to claim 1 or 2, wherein the data format comprises at least one of half-precision floating-point number, single-precision floating-point number, brain floating-point number, double-precision floating-point number, and custom floating-point number. 4.The multiplier according to claim 1 or 2, wherein the floating-point number further comprises a sign, and the multiplier further comprises: a sign processing unit for obtaining a sign after the multiplication according to a sign of the first floating-point number and a sign of the second floating-point number. 5.The multiplier according to claim 4, wherein the sign processing unit comprises an exclusive-OR logic circuit, which is used to perform an exclusive-OR operation according to the sign of the first floating-point number and the sign of the second floating-point number to obtain the sign after the multiplication. 6.The multiplier according to claim 1 or 2, further comprising: a normalization processing unit for performing normalization processing on the first floating-point number or the second floating-point number according to the operation mode to obtain a corresponding exponent and mantissa when the first floating-point number or the second floating-point number is a non-normalized non-zero floating-point number. 7.The multiplier according to claim 1, wherein the partial product operation unit comprises a Booth encoding circuit, which is used to pad 0 to high and low bits of the mantissa of the first floating-point number or the second floating-point number, and perform Booth encoding processing to obtain the intermediate result. 8.The multiplier according to claim 7, wherein the partial product summation unit comprises an adder, which is used to sum the intermediate result to obtain the summation result. ​ ​ ​ ​ ​ ​ ​ ​ 9. The multiplier of claim 7, wherein the partial product summing unit comprises Wallace trees and an adder, wherein the Wallace trees are configured to sum the intermediate results to obtain second intermediate results, and the adder is configured to sum the second intermediate results to obtain the sum result.

10. The multiplier of claim 8 or 9, wherein the adder comprises at least one of a full adder, a serial adder, and a carry-lookahead adder.

11. The multiplier of claim 9, wherein when the number of intermediate results is less than M, zero values are padded as intermediate results so that the number of intermediate results is equal to M, wherein M is a predetermined positive integer.

12. The multiplier of claim 11, wherein each of the Wallace trees has M inputs and N outputs, and the number of the Wallace trees is not less than K, wherein N is a predetermined positive integer less than M, and K is a positive integer not less than the maximum bit width of the intermediate results.

13. The multiplier of claim 12, wherein the partial product summing unit is configured to select one or more groups of the Wallace trees to sum the intermediate results according to an operation mode, wherein each group of the Wallace trees has X Wallace trees, and X is the number of bits of the intermediate results, wherein the Wallace trees in each group have a carry-lookahead relationship, and the Wallace trees in different groups do not have a carry-lookahead relationship.

14. The multiplier of claim 1, wherein the partial product summing unit further comprises a shifter configured to, when the control circuit invokes the mantissa processing unit multiple times according to the operation mode, shift the existing sum result in each invocation, and add the shifted sum result to the sum result obtained in the current invocation to obtain a new sum result, and the new sum result obtained in the last invocation is the mantissa after the multiplication operation.

15. The multiplier of claim 14, further comprising a normalization unit configured to: perform floating point normalization on the mantissa after the multiplication operation and the exponent to obtain a normalized exponent result and a normalized mantissa result, and the normalized exponent result and the normalized mantissa result are the exponent after the multiplication operation and the mantissa after the multiplication operation.

16. The multiplier of claim 15, further comprising: a rounding unit configured to perform rounding on the normalized mantissa result according to a rounding mode to obtain a rounded mantissa, and the rounded mantissa is the mantissa after the multiplication operation.

17. The multiplier of claim 1 or 2, further comprising: a mode selection unit configured to select an operation mode from a plurality of operation modes supported by the multiplier, wherein the operation mode indicates the data format of the first floating point number and the second floating point number.

18. A method of performing floating point multiplication using a multiplier, wherein the floating point number comprises at least an exponent and a mantissa, and the multiplier performs multiplication based on an operation mode, the method comprising: an exponent processing unit of the multiplier is configured to obtain an exponent after the multiplication according to the operation mode, an exponent of the first floating-point number and an exponent of the second floating-point number; a mantissa processing unit of the multiplier is configured to obtain a mantissa after the multiplication according to the operation mode, a mantissa of the first floating-point number and a mantissa of the second floating-point number; wherein the operation mode is used to indicate a data format of the first floating-point number and a data format of the second floating-point number, and the data format of the first floating-point number is different from the data format of the second floating-point number; a partial product operation unit of the multiplier is configured to obtain an intermediate result according to the mantissa of the first floating-point number and the mantissa of the second floating-point number; a partial product summation unit of the multiplier is configured to sum the intermediate result to obtain a summation result, and the summation result is used as the mantissa after the multiplication; wherein when the operation mode indicates that a mantissa bit width of at least one of the first floating-point number or the second floating-point number is greater than a data bit width that can be processed by the mantissa processing unit at one time, a control circuit of the mantissa processing unit is configured to call the mantissa processing unit multiple times according to the operation mode.

19. An integrated circuit chip comprising the multiplier of any one of claims 1-17.

20. A computing device comprising the multiplier of any one of claims 1-17 or the integrated circuit chip of claim 19.

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