Method for modeling high-speed channel, method for designing and manufacturing semiconductor package

Abstract

A method for modeling a high-speed channel in a semiconductor package, the high-speed channel including a plurality of first connecting wirings on the upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate, the method comprising: receiving design information of the high-speed channel; dividing the design information into a first layout including the plurality of first connecting wirings and a second layout including the plurality of through electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool and at least a portion of the first layout; and obtaining an integrated modeling result of the entire high-speed channel by combining the results of the first modeling operation and the second modeling operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0126791 filed on October 14, 2019, and Korean Patent Application No. 10-10-2020-0012968 filed on February 4, 2020, both of which are hereby incorporated by reference in their entirety. Technical Field

[0003] The present disclosure generally relates to a semiconductor integrated circuit, and more particularly, to a method for modeling a high-speed channel in a semiconductor package, a method for designing a semiconductor package using the method for modeling a high-speed channel, and a method for manufacturing a semiconductor package using the method for designing a semiconductor package. Background Art

[0004] Recently, it has become desirable to increase memory bandwidth for high performance computing (HPC) such as artificial intelligence (AI) and graphics processing units (GPUs), as accelerator designs for machine learning can be affected by whether the system can become compute-bound and / or memory bandwidth-bound.

[0005] The increase in memory bandwidth may involve innovations in processing technology. Developments in process technology have led to higher densities of integrated circuits (ICs). Three-dimensional (3D) integration may enable continued increases in the density of ICs. In addition, 2.5D plug-ins and through-silicon vias (TSVs) also play an important role. The growing bandwidth requirements of HPC have led to 2.5D silicon plug-ins becoming an important solution due to their large number of fine channels and therefore greater channel bandwidth. Therefore, it may be useful to accurately model high-speed channels in 2.5D and / or 3D ICs through plug-ins and TSVs. Summary of the invention

[0006] At least one example embodiment of the present disclosure provides a method of effectively modeling a high-speed channel formed by TSVs and metal wirings in a semiconductor package implemented in a 2.5D structure and / or a 3D structure.

[0007] At least one example embodiment of the present disclosure provides a method of designing a semiconductor package using a method of modeling a high-speed channel.

[0008] At least one example embodiment of the present disclosure provides a method of manufacturing a semiconductor package using a design method of the semiconductor package.

[0009] According to an example embodiment, in a method for modeling a high-speed channel in a semiconductor package, the high-speed channel is formed by a plurality of first connecting wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate. Design information of the high-speed channel is received. The design information is divided into a first layout including a plurality of first connecting wirings and a second layout including a plurality of through electrodes. A first modeling operation is performed on the first layout using a first modeling scheme and a first modeling tool. A second modeling operation is performed on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout. The second modeling scheme is different from the first modeling scheme, and the second modeling tool is different from the first modeling tool. An integrated modeling result of the entire high-speed channel is obtained by combining the result of the first modeling operation and the result of the second modeling operation.

[0010] According to an example embodiment, in a design method of a semiconductor package, a design of at least one semiconductor device included in a semiconductor package is generated. A design of a high-speed channel included in a semiconductor package is generated. The high-speed channel is modeled. The modeling result of the high-speed channel is analyzed and verified. The high-speed channel is formed by a plurality of first connecting wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate. Modeling the high-speed channel includes: receiving design information of the high-speed channel; dividing the design information into a first layout including a plurality of first connecting wirings and a second layout including a plurality of through electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout, wherein the second modeling scheme is different from the first modeling scheme, and the second modeling tool is different from the first modeling tool; and obtaining an integrated modeling result of the entire high-speed channel by combining the result of the first modeling operation with the result of the second modeling operation.

[0011] According to an example embodiment, in a method for manufacturing a semiconductor package, a design of a semiconductor package including at least one semiconductor device and a high-speed channel is generated. A semiconductor package is manufactured based on the design result of the semiconductor package. Designing a semiconductor package includes: generating a design of at least one semiconductor device; generating a design of a high-speed channel; modeling the high-speed channel; and analyzing and verifying the modeling result of the high-speed channel. The high-speed channel includes a plurality of first connection wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate. Modeling the high-speed channel includes: receiving design information of the high-speed channel; dividing the design information into a first layout including a plurality of first connection wirings and a second layout including a plurality of through electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout, wherein the second modeling scheme is different from the first modeling scheme, and the second modeling tool is different from the first modeling tool; and obtaining an integrated modeling result of the entire high-speed channel by combining the result of the first modeling operation with the result of the second modeling operation.

[0012] In the method for modeling a high-speed channel in a semiconductor package, the method for designing a semiconductor package and the method for manufacturing a semiconductor package according to an example embodiment, the parameter extraction scheme using an on-chip tool, and the full-wave 3D electromagnetic scheme using an off-chip tool can be combined, merged, or integrated, so that a model for a high-speed channel in a semiconductor package can be accurately and effectively obtained. In addition, the material and structure of the connection wiring can be changed in the full-wave 3D electromagnetic scheme using an off-chip tool, so the accuracy of the model can be maintained while reducing the amount of calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figure 1 is a flowchart illustrating a method of modeling a high-speed channel in a semiconductor package according to an example embodiment of the inventive concepts.

[0015] Figure 2 is a cross-sectional view of an example of a semiconductor package implemented by a method of modeling a high-speed channel according to an example embodiment of the inventive concept.

[0016] Figure 3 is included in Figure 2 A cross-sectional view of an example of an interposer in a semiconductor package.

[0017] Figure 4 It is shown Figure 1 A flowchart of an example of performing a first modeling operation on a first layout in .

[0018] Figure 5 It is shown Figure 1 A flowchart of an example of performing a second modeling operation on a second layout.

[0019] Figure 6 It is shown Figure 5 A flowchart of an example of forming at least one integrated connection wiring.

[0020] Fig. 7A , Figure 7B , Figure 7C and Fig.7D Is used to describe Figure 6 Schematic diagram of the operation of .

[0021] Figure 8 It is shown Figure 1 Flowchart of an example of obtaining integrated modeling results for the entire highway channel.

[0022] Fig. 9 is a diagram illustrating an example of S parameters obtained by a method of modeling a high-speed channel according to an example embodiment of the inventive concept.

[0023] Fig.10 is a cross-sectional view of another example of a semiconductor package implemented by a method of modeling a high-speed channel according to example embodiments of the inventive concepts.

[0024] Fig.11 is a block diagram illustrating a modeling and design system for a semiconductor package according to an example embodiment of the inventive concept.

[0025] Fig.12 is a flowchart illustrating a method of designing a semiconductor package according to example embodiments of the inventive concepts.

[0026] Fig.13 is a flowchart illustrating a method of manufacturing a semiconductor package according to example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0027] Various example embodiments of the present invention will be more fully described with reference to the accompanying drawings in which embodiments of the present invention are shown. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments described herein. Throughout this application, the same reference numerals represent the same elements.

[0028] Figure 1 is a flow chart illustrating a method of modeling a high-speed channel in a semiconductor package according to example embodiments.

[0029] Reference Figure 1, example embodiments may be used to model a high-speed channel included in a semiconductor package. The high-speed channel may be formed or implemented by a plurality of first connection wirings on an upper surface of a semiconductor substrate included in the semiconductor package and a plurality of through electrodes penetrating the semiconductor substrate. Figure 2 , Figure 3 and Fig.10 To describe the detailed configuration of the semiconductor package and the high-speed channel.

[0030] In a method of modeling a highway channel in a semiconductor package according to an example embodiment of the inventive concept, design information of the highway channel is received (step S100 ). For example, the design information may be provided in the form of a Graphic Database System (GDS) file.

[0031] If you will refer to Fig.12 As described, when designing a semiconductor package, at least one semiconductor device included in the semiconductor package may be designed, and then a high-speed channel for semiconductor devices in the semiconductor package to communicate with each other and / or for semiconductor devices in the semiconductor package and an external circuit to communicate with each other may be designed. Afterwards, a GDS file may be received as a result of designing the high-speed channel.

[0032] The design information may be divided into a first layout including a plurality of first connection wirings and a second layout including a plurality of through electrodes (step S200). For example, the first layout may be obtained by extracting a layout of a first wiring layer including a plurality of first connection wirings on an upper surface of a semiconductor substrate from a GDS file, and the second layout may be obtained by extracting a layout of a plurality of through electrodes in a semiconductor substrate excluding the first wiring layer from the GDS file.

[0033] In some example embodiments, as will be referred to Figure 2 and Figure 3 As described, the semiconductor package may also include a plurality of second connection wirings on the lower surface of the semiconductor substrate and a plurality of solder bumps under the plurality of second connection wirings. In this example, the second layout may include a plurality of through electrodes, a plurality of second connection wirings, and a plurality of solder bumps. In other words, the second layout may be obtained by extracting a layout of a plurality of through electrodes, a plurality of second connection wirings, and a plurality of solder bumps in addition to the first wiring layer from the GDS file.

[0034] A first modeling operation may be performed on the first layout using a first modeling scheme and a first modeling tool (step S300). For example, the first modeling tool may be an on-chip tool, and the first modeling scheme may be a parameter extraction (PEX) scheme using the on-chip tool. For example, the on-chip tool may be a StarRC program from Synopsys. However, example embodiments are not limited thereto, and the on-chip tool may be one of various programs (e.g., software) for calculating resistance. Figure 4 Step S300 is described in detail.

[0035] A second modeling operation (step S400) may be performed on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout. The second modeling scheme may be different from the first modeling scheme, and the second modeling tool may be different from the first modeling tool. For example, the second modeling tool may be an off-chip tool, and the second modeling scheme may be a full-wave three-dimensional (3D) electromagnetic (EM) scheme using the off-chip tool. For example, the off-chip tool may be a high frequency electromagnetic field simulation software (HFSS) from ANSYS. However, example embodiments are not limited thereto, and the off-chip tool may be one of various programs for solving Maxwell's equations in 3D.

[0036] In some example embodiments, when a full-wave 3D electromagnetic scheme is performed using an off-chip tool in step S400, at least some of the plurality of first connection wirings included only in the first layout may be used to reduce the amount of calculation (or operation), and the material and structure (e.g., shape) of at least some of the plurality of first connection wirings may also be changed. Figure 5 and Figure 6 Step S400 is described in detail.

[0037] although Figure 1 It is shown that step S300 and step S400 are performed substantially simultaneously or concurrently, but example embodiments are not limited thereto, and one of step S300 and step S400 may be performed first, and the other of step S300 and step S400 may be performed subsequently.

[0038] The integrated modeling result of the entire highway channel is obtained by combining the result of the first modeling operation and the result of the second modeling operation (step S500). Figure 8 Step S500 is described in detail.

[0039] In the method for modeling a high-speed channel in a semiconductor package according to an example embodiment, a parameter extraction scheme using an on-chip tool and a full-wave 3D electromagnetic scheme using an off-chip tool can be combined, merged or integrated, so that a model for a high-speed channel in a semiconductor package can be accurately and efficiently obtained. In addition, the material and structure of the connection wiring can be changed in the full-wave 3D electromagnetic scheme using an off-chip tool, so the accuracy of the model can be maintained while reducing the amount of calculation. By improving the accuracy of the model, the performance of the manufactured semiconductor package can be improved. In addition, by reducing the amount of calculation, the computing resources required for designing and / or manufacturing a semiconductor package can be reduced. Therefore, the embodiments of the inventive concept described herein provide technical improvements to technical equipment for designing and / or manufacturing semiconductor packages and semiconductor packages designed and / or manufactured using the embodiments of the inventive concept described herein.

[0040] Figure 2 is a cross-sectional view of an example of a semiconductor package implemented by a method of modeling a high-speed channel according to example embodiments.

[0041] Reference Figure 2 , the semiconductor package 100 may include a package substrate 101 , a first semiconductor device ( SD1 ) 110 , a second semiconductor device ( SD2 ) 120 , and an interposer 130 . The semiconductor package 100 may further include a sealing member 140 .

[0042] The semiconductor package 100 may be a memory package having a stacked chip structure in which a plurality of bare dies (or chips) are stacked. For example, the semiconductor package 100 may be implemented in a 2.5D structure and may include a semiconductor device and a memory device having a 2.5D chip structure. For example, the first semiconductor device 110 may include a logic semiconductor device, and the second semiconductor device 120 may include a memory device. For example, the logic semiconductor device may operate as a host and may include a central processing unit (CPU), a GPU, a system on chip (SoC), an application specific integrated circuit (ASIC), etc. For example, the memory device may include a high bandwidth memory (HBM) device.

[0043] The package substrate 101 may have an upper surface and a lower surface opposite to each other. For example, the package substrate 101 may be a printed circuit board (PCB). The PCB may be a multi-layer circuit board including vias and various circuits therein.

[0044] The plug-in 130 may be disposed on the package substrate 101. The plug-in 130 may be mounted on the package substrate 101 by means of solder bumps 135. For example, the solder bumps 135 may be C4 bumps. For example, the planar area of ​​the plug-in 130 may be smaller than the planar area of ​​the package substrate 101. In other words, the plug-in 130 may be disposed within the region of the package substrate 101 in a plan view.

[0045] The plug 130 may include a plurality of connection wirings 131 and a plurality of through electrodes 133 therein. For example, the plug 130 may be a silicon plug including a silicon substrate as a semiconductor substrate, and the plurality of through electrodes 133 may be through silicon vias (TSVs) penetrating the silicon substrate. The semiconductor substrate (e.g., silicon substrate), the plurality of connection wirings 131, and the plurality of through electrodes (e.g., TSVs) 133 may be respectively connected to the reference numerals 134 and 135. Figure 1 The description corresponds to a semiconductor substrate, a plurality of first connection wirings, and a plurality of through electrodes included in a semiconductor package.

[0046] The first semiconductor device 110 and the second semiconductor device 120 may be connected to each other through a plurality of connection wirings 131 and / or may be electrically connected to the package substrate 101 through a plurality of through electrodes (e.g., TSVs) 133 and solder bumps (e.g., C4 bumps) 135. The plug-in 130 (e.g., a silicon plug-in) may provide high-density interconnection between the first semiconductor device 110 and the second semiconductor device 120.

[0047] The first semiconductor device 110 and the second semiconductor device 120 may be disposed on the interposer 130. The first semiconductor device 110 and the second semiconductor device 120 may be mounted on the interposer 130 by a flip chip bonding scheme. For example, the first semiconductor device 110 and the second semiconductor device 120 may be mounted on the interposer 130 such that active surfaces of the first semiconductor device 110 and the second semiconductor device 120 on which chip pads are disposed face the interposer 130. The chip pads of the first semiconductor device 110 and the second semiconductor device 120 may be electrically connected to connection pads of the interposer 130 by solder bumps 137 as conductive bumps. For example, the solder bumps 137 may be uBumps.

[0048] although Figure 2 The semiconductor package 100 is shown to include a first semiconductor device 110 and a second semiconductor device 120, but example embodiments are not limited thereto. For example, the second semiconductor device 120 may include a buffer die and a plurality of memory dies (or chips) stacked on the buffer die. The buffer die and the plurality of memory dies may be electrically connected to each other through TSVs.

[0049] The first semiconductor device 110 , the second semiconductor device 120 , and the interposer 130 may be fixed by a sealing member 140 .

[0050] In some example embodiments, although Figure 2 Although not shown in the drawings, the semiconductor package 100 may further include a first adhesive underfilled between the interposer 130 and the package substrate 101, a second adhesive underfilled between the first semiconductor device 110 and the interposer 130, and / or a third adhesive underfilled between the second semiconductor device 120 and the interposer 130. For example, the first adhesive, the second adhesive, and the third adhesive may include an epoxy material to enhance a gap between the interposer 130 and the package substrate 101 and / or a gap between the interposer 130 and each of the first semiconductor device 110 and the second semiconductor device 120.

[0051] External connection pads may be provided on the lower surface of the package substrate 101, and external connectors 103 for electrical connection to an external device may be provided on the external connection pads. For example, the external connectors 103 may be solder balls (e.g., ball grid array (BGA)). The semiconductor package 100 may be mounted on the module substrate 10 through the external connectors 103, thereby constituting a memory module.

[0052] In addition to the semiconductor package 100, a power management integrated circuit (PMIC) 200, a serializer and deserializer (SERDES) interface circuit 300, etc. may be additionally mounted on the module substrate 10. The PMIC 200 may manage and / or control power supplied to the semiconductor package 100. The SERDES interface circuit 300 may perform serial communication with the semiconductor package 100.

[0053] The first semiconductor device 110 may include an interface (IF) 111 for communicating with the outside of the semiconductor package 100. For example, the interface 111 may include at least one of various serial interfaces. The first high-speed path HP1 for communicating with the PMIC 200 and / or the SERDES docking circuit 300 outside the semiconductor package 100 may be formed or implemented by the interface 111, the through-electrodes 133 (e.g., TSV) in the plug-in 130, the solder bumps 135 (e.g., C4 bumps), and the connection wiring in the package substrate 101 and the module substrate 10. For example, the first high-speed path HP1 may be referred to as a high-speed serial input / output (I / O) path.

[0054] The first semiconductor device 110 may include an interface 113 for communicating with the second semiconductor device 120, and the second semiconductor device 120 may include an interface 121 for communicating with the first semiconductor device 110. For example, each of the interfaces 113 and 121 may include an HBM PHY unit for a memory interface. The second high-speed path HP2 may be formed or implemented in the semiconductor package 100 through the interfaces 113 and 121 and the connection wiring 131 in the plug-in 130. For example, the second high-speed path HP2 may be referred to as a high-speed memory I / O path.

[0055] The first high-speed path HP1 (eg, a high-speed serial I / O path) and the second high-speed path HP2 (eg, a high-speed memory I / O path) described above may form a high-speed channel of the semiconductor package 100 .

[0056] When Figure 2 When the semiconductor package 100 is implemented in a 2.5D structure as shown in FIG, a high-speed channel including a first high-speed path HP1 and a second high-speed path HP2 can be formed by the plug-in 130. Figure 2 The method of modeling a high-speed channel of the semiconductor package 100 may be described as a method of modeling an interposer.

[0057] Figure 3 is included in Figure 2 FIG. 1 is a cross-sectional view of an example of an interposer 130 in a semiconductor package.

[0058] Reference Figure 2 and Figure 3 , the interposer 130 may include a semiconductor substrate 410 and a first wiring layer on an upper surface of the semiconductor substrate 410. The interposer 130 may further include a second wiring layer on a lower surface of the semiconductor substrate 410 and solder bumps BMB under the second wiring layer.

[0059] Typically, when manufacturing or fabricating the interposer 130, a configuration associated with or related to the semiconductor substrate 410 may be first manufactured at the front end of the process, and then a configuration associated with or related to the first wiring layer may be subsequently manufactured at the back end of the process. Therefore, the structure including the semiconductor substrate 410 may be referred to as the front end of the line (FEOL) portion, and the structure including the first wiring layer may be referred to as the back end of the line (BEOL) portion.

[0060] The first wiring layer may include a plurality of connection wirings LR, Mi1, Mi2, Mi3, and Mi4 and a plurality of vias IV, Vi1, Vi2, and / or Vi3 for connecting the plurality of connection wirings LR, Mi1, Mi2, Mi3, and / or Mi4 to each other. Figure 2 Corresponding to the multiple connection wirings 131 in.

[0061] The first wiring layer may further include insulating layers 440a and 440b for electrical insulation between the plurality of connection wirings LR, Mi1, Mi2, Mi3, and Mi4. An opening FMO for exposing the connection wiring LR may be formed on the uppermost portion of the first wiring layer. Figure 3 Not shown, but Figure 2 A solder bump 137 (eg, uBump) may be formed on the opening FMO.

[0062] In some example embodiments, the connection wiring LR and the via IV may include a first metal (e.g., aluminum (Al)), and the connection wirings Mi1, Mi2, Mi3, and Mi4 and the vias Vi1, Vi2, and Vi3 may include a second metal (e.g., copper (Cu)) different from the first metal. The connection wirings LR, Mi1, Mi2, Mi3, and Mi4 may be formed on the upper surface of the semiconductor substrate 410 and may therefore be referred to as a front metal.

[0063] The semiconductor substrate 410 may include a plurality of through electrodes (eg, TSVs) 420 penetrating therethrough. For example, the semiconductor substrate 410 may be a silicon substrate. The plurality of through electrodes 420 may be connected to Figure 2 Corresponding to the multiple through electrodes 133 in.

[0064] An insulating layer 430 for electrical insulation may be formed between the semiconductor substrate 410 and the first wiring layer and between the semiconductor substrate 410 and the plurality of through electrodes 420. For example, the insulating layer 430 may include silicon oxide (eg, SiO 2 ).

[0065] The second wiring layer may include a first passivation layer 450a, a connection wiring BM1, and a second passivation layer 450b sequentially formed on the lower surface of the semiconductor substrate 410. For example, the first passivation layer 450a and the second passivation layer 450b may include an insulating material. The connection wiring BM1 may be formed on the lower surface of the semiconductor substrate 410, and thus may be referred to as a post-metal. An opening BMO for exposing the connection wiring BM1 and forming a solder bump BMB may be formed under the second passivation layer 450b. The solder bump BMB may be connected to the substrate 410. Figure 2 The solder bump 135 (eg, C4 bump) corresponds to .

[0066] In order to model the high-speed channel in the semiconductor package 100 to have a desired and / or expected signal characteristic (e.g., signal strength), the characteristics of the connection wirings Mi1, Mi2, Mi3, and Mi4 included in the first wiring layer (e.g., BEOL section) may be modeled, and the characteristics of the through-electrodes (e.g., TSVs) 420 in the semiconductor substrate 410 and the connection wirings BM1 and solder bumps BMB under the semiconductor substrate 410 may also be modeled. However, as will be described with reference to Fig. 7A As described, the size (or area) of the through-electrode 420 is much larger than the size (or area) of other components, so it may be difficult to model all of the above-mentioned components at once using conventional modeling schemes. In addition, since conventional modeling methods may regard or consider the semiconductor substrate 410 around the through-electrode 420 as a ground node, conventional modeling methods may not be able to extract the coupling between the through-electrodes 420 passing through (via) the semiconductor substrate 410. The coupling between the through-electrodes 420 through the semiconductor substrate 410 can dominate the accuracy of the model in the GHz frequency range. The coupling between the through-electrodes 420 through the semiconductor substrate 410 may be important for most high-speed signals that propagate at several gigabits per second (Gbps) and at the corresponding Nyquist frequency in the GHz region, so this coupling must be considered to model the high-speed channel. In the method of modeling a high-speed channel in a semiconductor package 100 according to an example embodiment, a parameter extraction scheme using an on-chip tool and a full-wave 3D electromagnetic scheme using an off-chip tool may be combined, merged and / or integrated, so that the high-speed channel in the semiconductor package 100 may be accurately and efficiently modeled.

[0067] Figure 4 It is shown Figure 1 A flowchart of an example of performing a first modeling operation on a first layout in .

[0068] Reference Figure 1 , Figure 3 and Figure 4 When the first modeling operation is performed on the first layout (step S300), the material of the plurality of first connection wirings may be set to the first material (step S310). Figure 3 The material of all the connection wirings Mi1, Mi2, Mi3, and Mi4 in the first wiring layer (eg, BEOL section) is set to the first material. For example, the first material may be copper. The material condition may be uniquely and distinctively set through step S310.

[0069] An angle-aware parameter extraction process (step S320) can be performed based on a plurality of first connection wirings set as a first material and a structure of the plurality of first connection wirings, and the resistance of the plurality of first connection wirings (e.g., the resistance of the first wiring layer) as a result of the angle-aware parameter extraction process can be obtained (step S330). For example, the angle-aware process, scheme, or process can indicate that a specific predetermined condition is set to be associated with the characteristics of the connection wirings Mi1, Mi2, Mi3, and Mi4. An angle-aware model for the first wiring layer (e.g., BEOL section) can be generated by step S320. For example, the resistance obtained by step S330 can be obtained in the form of a schematic circuit diagram (e.g., a subcircuit in a simulation program with integrated circuit emphasis (SPICE) type and / or format).

[0070] A first S parameter (for example, an S parameter for a first wiring layer) for the plurality of first connection wirings may be obtained based on the resistance obtained in step S330 (step S340). An S parameter is one of various parameters representing channel characteristics, and will be referred to as Fig. 9 Give a description.

[0071] In some example embodiments, the first S parameter may be obtained by converting the resistance obtained by step S330 using an additional tool different from the first modeling tool and the second modeling tool. As described above, the on-chip tool may not directly output the S parameter, but may output the resistance in the form of a schematic circuit diagram. Therefore, the resistance obtained by step S330 may be converted to obtain the first S parameter by using an additional tool different from the on-chip tool (e.g., a circuit simulation tool).

[0072] The parameter extraction scheme using the on-chip tool can effectively generate an angle-aware model for the first wiring layer (e.g., BEOL section). However, since the angle-aware parameter extraction process regards the semiconductor substrate 410 around the through-electrode (e.g., TSV) 420 as a ground node (e.g., since the angle-aware parameter extraction process cannot process the semiconductor substrate 410), the coupling between the through-electrodes 420 passing through the semiconductor substrate 410 may not be extracted, the capacitance appearing in the insulating layer 430 between the connecting wiring Mi1 and the semiconductor substrate 410 may not be considered or the capacitance appearing in the insulating layer 430 between the connecting wiring Mi1 and the semiconductor substrate 410 may not be available, and therefore, the characteristics of the through-electrode 420 may not be accurately determined, detected, or identified. Therefore, as will be referred to in Figure 5 As described, the through-electrode (eg, TSV) 420 may be modeled using a different scheme other than the parameter extraction scheme.

[0073] Figure 5 It is shown Figure 1A flowchart of an example of performing a second modeling operation on a second layout.

[0074] Reference Figure 1 , Figure 3 and Figure 5 When performing the second modeling operation on the second layout (step S400), some (e.g., a subset) of the plurality of first connection wirings may be used to form at least one integrated connection wiring (step S410). For example, the material and structure (e.g., shape) of at least some of the plurality of first connection wirings may be changed to obtain at least one integrated connection wiring.

[0075] Figure 6 It is shown Figure 5 A flowchart of an example of forming at least one integrated connection wiring. Fig. 7A , Figure 7B , Figure 7C and Fig.7D Is used to describe Figure 6 For ease of explanation, Fig. 7A , Figure 7B , Figure 7C and Fig.7D Only the connection wiring and the through-electrodes (eg, TSVs) are shown.

[0076] Reference Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Figure 7C and Fig.7D When at least one integrated connection wiring is formed (step S410), a connection wiring closest to the plurality of through electrodes may be selected from among and / or from the plurality of first connection wirings (step S412). Figure 3 Among the connection wirings Mi1, Mi2, Mi3, and Mi4 in the first wiring layer (for example, BEOL portion), the connection wiring Mi1 closest to the through-electrode 420 (for example, TSV) may be selected.

[0077] The material of the selected connection wiring may be set to a second material different from the first material (step S414). For example, the second material may be a perfect conductor (PEC) having approximately zero resistance. As in step S310, the material condition may be uniquely and distinctively set by step S414. Specifically, repeated extraction of the resistance of the connection wiring Mi1 may be avoided by setting the material of the connection wiring Mi1 to a material having approximately zero resistance.

[0078] At least one integrated connection wiring may be obtained by filling at least a portion of the empty areas between the selected connection wirings with the second material (e.g., replacing at least a portion of the empty areas in the layout with the second material) and / or by combining or merging at least some of the selected connection wirings (step S416). Figure 7B , Figure 7C and Fig.7D As shown in , the at least one integrated connecting wire can be a solid, unified or combined connecting wire.

[0079] For example, Fig. 7A As shown in FIG. 1 , when the plug 130 actually implemented or manufactured is viewed in a top view or a plan view, the size (e.g., diameter) of each of the through electrodes 420 (e.g., TSV) may be much larger than the size (e.g., width) of each of the connection wirings M1, and one through electrode 420 may overlap with several connection wirings M1. In other words, one through electrode 420 may overlap with two or more selected connection wirings. In some embodiments, the connection wirings M1 may overlap with the through electrodes 420. Figure 3 Corresponding to the connection wiring Mi1.

[0080] like Figure 7B , Figure 7C and Fig.7D As shown in Fig. 7A At least a portion of the empty area between the connection wirings M1 in the Fig. 7A at least some of the connection wirings M1 in the connection wirings M1) to form integrated connection wirings M1a, M1b and / or M1c from some of the connection wirings M1.

[0081] In some example embodiments, Figure 7B As shown in FIG. 4 , at least one integrated connection wiring may be formed or implemented such that one through-electrode 420 overlaps with one integrated connection wiring M1 a .

[0082] In other example embodiments, Figure 7C and Fig.7D As shown in , at least one integrated connection wiring may be formed or implemented such that two or more of the plurality of through electrodes 420 overlap with one integrated connection wiring M1b or M1c. Figure 7C In the example of , two through electrodes 420 may overlap with one integrated connection wiring M1b. Fig.7D In the example of FIG. 4 , more than two and / or all (eg, four) through electrodes 420 may overlap with one integrated connection wiring M1 c .

[0083] As reference Figure 7B , Figure 7C and Fig.7DAs described, when a solid plane along the outline of the mesh grid pattern in the connection wiring M1 is used instead of the actual mesh grid pattern in the connection wiring M1, the amount of calculation can be reduced with almost no error compared to the case where all the connection wirings Mi1, Mi2, Mi3, and Mi4 are used. Therefore, subsequent calculations or operations can be performed by considering only the integrated connection wiring M1a, M1b, or M1c instead of considering all the connection wirings Mi1, Mi2, Mi3, and Mi4.

[0084] Refer again Figure 1 , Figure 3 and Figure 5 , a coupled sensing full-wave 3D electromagnetic process (step S420) can be performed based on the structure of at least one integrated connection wiring (e.g., M1a, M1b and / or M1c) and multiple through-electrodes set as the second material, and the resistance, inductance, capacitance and conductance of at least one integrated connection wiring (e.g., M1a, M1b and / or M1c) and multiple through-electrodes (e.g., TSV) can be obtained as a result of the coupled sensing full-wave 3D electromagnetic process (step S430). For example, the through-electrode can be a TSV, and therefore, the coupled sensing full-wave 3D electromagnetic process can be a process based on TSV coupled sensing full-wave 3D electromagnetic. As described above, the TSV sensing process can be performed by considering only the integrated connection wirings M1a, M1b and / or M1c instead of all the connection wirings Mi1, Mi2, Mi3 and Mi4.

[0085] Second S parameters for the plurality of through-electrodes may be obtained based on the resistance, inductance, capacitance, and conductance obtained through step S430 (step S440 ).

[0086] In some example embodiments, the second S parameters may be obtained directly from the second modeling tool without using an additional tool. In other words, the second S parameters may be obtained directly from the 3D simulation performed by the off-chip tool without any additional tools.

[0087] In some example embodiments, as shown in FIG. Figure 3As described, the second layout may also include a plurality of second connection wirings (e.g., connection wiring BM1) on the lower surface of the semiconductor substrate and a plurality of solder bumps (e.g., solder bumps BMB) below the plurality of second connection wirings. In this example, the coupled sensing full-wave 3D electromagnetic process may be performed in step S420 by applying the structures of the plurality of second connection wirings and the plurality of solder bumps together (e.g., combining and analyzing the structures of the plurality of second connection wirings and the plurality of solder bumps together). In this way, the resistance, inductance, capacitance, and conductance obtained by step S430 may be the resistance, inductance, capacitance, and conductance of at least one integrated connection wiring, a plurality of through electrodes, a plurality of second connection wirings, and a plurality of solder bumps, and the second S parameters obtained by step S440 may be S parameters for a plurality of through electrodes, a plurality of second connection wirings, and a plurality of solder bumps.

[0088] A full-wave 3D EM approach using off-chip tools may avoid and / or reduce problems caused by parameter extraction approaches using on-chip tools, and may achieve very high accuracy for coupling associated with through-electrodes 420 (e.g., TSVs). However, in a full-wave 3D EM approach, angle-aware parameter extraction may not be possible, modeling of the first wiring layer (e.g., BEOL section) may be difficult, and the time and memory requirements for processing the first wiring layer may be very large, and thus the turnaround time (TAT) may not be met.

[0089] In the method for modeling a high-speed channel in a semiconductor package according to an example embodiment, a parameter extraction scheme using an on-chip tool and a full-wave 3D electromagnetic scheme using an off-chip tool can be combined, merged or integrated. Angle-aware parameter extraction can be effectively performed on the BEOL part based on the parameter extraction scheme, and coupling-aware parameter extraction can be effectively performed on the TSV based on the full-wave 3D electromagnetic scheme, so the model of the high-speed channel in the semiconductor package can be accurately and effectively obtained by combining the two modeling results. In addition, the material and structure of the connection wiring can be changed in the full-wave 3D electromagnetic scheme using the off-chip tool, so the accuracy of the model can be maintained while reducing the amount of calculation.

[0090] Figure 8 It is shown Figure 1 Flowchart of an example of obtaining integrated modeling results for the entire highway channel.

[0091] Reference Figure 1 and Figure 8 When the integrated modeling result of the entire high-speed channel is obtained (step S500), the first S parameter (e.g., from Figure 4 Step S340 of FIG. 1 and a second S parameter (eg, from Figure 5The integrated S parameters can represent the S parameters for the entire high-speed channel.

[0092] Fig. 9 is a diagram illustrating an example of S parameters obtained by a method of modeling a high-speed channel according to an example embodiment of the inventive concept.

[0093] Reference Fig. 9 , the S parameter S can be represented by an n*m matrix, which includes the elements S 11 , S 12 ,……,S 1m , S 21 , S 22 ,……,S 2m ,……,S n1 , S n2 ,……,S nm , where each of n and m is a natural number greater than or equal to two. 11 、V 12 ,……,V 1m The channel input V1 is multiplied by the S parameter S to obtain the element V 21 、V 22 ,……,V 2n The channel output V2. Therefore, the S parameter S can represent the channel characteristics.

[0094] Fig.10 is a cross-sectional view of another example of a semiconductor package implemented by a method for modeling a high-speed channel according to an example embodiment of the inventive concept. Figure 2 The components are the same or similar to the description of the components.

[0095] Reference Fig.10 , the semiconductor package 500 includes a package substrate 501 , a first semiconductor device 510 , and a second semiconductor device 520 . The semiconductor package 500 may further include a sealing member 540 .

[0096] In addition to omitting Figure 2 In addition to plugin 130, Fig.10 The semiconductor package 500 may be Figure 2 Similar to the semiconductor package 100 , the first semiconductor device 510 and the second semiconductor device 520 may be stacked in a vertical direction, and through electrodes and connection wirings may be included in the first semiconductor device 510 and the second semiconductor device 520 instead of being included in an interposer.

[0097] The semiconductor package 500 may be a memory package having a stacked chip structure in which a plurality of bare dies (or chips) are stacked. For example, the semiconductor package 500 may be implemented in a 3D structure and may include a semiconductor device and a memory device having a 3D chip structure. For example, the first semiconductor device 510 may include a logic semiconductor device, and the second semiconductor device 520 may include a memory device.

[0098] The package substrate 501, the external connector 503 and the sealing member 540 may be substantially respectively Figure 2 The package substrate 101, the external connector 103 and the sealing member 140 are the same.

[0099] The first semiconductor device 510 may be disposed on the package substrate 501. The first semiconductor device 510 may be mounted on the package substrate 501 by a flip chip bonding scheme. For example, the first semiconductor device 510 may be mounted on the package substrate 501 such that an active surface of the first semiconductor device 510 on which a chip pad is disposed faces the package substrate 501. The chip pad of the first semiconductor device 510 may be electrically connected to a connection pad of the package substrate 501 by a solder bump (e.g., uBump) 537 as a conductive bump.

[0100] The first semiconductor device 510 may include a semiconductor substrate 512 and a wiring layer 514. The semiconductor substrate 512 may include a circuit structure (not shown) such as a transistor, and may include a plurality of through electrodes (e.g., TSVs) 533 penetrating therethrough. Although not shown in detail, the wiring layer 514 may include a plurality of connection wirings 531 and a plurality of vias.

[0101] The second semiconductor device 520 may be disposed on the first semiconductor device 510. The second semiconductor device 520 may be mounted on the first semiconductor device 510 through a flip chip bonding scheme. For example, the second semiconductor device 520 may be mounted on the first semiconductor device 510 such that an active surface of the second semiconductor device 520 on which a chip pad is disposed faces the first semiconductor device 510. The chip pad of the second semiconductor device 520 may be electrically connected to a plurality of through electrodes (e.g., TSVs) 533 of the first semiconductor device 510 through solder bumps (e.g., C4 bumps) 535 as conductive bumps.

[0102] The second semiconductor device 520 may include a semiconductor substrate 522 and a wiring layer 524. The semiconductor substrate 522 may include a circuit structure (not shown) such as a transistor. Although not shown in detail, the wiring layer 524 may include a plurality of connection wirings 532 and a plurality of vias.

[0103] although Fig.10The semiconductor package 500 is shown to include one first semiconductor device 510 and one second semiconductor device 520, but example embodiments are not limited thereto. For example, at least one other second semiconductor device may be stacked on the second semiconductor device 520. In some embodiments, like the first semiconductor device 510, the semiconductor substrate 522 of the second semiconductor device 520 may include a through electrode.

[0104] exist Fig.10 In the semiconductor package 500 of FIG. 1 , the through-electrodes 533 and the solder bumps 535 may be respectively connected to the semiconductor package 500 of FIG. 1 . Figure 2 The through electrodes 133 and the solder bumps 135 in the plug 130 correspond to each other, and the connecting wirings 531 and 532 in the wiring layers 514 and 524 may correspond to those included in the Figure 2 The connection wiring 131 in the plug-in 130 corresponds to the connection wiring 131 in the plug-in 130. Therefore, the method for modeling a high-speed channel according to the example embodiment can be performed to accurately and effectively obtain Fig.10 A model of a high-speed channel in a semiconductor package 500 .

[0105] Fig.11 is a block diagram illustrating a modeling and design system for a semiconductor package according to example embodiments.

[0106] Reference Fig.11 , a modeling and design system 1000 for a semiconductor package includes a processor 1100 , a storage device 1200 , a modeling and design module 1300 , and an analyzer (or analysis module) 1400 .

[0107] As used herein, the term "module" may indicate, but is not limited to, software and / or hardware components, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) that performs a specific task. A module may be configured to reside in a tangible addressable storage medium, and may be configured to execute on one or more processors. For example, a "module" may include components such as software components, object-oriented software components, class components, and task components, as well as procedures, functions, routines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. A "module" may be divided into multiple "modules" that perform detailed functions.

[0108] The processor 1100 may be used when the modeling and design module 1300 and / or the analyzer 1400 perform calculations. For example, the processor 1100 may include a microprocessor, an application processor (AP), a digital signal processor (DSP), a GPU, etc. Fig.11In the embodiment, only one processor 1100 is shown, but example embodiments are not limited thereto. For example, a plurality of processors may be included in the modeling and designing system 1000. In addition, the processor 1100 may include a cache memory to improve computing power.

[0109] The storage device 1200 may include a first database (DB1) 1210 for a first modeling tool (TOOL1) 1310 and a second database (DB2) 1220 for a second modeling tool (TOOL2) 1320, and may also include design rules (DR) 1230. The first database 1210, the second database 1220, and the design rules 1230 may be provided from the storage device 1200 to the modeling and design module 1300 and / or the analyzer 1400. The design rules 1230 may provide a set of criteria for constructing various masks required when manufacturing integrated circuits. For example, the design rules 1230 may include minimum width and minimum spacing requirements between cells on the same layer and / or between cells on different layers. In addition, the design rules 1230 may include a minimum line width for wiring.

[0110] In some example embodiments, the storage device or storage medium 1200 may include any non-transitory computer-readable storage medium for providing commands and / or data to a computer. For example, the non-transitory computer-readable storage medium 1200 may include volatile memory (such as random access memory (RAM), read-only memory (ROM), etc.) and / or non-volatile memory (such as flash memory, magnetoresistive RAM (MRAM), phase change RAM (PRAM), resistive RAM (RRAM), etc.). The non-transitory computer-readable storage medium 1200 may be inserted into a computer, may be integrated into a computer, or may be coupled to a computer via a communication medium (such as a network and / or a wireless link).

[0111] The modeling and design module 1300 may include a first modeling tool 1310 and a second modeling tool 1320. Figure 1 Step S300 in Figure 4 As described in steps S310 to S340 in FIG. 1 , the first modeling tool 1310 may use a first modeling scheme to perform a first modeling operation on the BEOL portion. Figure 1 Step S400, Figure 5 Steps S410 to S440 and Figure 6 As described in steps S412 to S416 in FIG. 1 , the second modeling tool 1320 may perform a second modeling operation on the TSV, lower wiring, and solder bump instead of the BEOL portion using a second modeling scheme.

[0112] The analyzer 1400 may analyze and verify the results of the modeling operation performed by the modeling and design module 1300. When it is determined based on the results of the analysis that the channel characteristics satisfy the predetermined signal characteristics, the modeling and design module 1300 may output data and / or signals indicating that the modeling operation is successful. When it is determined based on the results of the analysis that the channel characteristics do not satisfy the predetermined signal characteristics, the channel structure may be changed by modifying or adjusting the channel design and / or chip design, and the analysis and verification may be performed again.

[0113] The modeling and design module 1300 and / or the analyzer 1400 may be implemented in software, but example embodiments are not limited thereto. When both the modeling and design module 1300 and the analyzer 1400 are implemented in software, the modeling and design module 1300 and the analyzer 1400 may be stored in the storage device 1200 in the form of code, or may be stored in another storage device (not shown) separated from the storage device 1200 in the form of code.

[0114] Fig.12 is a flowchart illustrating a method of designing a semiconductor package according to example embodiments of the inventive concepts.

[0115] Reference Fig.12 In the method of designing a semiconductor package according to an example embodiment, at least one semiconductor device included in the semiconductor package is designed (step S1100), and a high-speed channel included in the semiconductor package is designed (step S1200). For example, reference Figure 2 and Fig.10 The first semiconductor device and the second semiconductor device (eg, a logic semiconductor device and a memory device) described above can then be designed with reference to Figure 2 and Fig.10 A first high-speed path and a second high-speed path (eg, a high-speed serial I / O path and a high-speed memory I / O path) are described.

[0116] In some example embodiments, when a semiconductor package has a Figure 2 When the semiconductor package 100 has a 2.5D structure, step S1100 may be first performed to design a semiconductor device, and then step S1200 may be subsequently performed to design an insert for implementing a high-speed channel. In other example embodiments, when the semiconductor package has a 2.5D structure such as Fig.10 When designing a 3D structure of the semiconductor package 500 , step S1100 and step S1200 may be performed substantially simultaneously or concurrently to design the semiconductor device and the high-speed channel simultaneously or at one time.

[0117] The designed high-speed channel can be modeled (step S1300), and the modeling result of the high-speed channel can be analyzed and verified (step S1400). Figures 1 to 10 The method of modeling a highway channel according to the example embodiment is described to perform the modeling operation in step S1300 .

[0118] When the operation of analyzing and verifying the modeling result of the highway channel is successful (step S1400 : Yes) (eg, when it is determined based on the analysis result that the characteristics of the highway channel satisfy the predetermined signal characteristics), the operation of designing the semiconductor package may be completed.

[0119] When the operation of analyzing and verifying the modeling result of the high-speed channel fails (step S1400: No) (for example, when it is determined based on the result of the analysis that the characteristics of the high-speed channel do not satisfy the predetermined signal characteristics), the design of the semiconductor package may be changed (step S1500), and steps S1300 and S1400 may be performed again based on the result of the changed design. In some example embodiments, the operation of changing the design in step S1500 may include only the operation of changing the design of the semiconductor device similar to step S1100, or may include only the operation of changing the design of the high-speed channel similar to step S1200, or may include both the operation of changing the design of the semiconductor device and the operation of changing the design of the high-speed channel.

[0120] In some example embodiments, when the design of the semiconductor package is changed, the design conditions for the semiconductor device and / or the high-speed channel may be changed. For example, the semiconductor device and / or the high-speed channel may be redesigned to change the circuit configuration, layout, and / or another characteristic. In other example embodiments, when the design of the semiconductor package is changed, the process or process conditions for manufacturing the semiconductor device and / or the high-speed channel may be changed. For example, the process equipment, the process sequence, various parameters in the process, etc. may be adjusted. In yet another example embodiment, when the design of the semiconductor package is changed, the product specifications for the semiconductor device and / or the high-speed channel may be changed. According to example embodiments, at least two of the design conditions, process conditions, and product specifications may be changed simultaneously or concurrently.

[0121] Fig.13 is a flowchart illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0122] Reference Fig.13 In a method for manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept, a semiconductor package including at least one semiconductor device and a high-speed channel is designed (step S2100), and a semiconductor package is manufactured based on a result of designing the semiconductor package (step S2200). Fig.12 The method of designing a semiconductor package according to example embodiments is described to perform the design operation in step S2100 .

[0123] As will be appreciated by those skilled in the art, the inventive concept may be embodied as a system, method, computer program product, and / or a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon. The computer-readable program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be any tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or apparatus. For example, a computer-readable medium may be a non-transitory computer-readable medium.

[0124] The present invention can be applied to various devices and / or systems including semiconductor packages. For example, the present invention can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, portable cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0125] The foregoing is an illustration of example embodiments and is not to be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications can be made to the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Therefore, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Therefore, it will be understood that the foregoing is an illustration of various example embodiments and is not to be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A method for modeling a high-speed channel in a semiconductor package, wherein the high-speed channel includes a plurality of first connection wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate, the method comprising: Receiving design information of the high-speed channel; dividing the design information into a first layout including the plurality of first connection wirings and a second layout including the plurality of through-electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout, wherein the second modeling scheme is different from the first modeling scheme, and wherein the second modeling tool is different from the first modeling tool; and An integrated modeling result of the entire highway channel is obtained by combining the result of the first modeling operation and the result of the second modeling operation.

2. The method according to claim 1, wherein: Performing the first modeling operation on the first layout includes: Setting the material of the plurality of first connecting wirings to a first material; performing an angle-aware parameter extraction process based on the plurality of first connection wirings set to the first material and the structure of the plurality of first connection wirings; obtaining a first resistance as a result of said angle-aware parameter extraction procedure; and A first S parameter for the plurality of first connection wirings is obtained based on the first resistance.

3. The method according to claim 2, wherein: The first modeling tool is an on-chip tool, and Wherein, the first modeling scheme is a parameter extraction scheme using the on-chip tool.

4. The method according to claim 2, wherein: The first material is copper.

5. The method according to claim 2, wherein: The first S parameter is obtained by converting the first resistance using an additional tool different from the first modeling tool and the second modeling tool.

6. The method according to claim 2, wherein: Performing the second modeling operation on the second layout includes: using some of the plurality of first connecting wirings to form at least one integrated connecting wiring; Performing a coupled sensing full-wave three-dimensional electromagnetic process based on the structure of the at least one integrated connection wiring and the plurality of through-electrodes; obtaining a second resistance, a first inductance, a first capacitance, and a first conductance as a result of the coupled sensing full-wave three-dimensional electromagnetic process; and A second S parameter for the plurality of through-electrodes is obtained based on the second resistance, the first inductance, the first capacitance, and the first conductance.

7. The method according to claim 6, wherein: The second layout further includes a plurality of second connection wirings on the lower surface of the semiconductor substrate and a plurality of solder bumps below the plurality of second connection wirings, wherein the coupled sensing full-wave three-dimensional electromagnetic process is performed by applying the plurality of second connecting wirings and the plurality of solder bump structures together, and The second S parameters represent S parameters for the plurality of through electrodes, the plurality of second connection wirings, and the plurality of solder bumps.

8. The method according to claim 6, wherein: Forming the at least one integrated connection wiring comprises: selecting a subset of the plurality of first connection wirings that is closest to the plurality of through-electrodes; setting a material of the subset of the plurality of first connecting wirings to a second material different from the first material; and The at least one integrated connecting wire is obtained by filling at least a part of empty areas between individual first connecting wires of the subset of the plurality of first connecting wires with the second material.

9. The method according to claim 8, wherein: In a plan view, a first through-electrode among the plurality of through-electrodes overlaps with two or more first connection wirings among the subset of the plurality of first connection wirings, and The at least one integrated connection wiring is formed such that the first through-electrode overlaps with the at least one integrated connection wiring.

10. The method according to claim 8, wherein: In a plan view, a first through-electrode among the plurality of through-electrodes overlaps with two or more first connection wirings among the subset of the plurality of first connection wirings, and The at least one integrated connection wiring is formed such that the first through-electrode and the second through-electrode among the plurality of through-electrodes overlap with the at least one integrated connection wiring.

11. The method according to claim 8, wherein: The second material is a perfect conductor with zero electrical resistance.

12. The method according to claim 6, wherein: The second modeling tool is an off-chip tool, and Wherein, the second modeling scheme is a full-wave three-dimensional electromagnetic scheme configured to use the off-chip tool.

13. The method according to claim 6, wherein: The second S-parameters are obtained directly from the second modeling tool without using an additional tool.

14. The method according to claim 6, wherein: The integrated modeling results of the entire high-speed channel are obtained including: An integrated S parameter is obtained by combining the first S parameter and the second S parameter.

15. The method according to claim 1, wherein: The semiconductor package comprises: Package substrate; An inserter, which is located on the packaging substrate; A first semiconductor device located on the interposer; and a second semiconductor device located on the interposer, the second semiconductor device being a semiconductor device of a different type than the first semiconductor device, The semiconductor substrate, the plurality of first connection wirings, and the plurality of through-electrodes are included in the interposer.

16. The method according to claim 15, wherein: The first semiconductor device includes a logic semiconductor device, and Wherein, the second semiconductor device includes a memory device.

17. The method according to claim 1, wherein: The semiconductor package comprises: Package substrate; A first semiconductor device is located on the packaging substrate; and a second semiconductor device located on the first semiconductor device, the second semiconductor device being a semiconductor device of a type different from that of the first semiconductor device, wherein the semiconductor substrate and the plurality of first connection wirings are included in the first semiconductor device, and The plurality of through-electrodes are included in at least one of the first semiconductor device and the second semiconductor device.

18. A method for designing a semiconductor package, the method comprising: generating a design of at least one semiconductor device included in the semiconductor package; generating a design of a high-speed channel included in the semiconductor package; Modeling the highway; as well as Analyze and verify the modeling results of the high-speed channel, The high-speed channel includes a plurality of first connection wirings on the upper surface of the semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate. Wherein, modeling the high-speed channel includes: Receiving design information of the high-speed channel; dividing the design information into a first layout including the plurality of first connection wirings and a second layout including the plurality of through-electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout, wherein the second modeling scheme is different from the first modeling scheme, and wherein the second modeling tool is different from the first modeling tool; and An integrated modeling result of the entire highway channel is obtained by combining the result of the first modeling operation and the result of the second modeling operation.

19. The method according to claim 18, wherein: In response to determining that the high-speed channel does not satisfy predetermined characteristics based on the modeling results of analyzing and verifying the high-speed channel, an operation of changing the design of the at least one semiconductor device and / or the design of the high-speed channel is performed on the semiconductor package.

20. A method for manufacturing a semiconductor package, the method comprising: generating a design of a semiconductor package including at least one semiconductor device and a high-speed channel; as well as manufacturing the semiconductor package based on a result of designing the semiconductor package, Wherein, designing the semiconductor package comprises: generating a design for the at least one semiconductor device; generating a design of the high-speed channel; Modeling the highway; and Analyze and verify the modeling results of the high-speed channel, The high-speed channel includes a plurality of first connection wirings on the upper surface of the semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate. Wherein, modeling the high-speed channel includes: Receiving design information of the high-speed channel; dividing the design information into a first layout including the plurality of first connection wirings and a second layout including the plurality of through-electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout, wherein the second modeling scheme is different from the first modeling scheme, and wherein the second modeling tool is different from the first modeling tool; and An integrated modeling result of the entire highway channel is obtained by combining the result of the first modeling operation and the result of the second modeling operation.

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