Display substrate and manufacturing method thereof, and display device

Abstract

The present invention provides a display substrate, a manufacturing method thereof, and a display device, wherein the display substrate includes a display area and a non-display area, and a signal is transmitted to the display area through the non-display area, wherein the non-display area includes a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer sequentially located on a base substrate, and a binding area includes a first via hole penetrating the first insulating layer and a second via hole penetrating the second insulating layer, the first via hole is configured to electrically connect the first conductive layer and the second conductive layer, and the second via hole is configured to electrically connect the second conductive layer and the third conductive layer, and the binding area is located in the non-display area, and the orthographic projection of the first via hole on the base substrate does not overlap with the orthographic projection of the second via hole on the base substrate. The display substrate, the manufacturing method thereof, and the display device provided by the present invention can improve the transmission speed of the signal transmitted by the binding area in the display device.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] The display substrate generally includes a display area and a non-display area, wherein the non-display area includes a bonding area, and pads in the bonding area are respectively connected to signal lines and peripheral circuits in the display area to ensure normal operation of the display substrate.

[0003] In the related art, in order to improve the display effect of the display device, more and more pixel units are made in the display substrate. However, in a high PPI (number of pixels per inch of the screen) display device, the original signal transmission speed of the pad in the binding area of ​​the display substrate cannot meet the signal transmission speed requirement of the high PPI display device. Summary of the invention

[0004] The embodiments of the present invention provide a display substrate and a manufacturing method thereof, and a display device to solve the problem in the related art that the original signal transmission speed of the binding area in the display substrate cannot meet the signal transmission speed requirement of the high PPI display device.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] In a first aspect, an embodiment of the present invention provides a display substrate, comprising a display area and a non-display area, wherein a signal is transmitted to the display area through the non-display area, wherein the non-display area comprises a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer and a third conductive layer sequentially located on a base substrate, and a binding area comprises a first via hole penetrating the first insulating layer and a second via hole penetrating the second insulating layer, wherein the first via hole is configured to electrically connect the first conductive layer and the second conductive layer, and the second via hole is configured to electrically connect the second conductive layer and the third conductive layer, and the binding area is located in the non-display area, and an orthographic projection of the first via hole on the base substrate does not overlap with an orthographic projection of the second via hole on the base substrate.

[0007] Further, the shortest distance between an orthographic projection outline of the first via hole on the substrate and an orthographic projection outline of the second via hole on the substrate is greater than or equal to half of a size of the first via hole.

[0008] Furthermore, the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

[0009] Further, a size of the first via hole is larger than a size of the second via hole.

[0010] Furthermore, the slope angle of the first via hole is greater than the slope angle of the second via hole.

[0011] Further, the via holes in the same row among the multiple pads are all first via holes or all second via holes.

[0012] Furthermore, the display area includes sub-pixels, gate lines and data lines arranged in an array, the sub-pixels include a thin film transistor array layer and an electrode, the gate of the thin film transistor array layer is connected to the gate line, the source of the thin film transistor array layer is connected to the data line, and the drain of the thin film transistor array layer is connected to the electrode.

[0013] Furthermore, the thin film transistor array layer includes an active layer, a gate insulating layer, a gate, an interlayer insulating layer and a metal layer stacked in sequence on the base substrate, wherein the orthographic projection area of ​​the gate on the base substrate is located within the orthographic projection area of ​​the gate insulating layer on the base substrate, and the interlayer insulating layer is provided with third via holes penetrating the interlayer insulating layer on both sides of the gate, and two metal segments separated from each other in the metal layer are electrically connected to the active layer through the third via holes to form a source and a drain.

[0014] Furthermore, the first conductive layer is made of the same material as the gate, and the first conductive layer extends into the display area.

[0015] Furthermore, the second conductive layer is made of the same material as the metal layer, and the display area does not include the second conductive layer.

[0016] Furthermore, the third conductive layer is a transparent conductive layer, the third conductive layer is made of the same material as the electrode, and the display area does not include the third conductive layer.

[0017] Furthermore, the second insulating layer is a passivation layer, and the second insulating layer extends to the display area and covers a portion of the metal layer.

[0018] Furthermore, a buffer layer is included, wherein a portion of the buffer layer in the binding area is located between the first conductive layer and the base substrate, and a portion of the buffer layer in the display area is located between the active layer and the base substrate.

[0019] Furthermore, an orthographic projection area of ​​the first via hole on the base substrate includes a first conductive layer, a second conductive layer, a second insulating layer and a third conductive layer sequentially located on the base substrate.

[0020] Furthermore, an orthographic projection area of ​​the second via hole on the base substrate includes a first conductive layer, a first insulating layer, a second conductive layer and a third conductive layer sequentially located on the base substrate.

[0021] Furthermore, the display substrate also includes a third insulating layer located on the side of the third conductive layer away from the base substrate, the third insulating layer is provided with a channel penetrating the third insulating layer, the orthographic projections of the first via hole and the second via hole on the base substrate are located within the orthographic projections of the channel on the base substrate, and the third insulating layer is located outside the binding area.

[0022] In a second aspect, an embodiment of the present invention further provides a method for manufacturing the display substrate as described above, the method comprising:

[0023] forming a first conductive layer on the base substrate;

[0024] forming a first insulating layer covering the first conductive layer, and forming a first via hole penetrating the first insulating layer in the binding area;

[0025] forming a second conductive layer covering the first insulating layer, wherein the second conductive layer is connected to a portion of the first conductive layer through the first via hole;

[0026] forming a second insulating layer covering the second conductive layer, and forming a second via hole penetrating the second insulating layer in the binding area, wherein an orthographic projection of the first via hole on the base substrate does not overlap with an orthographic projection of the second via hole on the base substrate;

[0027] A third conductive layer covering the second insulating layer is formed, and the third conductive layer is connected to a portion of the second conductive layer through the second via hole.

[0028] Further, the step of forming a second insulating layer covering the second conductive layer and forming a second via hole penetrating the second insulating layer in the binding area includes:

[0029] forming a second insulating layer covering the second conductive layer;

[0030] forming a third insulating layer covering the second conductive layer, and forming a channel penetrating the third insulating layer, wherein an orthographic projection of the channel on the substrate covers the binding area;

[0031] A second via hole penetrating the second insulating layer is formed in the binding area through the channel, and the orthographic projections of the first via hole and the second via hole on the base substrate are located within the orthographic projection of the channel on the base substrate.

[0032] In a third aspect, an embodiment of the present invention further provides a display device, comprising the display substrate as described above.

[0033] In the technical solution provided by the present invention, the orthographic projection of the first via hole on the base substrate does not overlap with the orthographic projection of the second via hole on the base substrate, thereby avoiding the situation where the binding area of ​​the display substrate is relatively uneven when overlapping, and the smoothness of the binding area in the display substrate can be ensured, which can also increase the contact area between the third conductive layer and the charged particles in the conductive glue in the binding area, thereby achieving the effect of increasing the signal transmission speed. Therefore, the technical solution provided by the present invention can increase the smoothness of the binding area in the display substrate, thereby increasing the transmission speed of the signal transmitted by the binding area in the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0035] Figure 1 A top view of a binding area of ​​a display substrate provided in one embodiment of the present invention;

[0036] Figure 2 for Figure 1 Sectional view along line A-A';

[0037] Figure 3 A schematic diagram showing the distribution of pads in a binding area of ​​a display substrate provided in one embodiment of the present invention;

[0038] Figure 4 A schematic diagram of the position relationship of pads in a display substrate provided by an embodiment of the present invention;

[0039] Figure 5 A positional relationship diagram between an orthographic projection of a first via hole on a base substrate and an orthographic projection of a second via hole on a base substrate in a display substrate provided by another embodiment of the present invention;

[0040] Figure 6 A schematic diagram of the structure of a portion of film layers in a display area and a binding area of ​​a display substrate provided in an embodiment of the present invention;

[0041] Figure 7 The present invention is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] In the related art, in order to improve the display effect of the display device, more and more pixel units are made in the display substrate. However, in a high PPI (number of pixels per inch of the screen) display device, the original signal transmission speed of the pad in the binding area of ​​the display substrate cannot meet the signal transmission speed requirement of the high PPI display device.

[0044] In view of the above problems, the embodiments of the present invention provide a display substrate and a method for manufacturing the same, and a display device, which can solve the problem that the original signal transmission speed of the pads in the binding area of ​​the display substrate in the related art cannot meet the signal transmission speed requirements of the high PPI display device.

[0045] An embodiment of the present invention provides a display substrate, comprising a display area and a non-display area, wherein a signal is transmitted to the display area via the non-display area, wherein: Figure 1 and Figure 2 As shown, the non-display area includes a first conductive layer 130, a first insulating layer 110, a second conductive layer 140, a second insulating layer 120 and a third conductive layer 150 which are sequentially located on the base substrate 100, wherein the binding area of ​​the display substrate includes a first via hole 111 penetrating the first insulating layer 110 and a second via hole 121 penetrating the second insulating layer 120, the first via hole 111 is configured to electrically connect the first conductive layer 130 and the second conductive layer 140, the second via hole 121 is configured to electrically connect the second conductive layer 140 and the third conductive layer 150, the binding area is located in the non-display area, and the orthographic projection of the first via hole 111 on the base substrate does not overlap with the orthographic projection of the second via hole 121 on the base substrate.

[0046] In the embodiment of the present invention, the orthographic projection of the first via hole on the base substrate does not overlap with the orthographic projection of the second via hole on the base substrate, thereby avoiding the situation where the binding area of ​​the display substrate is uneven to a large extent when overlapping, and can ensure the smoothness of the binding area in the display substrate, so that the contact area between the third conductive layer and the charged particles in the conductive glue in the binding area can be increased, thereby achieving the effect of increasing the signal transmission speed. Therefore, the technical solution provided by the present invention can increase the smoothness of the binding area in the display substrate, thereby increasing the transmission speed of the signal transmitted by the binding area in the display device.

[0047] In the embodiment of the present invention, the positional relationship of each film layer in the binding area is as follows: Figure 1 and Figure 2 As shown (in order to facilitate the observation of the solution of the present invention, Figure 1 The film layers above the third conductive layer 150 are hidden in the figure. The first conductive layer 130 and the second conductive layer 140 are the film layers covered by the third conductive layer 150. Figure 1 The first via hole 111 and the second via hole 121 are also covered by the third conductive layer 150, which is to illustrate the positions of the first via hole 111 and the second via hole 121. Figure 1 The order of forming each film layer on the base substrate 100 may be to form a first conductive layer 130, a first insulating layer 110, a second conductive layer 140, a second insulating layer 120 and a third conductive layer 150 in sequence from the base substrate to one side.

[0048] After the first insulating layer 110 is formed, a first via hole 111 penetrating the first insulating layer 110 is opened so that when the second conductive layer 140 is formed, the second conductive layer 140 can be connected to the first conductive layer 130 through the first via hole 111 and the first insulating layer 110 .

[0049] Similarly, after forming the second insulating layer 120 , by opening a second via hole 121 penetrating the second insulating layer 120 , when forming the third conductive layer 150 , the third conductive layer 150 can be connected to the second conductive layer 140 through the second via hole 121 and through the second insulating layer 120 .

[0050] The first conductive layer 130, the first insulating layer 110, the second conductive layer 140, the second insulating layer 120 and the third conductive layer 150, as well as the first via hole 111 in the first insulating layer 110 and the second via hole 121 in the second insulating layer 120 together constitute a pad. The plurality of pads are arranged in an array in the bonding area, such as Figure 3 As shown, the pad may be a rectangular structure, such as Figure 4 As shown, the length of the pad can be 1200um, the width of the pad can be 15um, and the pitch value between adjacent pads can be 28.5um. Of course, the above is just an example, the length of the pad can also be 1201um, the width of the pad can also be 16um, the pitch value between adjacent pads can be 29um, and so on. It should be noted that the above pitch value is the distance between the same long sides of two adjacent pads.

[0051] When the orthographic projection of the first via hole on the base substrate coincides with the orthographic projection of the second via hole on the base substrate, the step difference between the opening area and the non-opening area in the binding area is very large, and the contact area between the conductive adhesive and the third conductive layer 150 is reduced, resulting in the signal transmission speed of the pad in the binding area being unable to meet the signal transmission speed requirements of the high PPI display device.

[0052] In the embodiment of the present invention, the orthographic projection of the first via hole 111 on the base substrate and the orthographic projection of the second via hole 121 on the base substrate are designed not to overlap, such as Figure 2 As shown, this can shorten the step difference between the parts of the binding area, while increasing the contact area between the conductive adhesive and the third conductive layer 150, improving the signal transmission speed of the pad in the binding area, and meeting the signal transmission speed requirements of the high PPI display device.

[0053] The first vias 111 are arranged in an array on the first insulating layer 110, and the second vias 121 are arranged in an array on the second insulating layer 120. The first vias 111 and the second vias 121 are arranged in an offset manner. The flatness of the display substrate in the binding area can be adjusted by adjusting the arrangement distance between the first vias 111 and the arrangement distance between the second vias 121.

[0054] Furthermore, if Figure 2 As shown, the orthographic projection area of ​​the first via hole 111 on the base substrate 100 includes a first conductive layer 130 , a second conductive layer 140 , a second insulating layer 120 and a third conductive layer 150 sequentially located on the base substrate 100 .

[0055] Furthermore, if Figure 2 As shown, the orthographic projection area of ​​the second via hole 121 on the base substrate 100 includes a first conductive layer 130 , a first insulating layer 110 , a second conductive layer 140 and a third conductive layer 150 sequentially located on the base substrate 100 .

[0056] Further, the shortest distance between an orthographic projection outline of the first via hole 111 on the base substrate and an orthographic projection outline of the second via hole 121 on the base substrate is greater than or equal to half of the size of the first via hole 111 .

[0057] like Figure 5 As shown, Figure 5 The d indicated in is the shortest distance between the orthographic projection outline 111 ′ of the first via hole 111 on the substrate and the orthographic projection outline 121 ′ of the second via hole 121 on the substrate.

[0058] Setting d to be greater than or equal to half of the size of the first via hole 111 can ensure the overall smoothness of the binding area. The size of the first via hole 111 and the second via hole 121 is usually 8-10um. When the size of the first via hole 111 is 8um, d can be 4um.

[0059] The thickness of the first insulating layer 110 may be greater than the thickness of the second insulating layer 120 .

[0060] At this time, the size of the first via hole 111 opened on the first insulating layer 110 by the etching process is larger than the size of the second via hole 121 opened on the second insulating layer 121 .

[0061] In addition, the slope angle of the first via hole 111 opened on the first insulating layer 110 by using the etching process is also greater than the slope angle of the second via hole 121 opened on the second insulating layer 121 .

[0062] Further, the via holes in the same row among the multiple pads are all first via holes or all second via holes.

[0063] Right now Figure 3 Among the multiple pads, the vias in a row are all first vias, and the vias in the upper and lower rows of the row are all second vias.

[0064] In this way, it can be ensured that the positions of the pads in the non-display area are neatly arranged, which is convenient for connecting the signal lines in the display substrate and transmitting the signals.

[0065] Furthermore, if Figure 6 As shown, the display area includes sub-pixels 600, gate lines and data lines arranged in an array, and the sub-pixels include a thin film transistor array layer 610 and an electrode 620. The gate 611 of the thin film transistor array layer 610 is connected to the gate line, the source 612 of the thin film transistor array layer 610 is connected to the data line, and the drain 613 of the thin film transistor array layer 610 is connected to the electrode 620.

[0066] like Figure 6 As shown, when the electrode 620 is charged, the gate line is used to provide a conduction signal to the gate 611 of the thin film transistor array layer 610, so that the source 612 and the drain 613 of the thin film transistor array layer 610 are turned on. At this time, the data signal in the data line can charge the electrode 620, so that the sub-pixel emits light according to the preset brightness.

[0067] Among them, the thin film transistor array layer 610 includes an active layer 614, a gate insulating layer 615, a gate 611, an interlayer insulating layer 616 and a metal layer stacked in sequence on the base substrate, wherein the orthographic projection area of ​​the gate 611 on the base substrate 100 is located within the orthographic projection area of ​​the gate insulating layer 615 on the base substrate 100, and the interlayer insulating layer 616 is respectively provided with third vias 617 penetrating the interlayer insulating layer 616 on both sides of the gate 611, and two metal segments separated from each other in the metal layer are electrically connected to the active layer 614 through the third vias 617 to form a source 612 and a drain 613.

[0068] In addition, a shading layer 618 may be formed between the buffer layer 160 and the base substrate 100, and the orthographic projection of the shading layer 618 on the base substrate 100 coincides with the orthographic projection of the active layer 614 on the base substrate 100, so as to block external light, prevent the active layer from being affected by external light, and improve the reliability of the thin film transistor array layer 610.

[0069] Furthermore, the first conductive layer 130 is made of the same material as the gate 611 , and the first conductive layer 130 extends into the display area.

[0070] The first conductive layer 130 may be a metal material layer. When a gate electrode 611 of a thin film crystal array layer is formed in the display area, a metal layer may be simultaneously formed on the entire surface of the display substrate. Thereafter, a single patterning process is performed to form the gate electrode 611 in the display area and the first conductive layer 130 in the non-display area.

[0071] When the pad is located on the source side of the data signal, the first conductive layer 130 is extended to the display area and connected to the data line through the wiring in the display area to transmit the data signal. When the display device does not use the array substrate row driver (Gate Driver on Array, referred to as GOA) and the pad is located on the source side of the gate scan signal, the first conductive layer 130 can be extended to the display area and directly connected to the gate line.

[0072] Furthermore, the second conductive layer 140 is made of the same material as the metal layer, and the display area does not include the second conductive layer 140 .

[0073] The second conductive layer 140 does not extend to the display area, and is only used to transmit electrical signals in the binding area. When manufacturing the second conductive layer 140, a metal material layer can be formed on the entire surface of the display substrate at the same time, and then a metal layer is formed in the display area and the second conductive layer 140 is formed in the non-display area through a single patterning process.

[0074] In this way, compared with separately manufacturing the metal layer and the second conductive layer 140 , time and processes are saved, and the manufacturing efficiency of the display substrate is improved.

[0075] Furthermore, the third conductive layer 150 may be a transparent conductive layer, and the third conductive layer 150 and the electrode 620 may be made of the same material.

[0076] The material of the third conductive layer 150 may be indium tin oxide (ITO) or indium zinc oxide (IZO). The material of the electrode 620 may also be indium tin oxide (ITO) or indium zinc oxide (IZO).

[0077] Therefore, in this embodiment, a transparent conductive material layer can be formed on the entire surface of the display substrate at the same time, and then the electrode 620 is formed in the display area and the third conductive layer 150 is formed in the non-display area through a single patterning process.

[0078] In this way, compared with separately manufacturing the electrode 620 and the third conductive layer 150 , time and processes are saved, and the manufacturing efficiency of the display substrate is improved.

[0079] It should be noted that any one of the first conductive layer 130, the second conductive layer 140 and the third conductive layer 150 extending to the display area can achieve the function of transmitting the signal from the non-display area to the display area. However, in the present embodiment, the reason for extending only the first conductive layer 130 to the display area is that there are other signal lines on the side of the third conductive layer 150 away from the substrate in the area between the binding area and the display area. Compared with the second conductive layer 140 and the third conductive layer 150, the first conductive layer 130 is farthest from other signals and has the most insulating layers between them. In this way, the first conductive layer 130 is the conductive layer that is least likely to short-circuit with other lines among the three conductive layers, and the reliability of extending the first conductive layer 130 to the display area to transmit signals is the highest.

[0080] Of course, in other embodiments of the present invention, the second conductive layer 140 or the third conductive layer 150 may be extended to the display area, which is not limited here.

[0081] Furthermore, the second insulating layer 120 may be a passivation layer, and the second insulating layer extends to the display area and covers a portion of the metal layer.

[0082] The passivation layer can protect the second conductive layer 140 from being easily oxidized, ensuring the normal operation of the second conductive layer 140 in the binding area. Similarly, the metal layer in the display area also needs a passivation layer to protect it from being oxidized, ensuring the normal operation of the metal layer.

[0083] Therefore, when forming the passivation layer in the binding area, a passivation layer covering the metal layer can be formed in the display area at the same time, thereby improving the manufacturing efficiency of the display substrate.

[0084] Furthermore, if Figure 2 and Figure 6 As shown, the binding area of ​​the display substrate may further include a buffer layer 160, wherein the buffer layer 160 is located between the first conductive layer 130 and the base substrate 100 in the binding area, and the buffer layer 160 is located between the active layer 614 and the base substrate 100 in the display area.

[0085] First, the buffer layer 160 can provide a flat surface for the first conductive layer 130 ; in addition, since the binding area is usually located at the edge of the display substrate and is susceptible to external impact, the buffer layer 160 can also protect the first conductive layer 130 and reduce the impact on the first conductive layer 130 .

[0086] At the same time, the display area also requires a buffer layer 160 to provide a flat manufacturing surface for the thin film transistor array layer 610. Therefore, when forming a flat layer in the binding area, a flat layer can be formed in the display area at the same time, thereby improving the manufacturing efficiency of the display substrate.

[0087] Furthermore, if Figure 6 As shown, the binding area also includes a channel 171 passing through the third insulating layer 170, and the third insulating layer 170 is located on the side of the first insulating layer 110 and the second insulating layer 120 away from the base substrate 100, and the orthographic projections of the first via 111 and the second via 121 on the base substrate 100 are located within the orthographic projection of the channel 170 on the base substrate 100.

[0088] In this embodiment, in the process of forming the display substrate, after forming the second insulating layer 120 and before forming the second via hole 121, a third insulating layer 170 is formed on the second insulating layer 120; then, a channel 171 penetrating the third insulating layer 170 is formed on the third insulating layer 170, wherein the channel 171 is greater than or equal to the binding area, and the binding area is located in the channel 171; then, the second via hole 121 penetrating the second insulating layer 120 is formed through the channel 171.

[0089] In the process of manufacturing the display substrate, the outer film layer in the binding area can be manufactured, and the manufacturing of the pad in the binding area can be improved by opening the channel 171 without affecting the manufacturing of the display substrate.

[0090] The embodiment of the present invention also provides a method for manufacturing a display substrate, such as Figure 7 As shown, the method includes:

[0091] Step 701: forming a first conductive layer on a substrate;

[0092] Step 702: forming a first insulating layer covering the first conductive layer, and forming a first via hole penetrating the first insulating layer in the binding area;

[0093] Step 703: forming a second conductive layer covering the first insulating layer, wherein the second conductive layer is connected to a portion of the first conductive layer through the first via hole;

[0094] Step 704: forming a second insulating layer covering the second conductive layer, and forming a second via hole penetrating the second insulating layer in the binding area, wherein the orthographic projection of the first via hole on the base substrate does not overlap with the orthographic projection of the second via hole on the base substrate;

[0095] Step 705: forming a third conductive layer covering the second insulating layer, wherein the third conductive layer is connected to a portion of the second conductive layer through the second via hole.

[0096] In the embodiment of the present invention, the orthographic projection of the first via hole on the base substrate does not overlap with the orthographic projection of the second via hole on the base substrate, thereby avoiding the situation where the binding area of ​​the display substrate is uneven to a large extent when overlapping, and can ensure the smoothness of the binding area in the display substrate, so that the contact area between the third conductive layer and the charged particles in the conductive glue in the binding area can be increased, thereby achieving the effect of increasing the signal transmission speed. Therefore, the technical solution provided by the present invention can increase the smoothness of the binding area in the display substrate, thereby increasing the transmission speed of the signal transmitted by the binding area in the display device.

[0097] In the embodiment of the present invention, the positional relationship of each film layer in the binding area is as follows: Figure 1 and Figure 2 As shown (in order to facilitate the observation of the solution of the present invention, Figure 1 The film layers above the third conductive layer 150 are hidden in the figure. The first conductive layer 130 and the second conductive layer 140 are the film layers covered by the third conductive layer 150. Figure 1 The first via hole 111 and the second via hole 121 are also covered by the third conductive layer 150, which is to illustrate the positions of the first via hole 111 and the second via hole 121. Figure 1 The order of forming each film layer on the base substrate 100 may be to form a first conductive layer 130, a first insulating layer 110, a second conductive layer 140, a second insulating layer 120 and a third conductive layer 150 in sequence from the base substrate to one side.

[0098] After the first insulating layer 110 is formed, a first via hole 111 penetrating the first insulating layer 110 is opened so that when the second conductive layer 140 is formed, the second conductive layer 140 can be connected to the first conductive layer 130 through the first via hole 111 and the first insulating layer 110 .

[0099] Similarly, after forming the second insulating layer 120 , by opening a second via hole 121 penetrating the second insulating layer 120 , when forming the third conductive layer 150 , the third conductive layer 150 can be connected to the second conductive layer 140 through the second via hole 121 and through the second insulating layer 120 .

[0100] The first conductive layer 130, the first insulating layer 110, the second conductive layer 140, the second insulating layer 120 and the third conductive layer 150, as well as the first via hole 111 in the first insulating layer 110 and the second via hole 121 in the second insulating layer 120 together constitute a pad. The plurality of pads are arranged in an array in the bonding area, such as Figure 3 As shown, the pad may be a rectangular structure, such as Figure 4 As shown, the length of the pad can be 1200um, the width of the pad can be 15um, and the pitch value between adjacent pads can be 28.5um. Of course, the above is just an example, the length of the pad can also be 1201um, the width of the pad can also be 16um, the pitch value between adjacent pads can be 29um, and so on. It should be noted that the above pitch value is the distance between the same long sides of two adjacent pads.

[0101] When the orthographic projection of the first via hole on the base substrate coincides with the orthographic projection of the second via hole on the base substrate, the step difference between the opening area and the non-opening area in the binding area is very large, and the contact area between the conductive adhesive and the third conductive layer 150 is reduced, resulting in the signal transmission speed of the pad in the binding area being unable to meet the signal transmission speed requirements of the high PPI display device.

[0102] In the embodiment of the present invention, the orthographic projection of the first via hole 111 on the base substrate and the orthographic projection of the second via hole 121 on the base substrate are designed not to overlap, such as Figure 2 As shown, this can shorten the step difference between the parts of the binding area, while increasing the contact area between the conductive adhesive and the third conductive layer 150, improving the signal transmission speed of the pad in the binding area, and meeting the signal transmission speed requirements of the high PPI display device.

[0103] The first vias 111 are arranged in an array on the first insulating layer 110, and the second vias 121 are arranged in an array on the second insulating layer 120. The first vias 111 and the second vias 121 are arranged in an offset manner. The flatness of the display substrate in the binding area can be adjusted by adjusting the arrangement distance between the first vias 111 and the arrangement distance between the second vias 121.

[0104] Further, the step of forming a second insulating layer covering the second conductive layer and forming a second via hole penetrating the second insulating layer includes:

[0105] forming a second insulating layer covering the second conductive layer;

[0106] forming a third insulating layer covering the second conductive layer, and forming a channel penetrating the third insulating layer, wherein an orthographic projection of the channel on the substrate covers the binding area;

[0107] A second via hole penetrating the second insulating layer is formed in the binding area through the channel, and the orthographic projections of the first via hole and the second via hole on the base substrate are located within the orthographic projection of the channel on the base substrate.

[0108] In this embodiment, in the process of forming the display substrate, after forming the second insulating layer and before forming the second via hole, a third insulating layer is formed on the second insulating layer; then, a channel penetrating the third insulating layer is formed on the third insulating layer, wherein the channel is greater than or equal to the binding area, and the binding area is located in the channel; then, a second via hole penetrating the second insulating layer is formed through the channel.

[0109] In the process of manufacturing the display substrate, not only can the manufacturing of the outer film layer in the binding area be completed, but also the manufacturing of the pad in the binding area can be improved by opening a channel without affecting the manufacturing of the display substrate.

[0110] An embodiment of the present invention further provides a display device, comprising the display substrate as described above.

[0111] The display device can be a monitor, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, etc.

[0112] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0113] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0114] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A display substrate, comprising a display area and a non-display area, wherein a signal is transmitted to the display area via the non-display area, characterized in that: The non-display area includes a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer and a third conductive layer sequentially located on the base substrate, the binding area includes a first via hole penetrating the first insulating layer and a second via hole penetrating the second insulating layer, the first via hole is configured to electrically connect the first conductive layer and the second conductive layer, the second via hole is configured to electrically connect the second conductive layer and the third conductive layer, the binding area is located in the non-display area, and the orthographic projection of the first via hole on the base substrate does not overlap with the orthographic projection of the second via hole on the base substrate; The shortest distance between the orthographic projection outline of the first via hole on the substrate and the orthographic projection outline of the second via hole on the substrate is greater than or equal to one half of the size of the first via hole; The thickness of the first insulating layer is greater than the thickness of the second insulating layer.

2. The display substrate according to claim 1, characterized in that: A size of the first via hole is greater than a size of the second via hole.

3. The display substrate according to claim 1, characterized in that: The slope angle of the first via hole is greater than the slope angle of the second via hole.

4. The display substrate according to claim 1, characterized in that: The via holes in the same row among the plurality of pads are all first via holes or are all second via holes.

5. The display substrate according to claim 1, characterized in that: The display area includes sub-pixels, gate lines and data lines arranged in an array, the sub-pixels include a thin film transistor array layer and an electrode, the gate of the thin film transistor array layer is connected to the gate line, the source of the thin film transistor array layer is connected to the data line, and the drain of the thin film transistor array layer is connected to the electrode.

6. The display substrate according to claim 5, characterized in that: The thin film transistor array layer includes an active layer, a gate insulating layer, a gate, an interlayer insulating layer and a metal layer stacked in sequence on the base substrate, wherein the orthographic projection area of ​​the gate on the base substrate is located within the orthographic projection area of ​​the gate insulating layer on the base substrate, the interlayer insulating layer is provided with third via holes penetrating the interlayer insulating layer on both sides of the gate, and two metal segments separated from each other in the metal layer are electrically connected to the active layer through the third via holes to form a source and a drain.

7. The display substrate according to claim 6, characterized in that: The first conductive layer is made of the same material as the gate, and the first conductive layer extends into the display area.

8. The display substrate according to claim 7, characterized in that: The second conductive layer is made of the same material as the metal layer, and the display area does not include the second conductive layer.

9. The display substrate according to claim 8, characterized in that: The third conductive layer is a transparent conductive layer. The material of the third conductive layer is the same as that of the electrode. The display area does not include the third conductive layer.

10. The display substrate according to claim 6, characterized in that: The second insulating layer is a passivation layer, and the second insulating layer extends to the display area and covers a portion of the metal layer.

11. The display substrate according to claim 6, characterized in that: A buffer layer is also included. A portion of the buffer layer in the binding area is located between the first conductive layer and the base substrate. A portion of the buffer layer in the display area is located between the active layer and the base substrate.

12. The display substrate according to claim 1, characterized in that: The orthographic projection area of ​​the first via hole on the base substrate includes a first conductive layer, a second conductive layer, a second insulating layer and a third conductive layer which are sequentially located on the base substrate.

13. The display substrate according to claim 1, characterized in that: The orthographic projection area of ​​the second via hole on the base substrate includes a first conductive layer, a first insulating layer, a second conductive layer and a third conductive layer which are sequentially located on the base substrate.

14. The display substrate according to claim 1, characterized in that: The display substrate also includes a third insulating layer located on the side of the third conductive layer facing away from the base substrate, the third insulating layer is provided with a channel penetrating the third insulating layer, the orthographic projections of the first via hole and the second via hole on the base substrate are located within the orthographic projections of the channel on the base substrate, and the third insulating layer is located outside the binding area.

15. A method for manufacturing a display substrate according to any one of claims 1 to 14, characterized in that: The method comprises: forming a first conductive layer on the base substrate; forming a first insulating layer covering the first conductive layer, and forming a first via hole penetrating the first insulating layer in the binding area; forming a second conductive layer covering the first insulating layer, wherein the second conductive layer is connected to a portion of the first conductive layer through the first via hole; forming a second insulating layer covering the second conductive layer, and forming a second via hole penetrating the second insulating layer in the binding area, wherein an orthographic projection of the first via hole on the base substrate does not overlap with an orthographic projection of the second via hole on the base substrate; A third conductive layer covering the second insulating layer is formed, and the third conductive layer is connected to a portion of the second conductive layer through the second via hole.

16. The method according to claim 15, characterized in that The step of forming a second insulating layer covering the second conductive layer and forming a second via hole penetrating the second insulating layer in the binding area includes: forming a second insulating layer covering the second conductive layer; forming a third insulating layer covering the second conductive layer, and forming a channel penetrating the third insulating layer, wherein an orthographic projection of the channel on the substrate covers the binding area; A second via hole penetrating the second insulating layer is formed in the binding area through the channel, and the orthographic projections of the first via hole and the second via hole on the base substrate are located within the orthographic projection of the channel on the base substrate.

17. A display device, characterized in that: The invention comprises a display substrate as claimed in any one of claims 1 to 14.

Images