Memory device and method of repairing the same

Abstract

A memory device and a repair method thereof are provided. The memory device includes a row decoder, a column decoder, and repair control circuitry. The repair control circuitry is configured to: (i) compare a row address with a stored faulty row address; (ii) compare a column address with a stored faulty column address; (iii) control the row decoder to activate at least one of a plurality of redundant word lines when the row address corresponds to the faulty row address; and (iv) control the column decoder to activate at least one of a plurality of redundant bit lines when the column address corresponds to the faulty column address. The repair control circuitry modifies the repair cell according to the input address during the repair operation.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0134559, filed on October 28, 2019, with the Korean Intellectual Property Office, the publication of which is hereby incorporated by reference. Technical Field

[0002] The present invention relates to a memory device with variable memory cell repair capability and a method for repairing the memory device using memory cell redundancy. Background Technology

[0003] Typically, as the manufacturing process of Dynamic Random Access Memory (DRAM) becomes miniaturized, the incidence of memory cells with hard or soft defects (i.e., faulty memory cells) increases. In this context, a memory cell with a hard defect can represent a memory cell with a relatively permanent defect, while a memory cell with a soft defect can represent a memory cell with a relatively minor, temporary defect. To ensure the full memory capacity of the DRAM, a repair method that replaces faulty cells with spare or redundant cells, set up independently of normal cells, can be employed. For example, a repair method that replaces the entire row containing the faulty cell with a spare or redundant row (i.e., row repair) or replaces the column containing the faulty cell with a spare or redundant column (i.e., column repair) can be employed. Summary of the Invention

[0004] One aspect of the present invention is to provide a memory device for modifying the repair unit and a repair method thereof.

[0005] According to one aspect of the present invention, a memory device is provided, the memory device comprising: an address buffer configured to store a plurality of bits of a received address (e.g., a row address, a column address); and a first non-volatile memory configured to store a plurality of bits of a fault address. A plurality of first logic circuits are also provided, each of these logic circuits being configured to compare a bit of the received address stored in the address buffer with a corresponding bit of the fault address stored in the first non-volatile memory. A first selector is provided, the first selector being configured to output an output value selected from two output values ​​of two of the plurality of first logic circuits in response to a select signal. A second logic circuit is provided, the second logic circuit being configured to output an address matching signal based on the selected output value and the output values ​​of the remaining first logic circuits excluding the two first logic circuits. A second non-volatile memory is provided, the second non-volatile memory being configured to store an address bit value corresponding to the select signal. A second selector is provided, the second selector being configured to output a bit of the address corresponding to the two first logic circuits in response to a true version or an inverted version of the select signal. A third logic circuit is provided, configured to perform an AND operation on the address matching signal and the output value of the second selector. According to some of these embodiments of the invention, each of the first logic circuits is configured to perform an XNOR (or XOR) operation, while the second logic circuit performs an AND (or NAND) operation.

[0006] A memory device according to another embodiment of the invention may include: a memory cell array having redundant regions (corresponding to redundant word lines and / or redundant bit lines) and normal regions (corresponding to word lines and bit lines). A row decoder is provided, configured to activate at least one of the word lines and / or activate at least one of the redundant word lines in response to a row address. A column decoder is provided, configured to activate at least one of the bit lines and / or activate at least one of the redundant bit lines in response to a column address. Repair control circuitry is provided, configured to: (i) compare a row address with a stored faulty row address, (ii) compare a column address with a stored faulty column address, (iii) control the row decoder to activate the at least one of the redundant word lines when the row address corresponds to the faulty row address, and (iv) control the column decoder to activate the at least one of the redundant bit lines when the column address corresponds to the faulty column address. According to a further aspect of these embodiments, the repair control circuitry is operable to change a repair cell based on an input address during a repair operation.

[0007] According to another aspect of the present invention, a memory device includes: a memory cell array having redundant regions corresponding to redundant word lines or redundant bit lines and normal regions corresponding to word lines and bit lines. The memory device further includes: a row decoder configured to activate at least one of the word lines or at least one of the redundant word lines in response to a row address; and a column decoder configured to activate at least one of the bit lines or at least one of the redundant bit lines in response to a column address. A repair control circuit is provided, configured to: compare a row address with a stored faulty row address, compare a column address with a stored faulty column address, control the row decoder to activate the at least one of the redundant word lines when the row address corresponds to the faulty row address, and control the column decoder to activate the at least one of the redundant bit lines when the column address corresponds to the faulty column address. The repair control circuit can change the repair cell according to the input address during a repair operation.

[0008] According to another embodiment of the inventive concept, a method for repairing a memory device includes: receiving an address; determining a repair unit using at least one address bit (among the address bits of the received address) that will be ignored in the repair operation; and comparing the received address with a stored fault address. Furthermore, when the received address corresponds to a stored fault address, a redundant cell array having the repair unit is accessed in response to the address operation being performed. Attached Figure Description

[0009] The above and other aspects, features, and advantages of the present invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a diagram illustrating an example of a memory device 100 according to a concept of the present invention.

[0011] Figure 2 This is a diagram illustrating an example of a memory cell array according to a concept of the present invention.

[0012] Figure 3 This is a block diagram illustrating an example of a repair control circuit 140 according to a concept of the present invention.

[0013] Figure 4 This is a diagram illustrating an example of a repair control circuit 140 according to an embodiment of the present invention.

[0014] Figure 5 This is a diagram illustrating an example of a repair control circuit 140a according to another embodiment of the concept of the present invention.

[0015] Figure 6 This is a diagram illustrating the repair operation based on the fixed repair unit.

[0016] Figure 7 This is a diagram illustrating an example of a repair operation based on a variable repair unit according to an invention concept.

[0017] Figure 8 This is a flowchart illustrating a repair method for a memory device 100 according to an example.

[0018] Figure 9 This is a flowchart illustrating an example of a process for repairing a memory device during a test operation, according to a concept based on the present invention.

[0019] Figure 10 This is a diagram illustrating another example of a memory device 100a according to the concept of the present invention.

[0020] Figure 11 This is a diagram illustrating another example of a memory device 100b according to the concept of the present invention.

[0021] Figure 12 This is a diagram illustrating another example of a memory device according to the concept of the present invention.

[0022] Figure 13 This is a block diagram illustrating a memory chip according to a disclosed example.

[0023] Figure 14 This is a diagram illustrating a mobile device 3000 according to an example.

[0024] Figure 15 This is a diagram illustrating a computing system 4000 as an example.

[0025] Figure 16 This is a diagram illustrating an example of a data server system 5000 according to a concept of the present invention. Detailed Implementation

[0026] The invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals always denote the same elements.

[0027] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of the invention, the first element, first component, first region, first layer, or first portion discussed below may be referred to as a second element, second component, second region, second layer, or second portion.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as used herein. It will also be understood that the terms “comprising,” “including,” “having,” and variations thereof, when used in this specification, indicate the presence of the described features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Conversely, the term “consisting of”, when used in the specification, specifies the described features, steps, operations, elements, and / or components and excludes additional features, steps, operations, elements, and / or components.

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense.

[0030] Figure 1 This is a diagram illustrating an example of a memory device 100 according to the concept of the present invention. (Refer to...) Figure 1The memory device 100 may include a memory cell array 110, a row decoder 120, a column decoder 130, and a repair control circuit 140. The memory cell array 110 may include a normal region 112 with a plurality of memory cells and a redundant region 114 with a plurality of redundant memory cells. In one example, the normal region 112 may include a plurality of memory cells that can be respectively disposed in the intersection regions of a plurality of word lines WL and a plurality of bit lines BL. In this case, each of the plurality of memory cells may include a volatile memory cell or a non-volatile memory cell. In one example, a first portion of the redundant region 114 may be disposed adjacent to the normal region 112 in the extension direction of the word lines WL. For example, the redundant region 114 may include a plurality of redundant memory cells that can be respectively disposed in the intersection regions of a plurality of redundant bit lines RBL and a plurality of word lines WL. Furthermore, a second portion of the redundant region 114 may be disposed adjacent to the normal region 112 in the extension direction of the bit lines BL. For example, the redundant region 114 may include a plurality of redundant memory cells that can be respectively disposed in the intersection regions of a plurality of redundant word lines RWL and a plurality of bit lines BL.

[0031] A fault may occur in at least one of the memory cells located in normal region 112. The faulty cell may be a single bit, a weak cell, or a defective cell. The faulty cell generated in normal region 112 may be replaced by a redundant memory cell included in redundant region 114. This replacement operation may be referred to as a "repair operation." Through the repair operation, data to be stored in or read from the faulty cell may be stored in or read from the "replacement" redundant memory cell.

[0032] The line decoder 120 can, in response to a line address (RA), select at least one word line from a plurality of word lines (WL) and activate the selected word line. Furthermore, the line decoder 120 can, in response to a line address match signal, select at least one redundant word line from a plurality of redundant word lines (RWL) and activate the selected redundant word line. For example, the line decoder 120 can, in response to a line address match signal, deactivate the line address (RA) and activate the selected redundant word line.

[0033] Column decoder 130 may, in response to a column address (CA), select at least one bit line from a plurality of bit lines BL and activate the selected bit line. Furthermore, column decoder 130 may, in response to a column address match signal, select at least one redundant bit line from a plurality of redundant bit lines RBL and activate the selected redundant bit line. For example, column decoder 130 may, in response to a column address match signal, deactivate the column address (CA) and activate the selected redundant bit line.

[0034] The repair control circuit 140 can be implemented to perform a repair operation on a faulty cell among a plurality of memory cells. For example, when the input row address (RA) corresponds to a faulty cell, the repair control circuit 140 can generate a row address matching signal. Furthermore, when the input column address (CA) corresponds to a faulty cell, the repair control circuit 140 can generate a column address matching signal.

[0035] Furthermore, the repair control circuit 140 can change the extent of the repair region based on the type of fault (e.g., short-circuit error, open-circuit error, or progressive error). In this case, the repair region may be a region corresponding to a single redundant address (CRENI). For example, the repair control circuit 140 can change the type (e.g., normal address, redundant address, row address, or column address) or the number of address bits corresponding to the faulty cell. The repair control circuit 140 can store repair mapping information regarding the type or number of address bits in non-volatile memory (e.g., a fuse).

[0036] A typical memory device can compare an input address with a stored fault address and, based on the comparison result, perform a repair operation by changing the address to the repair address. The repair operation can be performed in a fixed repair unit.

[0037] In an example memory device 100 conceived according to the present invention, by performing repair operations differently according to the fault type of the memory cell, and even with the same redundant resources, by changing the repair cells (e.g., the type and number of addresses) according to the fault type, yield can be expected to be improved.

[0038] Figure 2 This is a diagram illustrating an example of a memory cell array according to a concept of the present invention. (Refer to...) Figure 2 The memory cell array may include a normal cell array (NCA) and a redundant cell array (RCA). The normal cell array (NCA) 112 may include multiple memory cells located at the intersections between word lines WL1 to WLm and bit lines BL1 to BLn, where m is a two-or-greater integer and n is a two-or-greater integer. The redundant cell array (RCA) 114 may include multiple redundant memory cells located at the intersections between redundant word lines RWL1 to RWLi and redundant bit lines RBL1 to RBLj, where i is a two-or-greater integer and j is a two-or-greater integer.

[0039] Figure 2The redundant word lines RWL1 to RWLi shown can be positioned above word lines WL1 to WLm, but their positions are not limited to this. Therefore, the redundant word lines RWL1 to RWLi can be positioned below word lines WL1 to WLm, can be a single group between word lines WL1 to WLm, or can be arranged as multiple groups between word lines WL1 to WLm.

[0040] Figure 2 The redundant bit lines RBL1 to RBLj shown can be located to the right of bit lines BL1 to BLn, but their positions are not limited to this. Therefore, the redundant bit lines RBL1 to RBLj can be located to the left of bit lines BL1 to BLn, can be set as a single group between bit lines BL1 to BLn, or can be arranged as multiple groups between bit lines BL1 to BLn.

[0041] Figure 3 This is a block diagram illustrating an example of a repair control circuit 140 according to the concept of the present invention. (Refer to...) Figure 3 The repair control circuit 140 may include a fault address memory 142, a repair unit determiner 144, and an address comparator 146. The fault address memory 142 may be implemented to store the addresses of units detected as faulty during a test operation. In one example, the fault address memory 142 may include non-volatile memory. The repair unit determiner 144 may store ignore address bit information corresponding to address bits ignored during the test operation, and may use the ignore address bit information to determine the repair unit corresponding to the received address (ADDR). In this case, the repair unit may include the type and number of address bits. Finally, the address comparator 146 may compare the received address (ADDR) with the address stored in the fault address memory 142. When the received address (ADDR) matches the stored address, the address comparator 146 may generate an address match signal (HIT).

[0042] Figure 4 This is a diagram illustrating an example of a repair control circuit 140 according to an embodiment of the present invention. (Refer to...) Figure 4The repair control circuit 140 may include a fault address memory 142, a repair unit determiner 144, and an address comparator 146. The fault address memory 142 may store address bit values ​​corresponding to faulty units. For example, the fault address memory 142 may include a first non-volatile memory NVM storing address bits (A0, ..., Ai, Aj, and Ak). In this example, the first non-volatile memory may include multiple fuses corresponding to the address bits (A0, ..., Ai, Aj, and Ak). The repair unit determiner 144 may include a second non-volatile memory 144-1 NVM and an inverter 144-2 (e.g., a third logic circuit). The non-volatile memory 144-1 may store bit values ​​of negligible address bits among the received address bits. These bit values ​​may be used as a select signal (SEL). The inverter 144-2 may receive the output value of the non-volatile memory 144-1 and may invert the received output value to output an inverted select signal (SELB). Address comparator 146 may include first logic circuit 146-1, first selector 146-2 and second logic circuit 146-3 (e.g., AND gate).

[0043] Each of the first logic circuits 146-1 can be implemented as one of the address bits of the receive address buffer 151 and one of the address bits of the corresponding fault address memory 142, and performs an XNOR operation. In one example, the address buffer 151 can be implemented to store the address (ADDR) received from an external device (see [link to relevant documentation]). Figure 3 The received address (ADDR) can store address bit values ​​"1" or "0" corresponding to multiple address bit storage units. Furthermore, at least two address bits (e.g., Ak and Aj) among the multiple address bits (A0, ..., Ai, Aj, and Ak) can be used to determine the type and number of address bits used to determine the repair unit during the repair operation. The repair address bits (Aj and Ak) can be bits that can be ignored ("not concerned") to determine the repair unit.

[0044] The first selector 146-2 can be implemented such that, in response to the select signal (SEL), it outputs any one of the output values ​​of the first logic circuit corresponding to the address bits (Ak and Aj) (e.g., an output value corresponding to SEL). The second logic circuit 146-3 (AND) can be implemented such that it receives the output value of the first logic circuit corresponding to the first address bits (A0, ..., Ai) and the output value of the selector 146-2, and outputs an address match signal (HIT) by performing an AND operation on the received output value.

[0045] Repair line activator 125 can operate in response to the aforementioned address match signal (HIT) to perform a repair operation. Repair line activator 125 may include a second selector 125-1 and a third logic circuit 125-2. The second selector 125-1 can select either address bit (Ak or Aj) in response to an inverted select signal (SELB). For example, if the first selector 146-2 outputs the output value of the first logic circuit corresponding to address bit Ak, the second selector 125-1 selects Aj; if the first selector 146-2 outputs the output value of the first logic circuit corresponding to address bit Aj, the second selector 125-1 selects Ak. The third logic circuit 125-2 can receive the address match signal (HIT) and the output value of selector 125-1, and can perform an AND operation to activate the word line WL or column select line CSL required to drive the redundant unit.

[0046] although Figure 4 The repair control circuit 140 shown uses logic circuit 146-1 to perform an XNOR operation when comparing address bits, but the inventive concept is not limited thereto. For example, the repair control circuit of the inventive concept can also be implemented by logic circuits that perform an XOR operation.

[0047] Figure 5 This is a diagram illustrating an example of a repair control circuit 140a according to another embodiment of the concept of the present invention. (Refer to...) Figure 5 ,and Figure 4 Compared to the "complementary" repair control circuit 140 shown, the repair control circuit 140a can be implemented by logic circuits 146-1a and 146-3a that perform XOR operations. Logic circuit 146-3a performs NAND operations on the output values ​​of the corresponding logic circuits and the output values ​​of selector 146-2.

[0048] In the following description, for ease of explanation, it is assumed that the address is a row address (RA), which comprises 16 address bits (RA1, ..., RA14, RA15, and RA16), and that the repair control circuitry comprises multiple fuse circuits (e.g., fuse circuits FUSE1 to FUSE4 that generate address matching signals HIT1 to HIT4) with a fault address memory and an address comparator. Under these assumptions, Figure 6 This is a diagram illustrating the repair operation based on the fixed repair unit. (Refer to...) Figure 6 Fuse circuits FUSE1 to FUSE4 can each perform repair operations via two redundant word lines. For example... Figure 6 As shown, three fuse circuits, FUSE1, FUSE2 and FUSE3, may be required to repair a faulty cell with a first shape A and a faulty cell with a second shape B.

[0049] Figure 7 This is a diagram illustrating an example of a repair operation based on a variable repair unit according to an invention concept. (Refer to...) Figure 7 The repair operation of the first repair unit RU1 can be performed by fuse circuit FUSE1, and the repair operation of the second repair unit RU2 can be performed by fuse circuit FUSE3. In this case, the first repair unit RU1 can be a unit corresponding to the four redundant word lines RWL1 to RWL4, and the second repair unit RU2 can be a unit corresponding to the two redundant word lines RWL5 and RWL6.

[0050] according to Figure 7 The shapes A and B of the faulty cells shown can be repaired by the type of address bits in RA16 and the number of two repair address bits, where RA16_H represents the 16th bit value of RA (high level) and RA16_L represents the 16th bit value of RA (low level). However, it should be understood that the repair operation conceived in this invention is not limited to such address bit type and number.

[0051] According to an example of a repair control circuit 140 (see reference) Figure 1 The resources of fixed redundant units (e.g., [2KB, 2PXI]) can be converted into flexible redundant units (e.g., [2KB, 2PXI]), [1KB, 4BXI], etc.). Therefore, flexibility is increased even when using the same fuses and redundancy flag signal PRENI. In other words, the repair control circuit 140 can provide convertible redundancy to the memory chip.

[0052] Due to the reduced page size of the circuit, existing circuitry can be used without adding sub-word line drivers SWD and word line enable signals PXB. By adding a multiplexed MUX with a redundant enable signal PRENI, 1 MUX / 1 PRENI may be required at the compare address used to generate the match signal HIT. Furthermore, redundant row addresses can be separated, and the logic for mode register addresses MA1 and MA2 can be increased. The reference fuse F-ref can be changed to serve as a counter input for the data row address DRA. The first fuse address can be changed so that only the first row address RA0 starts with another word line WL (+1 / -1), and the second fuse address can be input as a redundant row address.

[0053] Typically, a minimum page unit (e.g., [1K, 512M]) is feasible without adding SWD, but changes to circuitry such as SWD may be required when implementing more compact page units. Column-blockable failure resolution via row resources is feasible. Operating other units within a single chip (adding 1 bit / 2 PRENI) is feasible, but considering row address RA, etc., setting the TMRSF flag in the test mode register for each chip is also possible.

[0054] Figure 8 This is a flowchart illustrating a repair method according to an example memory device 100. (Refer to...) Figures 1 to 8 The repair method for memory device 100 can be performed as follows. When performing a read operation or a write operation, memory device 100 can receive corresponding commands and addresses (ADDR) from an external device (e.g., a memory controller) (see...). Figure 3 (S110). Repair unit determiner 144 (refer to) Figure 3 It can determine at least one address bit in the received address (ADDR) that will be ignored (S120). For example, such as Figure 7 As shown, when the address (ADDR) is a row address (RA), the fuse circuit FUSE1 and the repair unit determiner 144 (see...) Figure 4 The bits at address 16 (RA16) can be ignored. Address controller 140 (see reference) Figure 3 The received address (ADDR) can be compared with the address stored in the fault address memory 142 (refer to...). Figure 3 The address in the received address (ADDR) is compared (S130). As a result of the address comparison, an address match signal (HIT) can be generated. Subsequently, in response to the address match signal (HIT), the redundant word line or redundant column select line corresponding to the physical address associated with the received address (ADDR) can be activated. Subsequently, a read operation can be performed on the memory cell connected to the activated redundant word line or activated redundant column select line, or a write operation can be performed on the memory cell connected to the activated redundant word line or activated redundant column select line (S140).

[0055] Figure 9 This is a flowchart illustrating an example of a process for repairing a memory device during a test operation, based on an embodiment of the present invention. (Refer to...) Figures 1 to 9 The repair process during the test operation of the memory device 100 can be performed as follows: The test operation can be performed in the wafer-level memory device 100 (S210). Repair processing can be performed based on the fault of the memory cell. Depending on the type of the faulty memory cell, an address bit to be ignored can be set by a fuse-cutting operation (S220). For example, the bit value corresponding to the address bit to be ignored can be stored... Figure 4 The non-volatile memory 144-1 shown in the figure. Thereafter, the fuse information corresponding to the fault address can be stored via a fuse-breaking operation (S230).

[0056] Despite Figure 1 In this context, both row and column addresses have redundant regions, but the present invention is not limited to this. For example, Figure 10 This is a diagram illustrating another example of a memory device 100a according to the concept of the present invention. (Refer to...) Figure 10 ,and Figure 1 Compared to the memory device 100 shown, the memory device 100a may include a memory cell array 110a having a redundant cell array corresponding to row addresses and a repair control circuit 140a that performs repair operations corresponding to the redundant row addresses. Conversely, Figure 11 This is a diagram illustrating another example of a memory device 100b according to the concept of the present invention. (Refer to...) Figure 11 ,and Figure 1 Compared to the memory device 100 shown, the memory device 100b may include a memory cell array 110b having a redundant cell array corresponding to column addresses and a repair control circuit 140b that performs repair operations corresponding to the redundant column addresses.

[0057] Figure 12 This is a diagram illustrating another example of a memory device according to the concept of the present invention. (Refer to...) Figure 12 The memory device 200 may include a memory cell array 210, a row decoder 220, a column decoder 230, a sense amplifier circuit 240, an address register 250, a memory bank control logic 252, a refresh counter 254, a row address multiplexer 256, a column address latch 258, control logic 260, a repair control circuit 266, a timing control circuit 264, an input / output gating circuit 270, an error correction circuit 280, and a data input / output buffer 282.

[0058] The memory cell array 210 may include first memory cell arrays 211 to eighth memory cell arrays 218; however, the number of memory cell arrays constituting the memory cell array 210 is not limited thereto. The row decoder 220 may include first memory cell row decoders 221 to eighth memory cell row decoders 228 respectively connected to the first memory cell arrays 211 to eighth memory cell arrays 218. The column decoder 230 may include first memory cell column decoders 231 to eighth memory cell column decoders 238 respectively connected to the first memory cell arrays 211 to eighth memory cell arrays 218. The sense amplifier circuit 240 may include first memory cell sense amplifiers 241 to eighth memory cell sense amplifiers 248 respectively connected to the first memory cell arrays 211 to eighth memory cell arrays 218.

[0059] The first memory arrays 211 to 218, the first memory row decoders 221 to 228, the first memory column decoders 231 to 238, and the first memory sense amplifiers 241 to 248 can be configured with the first to eighth memory banks respectively. Each of the first memory arrays 211 to 218 may include a plurality of memory cells MC formed at the intersection between the word line WL and the bit line BL.

[0060] In one embodiment of the inventive concept, each of the first memory array 211 to the eighth memory array 218 may include Figure 1 The memory cell array 110 shown includes a normal region 112 and a redundant region 114. Address register 250 can receive and store an address (ADDR) having a bank address (BANK_ADDR), a row address (ROW_ADDR), and a column address (COL_ADDR) from an external memory controller. Address register 250 can provide the received bank address (BANK_ADDR) to bank control logic 252, the received row address (ROW_ADDR) to row address multiplexer 256, and the received column address (COL_ADDR) to column address latch 258.

[0061] The memory bank control logic 252 can generate a memory bank control signal in response to the memory bank address (BANK_ADDR). In response to the memory bank control signal, the memory bank row decoder corresponding to the memory bank address (BANK_ADDR) among the first memory bank row decoders 221 to the eighth memory bank row decoders 228 can be activated. In response to the memory bank control signal, the memory bank column decoders corresponding to the memory bank address (BANK_ADDR) among the first memory bank column decoders 231 to the eighth memory bank column decoders 238 can be activated.

[0062] The row address multiplexer 256 can receive a row address (ROW_ADDR) from the address register 250 and a refresh row address (REF_ADDR) from the refresh counter 254. The row address multiplexer 256 can selectively output either the row address (ROW_ADDR) or the refresh row address (REF_ADDR) as a row address (RA). The row address (RA) output from the row address multiplexer 256 can be applied to the first memory bank row decoder 221 through the eighth memory bank row decoder 228, respectively.

[0063] The bank row decoders activated by the bank control logic 252, from the first bank row decoder 221 to the eighth bank row decoder 228, can decode the row address (RA) output from the row address multiplexer 256 to activate the word line corresponding to the row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address. The activated bank row decoder can also activate the word line corresponding to the row address and can simultaneously activate the redundant word line corresponding to the spare row address (SRA) (also called the 'redundant row address') output from the repair control circuit 266.

[0064] Column address latch 258 can receive a column address (COL_ADDR) from address register 250 and can temporarily store the received column address (COL_ADDR). Furthermore, column address latch 258 can gradually increment the received column address (COL_ADDR) in burst mode. Column address latch 258 can apply the temporarily stored or gradually incremented column address (COL_ADDR) to column decoders 231 through 238 of the first memory bank, respectively.

[0065] The memory bank column decoders 231 through 238, activated by the memory bank control logic 252, can activate sense amplifiers corresponding to the memory bank address (BANK_ADDR) and column address (COL_ADDR) via the input / output gating circuit 270. Furthermore, the activated memory bank column decoders can perform column repair operations in response to the column repair signal (CRP) output from the repair control circuit 266.

[0066] Each input / output gating circuit in the input / output gating circuit 270 may include, in addition to circuitry for gating input / output data, input data masking logic, a read data latch for storing data output from the first memory array 211 to the eighth memory array 218, and a write driver for writing data to the first memory array 211 to the eighth memory array 218.

[0067] Codewords (CW) read from one of the memory arrays 211 through 218 can be sensed by a sense amplifier corresponding to said memory array and stored in a read data latch. After ECC decoding is performed by error correction circuit 280, the codewords (CW) stored in the read data latch are provided to the memory controller via data input / output buffer 282. After ECC encoding is performed by error correction circuit 280, data (DQ) to be written to one of the memory arrays 211 through 218 can be written to said memory array via a write driver.

[0068] The data input / output buffer 282 can provide data (DQ) to the error correction circuit 280 based on the clock signal (CLK) provided from the memory controller during a write operation, and can provide data (DQ) provided from the error correction circuit 280 to the memory controller during a read operation.

[0069] Error correction circuit 280 can generate parity bits based on the data bits of data (DQ) provided from data input / output buffer 282 during a write operation, and can provide a codeword (CW) including data (DQ) and parity bits to input / output gating circuit 270, which can write the codeword (CW) to the memory array.

[0070] Furthermore, during a read operation, the error correction circuit 280 can receive a codeword (CW) read from a memory bank array from the input / output gating circuit 270. The error correction circuit 280 can perform an ECC decoding operation on the data (DQ) by using parity bits included in the read codeword (CW) to correct at least one erroneous bit included in the data (DQ), and provide the corrected bit to the data input / output buffer 282.

[0071] The control logic circuit 260 can be implemented to control the operation of the memory device 200. For example, the control logic circuit 260 can generate control signals that cause the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 260 may include a command decoder 261 for decoding commands (CMD) received from the memory controller and a mode register 262 for setting the operating mode of the memory device 200.

[0072] For example, command decoder 261 can decode write enable signal ( / WE), row address strobe signal ( / RAS), column address strobe signal ( / CAS), chip select signal ( / CS), etc., to generate operation control signals (ACT, PCH, WR, and RD) corresponding to command CMD. Control logic circuit 260 can provide operation control signals (ACT, PCH, WR, and RD) to timing control circuit 264. Control signals (ACT, PCH, WR, and RD) may include activation signal (ACT), precharge signal (PCH), write signal (WR), and read signal (RD). Timing control circuit 264 can generate a first control signal (CTL1) controlling the voltage level of word line WL and a second control signal (CTL2) controlling the voltage level of bit line BL in response to operation control signals (ACT, PCH, WR, and RD), and can provide the first control signal (CTL1) and the second control signal (CTL2) to memory cell array 210.

[0073] Repair control circuit 266 can generate repair control signals (CRP, SEL, EN, and SRA) to control repair operations of a first cell region and a second cell region in at least one memory bank array, based on fuse information for each of the word lines of the row address (ROW_ADDR), column address (COL_ADDR), and address (ADDR) (or access address). Repair control circuit 266 can provide the spare row address (SRA) (or redundant row address) to the corresponding memory bank row decoder, provide the column repair signal (CRP) to the corresponding memory bank column decoder, and provide the select signal (SEL) and enable signal (EN) to the block control circuitry associated with the corresponding spare array block (or redundant array block).

[0074] The repair control circuit 266 can be configured to change the repair unit based on the input address during the repair operation. For example, the repair control circuit 266 can change the repair unit based on the address (ADDR) and fuse information. For example, the repair control circuit 266 can change the type and number of repair address bits based on the address (ADDR) and fuse information.

[0075] An example memory device according to the present invention may store mapping information of logical and physical addresses having multiple bits in a non-volatile memory (NVM), and the type and number of address bits corresponding to a mapping information may be changed. According to one example, the type and number of address bits used to generate such a condition may be changed when all addresses consisting of multiple bits match each other (when a mapping condition is established). In another example, the type and number of address bits may be determined during a test operation and may be stored in the NVM.

[0076] An example memory device according to the present invention may include multiple redundant cells, wherein repair mapping information of the redundant cells may be stored in a separate non-volatile memory (NVM), and due to a repair mapping information, a certain range of normal cells may be repaired to redundant cells of the same range. In this case, the range of the cell region corresponding to the repair mapping information may be changed.

[0077] In one example, during a test operation storing repair mapping information, repair units can be set independently for all mappings. In this case, the repair units set can be stored in each non-volatile memory (NVM). Alternatively, during a test operation storing repair mapping information, repair units can be set jointly for all mappings. In this case, the repair units set can be stored in a single non-volatile memory (NVM).

[0078] The memory chip conceived in this invention can be implemented as a stacked memory chip. For example, Figure 13This is a block diagram illustrating an example of a memory chip according to a concept of the present invention. (Refer to...) Figure 13 The memory chip 1000 may include a first memory die 1100 to a third memory die 1300 and through-silicon vias (TSVs) stacked vertically on the substrate. In this case, the number of stacked memory dies is not limited to... Figure 13 The quantities shown are as follows. For example, the first memory die 1100 and the second memory die 1200 can be slave dies, while the third memory die 1300 can be a master die or a buffer die.

[0079] The first memory die 1100 may include a first memory cell array 1110 and a first through-electrode region 1120 for accessing the first memory cell array 1110. The second memory die 1200 may include a second memory cell array 1210 and a second through-electrode region 1220 for accessing the second memory cell array 1210. In this case, the first through-electrode region 1120 may represent a region in the first memory die 1100 where a through-electrode for communication between the first memory die 1100 and the third memory die 1300 is provided. Similarly, the second through-electrode region 1220 may represent a region in the second memory die 1200 where a through-electrode for communication between the second memory die 1200 and the third memory die 1300 is provided. The through-electrode can provide an electrical path between the first memory die 1100 and the third memory die 1300.

[0080] The first memory die 1100 to the third memory die 1300 can be electrically connected to each other via through electrodes. For example, the number of through electrodes can be hundreds to thousands, and the through electrodes can be arranged in a matrix configuration. The third memory die 1300 may include a first peripheral circuit 1310 and a second peripheral circuit 1320. In this case, the first peripheral circuit 1310 may include circuitry for accessing the first memory die 1100, and the second peripheral circuit 1320 may include circuitry for accessing the second memory die 1200. In one example, each of the peripheral circuits 1310 and 1320 can be electrically connected to each other via through electrodes for performing reference. Figures 1 to 13 The described repair operation is achieved through a method and apparatus.

[0081] According to further embodiments of the inventive concept, the inventive concept can be applied to mobile devices. For example, Figure 14 This is a diagram illustrating a mobile device 3000 from which the inventive concept can be implemented. (Refer to...) Figure 14The mobile device 3000 may include an application processor 3100, at least one DRAM 3200, at least one storage device 3300, at least one sensor 3400, a display device 3500, an audio device 3600, a network processor 3700, and at least one input / output device 3800. For example, the mobile device 3000 may be implemented as a laptop computer, mobile phone, smartphone, tablet computer, or wearable computer.

[0082] Application processor 3100 can be implemented to control the overall operation of mobile device 3000. Application processor 3100 can execute applications that provide internet browsers, games, videos, etc. In one example, application processor 3100 may include single-core or multi-core processors. For example, application processor 3100 may include multi-core processors (such as dual-core, quad-core, hexa-core, etc.). In one example, application processor 3100 may also include internal or external cache memory.

[0083] Application processor 3100 may include controller 3110, neural processor (NPU) 3120, and interface 3130. In one example, NPU 3120 may optionally be provided. In one example, application processor 3100 may be implemented as a system-on-a-chip (SoC). The kernel of the operating system running in the SoC may include an input / output (I / O) scheduler and a device driver that controls storage device 3300. The device driver may control the access performance of storage device 3300 with reference to the number of synchronization queues managed by the I / O scheduler, or it may control CPU mode, DVFS level, etc. in the SoC.

[0084] DRAM 3200 can be connected to controller 3110. DRAM 3200 can store data required for the operation of application processor 3100. For example, DRAM 3200 can temporarily store operating system (OS) and application data, or can be used as execution space for various software codes.

[0085] DRAM 3200 can perform on-die mirroring operations based on requests from application processor 3100 or user selection. DRAM 3200 can be connected to NPU 3120. DRAM 3200 can store data related to artificial intelligence (AI) calculations.

[0086] DRAM 3200 offers relatively lower latency and greater bandwidth compared to I / O devices or flash memory. DRAM 3200 can be initialized when the mobile device is powered on and can be used as a temporary storage location for OS and application data, or as execution space for various software code. The mobile device can perform multitasking operations by simultaneously loading several applications, and the switching and execution speed between applications can be used as a performance indicator of the mobile device.

[0087] Storage device 3300 can be connected to interface 3130. In one example, interface 3130 can operate via any of the following communication protocols: DDR, DDR2, DDR3, DDR4, Low Power DDR (LPDDR), Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnect (PCI), High-Speed ​​Non-Volatile Memory (NVMe), High-Speed ​​Peripheral Component Interconnect (PCIe), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Universal Storage Bus (USB) Attached SCSI (UAS), Internet Small Computer System Interface (iSCSI), Fibre Channel, and Fibre Channel over Ethernet (FCoE). In one example, any storage device 3300 can be included in mobile device 3000 in an embedded form. In another example, any storage device 3300 can be included in mobile device 3000 in a removable manner.

[0088] Storage device 3300 can be implemented to store user data. For example, storage device 3300 can store data collected from sensor 3400, or it can store data network data, augmented reality (AR) / virtual reality (VR) data, or high-definition (HD) 4K content. Storage device 3300 may include at least one non-volatile memory device. For example, storage device 3300 may include a solid-state drive (SSD), an embedded multimedia card (eMMC), etc.

[0089] In one example, the storage device 3300 may be implemented as a separate chip within the application processor 3100, or it may be implemented together with the application processor 3100 as a single package. In another example, various types of packages can be used to mount the storage device 3300. For example, packages such as PoP, BGA, CSP, PLCC, PDIP, die-in-waffle pack, die-in-wafer form, COB, CERDIP, MQFP, TQFP, SOIC, SSOP, TSOP, SIP, MCP, WFP, and WSP can be used to mount the storage device 3300.

[0090] Sensor 3400 can be implemented to sense the external environment of mobile device 3000. In one example, sensor 3400 may include an image sensor that senses images. In this case, sensor 3400 can send the generated image information to application processor 3100. In another example, sensor 3400 may include a biosensor that senses biometric information. For example, sensor 3400 can sense fingerprints, iris patterns, vascular patterns, heart rate, blood glucose levels, etc., and can generate sensing data corresponding to the sensed information. On the other hand, sensor 3400 is not limited to image sensors and biosensors. For example, sensor 3400 may include other types of sensors (such as illuminance sensors, acoustic sensors, accelerometers, etc.).

[0091] The display device 3500 can be implemented to output data. For example, the display device 3500 can output image data sensed by the sensor 3400 or data calculated by the application processor 3100.

[0092] Audio device 3600 can be implemented to externally output voice data or sense external voice. Network processor 3700 can be implemented to communicate with external devices via wired or wireless communication methods. Input / output device 3800 can be implemented to input data to or output data from mobile device 3000. Input / output device 3800 may include devices that provide digital input and output functions (such as USB, storage devices, digital cameras, SD cards, touch screens, DVDs, modems, and network adapters).

[0093] The embodiments of this invention can also be applied to various types of computing systems (e.g., CPU / GPU / NPU platforms). For example, Figure 15 This is a diagram illustrating an example of a computing system 4000 according to a concept of the present invention. (Refer to...) Figure 15 The computing system 4000 may include a central processing unit (CPU) 4110, a graphics processing unit (GPU) 4120, and / or a neural processing unit (NPU) 4130 (or a dedicated processor) connected to a system bus 4001; a memory device 4210 and / or a storage device 4220 connected to the system bus 4001; and an input / output device 4310, a modem 4320, a network device 4330, and / or a storage device 4340 connected to an expansion bus 4002. In this case, the expansion bus 4002 may be connected to the system bus 4001 via an expansion bus interface 4003.

[0094] In one example, the CPU 4110, GPU 4120, and NPU 4130 may include on-chip caches 4111, 4121, and 4131, respectively. In another example, the CPU 4110 may include off-chip cache 4112. Although not explicitly stated... Figure 15 As shown, each of the GPU 4120 and NPU 4130 may also include an off-chip cache. In one example, the off-chip cache 4112 is internally connected to the CPU 4110, GPU 4120, and NPU 4130 via different buses.

[0095] In one example, on-chip / off-chip cache may include volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) or non-volatile memory (such as NAND flash memory, phase random access memory (PRAM), resistive random access memory (RRAM), etc.).

[0096] In one example, main memories 4114, 4124, and 4134 can be connected to CPU 4110, GPU 4120, and NPU 4130 via corresponding memory controllers 4113, 4123, and 4133. In another example, memories 4116, 4126, and 4136 can be connected to CPU 4110, GPU 4120, and NPU 4130 via bridges 4115, 4125, and 4135. Bridges 4115, 4125, and 4135 may include memory controllers that control the corresponding memories 4116, 4126, and 4136. In one example, bridges 4115, 4125, and 4135 may be implemented as a network device, a wireless network device, a switch, a bus, a cloud, or an optical channel, respectively.

[0097] In one example, memories 4124 and 4126 may include GPU memory. GPU memory can hold instructions and data that can interact with the GPU. Commands and data can be copied from main memory or a storage device. GPU memory can store image data and can have greater bandwidth than main memory. GPU memory can have its clock separate from the CPU. The GPU can read and process image data in GPU memory and then write it back to GPU memory. GPU memory can be configured to accelerate graphics processing.

[0098] In one example, memories 4134 and 4136 may include NPU memory. NPU memory stores instructions and data that can interact with the NPU. Commands and data can be copied from main memory or a storage device. NPU memory holds the weight data of the neural network. NPU memory can have greater bandwidth than memory. NPU memory can separate the clock from the CPU. The NPU can read and update the weight data in NPU memory and then write it back to NPU memory during training. NPU memory can be configured to accelerate machine learning (such as neural network training and inference).

[0099] In some examples, each of main memories 4114, 4116, 4124, 4126, 4134, and 4136 can be implemented as an execution reference. Figures 1 to 13 The memory chip described in the repair operation.

[0100] In one example, the main memory may include volatile memory (such as DRAM, SRAM, etc.) or non-volatile memory (such as NAND flash memory, PRAM, RRAM, etc.). The main memory has lower latency and lower capacity than the secondary storage devices 4210 and 4220.

[0101] CPU 4110, GPU 4120, or NPU 4130 can access auxiliary storage devices 4210 and 4220 via system bus 4001. Storage device 4210 can be controlled by memory controller 4211 connected to system bus 4001. Storage device 4220 can be controlled by memory controller 4221. Memory controller 4221 can be connected to system bus 4001.

[0102] Storage device 4220 may be implemented to store data. Storage controller 4221 may be implemented to read data from storage device 4220 and send the read data to a host. Storage controller 4221 may be implemented to store the sent data in storage device 4220 in response to a request from the host. Each of storage device 4220 and storage controller 4221 may include a buffer that stores metadata, a read cache for storing frequently accessed data, or a cache for improving write efficiency. For example, a write cache may receive and process a specific number of write requests. Furthermore, storage device 4220 may include volatile memory (such as a hard disk drive (HDD)) and non-volatile memory (such as NVRAM, SSD, SCM, or new memory).

[0103] One example of the inventive concept can be applied to a data server system. For example, Figure 16 This is a diagram illustrating an example of a data server system 5000 according to a concept of the present invention. (Refer to...) Figure 16 The data server system 5000 may include a first server 5100 (application server), a second server 5200 (storage server), a memory device 5310, and at least one storage device 5320.

[0104] Each of the first server 5100 and the second server 5200 may include at least one processor and memory. In one example, each of the first server 5100 and the second server 5200 may be implemented as a memory-processor pair. In another example, each of the first server 5100 and the second server 5200 may be implemented using a different number of processors and memory suitable for use.

[0105] In one example, the first server 5100 and the second server 5200 can communicate via the first network 5010. In one example, each of the first server 5100 and the second server 5200 can access the storage device 5310 via the first network 5010 and / or the second network 5020. In one example, each of the first server 5100 and the second server 5200 can access the storage device 5320 directly or indirectly via the first network 5010 and the second network 5020.

[0106] In one example, the interface I / F of storage device 5320 may include SATA, SAS, PCIe, DIMM, HBM, HMC, or NVDIMM. In one example, the second network 5020 may be a connection type for direct-attached storage (DAS), network-attached storage (NAS), and storage area network (SAN) solutions.

[0107] In one example, memory device 5310 and storage device 5320 can send device information to server 5200 via command or independently. In one example, memory device 5310 can be implemented to execute references. Figures 1 to 13 The described repair operation involves a memory chip. The data server system 5000 can perform big data AI computations. In this case, big data may include audio, photos, videos, or weighted data / training data.

[0108] In the memory device and its repair method according to the present invention, the repair unit is variable by setting the bit type or the number of addresses differently according to the fault address.

[0109] Although examples have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined in the appended claims.

Claims

1. A memory device, comprising: An address buffer is configured to store multiple bits of the received address; The first non-volatile memory is configured to store multiple bits of the fault address; Multiple first logic circuits are each configured to compare a bit of a received address stored in an address buffer with a corresponding bit of a fault address stored in a first non-volatile memory. The first selector is configured to output a selected output value from two output values ​​of two of the plurality of first logic circuits in response to a selection signal; The second logic circuit is configured to output an address matching signal based on the selected output value and the output values ​​of the remaining first logic circuits other than the two first logic circuits. The second non-volatile memory is configured to store the address bit value corresponding to the selection signal; The second selector is configured to output one of the address bits corresponding to the two first logic circuits in response to an inverted select signal. and The third logic circuit is configured to perform an AND operation on the address matching signal and the output value of the second selector.

2. The memory device according to claim 1, wherein, The received address is either a row address or a column address.

3. The memory device according to claim 1, wherein, Each of the plurality of first logic circuits is configured to perform an XOR operation; and wherein the second logic circuit performs an AND operation.

4. The memory device according to claim 1, wherein, Each of the plurality of first logic circuits is configured to perform an XOR operation; and wherein the second logic circuit performs a NAND operation.

5. The memory device according to claim 1, wherein, The received address is a 16-bit row address; and wherein the first address bit and the sixteenth address bit are among the address bits of each of the first selector and the second selector that receive the row address.

6. The memory device according to claim 5, wherein, The second non-volatile memory stores the bit value at address sixteen.

7. The memory device according to claim 5, wherein, Each of the first non-volatile memory and the second non-volatile memory includes at least one fuse.

8. The memory device according to any one of claims 5, 6, and 7, wherein, The first non-volatile memory stores mapping information about logical addresses and their corresponding physical addresses; and the bit type and number of addresses corresponding to the mapping information are variable.

9. A memory device, comprising: The memory cell array has redundant regions corresponding to redundant word lines and / or redundant bit lines, as well as normal regions corresponding to word lines and bit lines. The line decoder is configured to activate at least one word line and / or activate at least one redundant word line in response to a line address. The column decoder is configured to activate at least one of the bit lines and / or activate at least one of the redundant bit lines in response to a column address. and The repair control circuit is configured to: compare a row address with a stored faulty row address, compare a column address with a stored faulty column address, control the row decoder to activate at least one of the redundant word lines when the row address corresponds to the faulty row address, and control the column decoder to activate at least one of the redundant bit lines when the column address corresponds to the faulty column address. The repair control circuit includes an address comparator, which includes: Multiple first logic circuits are each configured to: compare one address bit from the received input address bits with the address bit corresponding to the one address bit from a plurality of stored fault address address bits; A selector is configured to select an output value of at least two of the plurality of first logic circuits in response to a selection signal; and The second logic circuit is configured to output an address matching signal based on the output value of the selector and the output values ​​of the remaining first logic circuits (excluding the at least two first logic circuits).

10. The memory device according to claim 9, wherein, The repair unit includes: the type of address bits and / or the number of address bits.

11. The memory device according to claim 9, wherein, Repairing the control circuit also includes: The fault address memory is configured to store fault row addresses and / or fault column addresses; and A repair unit determiner is configured to determine the repair unit corresponding to the input address, wherein the address comparator is configured to compare the row address with the faulty row address and / or compare the column address with the faulty column address.

12. The memory device according to claim 11, wherein, The fault address memory includes: a first non-volatile memory that stores multiple address bits corresponding to the fault address.

13. The memory device according to claim 12, wherein, The repair unit determiner includes: A second non-volatile memory is configured to store at least one address bit from the plurality of address bits that is ignored during the repair operation and outputs a selection signal; and An inverter is configured to invert the selection signal.

14. The memory device according to claim 13, wherein, Each of the plurality of first logic circuits is configured to: receive an address bit from the input address bits and an address bit corresponding to the stated address bit stored in a first non-volatile memory, and perform an XOR operation on the stated address bit and the stored address bit; and The second logic circuit is configured to output an address matching signal by performing a logical AND operation on the output value of the selector and the output values ​​of the remaining first logic circuits excluding at least two of the plurality of first logic circuits.

15. The memory device according to claim 13, wherein, Each of the plurality of first logic circuits is configured to: receive an address bit from the input address bits and an address bit corresponding to the stated address bit stored in a first non-volatile memory, and perform an XOR operation on the stated address bit and the stored address bit; and The second logic circuit is configured to output an address matching signal by performing a logical AND-NOT operation on the output value of the selector and the output values ​​of the remaining first logic circuits excluding at least two of the plurality of first logic circuits.

16. The memory device according to claim 14 or 15, wherein, In response to the address matching signal of the address comparator and the inverted selection signal of the repair unit determiner, redundant word lines and / or redundant bit lines are activated.

17. A method for repairing a memory device, comprising: Receiving address; The repair unit is determined using at least one address bit from the received address that will be ignored during the repair operation. Compare the received address with the stored fault address; and When the received address corresponds to a stored fault address, the redundant cell array with repair units is accessed in response to that address. The step of comparing the received address with the stored fault address includes: Multiple first logic circuits compare one address bit from the address bits of the received address with the address bit corresponding to the one address bit from the multiple address bits of the stored fault address. The selector responds to a selection signal to select an output value of at least two of the plurality of first logic circuits; and The second logic circuit outputs an address matching signal based on the output value of the selector and the output values ​​of the remaining first logic circuits (excluding the at least two first logic circuits).

18. The repair method according to claim 17, further comprising: During the test operation, the mapping information about the logical address and the physical address corresponding to the address is stored in non-volatile memory.

19. The repair method according to claim 17 or 18, wherein, The steps for determining the repair unit include: determining the type and number of address bits during the repair operation.

20. The repair method according to claim 17 or 18, further comprising: Store repair mapping information for redundant units; and The repair mapping information is used to repair normal cells using redundant cells, and The memory cell region corresponding to the repair mapping information is variable.

Images