Method of manufacturing a semiconductor device

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device. After a polishing step, a portion of each gate electrode is removed so that, in a cross-sectional view, an upper surface of each gate electrode is closer to a main surface of a semiconductor substrate than a damaged region formed in a gate insulating film located between the gate electrodes. Thus, a short defect occurring during operation of the semiconductor device can be suppressed.

Description

[0001] Technical Field The present invention relates to a method for manufacturing a semiconductor device, and the invention can be suitably used, for example, in a method for manufacturing a semiconductor device having non-volatile memory. Background Technology

[0002] Memory devices, such as flash memory (widely used as electrically writable and electrically erasable non-volatile semiconductor memory devices), have a conductive floating gate electrode or a trapped insulating film sandwiched between oxide films below the gate electrode of a MISFET. The charge accumulation state in the floating gate electrode or the trapped insulating film is then used as stored information, which is read out as the threshold of a transistor. Here, the trapped insulating film refers to an insulating film capable of accumulating charge, and, for example, a silicon nitride film can be given. By injecting charge into or releasing charge from the insulating film, the MISFET threshold is shifted to operate as a memory element.

[0003] As flash memory, for example, there are flash memories with an SG-MONOS (split-gate metal-oxide-semiconductor) structure disclosed in Japanese Unexamined Patent Application Publication No. 2008-211016 and Japanese Unexamined Patent Application Publication No. 2014-154790. In such a memory, since the silicon nitride film is used as the charge storage region and the charge is accumulated discretely, the reliability of data retention is superior to that of a conductive floating gate electrode. In addition, because of the excellent reliability of data retention, the thickness of the oxide film located above and below the silicon nitride film can be reduced, thereby reducing the voltage required for data write / erase operations.

[0004] The inventors have further investigated the miniaturization of semiconductor devices, enabling corresponding operations such as "writing," "reading," and "erasing" of data to be performed at high speeds compared to split-gate non-volatile memory, as shown in Japanese Unexamined Patent Application Publication No. 2008-211016 and Japanese Unexamined Patent Application Publication No. 2014-154790. When semiconductor devices are further miniaturized, it has been discovered that short-circuit defects may occur between the two gate electrodes of the memory cells constituting split-gate non-volatile memory.

[0005] Other objects and novel features will become clear from the description and accompanying drawings in this specification.

[0006] Typical embodiments disclosed in this application will be briefly described below.

[0007] A method of manufacturing a semiconductor device in one embodiment includes the step of removing a portion of each of a first gate electrode and a second gate electrode such that, in a cross-sectional view, the upper surface of each of the first gate electrode and the second gate electrode is closer to a first main surface of the semiconductor substrate than a damaged region formed in a second gate insulating film located between the first gate electrode and the second gate electrode.

[0008] The semiconductor device manufacturing method according to this embodiment can suppress short-circuit defects during the operation of the semiconductor device. Attached Figure Description

[0009] Figure 1 This is a process flow diagram illustrating the manufacturing process of a semiconductor device according to one embodiment;

[0010] Figure 2 This is a cross-sectional view of the main parts of a semiconductor device during the manufacturing process according to one embodiment;

[0011] Figure 3 It continues Figure 2 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0012] Figure 4 It continues Figure 3 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0013] Figure 5 It continues Figure 4 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0014] Figure 6 It continues Figure 5 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0015] Figure 7 It continues Figure 6 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0016] Figure 8 It continues Figure 7 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0017] Figure 9 It continues Figure 8 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0018] Figure 10 It continues Figure 9 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0019] Figure 11 It continues Figure 10 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0020] Figure 12 It continues Figure 11 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0021] Figure 13 It continues Figure 12 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0022] Figure 14 It continues Figure 13 A cross-sectional view of the main parts of a semiconductor device during the manufacturing process;

[0023] Figure 15 It is a cross-sectional view of the main part of the semiconductor device based on the modified Example 1;

[0024] Figure 16 It is a cross-sectional view of the main parts of a semiconductor device based on a research example;

[0025] Figure 17 This is an equivalent circuit diagram of the memory cell for each of the embodiments and research examples; and

[0026] Figure 18 This is an example table showing the voltage values ​​applied to each part of the selected memory cell during "Write", "Erase", and "Read". Detailed Implementation

[0027] In the following embodiments, for convenience, the embodiments are described by dividing them into multiple parts or embodiments. However, unless specifically stated otherwise, they are not independent of each other, and one part or embodiment relates to some or all of the other parts or embodiments, including examples of modifications, details, supplementary descriptions, etc. In the following embodiments, the number of elements, etc. (including the number of elements, numerical values, quantities, ranges, etc.) is not limited to a specific number, but may be not less than or equal to a specific number, unless specifically indicated and explicitly limited to a specific number in principle. Furthermore, in the following embodiments, it goes without saying that constituent elements (including element steps, etc.) are not essential, unless they are specifically specified or are considered obviously necessary in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., it is assumed that the shape, etc., is substantially approximate or similar to the shape, etc., unless they are specifically specified or are considered obviously necessary in principle. The same provisions apply to the numerical values ​​and ranges described above.

[0028] Details of the embodiments will be described based on the accompanying drawings. In all the drawings used to illustrate the embodiments, components with the same function are represented by the same reference numerals, and repeated descriptions are omitted. In the following embodiments, unless specifically necessary, descriptions of the same or similar parts will generally not be repeated.

[0029] In the accompanying drawings used in the embodiments, section lines may be omitted even in the case of cross-sectional views to make the drawings easier to read. Furthermore, section lines may be used even in the case of plan views to make the graphics easier to read.

[0030] (Research Example)

[0031] First, before describing the semiconductor device and its manufacturing method in this embodiment, for convenience, reference will be made to... Figures 16 to 18 Describe a research example conducted by the inventors. Figure 16 This is a cross-sectional view of the main part of the semiconductor device SMD11 studied by the inventors. Figure 17 It is formed in Figure 16 The equivalent circuit diagram of memory cell MC11 in memory cell formation region 1R is shown. Figure 18 This is an example table showing the voltage values ​​applied to each part of the selected memory cell during "Write", "Erase", and "Read". Figure 17 This is an equivalent circuit diagram of the memory cell MC1 of this embodiment, which will be described later. Figure 18 Each voltage value shown is also the voltage value used for each operation of the memory cell MC1 in this embodiment, which will be described later.

[0032] <Structure of the SMD11 semiconductor device in the research example>

[0033] like Figure 16 and 17 As shown, in the memory cell formation region 1R, a memory cell MC11, a so-called split-gate type non-volatile memory, is formed. This memory cell MC11 consists of a control transistor STR11 with a control gate electrode CG11 and a memory transistor MTR11 with a memory gate electrode MG11. On the other hand, in the peripheral circuit formation region 2R, as... Figure 16 As shown, a field-effect transistor (PTR) forms a component of peripheral circuits such as input / output circuits. Note that the control transistor STR11 and memory transistor MTR11 that form the memory cell MC11, as well as the PTR that forms the peripheral circuit, are electrically isolated from each other by a device isolation portion (not shown) formed in the device isolation region. In fact, multiple memory cells MC11 are formed in an array on the semiconductor substrate SB, and the multiple memory cells MC11 are also electrically isolated from each other by the aforementioned device isolation portion.

[0034] like Figure 16 As shown, the control gate electrode CG11 of the control transistor STR11 is formed on the main surface MS1 of the semiconductor substrate SB located in the memory cell formation region 1R, and a gate insulating film GI1 is inserted between the gate electrode CG11 and the main surface MS1. The memory gate electrode MG11 of the memory transistor MTR11 is formed on the main surface MS1 of the semiconductor substrate SB located in the memory cell formation region 1R via a gate insulating film GI2 having a charge storage region CTR. Furthermore, the gate electrode GE of the field-effect transistor PTR is formed on the main surface MS1 of the semiconductor substrate SB located in the peripheral circuit formation region 2R via a gate insulating film GI3 and an insulating film HK formed on the gate insulating film GI3. Each of the control gate electrode CG11 of the control transistor STR11 and the memory gate electrode MG of the memory transistor MTR11 is made of, for example, polysilicon. Specifically, each of the control gate electrode CG11 and the memory gate electrode MG is made of doped polysilicon that has been introduced or ion-implanted with impurities. On the other hand, the gate electrode GE of the field-effect transistor PTR is made of, for example, a metal such as aluminum (Al). Specifically, as Figure 16 As shown, the gate electrode GE is a laminated film formed on the insulating film HK, comprising a metal film ME1 made of titanium aluminum (TiAl) and a metal film ME2 made of aluminum (Al) formed on the metal film ME1. The threshold voltage of the field-effect transistor PTR can be adjusted (controlled) by the work function of the metal film ME1 made of titanium aluminum. The thickness of the metal film ME2 is greater than the thickness of the metal film ME1. The insulating film HK is a so-called high-k film (high dielectric constant film), which is made of a material with a dielectric constant (relative dielectric constant) higher than that of silicon nitride such as hafnium oxide.

[0035] like Figure 16As shown, the gate insulating film GI2, which has a charge storage region CTR, has an insulating film IF1 formed on the main surface MS1 of the semiconductor substrate SB located in the memory cell formation region 1R, an insulating film IF2 formed on the insulating film IF1, and an insulating film IF3 formed on the insulating film IF2. Of the three insulating films IF1, IF2, and IF3, the insulating film IF1 closest to the semiconductor substrate SB and the insulating film IF3 closest to the memory gate electrode MG are made of, for example, silicon oxide (SiO). On the other hand, the insulating film IF2 sandwiched between the two insulating films IF1 and IF3 is an insulating film with trapping properties and is made of, for example, silicon nitride (SiN). That is, the two insulating films IF1 and IF3 made of silicon oxide serve as charge blocking layers or charge confinement layers, and the insulating film IF2 made of silicon nitride serves as the aforementioned charge storage region CTR. In other words, the non-volatile memory discussed by the inventors is a MONOS (metal oxide nitride oxide semiconductor) structure. Of the three insulating films IF1, IF2, and IF3 that make up the gate insulating film GI2, the thickness of insulating film IF1, which is closest to the semiconductor substrate SB, and the thickness of insulating film IF3, which is closest to the memory gate electrode MG, are, for example, 2 nm to 10 nm. The thickness of insulating film IF2, which serves as the charge storage region CTR, is, for example, 5 nm to 15 nm.

[0036] The control transistor STR11 is also used as a selection transistor for the memory. Therefore, the control gate electrode CG11 serves as the selection gate electrode. On the other hand, the memory transistor MTR11 is a storage transistor.

[0037] The configuration of memory cell MC11 will be described in more detail below.

[0038] First, such as Figure 16 As shown, the gate insulating film GI2 has a portion CTP1 located between the gate electrode GE12 (serving as the memory gate electrode MG) and the semiconductor substrate SB, and a portion CTP2 located between the gate electrode GE1 and the gate electrode GE12 (serving as the control gate electrode CG11). That is, as Figure 16 As shown, two gate electrodes GE11 and GE12 are adjacent to each other, and a gate insulating film GI2 is disposed between the two gate electrodes GE11 and GE12. In other words, the two gate electrodes GE1 and GE2 are electrically isolated from each other through the gate insulating film GI2. A silicide layer SL2 is formed on each of the two gate electrodes GE11 and GE12 exposed from the interlayer insulating film IL1, which includes a contact interlayer insulating layer CIL. Figure 16As shown, the upper surfaces SLS11 and SLS12 of each silicide layer SL2, and the upper surface (end face) IFS of a portion of the CTP2 of the gate insulating film GI2 exposed from the two gate electrodes GE11 and GE12, are at substantially the same height. Note that the term "substantially the same height" here means that they are at the same height in design, and takes into account variations in manufacturing.

[0039] Next, Figure 16 The semiconductor region SDR1 shown is the semiconductor region used as the source / drain of the memory cell MC11. Conductive impurities are implanted into the semiconductor region SDR1 by ions. More specifically, as... Figure 16 As shown, a well region WELL containing conductive impurities implanted by ions is formed in a semiconductor substrate SB. A semiconductor region SDR1 is formed in the well region WELL. The polarity of the impurities constituting the well region WELL differs from the polarity of the impurities constituting the semiconductor region SDR1. For example, the well region WELL is formed by implanting p-type impurity ions, such as boron (B), into the semiconductor substrate SB. On the other hand, the semiconductor region SDR1 is formed by implanting n-type impurity ions, such as arsenic (As) or phosphorus (P), into the semiconductor substrate SB. That is, the memory cell MC11 is an n-channel field-effect transistor. The memory cell MC11 can be a p-channel field-effect transistor. In this case, n-type impurities are implanted into the well region WELL, and p-type impurities are implanted into the semiconductor region SDR1.

[0040] like Figure 16 As shown, the semiconductor region SDR1 has a lightly doped drain structure. Specifically, the semiconductor region SDR1 includes an extended region EX1 made of impurities of a first concentration of conductivity type, and a diffused region SD1 made of impurities of a second concentration of conductivity type, higher than the first concentration. The polarity of the impurities constituting the extended region EX1 is the same as the polarity of the impurities constituting the diffused region SD1. Figure 16 As shown, the diffusion region SD1 is in contact with the extension region EX1. Figure 16 As shown, the extended region EX1 and the diffused region SD1 are formed in a self-aligned manner relative to the gate electrodes GE11, GE12 and the sidewall spacer SW1, respectively. Furthermore, the extended region EX1 is formed under the following implantation conditions: the implantation energy of the aforementioned impurities is, for example, 5 keV to 25 keV, and the dose of the aforementioned impurities is, for example, about 1 × 10⁻⁶. 14 / cm 2 On the other hand, the diffusion region SD1 is a region formed under the following injection conditions: the injection energy of the aforementioned impurities is, for example, 5 keV to 25 keV, and the dose of the aforementioned impurities is, for example, about 1 × 10⁻⁶. 15 / cm 2 .

[0041] In addition, such as Figure 16 As shown, the extended region EX1 is formed at a location overlapping with the sidewall spacer SW1 in the well region WELL. Here, the sidewall spacer SW1 is formed from: an insulating film made of silicon oxide, an insulating film made of silicon nitride, or a laminated structure of an insulating film made of silicon oxide and an insulating film made of silicon nitride. Figure 16 As shown, sidewall spacers SW1 are formed on the respective side surfaces of the control gate electrode CG11 and the memory gate electrode MG11 to cover the respective side surfaces of the control gate electrode CG11 and the memory gate electrode MG11, as well as the main surface MS1 of the semiconductor substrate SB located in the memory cell formation region 1R. In other words, as Figure 16 As shown, sidewall spacers SW1 are formed on the main surface MS1 of the semiconductor substrate SB located in the memory cell formation region 1R, to sandwich two gate insulating films GI1 and GI2, and the gate electrodes GE11 and GE12 forming the memory cell MC11. On the other hand, as... Figure 16 As shown, the diffusion region SD1 is formed in the well region WELL at a location exposed from the corresponding sidewall SW1. That is, the extension region EX1 and the diffusion region SD1 are not formed at locations overlapping with the gate insulating films GI1 and GI2, and the gate electrodes GE11 and GE12 that constitute the memory cell MC11, respectively.

[0042] like Figure 16 As shown, the thickness of the diffusion region SD1 (i.e., the depth from the main surface MS1 of the semiconductor substrate SB to the bottom of the diffusion region SD1) is greater (deeper) than the thickness of the extension region EX1 (i.e., the depth from the main surface MS1 of the semiconductor substrate SB to the bottom of the extension region EX1).

[0043] In the well region WELL, the channel region of memory cell MC11 is the channel region between two adjacent extended regions EX1 in the gate length direction of memory cell MC11, and at the location where this channel region overlaps with each of the gate electrodes GE11 and GE12. Specifically, in semiconductor substrate SB, the channel region of control transistor STR11 is formed directly below the gate electrode GE11 (i.e., the gate insulating film GI1). In semiconductor substrate SB, the channel region of memory transistor MTR11 is formed directly below the gate electrode GE12 (i.e., a portion CTP1 of the gate insulating film GI2).

[0044] <Operation of the SMD11 semiconductor device in the research example>

[0045] Next, the operation of the memory cell MC11 studied by the inventors will be described. The operation of the memory cell MC11 includes a "write" operation for storing information in the memory cell MC11, a "read" operation for reading information stored in the memory cell MC11, and an "erase" operation for erasing information stored in the memory cell MC11.

[0046] First, the “write” operation studied by the inventors will be described. The inventors have used a so-called SSI (source-side injection) system, in which electrons are injected into the charge storage region CTR of the gate insulating film GI2, for example, when writing data to the memory cell MC11. Specifically, the inventors inject electrons into the selected memory cell (here, MC11). Figure 16 Each part of the memory cell MC11 shown is applied to Figure 18 The table shows the voltage values, each corresponding to a "write" operation. Here, in Figure 18 In the table, "Vcg" represents the components to be applied to... Figure 16 and 17 The voltage of the control gate electrode CG11 is shown, and "Vmg" is the voltage to be applied to the gate electrode. Figure 16 and 17 The voltage at the memory gate electrode MG11 is shown. "Vd" is the voltage applied to... Figure 16 and 17 The voltage of one of the two semiconductor regions SDR1 (here, the drain) is shown, and "Vs" is the voltage applied to... Figure 16 and 17 The voltage of the other (here, the source) in the two semiconductor regions SDR1 shown. Furthermore, "Vb" is the voltage applied to... Figure 16The base voltage of the well region WELL is shown. As described above, by applying a voltage corresponding to the "write" operation to the corresponding portion, a channel region is formed between the two semiconductor regions SDR1 constituting the selected memory cell (i.e., the overlapping location with each of the control gate electrode CG11 and the memory gate electrode MG11), and hot electrons (electrons accelerated by the electric field) generated in the channel region are injected into the charge storage region CTR of the selected memory cell (more specifically, the portion CTP1 of the insulating film IF2 located between the memory gate electrode MG11 and the semiconductor substrate SB), the selected memory cell being formed in the well region WELL in the semiconductor substrate SB. The hot electrons injected into the charge storage region CTR are trapped by the trapping energy level of the insulating film IF2 made of silicon nitride, and due to the trapping energy level of the hot electrons injected into the charge storage region CTR, the threshold voltage of the memory transistor MTR11 rises. That is, the memory transistor MTR11 is in a write state. In the SSI type, hot electrons are injected into the charge storage region CTR (i.e., insulating film IF2) through insulating film IF1, which is located between insulating film IF2, which serves as the charge storage region CTR, and the semiconductor substrate SB. Therefore, in order to perform the "write" operation at high speed, it is preferable to reduce the thickness of the gate insulating film GI2 (i.e., insulating film IF1).

[0047] Next, the "erasure" operation studied by the inventors will be described. The inventors have used, for example, the so-called BTBT (band-to-band tunneling) method, in which holes are injected into the charge storage region CTR of the gate insulating film GI2 when erasing data written into the memory cell MC11. Specifically, the inventors inject holes into the selected memory cell (here, MC11). Figure 16 Each part of the memory cell MC11 shown is applied to Figure 18 The table shows the voltage values ​​corresponding to each "erase" operation. As described above, by applying each voltage corresponding to the "erase" operation to each part, the generated holes are accelerated by the electric field, and the accelerated holes are injected into the charge accumulation region CTR. As a result, the threshold voltage of the memory transistor MTR11 decreases. That is, the memory transistor MTR11 is erased. In the SSI type, holes are injected into the charge storage region CTR (i.e., insulating film IF2) through the insulating film IF1, which is located between the insulating film IF2, which serves as the charge storage region CTR, and the semiconductor substrate SB. Therefore, in order to perform the "erase" operation at high speed, it is preferable to reduce the thickness of the gate insulating film GI2 (i.e., insulating film IF1).

[0048] Next, the "read" operation studied by the inventors will be described. For example, when reading data written to memory cell MC11, the inventors direct the data to the selected memory cell (here, MC11). Figure 16 Each part of the memory cell MC11 shown is applied to Figure 18 The table shows the voltage values ​​corresponding to each "read" operation. Specifically, in order to distinguish each of the read, write, and erase states, the inventors set the voltage Vmg applied to the memory gate electrode MG11 during the "read" operation to a value between the voltage Vmg applied to the memory gate electrode MG11 during the "write" operation and the voltage Vmg applied to the memory gate electrode MG11 during the "erase" operation.

[0049] <Problems discovered by the inventor>

[0050] The problems discovered by the inventors will be described below.

[0051] The inventor has discovered that when Figure 18 The voltage shown in the table is applied to Figure 16 When the corresponding portion of the memory cell MC11 shown is used, a short-circuit defect may occur between the gate electrode GE11 (i.e., the control gate electrode CG11) constituting the memory cell MC11 and the gate electrode GE12 (i.e., the memory gate electrode MG11) also constituting the memory cell MC11. Figure 16 As shown, the inventors of this invention investigated the cause and found that a damaged region (damaged layer) DMG was formed in a portion of the CTP2 of the gate insulating film GI2 located between the two gate electrodes GE11 and GE12 (more specifically, between the silicide layer SL2 formed on the gate electrode GE11 and the silicide layer SL2 formed on the gate electrode GE12). Furthermore, it has been clarified through the inventors' research that the aforementioned short-circuit fault is likely to occur through the damaged region. According to the inventors' research, this short-circuit defect tends to occur when the thickness of the gate insulating film GI2 is thinner. Moreover, the greater the difference between the voltage Vcg applied to the control gate CG11 and the voltage Vmg applied to the memory gate electrode MG11, the more likely this difference is to occur. In the semiconductor device SMD11 studied by the inventors, short-circuit defects are likely to occur significantly, especially during "write" operations (see...). Figure 18 ).

[0052] like Figure 16 As shown, the damaged region DMG includes the exposed upper surface IFS of each of the two gates GE11 and GE12 within a portion of the CTP2 of the gate insulating film GI2 located between the two gates GE11 and GE12. That is, as Figure 16 As shown, the damaged area DMG is not on the main surface MS1 side of the semiconductor substrate SB, but on the interlayer insulating film IL2 side, which includes the contact interlayer insulating layer CIL. The contact interlayer insulating layer CIL is located in part of CTP2 of the gate insulating film GI2 between the two gate electrodes GE11 and GE12.

[0053] Therefore, the inventors investigated when the aforementioned damaged region DMG was formed. As a result, it was found that the damaged region DMG was generated through an ion implantation process used to form the semiconductor region SDR1, which includes the memory cell MC11. Specifically, to form the semiconductor region SDR1, conductive impurity ions were implanted from the main surface MS1 side of the semiconductor substrate SB to the semiconductor substrate SB side, thus forming the damaged region DMG. The concentration of the impurities constituting the damaged region DMG was two orders of magnitude or more higher than the concentration of the impurities in the portion of CTP2 of the gate insulating film GI2 located between the two gate electrodes GE11 and GE12, excluding the damaged region DMG.

[0054] Here, as Figure 16 As shown, the semiconductor device SMD11 studied by the inventors includes a field-effect transistor PTR having a gate electrode GE made of metal. Therefore, although a detailed process will be described later, a portion of the gate insulating film GI2 formed in the memory cell formation region 1R is also removed by a polishing process using the interlayer insulating film IL1. That is, even if a damaged region DMG is formed on the gate insulating film GI2 by an ion implantation process used to form the semiconductor region SDR1, the damaged region DMG is removed by a polishing process performed after the ion implantation process. However, in recent years, with the miniaturization of semiconductor devices, the thickness (height) of the corresponding gate electrode has tended to decrease. Therefore, the amount of gate electrode removed by the polishing process needs to be as small as possible. As a result, as Figure 16 As shown, the damaged region DMG formed in a portion of the CTP2 of the gate insulating film GI2 located between the two gate electrodes GE11 and GE12 is prone to residue due to the ion implantation process used to form the semiconductor region SDR1.

[0055] (Example)

[0056] Next, the semiconductor device SMD1 and its manufacturing method in this embodiment will be described.

[0057] <Semiconductor device in this embodiment>

[0058] First, the differences between the semiconductor device SMD1 of this embodiment and the semiconductor device SMD11 of the research example studied by the inventors will be described. In the semiconductor device SMD1 of this embodiment, the description of the parts common to the semiconductor device SMD11 of the research example studied by the inventors will be omitted.

[0059] like Figure 14 As shown, similar to the semiconductor device SMD11 in the research example studied by the inventors, the semiconductor device SMD1 of this embodiment has a memory cell formation region 1R and a peripheral circuit formation region 2R separated from the memory cell formation region 1R by a component isolation portion (not shown). Figure 14 As shown, although the memory cells of the split-gate non-volatile memory are formed in the memory cell forming region 1R, a field-effect transistor (PTR) is formed in the peripheral circuit forming region 2R. The PTR forms peripheral circuits such as input / output circuits and has a gate electrode GE made of metal. However, the memory cell MC1 of this embodiment differs from the memory cell MC11 of the research example discussed by the inventors.

[0060] More specifically, as described above, in the memory cell MC11 of the research example studied by the inventors, the upper surfaces SLS11 and SLS12 of each silicide layer SL2 formed on each gate electrode GE11, GE12, and the IFS (in the research example) of the portion of CTP2 of the gate insulating film GI2 exposed from the two gate electrodes GE11, GE12 are located at substantially the same height. On the other hand, in the memory cell MC1 of this embodiment, the upper surfaces SLS1 and SLS2 of each silicide layer SL2 formed on each gate electrode GE1, GE2, and the IFS (end face) (in this embodiment) of the portion of CTP2 of the gate insulating film GI2 exposed from the two gate electrodes GE11, GE12 are located at different heights. That is, as Figure 14 As shown, gate electrodes GE1 and GE2 are formed such that the upper surfaces SLS1 and SLS2 of the silicide layer SL2 are closer to the main surface MS1 of the semiconductor substrate SB than the damaged region DMG formed in the gate insulating film GI2. Note that... Figure 14 The thickness of the damaged region DMG shown (in other words, the implantation depth of impurities from the portion of CTP2 of the gate insulating film GI2, to the upper surface IFS exposed by the two gate electrodes GE1, GE2) is, for example, 5 nm to 15 nm. The impurity concentration in the damaged region DMG is two orders of magnitude higher than the impurity concentration in the portion of CTP2 of the gate insulating film GI2 where the damaged region DMG is not formed. The horizontal difference between the upper surface IFS of the portion of CTP2 of the gate insulating film GI2 and the upper surfaces SLS1 and SLS2 of the silicide layer SL2 is, for example, 10 nm to 20 nm.

[0061] <Effect of the SMD1 semiconductor device in this embodiment>

[0062] As described above, in this embodiment, the control gate electrode CG1, which forms the gate electrode GE1 of the control transistor STR1, and the memory gate electrode MG1, which forms the gate electrode GE2 of the memory transistor MTR1, do not contact the damaged region DMG formed in the gate insulating film GI2. In other words, the damaged region DMG is not inserted between the control gate electrode CG1 and the memory gate electrode MG1. That is, since the control gate electrode CG1 and the memory gate electrode MG1 are electrically insulated from each other through the gate insulating film GI2, the occurrence of the short-circuit defect can still be suppressed even when the above-described operations ("write", "read", and "erase") are performed on the memory cell MC1.

[0063] In this embodiment, as Figure 14 As shown, the thickness of each of the gate electrodes GE1 and GE2 is half or more of the height from the main surface MS1 of the semiconductor substrate SB to the upper surface (end face) IFS of the portion of the gate insulating film GI2 located between the two gate electrodes GE1 and GE2 on the upper surface (end face) of CPT2. That is, in this embodiment, when a portion of each of the gate electrodes GE1 and GE2 is removed, such that the upper surfaces SLS1 and SLS2 of each silicide layer SL2 formed in each gate electrode GE1 and GE2 are closer to the main surface MS1 of the semiconductor substrate SB than the damaged region DMG, each gate electrode GE1 and GE2 is not removed more than the required amount. As a result, the increase in parasitic resistance of the gate electrodes GE1 and GE2 constituting the field-effect transistors STR1 and MTR1 can be suppressed. Figure 14 As shown, even if the silicide layer SL2 is formed on the gate electrodes GE1 and GE2, silicide formation on all gate electrodes GE1 and GE2 can be suppressed. In this embodiment, the thickness of the corresponding gate electrodes GE1 and GE2 is greater than the thickness of the silicide layer SL2.

[0064] In this embodiment, as Figure 14 As shown, a silicide layer SL2 is formed on the corresponding gate electrodes GE1 and GE2. Therefore, the contact resistance between the wiring (here, wiring M1) constituting the multi-wiring layer FNL and the gate electrodes GE1 and GE2 via contact plugs (not shown), where the contact plugs are used to electrically connect the gate electrodes GE1 and GE2 to each other, is reduced. This multi-wiring layer FNL is formed on the inter-contact insulating layer CIL covering the memory cell MC1. In this embodiment, as... Figure 14As shown, a silicide layer SL1 is formed in the diffusion region SD1 of the semiconductor region SDR1 constituting the memory cell MC1, and in the diffusion region SD2 of the semiconductor region SDR2 constituting the field-effect transistor PTR. Therefore, the contact resistance between the wiring (here, wiring M1) constituting the aforementioned multi-wiring layer FNL and the diffusion regions SD1 and SD2 of the contact plug CVF, which electrically connects the aforementioned diffusion regions SD1 and SD2, can be reduced. As a result, the memory cell MC1 and the field-effect transistor PTR, i.e., the semiconductor device SMD1, can be accelerated.

[0065] In addition, such as Figure 14 As shown, this embodiment employs a so-called LDD structure, wherein extended regions EX1 and EX2 are formed between the channel regions formed directly below the gate electrodes GE1, GE2, and GE of the field-effect transistors STR1, MTR1, and PTR, and between each diffusion region SD1 and SD2 connected to the contact plug CVF. These extended regions EX1 and EX2 are made of impurities with a lower density than the diffusion regions SD1 and SD2. Therefore, the generation of leakage current, which becomes significant with the miniaturization of semiconductor devices, can be suppressed.

[0066] Furthermore, in this embodiment, since the gate electrode GE of the field-effect transistor PTR formed in the peripheral circuit formation region 2R is made of metal, gate electrode depletion can be suppressed compared to the case where polysilicon is used to form the gate electrode GE. That is, since the parasitic capacitance of the gate electrode can be reduced, it is suitable for miniaturization of the field-effect transistor PTR.

[0067] <Method for manufacturing semiconductor device SMD1 in this embodiment>

[0068] Next, we will refer to Figures 1 to 14 This embodiment describes a method for manufacturing the semiconductor device SMD1. Figure 1 This is a process flow diagram illustrating the manufacturing process of the semiconductor device SMD1 in this embodiment. Figures 2 to 14 This is a cross-sectional view of the main parts during the manufacturing process of the semiconductor device in this embodiment.

[0069] 1. Provide substrate ( Figure 1 Step S1)

[0070] First of all, as Figure 1 As shown in step S1, the semiconductor substrate SB is prepared. Figure 2 As shown, the fabricated semiconductor substrate SB has a memory cell formation region 1R and a peripheral circuit formation region 2R. The two regions 1R and 2R are separated from each other by a device isolation portion formed in a device isolation region (not shown). Figure 2As shown, the semiconductor substrate SB has a main surface MS1 and a main surface MS2. Semiconductor elements such as memory cells MC1 and field-effect transistors PTRs are then formed on the main surface MS1. The main surface MS2 is on the other side of the main surface MS1, opposite to the semiconductor elements such as memory cells MC1 and field-effect transistors PTRs. In this embodiment, the semiconductor substrate SB is made of p-type single-crystal silicon with a resistivity of, for example, 1 Ωcm to 10 Ωcm.

[0071] 2. Forming the gate electrode ( Figure 1 Step S2)

[0072] Next, in Figure 1 In step S2, gate electrodes GE1, GE2, and GE3 are formed in corresponding regions 1R and 2R. Specifically, firstly, p-type impurity ions, such as boron (B), are implanted into the semiconductor substrate SB to form a well region WELL in the semiconductor substrate SB. Then, gate electrode GE1 is formed on the main surface MS1 of the semiconductor substrate SB located in the memory cell formation region 1R via gate insulating film GI1. Gate electrode GE2 is formed on each of the main surface MS1 and the side surface GE1S of the semiconductor substrate SB located in the memory cell formation region 1R via gate insulating film GI2. Furthermore, gate electrode GE3 is formed on the main surface MS1 of the semiconductor substrate SB located in the peripheral circuit formation region 2R via gate insulating film GI3. In this embodiment, the gate insulating film GI1 formed between gate electrode GE1 and the semiconductor substrate SB, and the gate insulating film GI3 formed between gate electrode GE3 and the semiconductor substrate SB, are made of, for example, silicon oxide. Figure 3 As shown, the gate insulating film GI2 includes a portion CTP1 located between the gate electrode GE2 and the semiconductor substrate SB, and a portion CTP2 located between the gate electrode GE2 and the gate electrode GE1. The gate insulating film GI2 has two insulating films IF1 and IF2, for example, made of silicon oxide, and an insulating film GE2 (i.e., the charge storage region CTR) made of silicon nitride sandwiched between the two insulating films IF1 and IF3. Each gate electrode GE1, GE2, GE3 formed in each of regions 1R and 2R is made of, for example, polysilicon, particularly doped polysilicon with introduced or ion-implanted impurities. Furthermore, as... Figure 3 As shown, a cover insulating film CAP, made of, for example, silicon nitride, is formed on each of the gate electrode GE1 and the gate insulating film GE3. The cover insulating film CAP serves as a protective film to prevent the formation of a silicide layer SL1, described later, on the respective gate electrodes GE1 and GE3.

[0073] 3. Formation of extended areas ( Figure 1 Step S3)

[0074] Next, as Figure 1 Step S3, as shown, forms extended regions EX1 and EX2 in regions 1R and 2R. Specifically, as... Figure 4 As shown, an n-type impurity IM1, such as arsenic (As) or phosphorus (P), is implanted into the semiconductor substrate SB from the main surface of the substrate SB using MS1 ions. The implantation conditions for impurity IM1 are, for example, 5 keV to 25 keV, and the impurity IM1 dose is, for example, about 1 × 10⁻⁶. 14 / cm 2 As a result, Figure 4 As shown, in the semiconductor substrate SB (more specifically, the well region WELL) located in the memory cell formation region 1R, an extended region (semiconductor region, impurity diffusion layer) EX1 made of n-type impurities is formed in each exposed portion from the two gate electrodes GE1, GE2 and the gate insulating film GI2. Similarly, as Figure 4 As shown, in a portion of the semiconductor substrate SB located in the peripheral circuit formation region 2R exposed from the gate electrode GE3 (more specifically, the well region WELL), an extended region (semiconductor region, impurity diffusion layer) EX2 made of n-type impurities is formed. Each of the gate electrodes GE1, GE2, GE3 and the gate insulating film GI2 serves as a mask, and each of the extended regions EX1, EX2 is formed in a self-aligned manner relative to each of the gate electrodes GE1, GE2, GE3, as shown. Figure 4 As shown. Each extended region EX1, EX2 is part of semiconductor regions SDR1, SDR2, which serve as the source or drain of each field-effect transistor STR1, MTR1 or PTR that is later formed in each region 1R, 2R.

[0075] Here, when extended regions EX1 and EX2 are formed in the corresponding regions 1R and 2R, impurity ions are also implanted into the portion of CTP2 of the gate insulating film GI2 exposed from the two gate electrodes GE1 and GE2. Therefore, by performing this step S3, as Figure 4 As shown, a damaged region (damaged layer) DMG made of the aforementioned impurities is formed in a portion of CTP2 of the gate insulating film GI2, with the gate insulating film GI2 located between two adjacent gate electrodes GE1 and GE2. The damaged region DMG has an upper surface IFS exposed from each of the two gate electrodes GE1 and GE2 in the aforementioned portion of CTP2. The thickness T1 of the damaged region DMG formed by performing step S3 (depth from the upper surface IFS) is, for example, 10 nm to 15 nm.

[0076] 4. Formation of sidewall spacers

[0077] Next, sidewall spacers SW1 and SW2 are formed in the corresponding regions 1R and 2R. Specifically, as follows: Figure 5 As shown, a sidewall spacer SW1 is formed on the main surface MS1 of the semiconductor substrate SB located in the memory cell formation region 1R to sandwich the two gate electrodes GE1, GE2 and the gate insulating film GI2. Similarly, as Figure 5 As shown, a sidewall spacer SW2 is formed on the main surface MS1 of the semiconductor substrate SB located in the peripheral circuit formation region 2R to sandwich the gate electrode GE3 therebetween. As a result, as... Figure 5 As shown, the side surfaces of gate electrode GE1 exposed from the covering insulating film CAP and gate insulating film GI2, and the side surfaces of gate electrode GE2 exposed from the gate insulating film GI2, are covered by sidewall spacers SW1. The sidewall spacers SW1 are formed on the semiconductor substrate SB located in the memory cell formation region 1R to cover a portion of the extended region EX1. Figure 5 As shown, the side surface of the gate electrode GE3 exposed from the covering insulating film CAP is covered by sidewall spacers SW2, which are formed on the semiconductor substrate SB located in the peripheral circuit formation region 2R to cover a portion of the extended region EX2. The sidewall spacers SW1 and SW2 are formed from insulating films made of silicon oxide, insulating films made of silicon nitride, or a stacked structure of insulating films made of silicon oxide and insulating films made of silicon nitride.

[0078] 5. Formation of diffusion zone

[0079] Next, diffusion regions SD1 and SD2 are formed in the corresponding regions 1R and 2R. Specifically, as follows: Figure 6 As shown, an n-type impurity IM2, such as arsenic (As) or phosphorus (P), is implanted into the semiconductor substrate SB from the main surface of the substrate SB using MS1 ions. The implantation conditions for impurity IM2 are, for example, 5 keV to 25 keV, and the impurity IM2 dose is, for example, about 1 × 10⁻⁶. 15 / cm 2 As a result, Figure 6 As shown, in each exposed portion of the semiconductor substrate SB (more specifically, the well region WELL) located in the memory cell formation region 1R, a diffusion region (semiconductor region, impurity diffusion layer) SD1 made of n+ type impurities is formed from the sidewall spacers SW1, the two gate electrodes GE1, GE2, and the gate insulating film GI2. Similarly, as Figure 6As shown, a diffusion region (semiconductor region, impurity diffusion layer) SD2, made of n+ type impurities, is formed in a portion (more specifically, the well region WELL) of the semiconductor substrate SB located in the peripheral circuit formation region 2R, exposed from the sidewall spacers SW2 and the gate electrode GE3. Each of the sidewall spacers SW1, SW2, the gate electrodes GE1, GE2, GE3, and the gate insulating film GI2 serves as a mask, and each diffusion region SD1, SD2 is formed in a self-aligned manner relative to each sidewall spacer SW1, SW2, as shown. Figure 6 As shown. Furthermore, each diffusion region SD1, SD2 is part of semiconductor regions SDR1, SDR2, which serve as the source or drain of each field-effect transistor STR1, MTR1, and PTR subsequently formed in each region 1R, 2R. That is, the semiconductor regions SDR1, SDR2 serving as the source / drain of each field-effect transistor STR1, MTR1, and PTR include each extended region EX1, EX2 and each diffusion region SD1, SD2.

[0080] Here, the concentration of the impurity to be ion-implanted in this step is higher than the concentration of the impurity ion-implanted in step S3 above. That is, the concentration of the impurity constituting each diffusion region SD1, SD2 is higher than the concentration of the impurity constituting each extension region EX1, EX2. In other words, the concentration of the impurity constituting each extension region EX1, EX2 is lower than the concentration of the impurity constituting each diffusion region SD1, SD2. Then, as... Figure 6 As shown, compared to the impurities constituting each extended region EX1, EX2, the impurities constituting each diffused region SD1, SD2 diffuse to a deeper location. In other words, compared to each extended region EX1, EX2, each diffused region SD1, SD2 has a portion (region) closer to the main surface MS2 of the semiconductor substrate SB.

[0081] When diffusion regions SD1 and SD2 are formed in the corresponding regions 1R and 2R, impurity ions are also implanted into the portion of CTP2 of the gate insulating film GI2 exposed from the two gate electrodes GE1 and GE2. Therefore, by performing this step, as... Figure 6 As shown, the damaged region DMG formed by performing step S3 further diffuses toward the main surface MS1 of the semiconductor substrate SB. By performing this step, the thickness T2 of the damaged region DMG (depth from the upper surface IFS) increases to, for example, 20 nm to 25 nm. Furthermore, after this step, the impurity concentration in the damaged region DMG is two orders of magnitude or more higher than the impurity concentration in the portion of the gate insulating film GI2 CTP2 where the damaged region DMG is not formed.

[0082] 6. Forming the intermediate layer of the insulating film ( Figure 1Step S4)

[0083] Next, as Figure 1 Step S4, as shown, involves forming an interlayer insulating film IL1 on the semiconductor substrate SB. Specifically, after forming silicide layers SL1 in each diffusion region SD1, SD2 formed in the previous step using, for example, self-aligned silicide technology, an interlayer insulating film IL1 is formed on the main surface MS1 of the semiconductor substrate SB, which constitutes the memory cell formation region 1R and the peripheral circuit formation region 2R, to cover the gate insulating film GI2. Each sidewall spacer SW1, SW2, each gate electrode GE1, GE2, GE3, and the damaged region DMG are formed in the interlayer insulating film IL1, as shown. Figure 7 As shown. The interlayer insulating film IL1 is made of, for example, silicon oxide and is formed by a CVD method. The silicide layer SL1 is, for example, a cobalt silicide layer, a nickel silicide layer, or a nickel silicide layer with platinum added.

[0084] 7. Polishing ( Figure 1 Step S5)

[0085] Next, in Figure 1 In step S5, a portion of the interlayer insulating film IL1 formed in step S4 above is removed. Specifically, the interlayer insulating film IL1, sidewall spacers SW1 and SW2, and the covering insulating film CAP are polished, exposing a portion of each gate electrode GE1, GE2, and GE3. At this time, a portion of the gate electrodes GE1, GE2, and GE3 and a portion of the gate insulating film GI2 are also polished. As a result, as shown... Figure 8 As shown, the gate electrodes GE1, GE2, and GE3, which are covered by the interlayer insulating film IL1 or the covering insulating film CAP, are reliably exposed. Figure 8 As shown, the upper surfaces (polished and exposed surfaces) of the interlayer insulating film IL1, sidewall spacers SW1 and SW2, gate electrodes GE1, GE2, GE3, and gate insulating film GI2 are at substantially the same height.

[0086] Here, the polishing conditions (polishing amount, polishing duration, etc.) in step S5 are primarily conditions under which the gate electrode to be replaced with another material (gate electrode GE3 in this embodiment) can be exposed. That is, the polishing conditions in step S5 are such that the gate electrode is not unnecessarily removed. Therefore, even after performing step S5, as... Figure 8As shown, the damaged DMG region remains between the two adjacent gate electrodes GE1 and GE2, in which the gate insulating film GI2 is inserted. The thickness T3 of the damaged DMG remaining after step S5 is, for example, 5 nm to 15 nm. Additionally, the thickness of the gate electrodes GE1 and GE2 remaining after step S5 is, for example, 50 nm to 100 nm. However, the gate electrode GE2 (which later becomes the memory gate electrode MG1 of the memory transistor MTR1) is formed on the semiconductor substrate SB located in the memory cell formation region 1R via the gate insulating film GI2, and the gate insulating film GI2 has a thickness greater than the thickness of the gate insulating film GI1 (total thickness). Therefore, the thickness of the gate electrode GE2 remaining after the main step S5 is thinner than the thickness of the gate electrode GE1 remaining after the main step S5.

[0087] 8. Displacement ( Figure 1 Step S6)

[0088] Next, as Figure 1 In step S6, the material constituting the gate electrode G3 is replaced with a material different from that material. Specifically, first, a mask (not shown) is used to cover the memory cell formation region 1R. Then, while the gate electrode GE3, located in the peripheral circuit formation region 2R and made of polysilicon, is removed, the memory cell formation region 1R is covered by a mask (not shown). Thereafter, a gate electrode GE, made of a metal film ME1 and a metal film ME2 formed on the metal film ME1, is formed on the gate insulating film GI3 exposed by removing the gate electrode GE3. An insulating film HK, which is a high-k film, is inserted between the insulating film GI3 and the gate electrode GE. The metal film ME1 is made of TiAl, for example. The metal film ME2 is made of aluminum (Al), for example. Furthermore, as... Figure 9 As shown, the insulating film HK is formed not only between the gate electrode GE and the gate insulating film GI3, but also between the gate electrode GE and the sidewall spacer SW2.

[0089] 9. Etching back the gate electrode ( Figure 1 Step S7)

[0090] Next, in Figure 1 In step S7, as shown, portions of the gate electrodes GE1 and GE2 exposed from the interlayer insulating film IL1 and sidewall spacers SW1 are removed. Specifically, first, the peripheral circuit formation region 2R is covered with a mask (not shown). Then, as... Figure 10As shown, while a portion of each gate electrode GE1, GE2 is removed by wet etching using chemical reagents, the peripheral circuit formation region 2R is covered by a mask (not shown), such that the upper surfaces GES1 and GES2 of each gate electrode GE1, GE2 exposed from the interlayer insulating film IL1 and sidewall spacers SW1 are closer to the main surface MS1 of the semiconductor substrate SB than the damaged region DMG. The thickness of each gate electrode GE1, GE2 to be removed in step S7 (i.e., the amount etched or removed from each gate electrode GE1, GE2) is greater than the thickness T3 of the damaged region DMG after step S5, and less than the thickness of each gate electrode GE1, GE2 after step S5. More specifically, the thickness of each gate electrode GE1, GE2 removed in step S7 is such that the remaining thickness of each gate electrode GE1, GE2 after the formation of the silicide layer SL2 is greater than the thickness of the silicide layer SL2 formed in the steps described later. That is, the thickness of the corresponding gate electrodes GE1 and GE2 to be removed in step S7 is, for example, 10 nm to 20 nm.

[0091] 10. Siliconization

[0092] Next, a silicide layer SL2 is formed on the corresponding gate electrodes GE1 and GE2. Specifically, similar to the silicide layer SL1, a metal film (not shown) is disposed on the upper surfaces GES1 and GES2 of each gate electrode GE1 and GE2 exposed from the interlayer insulating film IL1, each sidewall spacer SW1, and the gate insulating film GI2, and a silicide layer SL2 is formed on each gate electrode GE1 and GE2 by, for example, a self-aligned silicide technique. Like the silicide layer SL1, the silicide layer SL2 is, for example, a cobalt silicide layer, a nickel silicide layer, or a nickel silicide layer with platinum added. The silicide layer SL2 is formed by reacting a portion of the gate electrodes GE1 and GE2 with the aforementioned metal film (not shown). Therefore, as Figure 11 As shown, a portion of the gate electrodes GE1 and GE2 forms a silicide layer SL2. Specifically, the upper surfaces SLS1 and SLS2 of the silicide layer SL2 formed on the gate electrode GE1 and GE2, respectively, are located at substantially the same height as the upper surfaces GES1 and GES2 of the gate electrode GE1 after etchback. The horizontal difference between the upper surface IFS of a portion of the gate insulating film GI2 (CTP2) and the upper surfaces SLS1 and SLS2 of the silicide layer SL2 is, for example, 10 nm to 20 nm.

[0093] like Figure 11As shown, the silicide layer SL2 is formed on the corresponding gate electrodes GE1 and GE2, and thus does not contact the damaged region DMG formed on the gate insulating film GI2. In other words, the damaged region DMG is not located between the silicide layer SL2 formed on the gate electrode GE1 and the silicide layer SL2 formed on the gate electrode GE2.

[0094] The thickness of the silicide layer SL2 formed by performing this step is, for example, 10 nm to 20 nm. As described above, in this embodiment, the thickness of the gate electrodes GE1 and GE2 to be removed in the gate electrode etch-back step (step S7) (i.e., the amount of etching or removal of gate electrodes GE1 and GE2) is set to, for example, about 10 nm to 20 nm. Therefore, even if this step is performed, such as Figure 11 The diagram also shows that not all gate electrodes GE1 and GE2 were siliconized.

[0095] 11. Formation of interlayer insulation layer

[0096] Next, an interlayer insulating film IL2 is formed on the semiconductor substrate SB to cover the interlayer insulating film IL1, sidewall spacers SW1 and SW2, gate electrodes GE1, GE2, and GE3, and the gate insulating film GI2. The result is as follows: Figure 12 As shown, the upper surface GES1 of the gate electrode GE1 (i.e., the upper surface SLS1 of the silicide layer SL2), the upper surface GES2 of the gate electrode GE2 (i.e., the upper surface SLS2 of the silicide layer SL2), and the upper surface GEUS of the gate electrode GE exposed from the interlayer insulating film IL1, each sidewall spacer SW1, SW2, the gate insulating film GI2, and the insulating film HK are protected by the interlayer insulating film IL2. The interlayer insulating film IL1 remaining in step S5 and the interlayer insulating film IL2 formed in step S5 are used as materials constituting the contact interlayer insulating layer CIL, respectively.

[0097] 12. Forming a contact plug

[0098] Next, as Figure 13As shown, a contact hole CTH is formed on the interlayer insulating layer CIL, penetrating the interlayer insulating layer CIL, which consists of an interlayer insulating film IL1 formed on the semiconductor substrate SB and an interlayer insulating film IL2 formed on the interlayer insulating film IL1, to reach the main surface MS1 of the semiconductor substrate SB. A conductive component, such as tungsten (W), is then buried in the formed contact hole CTH. As a result, a contact plug CVF is formed in the contact hole CTH, which is electrically connected to a silicide layer SL1 formed in the corresponding semiconductor regions SDR1 and SDR2 (specifically, the corresponding diffusion regions SD1 and SD2 constituting the corresponding semiconductor regions SDR1 and SDR2). Before forming the contact hole CTH, an insulating film serving as an etch stop film can be formed on the main surface MS1 of the semiconductor substrate SB to cover the corresponding semiconductor regions SDR1 and SDR2.

[0099] 13. Forming multiple wiring layers

[0100] Next, an interlayer insulating film IL3 is formed on the interlayer insulating film IL2, and then on the contact interlayer insulating film CIL (specifically, the interlayer insulating film IL2) to cover and further cover the wiring M1. The wiring M1 and the interlayer insulating film IL3 are alternately stacked on the contact interlayer insulating film CIL to form a multilayer wiring layer FNL.

[0101] <Effects of the method for manufacturing the semiconductor device of this embodiment>

[0102] As described above, in this embodiment, during execution Figure 1 After the polishing step (step S5) shown (more specifically, after the polishing step and before forming the silicide layer SL2 on the gate electrodes GE1, GE2 exposed by the polishing step), a portion of each gate electrode GE1, GE2 is removed, such that the upper surface of each gate electrode GE1, GE2 is closer to the main surface MS1 of the semiconductor substrate SB than the damaged area DMG formed on the gate insulating film GI2. Therefore, even when the above-described operations such as "write", "read" and "erase" are performed on the manufactured semiconductor device SMD1 (especially the following operations: Figure 14 and 17 The value of the voltage Vcg applied to the control gate CG1 shown, and... Figure 14 and 17 The large difference between the voltage Vmg applied to the memory gate electrode MG1 can also suppress the occurrence of short-circuit defects between the gate electrode GE1, which is used as the control gate CG1, and the gate electrode GE2, which is used as the memory gate electrode MG1.

[0103] Furthermore, in this embodiment, when... Figure 1When the gate electrodes shown undergo an etch-back process (step 7), the amount of etching (removal) of each gate electrode GE1, GE2 to be etched (removed) in this etch-back process can be less than that in the process shown. Figure 1 The polishing process shown (step S5) is performed after the process and before the etchback of each gate electrode GE1, GE2, reducing the thickness of each gate electrode GE1, GE2 to half its original thickness. Therefore, the increase in parasitic resistance of the corresponding gate electrodes GE1, GE2 can be suppressed. As in this embodiment, even if a silicide layer SL2 is formed on the corresponding gate electrodes GE1, GE2, silicide formation on all gate electrodes GE1, GE2 can be avoided.

[0104] As a countermeasure to the aforementioned short-circuit defect, the inventors also considered using the following polishing conditions: when performing polishing step S5, all damaged DMG regions are removed. However, in this case, the polishing amount of each gate electrode exceeds the necessary amount. That is, the thickness of the gate electrode becomes thinner than desired, resulting in a higher parasitic resistance of the gate electrode. Therefore, the inventors also considered... Figure 1 In the gate electrode formation step (step S2) shown, the thickness (height) of the gate electrode film is made greater than (higher than) the desired thickness. However, in this case, after patterning the material including the gate electrode, the aspect ratio of the patterned gate electrode becomes too large, and as a result, the patterned gate electrode may collapse.

[0105] In this embodiment, as described above, during execution Figure 1 Following the polishing process shown (step S5), and before forming a silicide layer SL2 on the gate electrodes GE1 and GE2 exposed by the polishing process, the gate electrodes are etched back based on the polishing conditions (polishing amount, polishing time, etc.) as described above (step 7). Therefore, not only can short-circuit defects between the two gate electrodes GE1 and GE2 constituting the memory cell MC1 be suppressed, but the increase in parasitic resistance of the two gate electrodes GE1 and GE2 can also be suppressed.

[0106] In this embodiment, Figure 1 Following the displacement process shown (step 6), for Figure 1The gate electrode shown undergoes an etch-back process (step 7). That is, when the gate electrode GE3, made of polysilicon, formed in the peripheral circuit formation region 2R, is replaced with a gate electrode GE made of metal, the upper surfaces (polished surfaces, exposed surfaces) of the interlayer insulating film IL1, sidewall spacers SW1, each gate electrode GE1, GE2, and each gate insulating film GI2 in the memory cell formation region 1R are at substantially the same height. In other words, when replacement step 6 is performed, the surface of the memory cell formation region 1R is flat. Therefore, when the replacement process (step 6) is performed, it is easy to form the mask (not shown) to be formed in the memory cell formation region 1R. That is, when the mask used is removed, it is possible to prevent the mask from unintentionally remaining in the memory cell formation region 1R.

[0107] <Modification Example of This Embodiment>

[0108] Next, a modified example of this embodiment will be described.

[0109] (Modified Example 1)

[0110] In this embodiment, the gate electrodes GE1 and GE2 of the field-effect transistors STR1 and PTR1 that constitute the memory cell MC1 formed in the memory cell formation region 1R are not replaced with gate electrodes made of metal. However, similar to the gate electrode GE of the field-effect transistor PTR formed in the peripheral circuit formation region 2R, the gate electrodes GE1 and GE2 of the memory cell MC1 can be replaced with metal gate electrodes. That is, a semiconductor device SMD2 can be used in which a memory cell MC2 is formed in the memory cell formation region 1R, the memory cell MC2 including a control transistor STR2 and a memory transistor MTR2, the control transistor STR2 having a gate electrode GE with the same configuration as the gate electrode GE of the field-effect transistor PTR, and the memory transistor MTR2 having a gate electrode GE with the same configuration as the gate electrode GE of the field-effect transistor PTR. This makes it possible to provide a semiconductor device SMD2 that can cope with further miniaturization. Similarly, in this first modified example, as Figure 15 As shown, an etch-back process is performed on each gate electrode GE4, GE5, so that the upper surface of each replaced gate electrode GE4, GE5 is closer to the main surface MS1 of the semiconductor substrate SB than the damaged region DMG formed in the gate insulating film GI2. This suppresses the occurrence of the aforementioned short-circuit defects.

[0111] (Modified Example 2)

[0112] Furthermore, in this embodiment, it has been described that a portion of the gate electrode is removed by wet etching in the etch-back step S7 of the gate electrode. However, a portion of each gate electrode can also be removed by dry etching. In dry etching, plasma is used, which may create new damaged areas on the gate insulating film GI2 when a portion of the gate electrode is removed. Therefore, in the etch-back process (step S7) of the gate electrode, wet etching (step S7) is preferably used as in this embodiment.

[0113] (Modified Example 3)

[0114] In this embodiment, a memory cell MC1 having a semiconductor region SDR1 has been described. The semiconductor region SDR1 consists of an extended region EX1 and a diffused region SD1. The extended region EX1 is covered by an LDD-structured memory cell MC1 (i.e., sidewall spacers SW1), while the diffused region SD1 is not covered by the sidewall spacers SW1. However, the memory cell may not include the extended region EX1 and the sidewall spacers SW1. In this case, after performing the above-described "2. Gate electrode formation step", the above-described "3. Extended region formation step" and "4. Sidewall spacer formation step" are not performed, and the above-described "5. Diffusion region formation step" is performed. Alternatively, the memory cell may not include the sidewall spacers SW1 and the diffused region SD1. In this case, after performing the above-described "3. Extended region formation step", the above-described "4. Sidewall spacer formation step" and "5. Diffusion region formation step" are not performed, and the above-described "6. Interlayer insulating film formation step" is performed. Similarly, the field-effect transistor PTR can be a field-effect transistor that has neither the extended region EX2 nor the sidewall spacer SW2, or it can be a field-effect transistor that has neither the sidewall spacer SW2 nor the diffusion region SD2. On the other hand, in order to achieve miniaturization of semiconductor devices, an LDD structure having extended regions EX1, EX2 and diffusion regions SD1, SD2 is preferably adopted, such as the LDD structure of this embodiment.

[0115] (Modified Example 4)

[0116] In this embodiment, a silicide layer SL1 is formed in each semiconductor region SDR1, SDR2, and a silicide layer SL2 is formed in each gate electrode GE1, GE2. However, it is possible not to form silicide layers SL1 and SL2.

[0117] (Modified Example 5)

[0118] Furthermore, in this embodiment, a gate insulating film GI2 having a charge storage region CTR has been described. The gate insulating film GI2 includes an insulating film IF1 made of silicon oxide, an insulating film IF2 made of silicon nitride, and an insulating film IF3 made of silicon oxide. However, the insulating film IF2 used as the charge storage region CTR is not limited to silicon nitride, and may also be an insulating film made of hafnium silicate (HfSiO). The insulating film IF3 formed on the insulating film IF2 used as the charge storage region CTR is not limited to silicon oxide, and may also be an insulating film made of aluminum oxide (Al2O3).

[0119] The invention made by the inventors has been described in detail above based on the embodiments. However, the invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from the spirit of the invention.

[0120] For example, although various modification examples have been described above, some or all of the above modification examples can be applied in combination with each other within the scope consistent with the main idea of ​​each modification example described above.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: (a) A semiconductor substrate is provided, the semiconductor substrate including a first region and a second region, and having a first main surface; (b) After step (a), 1) a first gate electrode is formed on the first main surface of the semiconductor substrate in the first region via a first gate insulating film, 2) a second gate electrode is formed on each of the following via a second gate insulating film: the first main surface of the semiconductor substrate in the first region, and 3) a side surface of the first gate electrode, and a third gate electrode is formed on the first main surface of the semiconductor substrate in the second region via a third gate insulating film. The second gate insulating film has a charge storage region. The second gate insulating film includes a first portion located between the second gate electrode and the semiconductor substrate, and a second portion located between the second gate electrode and the first gate electrode. Each of the first gate electrode, the second gate electrode, and the third gate electrode is composed of a first material; (c) After step (b), ion implantation of a first impurity of a first conductivity type into the semiconductor substrate is performed, thereby 1) forming a first semiconductor region at the portion of the semiconductor substrate in the first region exposed from the first gate electrode, the second gate insulating film and the second gate electrode, 2) forming a second semiconductor region at the portion of the semiconductor substrate in the second region exposed from the third gate electrode, and 3) forming a damaged region at the upper surface of the second portion of the second gate insulating film, such that the damaged region is exposed from each of the first gate electrode and the second gate electrode; (d) After step (c), a first interlayer insulating film is formed on the first main surface of the semiconductor substrate, such that the first gate electrode, the second gate electrode and the third gate electrode are covered by the first interlayer insulating film. (e) After step (d), the first interlayer insulating film is polished such that a portion of each of the first gate electrode, the second gate electrode and the third gate electrode is exposed from the first interlayer insulating film; (f) After step (e), the first material of the third gate electrode is replaced with a second material, wherein the second material is different from the first material; as well as (g) After step (f), a portion of each of the first gate electrode and the second gate electrode is removed by etching such that, in a cross-sectional view, the upper surface of each of the first gate electrode and the second gate electrode exposed from the first interlayer insulating film is closer to the first main surface of the semiconductor substrate than the damaged area at the second portion of the second gate insulating film.

2. The method according to claim 1, further comprising the following steps after step (c) and before step (d): (h) A first sidewall spacer is formed on the semiconductor substrate in the first region to sandwich the first gate electrode, the second gate insulating film and the second gate electrode in a cross-sectional view, and a second sidewall spacer is formed on the semiconductor substrate in the second region to sandwich the third gate electrode in a cross-sectional view. as well as (i) After step (h), a third semiconductor region is formed in the first region at the portion of the semiconductor substrate exposed from the first main surface side by implanting a second impurity of the first conductivity type into the semiconductor substrate. This third semiconductor region is formed in the first region at the portion of the semiconductor substrate exposed from the first sidewall spacer, the first gate electrode, the second gate insulating film, and the second gate electrode. A fourth semiconductor region is formed in the second region at the portion of the semiconductor substrate exposed from the second sidewall spacer and the third gate electrode. Each of the first impurity and the second impurity is a third material that is identical to each other. The concentration of the second impurity in each of the third and fourth semiconductor regions is higher than the concentration of the first impurity in each of the first and second semiconductor regions. In step (g), a portion of each of the first gate electrode and the second gate electrode is removed such that, in a cross-sectional view, the upper surface of each of the first gate electrode and the second gate electrode exposed from the first interlayer insulating film is closer to the first main surface of the semiconductor substrate than the damaged region formed by performing step (i).

3. The method according to claim 2, further comprising the following step after step (g): (j) Siliconization is performed on the upper surface of each of the first gate electrode and the second gate electrode. Wherein, in step (g), the thickness of a portion of each of the first and second gate electrodes to be removed is greater than the thickness of the damaged region after step (e), and The thickness of the portion of each of the first and second gate electrodes to be removed in step (g) is less than half the thickness of each of the first and second gate electrodes after step (e) and before step (g).

4. The method according to claim 3, The thickness of the damaged region formed by performing step (c) is 10 nm to 15 nm. The thickness of the damaged region formed by performing step (i) is 20 nm to 25 nm. After step (e), the thickness of the damaged region is 5 nm to 15 nm. After step (e), the thickness of each of the first gate electrode and the second gate electrode is 50 nm to 100 nm. The thickness of the silicide layer to be formed in each of the first gate electrode and the second gate electrode by performing step (j) is 10 nm to 20 nm.

5. The method of claim 4, wherein in step (g), a portion of each of the first gate electrode and the second gate electrode is removed such that, after step (j), the thickness of each of the first gate electrode and the second gate electrode is greater than the thickness of the silicide layer formed by step (j).

6. The method of claim 5, wherein the concentration of the third material in the damaged region is two orders of magnitude higher than the concentration of the third material in the second portion of the second gate insulating film, excluding the damaged region.

7. The method of claim 6, wherein the second gate insulating film comprises: A first insulating layer is formed on the first main surface of the semiconductor substrate in the first region and is composed of silicon oxide. A second insulating layer is formed on the first insulating layer and is composed of silicon nitride. A third insulating layer is formed on the second insulating layer and is composed of silicon oxide.

8. The method according to claim 5, further comprising the following step after step (j): (k) A second interlayer insulating film is formed on the first main surface of the semiconductor substrate, such that the first gate electrode, the second gate electrode, the third gate electrode, and the first interlayer insulating film are covered by the second interlayer insulating film. (l) After step (k), a contact hole is formed that penetrates each of the first interlayer insulating film and the second interlayer insulating film to reach the first main surface of the semiconductor substrate, and a conductive material is embedded in the contact hole; as well as (m) After step (l), a multi-wire layer is formed on the second interlayer insulating film.

9. The method of claim 1, wherein in step (g), a portion of each of the first gate electrode and the second gate electrode is removed by wet etching.

10. The method of claim 1, wherein in step (f), the first material of each of the first gate electrode, the second gate electrode, and the third gate electrode is replaced with a second material different from the first material.

11. The method of claim 1, further comprising the following steps after step (b) and before step (c): (h) By implanting a second impurity of the first conductivity type into the semiconductor substrate from the first main surface side, a third semiconductor region is formed in the portion of the semiconductor substrate in the first region exposed from the first gate electrode, the second gate insulating film and the second gate electrode, and a fourth semiconductor region is formed in the portion of the semiconductor substrate in the second region exposed from the third gate electrode. as well as (i) After step (h), a first sidewall spacer is formed on the semiconductor substrate in the first region to sandwich the first gate electrode, the second gate insulating film, and the second gate electrode in a cross-sectional view, and a second sidewall spacer is formed on the semiconductor substrate in the second region to sandwich the third gate electrode in a cross-sectional view. In step (c), by ion implanting the first impurity of the first conductivity type from the first main surface side of the semiconductor substrate into the semiconductor substrate, a first semiconductor region is formed in the portion of the semiconductor substrate in the first region exposed from the first sidewall spacer, the first gate electrode, the second gate insulating film, and the second gate electrode; and a second semiconductor region is formed in the portion of the semiconductor substrate in the second region exposed from the second sidewall spacer and the third gate electrode. Wherein each of the first impurity and the second impurity is a third material that is identical to each other, and The concentration of the second impurity in each of the third semiconductor region and the fourth semiconductor region is lower than the concentration of the first impurity in each of the first semiconductor region and the second semiconductor region.

12. The method of claim 11, further comprising the following step after step (g): (j) Siliconization is performed on the upper surface of each of the first gate electrode and the second gate electrode. The thickness of a portion of each of the first and second gate electrodes to be removed in step (g) is greater than the thickness of the damaged region after step (e). The thickness of the portion of each of the first gate electrode and the second gate electrode to be removed in step (g) is less than half the thickness of each of the first gate electrode and the second gate electrode after step (e) and before step (g).

13. The method according to claim 12, The thickness of the damaged region formed by performing step (h) is 10 nm to 15 nm. The thickness of the damaged region formed by performing step (c) is 20 nm to 25 nm. The thickness of the damaged region after step (e) is 5 nm to 15 nm. Wherein, after step (e), the thickness of each of the first gate electrode and the second gate electrode is 50 nm to 100 nm, and The thickness of the silicide layer to be formed in each of the first gate electrode and the second gate electrode by performing step (j) is 10 nm to 20 nm.

14. The method of claim 13, wherein in step (g), a portion of each of the first gate electrode and the second gate electrode is removed such that, after step (j), the thickness of each of the first gate electrode and the second gate electrode is greater than the thickness of the silicide layer formed by step (j).

15. The method of claim 14, wherein the concentration of the third material in the damaged region is two orders of magnitude higher than the concentration of the third material in the second portion of the second gate insulating film excluding the damaged region.

16. The method of claim 15, wherein the second gate insulating film comprises: A first insulating layer is formed on the first main surface of the semiconductor substrate in the first region and is composed of silicon oxide. A second insulating layer is formed on the first insulating layer and is composed of silicon nitride. A third insulating layer is formed on the second insulating layer and is composed of silicon oxide.

17. The method of claim 14, further comprising the following step after step (j): (k) A second interlayer insulating film is formed on the first main surface of the semiconductor substrate, such that the first gate electrode, the second gate electrode, the third gate electrode, and the first interlayer insulating film are covered by the second interlayer insulating film. (l) After step (k), a contact hole is formed that penetrates each of the first interlayer insulating film and the second interlayer insulating film to reach the first main surface of the semiconductor substrate, and a conductive material is embedded in the contact hole; as well as (m) After step (l), a multi-wire layer is formed on the second interlayer insulating film.

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