Display panel

Abstract

The application provides a display panel, which comprises a data line, a transistor electrically connected with the data line, wherein the transistor comprises a patterned active layer arranged in a region corresponding to the data line, and a shielding layer arranged between the patterned active layer and the data line. By arranging the patterned active layer of the transistor electrically connected with the data line in the region corresponding to the data line, the patterned active layer and the data line are stacked in the thickness direction of the display panel, the space required for arranging the patterned active layer and the data line is reduced, the width of the repeated unit is reduced, and the display panel is beneficial to realize high-resolution display. In addition, the shielding layer is arranged between the patterned active layer and the data line, so as to avoid the influence of the voltage of the data line on the normal work of the patterned active layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0002] At present, virtual reality technology has been introduced in the military and aviation fields, and high resolution is the development trend of virtual reality technology. The resolution of about 1000 launched by the market still cannot meet the demand of virtual reality technology for high resolution.

[0003] Therefore, it is necessary to provide a technical scheme to improve the resolution. SUMMARY

[0004] The purpose of the present application is to provide a display panel, which avoids the influence of the data line on the normal work of the patterned active layer when the data line and the patterned active layer are stacked to improve the resolution.

[0005] To achieve the above purpose, the technical scheme is as follows:

[0006] A display panel, comprising:

[0007] a data line;

[0008] a transistor electrically connected with the data line, and the transistor comprises a patterned active layer, and the patterned active layer is arranged in a region corresponding to the data line; and

[0009] a shielding layer arranged between the patterned active layer and the data line.

[0010] Beneficial effects: the present application provides a display panel, by arranging the patterned active layer of the transistor electrically connected with the data line in the region corresponding to the data line, so that the patterned active layer and the data line are stacked in the thickness direction of the display panel, the space required for arranging the patterned active layer and the data line is reduced, the width of the repeated unit is reduced, which is beneficial to the display panel to realize high resolution display. In addition, the shielding layer is arranged between the patterned active layer and the data line to avoid the influence of the voltage of the data line on the normal work of the patterned active layer. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a sectional view of a display panel in the prior art;

[0012] Figure 2 is Figure 1 is a plan view of the display panel shown in the figure;

[0013] Figure 3 is a sectional view of a display panel of the first embodiment of the present application;

[0014] Figure 4 isFigure 3 a plan view of the display panel shown in FIG. 1;

[0015] Figure 5 FIG. 2 is a plan view of the display panel shown in FIG. 1; Figure 4

[0016] Figure 6 FIG. 3 is a plan view of the display panel shown in FIG. 1; Figure 4

[0017] Figure 7 FIG. 4 is a plan view of the display panel shown in FIG. 1;

[0018] Figure 8 FIG. 5 is a plan view of the display panel shown in FIG. 1; Figure 7

[0019] Figure 9 FIG. 6 is a plan view of the display panel shown in FIG. 1; Figure 4

[0020] Figure 10 FIG. 7 is a plan view of the display panel shown in FIG. 1; Figure 4

[0021] Figure 11 FIG. 8 is a cross-sectional view of the display panel shown in FIG. 1;

[0022] Figure 12 FIG. 9 is a cross-sectional view of the display panel shown in FIG. 1;

[0023] Figure 13 FIG. 10 is a plan view of the display panel shown in FIG. 1; Figure 12

[0024] Figure 14 FIG. 11 is a cross-sectional view of the display panel shown in FIG. 1;

[0025] Figure 15 FIG. 12 is a process diagram of manufacturing the display panel shown in FIG. 1. Figure 11 DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0027] Please refer to Figure 1 and Figure 2 , Figure 1 FIG. 13 is a cross-sectional view of a display panel in the prior art, Figure 2 ​​​​​​​For Figure 1 A plan view schematic diagram of a display panel is shown in FIG. 3. In the prior art, the display panel 300 includes a substrate 301, a light shielding layer 302, a buffer layer 303, a patterned active layer 304, a gate insulating layer 305, a gate 306, an interlayer insulating layer 307, a source 308, a drain 309, a first passivation layer 310, a common electrode 311, a second passivation layer 312, a pixel electrode 313, a scan line 314, and a data line 316.

[0028] The light shielding layer 302 is disposed on the substrate 301. The buffer layer 303 covers the light shielding layer 302 and the substrate 301. The patterned active layer 304 is disposed on the buffer layer 303, and the channel of the patterned active layer 304 is shielded by the light shielding layer 302. The patterned active layer 304 is in a U shape. The gate insulating layer 305 covers the patterned active layer 304 and the buffer layer 303. The scan line 314 is disposed on the gate insulating layer 305. The portion of the patterned active layer 304 overlapping with the scan line 314 is two gates, and the portion of the patterned active layer 304 overlapping with the scan line 314 is two channel regions. The interlayer insulating layer 307 covers the gate insulating layer 305 and the gate 306. The source electrode 308 and the drain electrode 309 are disposed on the interlayer insulating layer 307. The source electrode 308 is electrically connected to the portion of the patterned active layer 304 corresponding to the source electrode contact region through the first connection via hole 300a penetrating the interlayer insulating layer 307 and the gate insulating layer 305. The drain electrode 309 is electrically connected to the portion of the patterned active layer 304 corresponding to the drain electrode contact region through the second connection via hole 300b penetrating the interlayer insulating layer 307 and the gate insulating layer 305. The data line 316, the source electrode 308, and the drain electrode 309 are disposed in the same layer. The first passivation layer 310 covers the source electrode 308, the drain electrode 309, and the interlayer insulating layer 307. The common electrode 311 is disposed on the first passivation layer 310. The second passivation layer 312 covers the first passivation layer 310 and the common electrode 311. The pixel electrode 313 is disposed on the second passivation layer 312 and is electrically connected to the drain electrode 309 through the third connection via hole 300c penetrating the second passivation layer 312 and the first passivation layer 310. In the conventional technology, the drain electrode 309 is disposed between two adjacent data lines 316. The width of the data line 316 is L1, the distance between the drain electrode 309 and one adjacent data line 316 is L2, the width of the drain electrode 309 is L3, the distance between the drain electrode 309 and the other adjacent data line 316 is L4, and the width of the repeating unit composed of one data line 316, the transistor electrically connected to the data line 316, and the pixel electrode (not shown) is L1+L2+L3+L4. Limited by the process capability of panel exposure and the like, the minimum width of the metal line can only be about 1.5 microns, the minimum size of the via hole on the inorganic insulating layer is about 2 microns, and the minimum size of the via hole on the organic insulating layer is about 3-5 microns, resulting in that the minimum value of L1+L2+L3+L4 is 7-8 microns. Correspondingly, the maximum resolution can only reach about 1000, and the resolution of about 1000 cannot meet the demand for immersion of virtual reality technology.

[0029] In view of the problems of the prior art, the display panel of the present application sets the patterned active layer of the transistor electrically connected with the data line in the region corresponding to the data line, so that the patterned active layer is overlaid with the data line, thereby reducing the width of the repeating unit composed of the data line, the transistor electrically connected with the data line and the pixel electrode, and setting the source and the drain electrically connected with the patterned active layer in the region corresponding to the data line, and setting the via hole required for electrically connecting the source with the data line, the via hole required for electrically connecting the source with the patterned active layer, the via hole required for electrically connecting the drain with the patterned active layer and the via hole required for electrically connecting the drain with the pixel electrode in the region corresponding to the data line, so that the transistor electrically connected with the data line is set in the region corresponding to the data line, so that the pixel electrode is mainly set between two adjacent data lines, thereby realizing the minimum width of the repeating unit of about 4 microns under the existing process capability, and realizing the resolution of more than 2000, so that the resolution of the display panel is significantly improved, and the demand for high resolution in the virtual reality field is met. In addition, the patterned active layer is set in the region corresponding to the data line, and the change of the data voltage transmitted by the data line will affect the normal work of the patterned active layer, and the shielding layer is set between the patterned active layer and the data line, and the shielding layer plays a shielding role, so as to avoid the change of the data voltage affecting the normal work of the patterned active layer.

[0030] Please refer to Figures 3-4 , Figure 3 The figure is a cross-sectional schematic view of the display panel of the first embodiment of the present application. Figure 4 The figure is a plan view of the display panel shown in the figure. Figure 1 The display panel 100 is a liquid crystal display panel. It can be understood that the display panel 100 can also be an organic light-emitting diode display panel. The display panel 100 has a display area 100a and a peripheral area 100b, and the peripheral area 100b is located outside the display area 100a.

[0031] The display panel 100 includes a substrate 10, a data line 11, a first buffer layer 121, a second buffer layer 122, a gate insulating layer 13, an interlayer insulating layer 14, a first passivation layer 15, a second passivation layer 16, a transistor 20, a pixel electrode 17, a common electrode 18, a scan line 19 and a shielding layer 21. The transistor 20 is arranged in the display area 100a of the display panel 100.

[0032] The display panel 100 includes a plurality of repeating units arranged in an array and arranged in the display area 100a, each repeating unit including a data line 11, a transistor 20 and a pixel electrode 17, the transistor 20 being electrically connected with the data line 11 and the pixel electrode 17.

[0033] In the present embodiment, the substrate 10 is a glass substrate. It can be understood that the substrate 10 can also be a flexible substrate 10.

[0034] In this embodiment, the data line 11 is disposed on the substrate 10, and the data line 11 is located in the metal film layer where the conventional light-shielding layer is located, providing conditions for the data line 11 and the transistor 20 to be stacked in the thickness direction of the display panel 100. While transmitting data signals, the data line 11 also serves a light-shielding function. Figure 4 and Figure 5 As shown, Figure 5 for Figure 4 A planar schematic diagram of the data line. Data lines 11 are straight strips, each extending vertically, with multiple data lines 11 arranged parallel to each other. Unlike traditional light-shielding layers with a thickness of 500 angstroms, the thickness of the data lines 11 is greater than 500 angstroms to ensure that the impedance of the data lines 11 meets the requirements for transmitting data signals. The thickness of the data lines 11 is 2000-4000 angstroms, for example, 3000 angstroms. The material used to fabricate the data lines 11 is selected from at least one of molybdenum, aluminum, titanium, copper, and silver.

[0035] In this embodiment, transistor 20 is electrically connected to both data line 11 and pixel electrode 17. Transistor 20 acts as a switch, controlling whether the data signal transmitted through data line 11 is transmitted to pixel electrode 17. Transistor 20 is a low-temperature polycrystalline silicon transistor. It is understood that transistor 20 can also be a metal-oxide-semiconductor transistor or an amorphous silicon transistor.

[0036] In this embodiment, transistor 20 includes a patterned active layer 201, a source 2021, a drain 2022, and a gate 203. For example... Figure 4 and Figure 6 As shown, the patterned active layer 201 has a channel region 201a, a source contact region 201b, a drain contact region 201c, and a lightly doped region 201d. The channel region 201a of the patterned active layer 201 is the area where the patterned active layer 201 overlaps with the scan line 19. One lightly doped region 201d is disposed between the source contact region 201b and the channel region 201a, and another lightly doped region 201d is disposed between the drain contact region 201c and the channel region 201a. The portion of the patterned active layer 201 corresponding to the channel region 201a and the portion of the patterned active layer 201 corresponding to the lightly doped region 201d constitutes the channel of the patterned active layer 201. The source 2021 is electrically connected to the data line 11 and the portion of the patterned active layer 201 corresponding to the source contact region 201b. The drain 2022 is electrically connected to the pixel electrode 17 and the portion of the patterned active layer 201 corresponding to the drain contact region 201c.

[0037] In the embodiment, the patterned active layer 201 is arranged in the region corresponding to the data line 11, that is, the patterned active layer 201 and the data line 11 are arranged in the thickness direction of the display panel 100. The patterned active layer 201 adopts the same linear strip shape design as the data line 11 and is arranged in parallel with the data line 11.

[0038] The present application reduces the space required for arranging the patterned active layer 201 and the data line 11 by stacking the patterned active layer 201 and the data line 11, so that the width of the repeating unit composed of the data line 11, the transistor 20 electrically connected to the data line 11, and the pixel electrode 17 is greatly reduced, which is conducive to improving the resolution of the display panel 100. In addition, the stacking of the patterned active layer 201 and the data line 11 provides conditions for arranging the source 2021 and the drain 2022 of the transistor 20 in the region corresponding to the data line 11.

[0039] Further, the orthographic projection of the patterned active layer 201 on the substrate 10 is located within the orthographic projection of the data line 11 on the substrate 10, that is, the width of the data line 11 is greater than the width of the patterned active layer 201 and the length of the data line 11 is greater than the length of the corresponding patterned active layer 201, so that the data line 11 can completely shield the light incident on the channel of the patterned active layer 201 while avoiding the risk of the patterned active layer 201 climbing, thereby avoiding the failure of the patterned active layer 201 to crystallize by rapid thermal annealing.

[0040] In addition, since the patterned active layer 201 is arranged corresponding to the data line 11, the data line 11 carries data signals, and when the gate 203 of the transistor 20 is closed, the 5V data voltage transmitted by the data line 11 may cause the channel of the transistor 20 to open, which is equivalent to the data line 11 acting as a bottom gate to cause the transistor 20 to leak. In view of this, the present application provides a shielding layer 21 between the patterned active layer 201 and the data line 11, which shields the data voltage of the data line 11 from affecting the patterned active layer 201.

[0041] In the embodiment, the orthographic projection of the channel of the patterned active layer 201 on the substrate 10 is located within the orthographic projection of the shielding layer 21 on the substrate 10, so that the shielding layer 21 shields the data signals transmitted by the data line from affecting the channel of the patterned active layer. The first buffer layer 121 covers the data line 11 and the substrate 10, the shielding layer 21 is arranged on the first buffer layer 121, and the second buffer layer 122 covers the shielding layer 21 and the first buffer layer 121. The thickness of the shielding layer 21 is 450 angstroms-550 angstroms, for example, the thickness of the shielding layer 21 is 500 angstroms, to avoid the problem of annealing failure in the active layer process due to the excessive thickness of the shielding layer 21. The preparation material of the shielding layer 21 can be a transparent conductive material or a metal. The transparent conductive material can be indium zinc oxide or indium tin oxide. The metal can be at least one of molybdenum, aluminum, titanium, copper, and silver.

[0042] In the embodiment, at least one of the source 2021 and the drain 2022 electrically connected with the patterned active layer 201 can be overlaid with the data line 11, further reducing the width of the repeat unit, on the premise that the patterned active layer 201 is overlaid with the data line 11.

[0043] In the embodiment, the gate insulating layer 13 is disposed between the patterned active layer 201 and the source 2021. The material of the gate insulating layer 13 is selected from at least one of silicon nitride or silicon oxide.

[0044] Specifically, the gate insulating layer 13 covers the patterned active layer 201 and the second buffer layer 122, and the source 2021 is disposed on the gate insulating layer 13. As shown in Figure 4 , the source 2021 is in a linear strip shape, the source 2021 is parallel to the data line 11, and the source 2021 is disposed in a region corresponding to the data line 11, for example, the orthographic projection of the source 2021 on the substrate 10 is located within the orthographic projection of the data line 11 on the substrate 10.

[0045] In the embodiment, the gate insulating layer 13 is provided with a first via hole 13a, and the part of the source 2021 corresponding to the source contact region 201b of the patterned active layer 201 is electrically connected through the first via hole 13a, and the first via hole 13a is disposed in a region corresponding to the data line 11, so as to further reduce the width of the repeat unit, and further improve the resolution. Specifically, the orthographic projection of the first via hole 13a on the substrate 10 is located within the orthographic projection of the data line 11 on the substrate 10.

[0046] In the embodiment, the source 2021 is electrically connected with the data line 11 through a second via hole 13b penetrating the gate insulating layer 13, the first buffer layer 121 and the second buffer layer 122, and the second via hole 13b is disposed in a region corresponding to the data line 11, so as to further reduce the width of the repeat unit, and further improve the resolution. Specifically, the orthographic projection of the second via hole 13b on the substrate 10 is located within the orthographic projection of the data line 11 on the substrate 10.

[0047] In the embodiment, as shown in Figure 3 and Figure 9 , the scan line 19 is in the same layer as the source 2021 and is separately disposed, so that the source 2021 can be overlaid with the data line 11, which is conducive to reducing the width of the repeat unit. In addition, when the data line 11 is disposed in the film layer where the traditional light shielding film layer is located, the scan line 19 is disposed in the same layer as the source 2021, which is conducive to electrically connecting the source 2021 with the part of the data line 11 corresponding to the source contact region 201b of the patterned active layer 201.

[0048] The scan line 19 is insulated from and perpendicularly intersects the data line 11, and the portion of the scan line 19 intersecting the patterned active layer 201 corresponds to the gate 203 of the patterned active layer 201. Since the patterned active layer 201 perpendicularly intersects the scan line 19, the patterned active layer 201 has only one channel region 201a, and correspondingly, the transistor 20 is a transistor having one gate. In contrast to a conventional transistor being a transistor having two gates, the transistor 20 having one gate of the present application is also feasible as a switch.

[0049] In the present embodiment, since the data line 11 is electrically connected to the source 2021 through the second via hole 13b, the second via hole 13b is arranged corresponding to the data line 11, and if the shielding layer 21 is arranged corresponding to the data line 11 and parallel to the data line 11, the shielding layer 21 needs to be designed with a hole to avoid the second via hole 13b, and the hole design and the source 2021 passing through the via hole on the shielding layer 21 to be electrically connected to the data line 11 will increase the complexity of the process. In view of this, the shielding layer 21 is arranged corresponding to the scan line 19 and parallel to the scan line 19 to achieve the shielding function of the shielding layer 21 while avoiding the need for the shielding layer 21 to be designed with a hole.

[0050] Specifically, as shown in Figure 7 and Figure 8 , the Figure 7 is a plan view of the layout of the shielding layer, the patterned active layer, the scan line and the data line, Figure 8 is Figure 7 a plan view of the shielding layer. The shielding layer 21 includes a shielding trunk portion 211, which is arranged corresponding to the scan line 19 and parallel to the scan line 19 to avoid the portion of the patterned active layer 201 corresponding to the channel region 201a being affected by the data signal transmitted by the data line 11. The width of the shielding trunk portion 211 is greater than or equal to the width of the scan line 19.

[0051] Further, the shielding layer 21 further includes a shielding extension portion 212, which is extended from the shielding trunk portion 211 and arranged corresponding to the portion of the patterned active layer 201 corresponding to the lightly doped region 201d, to further avoid the data signal transmitted by the data line 11 affecting the portion of the patterned active layer 201 corresponding to the lightly doped region 201d, and further avoid the channel of the patterned active layer 201 being affected by the data signal transmitted by the data line 11.

[0052] In the embodiment, the interlayer insulating layer 14 is arranged between the source electrode 2021 and the drain electrode 2022, the drain electrode 2022 and the portion of the patterned active layer 201 corresponding to the drain contact region 201c are electrically connected through the third via hole 14a, the third via hole 14a penetrates the interlayer insulating layer 14 and the gate insulating layer 13, and the third via hole 14a is arranged in the region corresponding to the data line 11, so as to further reduce the width of the repeating unit and improve the resolution.

[0053] Specifically, as shown in Figure 3 and Figure 10 , the drain electrode 2022 is arranged on the interlayer insulating layer 14, and the drain electrode 2022 is arranged corresponding to the data line 11, and the drain electrode 2022 is in a linear strip shape. The orthographic projection of the third via hole 14a on the substrate 10 is located in the orthographic projection of the data line 11 on the substrate 10. The preparation material of the interlayer insulating layer 14 is selected from at least one of silicon nitride and silicon oxide.

[0054] In the embodiment, the first passivation layer 15 and the second passivation layer 16 are arranged between the drain electrode 2022 and the pixel electrode 17, the first passivation layer 15 is arranged close to the drain electrode 2022, and the second passivation layer 16 is arranged close to the pixel electrode 17. The pixel electrode 17 and the drain electrode 2022 are electrically connected through the fourth via hole 15a penetrating the first passivation layer 15 and the second passivation layer 16, and the fourth via hole 15a is arranged in the region corresponding to the data line 11.

[0055] Specifically, the first passivation layer 15 covers the drain electrode 2022 and the interlayer insulating layer 14, the common electrode 18 is arranged on the first passivation layer 15, the second passivation layer 16 covers the common electrode 18 and the first passivation layer 15, and the pixel electrode 17 is arranged on the second passivation layer 16. The orthographic projection of the fourth via hole 15a on the substrate 10 is located in the orthographic projection of the data line 11 on the substrate. Among them, the first passivation layer 15 is an inorganic insulating layer, and the second passivation layer 16 is also an inorganic insulating layer.

[0056] It can be understood that the first passivation layer 15 can be an organic insulating layer, and the second passivation layer 16 is an inorganic insulating layer. Compared with the first passivation layer 15 being an inorganic insulating layer, the size of the fourth via hole 15a is about 1.5 microns, the first passivation layer 15 being an organic insulating layer makes the size of the fourth via hole 15a about 3-5 microns, and the first passivation layer 15 being an organic insulating layer will cause the fourth via hole 15a to occupy more space.

[0057] In the embodiment, the pixel electrode 17 is arranged in the region between the two adjacent data lines 11. The preparation materials of the pixel electrode 17 and the common electrode 18 are both transparent metal oxides.

[0058] In the embodiment, as shown in Figure 4As shown, the width of a repeating unit is equal to the sum of the width L5 of the data line 11 and the spacing L6 between two adjacent data lines 11. The spacing L6 between two adjacent data lines 11 mainly depends on the width of the pixel electrode. Under the current manufacturing process capabilities of display panels, the minimum value of L5+L6 can be about 4 micrometers.

[0059] In this embodiment, the display panel 100 further includes a connecting wire 22 disposed in the peripheral area 100b, and a shielding layer 21 extending from the display area 100a to the peripheral area 100b. One end of the connecting wire 22 is electrically connected to the common electrode 18, and the other end of the connecting wire 22 is electrically connected to the shielding layer 21, so that the shielding layer 21 transmits a common voltage signal and the shielding layer 21 transmits a fixed voltage signal to perform a shielding function.

[0060] Specifically, the connecting wire 22 is disposed on the same layer as the drain 2022, and is electrically connected to the shielding layer 21 through the sixth via 22a that penetrates the interlayer insulating layer 14, the gate insulating layer 13 and the second buffer layer 122, and is electrically connected to the common electrode 18 through the seventh via 22b on the first passivation layer 15.

[0061] In this embodiment, the display panel places the patterned active layer of the transistor in the area corresponding to the data line electrically connected to the transistor. The source and corresponding via of the patterned active layer and the data line electrically connected, as well as the drain and corresponding via of the patterned active layer and the pixel electrode electrically connected, are all placed in the area corresponding to the data line, so that the transistor and the data line are stacked, thereby minimizing the width of the repeating unit.

[0062] like Figure 11 As shown, Figure 11 This is a cross-sectional schematic diagram of the display panel according to the second embodiment of this application. Figure 11 The display panel shown is Figure 3 The display panels shown are basically similar, except that the display panel 100 also includes a bridging wire 23 and a connecting wire 22 disposed in the peripheral area 100b. The connecting wire 22 is disposed on the same layer as the drain 2022, and the bridging wire 23 is disposed on the same layer as the pixel electrode 17. The bridging wire 23 bridges the connecting wire 22 and the common electrode 18 of the peripheral area 100b.

[0063] Specifically, the connecting wire 22 is disposed on the same layer as the drain electrode 2022, and the connecting wire 22 is electrically connected to the shielding layer 21 through a sixth via 22a that penetrates the interlayer insulating layer 14, the gate insulating layer 13, and the second buffer layer 122. The bridging wire 23 is disposed on the same layer as the pixel electrode 17, one end of the bridging wire 23 is electrically connected to the common electrode 18 through an eighth via 23a that penetrates the second passivation layer 16, and the other end of the bridging wire 23 is electrically connected to the connecting wire 23 through a ninth via 23b that penetrates the first passivation layer 15 and the second passivation layer 16.

[0064] As shown in Figure 12 and Figure 13 , a cross-sectional schematic view of a display panel of a third embodiment of the present application is shown. Figure 12 As shown in Figure 13 , a planar schematic view of the display panel is shown. Figure 12 As shown in Figure 12 The display panel shown in Figure 11 is basically similar to the display panel shown in The difference is that the source electrode 2021 is electrically connected to the data line 11 and the part of the patterned active layer 201 corresponding to the source contact region 201b of the patterned active layer 201 through the tenth via hole 13c penetrating through the gate insulating layer 13, the second buffer layer 122 and the first buffer layer 121.

[0065] As shown in Figure 14 , a cross-sectional schematic view of a display panel of a fourth embodiment of the present application is shown. Figure 14 As shown in Figure 3 , the display panel shown in is basically similar to the display panel shown in The difference is that the pixel electrode 17 is disposed on the first passivation layer 15, and the common electrode 18 is disposed on the second passivation layer 16. The pixel electrode 17 is electrically connected to the drain electrode 2022 through the eleventh via hole 15b penetrating through the first passivation layer 15, and the common electrode 18 located in the peripheral region 100b is electrically connected to the connection wire 22 through the twelfth via hole 22c penetrating through the first passivation layer 15 and the second passivation layer 16.

[0066] The present application also provides a manufacturing method of a display panel. Figure 11 As an example of the display panel shown in The manufacturing method of the display panel comprises the following steps:

[0067] S101: As shown in A of Figure 15 , a data line 11 is formed on a substrate 10, and the data line 11 extends from a display region 100a to a peripheral region 100b.

[0068] S102: As shown in B of Figure 15 , a first buffer layer 121 covering the data line 11 and the substrate 10 is formed, and a shielding layer 21 is formed on the first buffer layer 121, and the shielding layer 21 extends from the display region 100a to the peripheral region 100b. A second buffer layer 122 covering the shielding layer 21 and the first buffer layer 121 is formed, and a patterned active layer 201 is formed on the second buffer layer 122. The patterned active layer 201 is disposed corresponding to the data line 11.

[0069] S103: As shown in Figure 15As shown in C, a portion of the patterned active layer is ion-doped to form a lightly doped region 201d, a source contact region 201b, and a drain contact region 201c. The region between the two lightly doped regions 201d is the channel region 201a and is not ion-doped. The ion doping concentration of the portion of the patterned active layer 201 corresponding to the source contact region 201b and the drain contact region 201c is higher than the ion doping concentration of the portion of the patterned active layer 201 corresponding to the lightly doped region 201d.

[0070] S104: As Figure 15 As shown in D, a gate insulating layer 13 is formed to cover the patterned active layer 201. A second via 13b is formed in the display area 100a, penetrating the gate insulating layer 13, the first buffer layer 121, and the second buffer layer 122. The second via 13b is disposed in the area corresponding to the data line 11 and exposes the data line 11.

[0071] S105: As Figure 15 As shown in E, a first via 13a is formed in the display area 100a, penetrating the gate insulating layer 13. The first via 13a is disposed in the area corresponding to the data line 11, and the first via 13a exposes a portion of the source contact area 201b corresponding to the patterned active layer 201. The first via 13a and the second via 13b are formed respectively.

[0072] S106: As Figure 15 As shown in F, a source 2021 is formed in the first via 13a, the second via 13b, and on the gate insulating layer 13, while a gate 203 is formed on the gate insulating layer 13. The source 2021 is electrically connected to a portion of the source contact region 201b corresponding to the patterned active layer 201 through the first via 13a, and the source 2021 is electrically connected to the data line 11 through the second via 13b.

[0073] S107: As Figure 15 As shown in G, an interlayer insulating layer 14 is formed covering the gate insulating layer 13, the gate 203 and the source 2021, and a sixth via 22a is formed penetrating the interlayer insulating layer 14, the gate insulating layer 13 and the second buffer layer 122. The sixth via 22a is located in the peripheral region 100b and exposes the shielding layer 21.

[0074] S108: As Figure 15 As shown in H, a third via 14a is formed that penetrates the interlayer insulating layer 14 and the gate insulating layer 13, exposing a portion of the patterned active layer 201 corresponding to the drain contact region 201c. The third via 14a is located in the region corresponding to the data line 11.

[0075] S109: As Figure 15As shown in I of FIG. 6, a drain 2022 is formed in the third via hole 14a and on the interlayer insulating layer 14, and a connecting wire 22 is formed in the sixth via hole 22a and on the interlayer insulating layer 14. The drain 2022 is electrically connected to the part of the patterned active layer 201 corresponding to the drain contact region 201c through the third via hole 14a, and the connecting wire 22 is electrically connected to the shielding layer 21 through the sixth via hole 22a.

[0076] S110: As shown in Figure 15 As shown in J of FIG. 7, a first passivation layer 15 is formed to cover the connecting wire 22, the drain 2022 and the interlayer insulating layer 14, and a common electrode 18 is formed on the first passivation layer 15.

[0077] S111: As shown in Figure 15 As shown in K of FIG. 8, a second passivation layer 16 is formed to cover the common electrode 18 and the first passivation layer 15, and an eighth via hole 23a is formed through the second passivation layer 16 at the same time when a ninth via hole 23b and a fourth via hole 15a are formed through the first passivation layer 15 and the second passivation layer 16. The fourth via hole 15a is arranged in the region corresponding to the data line 11 and exposes the drain 2022, and the fourth via hole 15a is located in the display area 100a. The eighth via hole 23a exposes the common electrode 18 located in the peripheral area 100b. The ninth via hole 23b exposes the connecting wire 22.

[0078] S112: As shown in Figure 15 As shown in L of FIG. 9, a pixel electrode 17 is formed on the second passivation layer 16 in the display area 100a, and a bridge wire 23 is formed in the eighth via hole 23a, the ninth via hole 23b and on the second passivation layer 16. The pixel electrode 17 is electrically connected to the drain. The bridge wire 23 bridges the common electrode 18 and the connecting wire 22.

[0079] The above description of the embodiments is only used to help understand the technical solutions of the present application and its core idea; those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a data line disposed on the substrate; a scan line disposed on the substrate, insulated from and intersecting the data line; a transistor disposed on the substrate and electrically connected to the data line, the transistor comprising a patterned active layer located on a side of the data line facing away from the substrate, the patterned active layer overlapping the data line and having a channel and a lightly doped region; and a shielding layer disposed between the patterned active layer and the data line, and comprising: a shielding trunk portion overlapping and parallel to the scan line; a normal projection of the channel on the substrate being located within a normal projection of the shielding trunk portion on the substrate; and a shielding extension portion extending from the shielding trunk portion and overlapping a portion of the patterned active layer corresponding to the lightly doped region. The thickness of the shielding layer is 450 angstroms to 550 angstroms.

2. The display panel of claim 1, wherein, The shielding layer comprises a metal or a transparent conductive material.

3. The display panel of claim 1 or 2, wherein, The width of the shielding trunk portion is greater than the width of the scan line.

4. The display panel of claim 1, wherein, A normal projection of the patterned active layer on the substrate is located within a normal projection of the data line on the substrate.

5. The display panel of claim 1, wherein, The display panel further comprises a common electrode, the shielding layer being electrically connected to the common electrode.

6. The display panel of claim 5, wherein, The display panel has a peripheral region, and the display panel further comprises: a connection wire disposed in the peripheral region, one end of the connection wire being electrically connected to the common electrode, and the other end of the connection wire being electrically connected to the shielding layer.

7. The display panel of claim 5, wherein, The display panel has a peripheral region, and the display panel further comprises: a pixel electrode disposed on a side of the common electrode facing away from the shielding layer; a connection wire disposed in the peripheral region and electrically connected to the shielding layer; a bridge wire disposed in the peripheral region, the bridge wire being disposed in the same layer as the pixel electrode and being insulated, and the bridge wire bridging the connection wire and the common electrode.

8. The display panel of claim 1, wherein, The display panel further comprises a first buffer layer and a second buffer layer, the first buffer layer covering the data line and the substrate; the shielding layer being disposed on the first buffer layer; the second buffer layer covering the first buffer layer and the shielding layer; the patterned active layer being disposed on the second buffer layer and corresponding to the data line.

9. The display panel of claim 8, wherein, The patterned active layer has a source contact region and a drain contact region, the display panel further comprises a gate insulating layer and an interlayer insulating layer, and the transistor further comprises a source and a drain, the gate insulating layer covering the patterned active layer and the second buffer layer; the source being disposed on the gate insulating layer, and being electrically connected to a portion of the patterned active layer corresponding to the source contact region through a first via hole penetrating the gate insulating layer, and being electrically connected to the data line through a second via hole penetrating the gate insulating layer, the second buffer layer and the first buffer layer; the interlayer insulating layer covering the source and the gate insulating layer; the drain being disposed on the interlayer insulating layer, and being electrically connected to a portion of the patterned active layer corresponding to the drain contact region through a third via hole penetrating the interlayer insulating layer and the gate insulating layer. The source, the drain, the first via, the second via and the third via overlap with the data line.

10. The display panel of claim 9, wherein, The display panel further comprises a pixel electrode and a passivation layer, the passivation layer is arranged between the pixel electrode and the drain, The drain and the pixel electrode are electrically connected through a fourth via on the passivation layer, and the fourth via overlaps with the data line.

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