Generation and synchronization of pulse width modulation (PWM) waveforms for radio frequency (RF) applications

Abstract

Concepts, systems, circuits and techniques are described for methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase relative to a reference signal.

Description

Background Art

[0001] As is known in the art, impedance matching networks are commonly used to maximize power transfer within many radio frequency (RF) and microwave systems. For example, in an RF transmitter, an impedance matching network can be used to provide an impedance match from the output impedance of an RF power amplifier (PA) to the impedance of an RF load (e.g., an antenna). This impedance matching increases the power transmitted, reduces power losses, and reduces or eliminates the need for additional circuit elements (e.g., isolators, etc.).

[0002] One class of impedance matching networks is known as a tunable impedance matching network (TMN), sometimes referred to as an automatic antenna tuning unit. A conventional TMN can be implemented as a single element or lumped-element reactive network, in which at least one of the reactive elements is a variable (e.g., tunable) element such that the impedance of the variable element can be modified at a specific frequency or over a range of frequencies. The reactive elements within a TMN can be arranged in a circuit topology such as a ladder network, an L network, a T network, or a Pi network.

[0003] Conventional TMNs can be classified as analog (continuously adjustable) or digital (adjustable among a set of discrete values). Analog TMNs utilize variable reactive elements with reactance values ​​(at a certain frequency or over a frequency range) that can be tuned in a continuous manner by adjusting bias conditions. Digital TMNs implement variable reactive elements as digitally switched arrays of static reactive elements. This approach allows the impedance of the reactive value to be adjusted in finite and discrete steps.

[0004] Analog TMNs are typically implemented using varactors (or varactor circuits) or microelectromechanical systems (MEMS) varactors.Although analog TMNs allow for fast and accurate impedance matching over a wide impedance range, operation at high power levels requires relatively high bias voltages.

[0005] Digital TMNs are typically implemented using CMOS switches, MEMS switches, PIN diodes, or discrete power transistors. Although MEMS switches have low on-state resistance and can operate at frequencies up to tens of GHz with low power consumption, MEMS switches require large control voltages. Digital TMNs based on PIN diodes and CMOS switches exhibit low to moderate on-state resistances, and can therefore handle high power levels at the expense of some resistive power losses. Digital TMNs based on PIN diodes and CMOS switches are advantageous for on-die integration, such as software defined radio (SDR) integrated circuits (ICs) and other on-chip TMNs. However, digital TMNs exhibit limited tuning resolution, and therefore exhibit limited accuracy in impedance matching that can be achieved. In some high power applications (e.g., RF plasma drivers) that require accurate impedance matching over a very wide impedance range, the use of digital TMNs may be impractical due to the need for a large number of digital switches to achieve the required fine-tuning resolution. Summary of the invention

[0006] This Summary is provided to introduce some concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key or essential features or combinations of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0007] In general, the concepts, systems and techniques described herein are directed to methods and apparatus for generating one or more pulse width modulation (PWM) waveforms (signals) with the ability to dynamically control pulse width and phase relative to a reference signal. The pulse width and phase (relative to a reference signal) of each PWM waveform can be independently adjusted from 0° to 360° with arbitrarily fine resolution independent of any operating frequency. The generated PWM signals are capable of maintaining phase and frequency lock to the reference signal over a wide modulation range of reference signal frequencies. The concepts, systems, devices and techniques described herein are suitable for generating accurate and dynamically adjustable PWM waveforms for HF and VHF applications. They have particular value in applications where reference signals are derived from a radio frequency (RF) input source, for which precise timing of PWM must be maintained, including tunable matching networks (TMNs) and PSIM amplifiers based on phase switched impedance modulation (PSIM). For example, such circuits find application in high power microwave plasma systems for use in conjunction with semiconductor processing and cleaning of semiconductor processing equipment.

[0008] In one aspect of the concepts, systems, and techniques described herein, a pulse width modulation (PWM) generator includes a phase shift circuit having at least one input and a plurality of outputs. The phase shift circuit is configured to receive a reference signal and, in response, provide a phase shift signal on each of the two or more outputs. Each phase shift signal may have a phase shift relative to the reference signal. The PWM generator may further include a waveform combiner. The waveform combiner may have a plurality of inputs, wherein each input is coupled to a corresponding output of the phase shift circuit. The waveform combiner may be configured to receive a phase shift signal from the phase shift circuit and, in response, generate a PWM signal having a pulse width and a phase shift relative to the reference signal.

[0009] With this arrangement, a PWM generator for generating a PWM signal having a pulse width and a phase shift relative to a reference signal is provided. In an embodiment, the pulse width and the phase shift of the PWM signal relative to the reference signal can be dynamically controlled. Because the waveform combiner is configured to generate PWM in response to a phase shift signal, changing the phase shift signal can adjust the pulse width and the phase shift of the PWM signal relative to the reference signal.

[0010] In an embodiment, the phase shift circuit may include a plurality of phase shift elements coupled in a parallel architecture or a cascade architecture.

[0011] In an embodiment, the phase shift circuit may include an in-phase / quadrature phase (IQ) modulator having at least three inputs and at least one output. One input of the IQ modulator may be configured to receive a reference signal, and the other two inputs of the IQ modulator may be configured to receive a baseband signal derived from the reference signal. The IQ modulator may include an adder coupled between its output and at least two of its inputs.

[0012] In an embodiment, the waveform combiner may include at least one of an edge detector, a logic gate, a flip-flop, or an amplifier. The waveform combiner may also include a plurality of amplifiers, each having an input and an output. Each input of the amplifier may be configured to receive a phase shifted signal. The waveform combiner may further include a logic gate having a plurality of inputs and at least one output. Each input of the waveform combiner may be configured to be coupled to the output of at least one amplifier.

[0013] In an embodiment, the phase shift circuit can be configured to generate two or more phase shift signals based on at least one predetermined phase shift parameter. The phase shift circuit can also be configured to receive at least one predetermined phase shift parameter from a controller. The controller can be configured to generate at least one predetermined phase shift parameter based on the pulse width and phase shift of the generated PWM signal relative to a reference signal.

[0014] In an embodiment, the PWM generator may be implemented in an integrated circuit.

[0015] The PWM generation technique proposed herein relies on the use of phase shifting elements that take an input waveform and generate an output waveform that is locked to the input in both phase and frequency (or in both delay and frequency). The phase shift (or delay) between the input and output can be dynamically controlled (via digital or analog methods), and the resolution at which the phase shift can be set ultimately determines the resolution at which the phase and pulse width of the PWM signal can be adjusted. These phase shifting elements can be connected in cascade or in parallel to form a cascade or parallel system architecture, respectively.

[0016] In another aspect of the concepts, systems and techniques described herein, a device for generating a dynamically controlled pulse width modulation (PWM) signal. The device may include two or more phase shift elements. Each phase shift element may have an input and an output, wherein the input of each phase shift element may be configured to receive a reference signal. The device may further include a waveform combiner that may be electrically coupled to the output of the phase shift element. Each phase shift element may be configured to generate a corresponding phase shift signal at its output based on the reference signal and a corresponding predetermined phase shift parameter. In addition, the waveform combiner may be configured to generate a PWM signal having a pulse width and a pulse shift based on the phase shift signal generated at the output of the phase shift element.

[0017] With this particular arrangement, a parallel architecture for generating a desired PWM signal is provided. In an embodiment, the PWM signal may have a dynamically adjustable pulse width and phase shift relative to a reference signal. By adjusting the phase shift parameter of the phase shift element, the pulse width and phase shift of the PWM signal may be dynamically controlled.

[0018] In an embodiment, each predetermined phase shift parameter may include at least one of a predetermined phase shift or a predetermined pulse width.

[0019] In an embodiment, at least one of the phase shifting elements may include an in-phase / quadrature modulator or a phase locked loop.

[0020] In an embodiment, each phase shift element may be coupled to a corresponding control signal. Each corresponding control signal may include a corresponding predetermined phase shift parameter. The apparatus may further include a phase detector coupled to the reference signal and the generated PWM signal. In an embodiment, the phase detector may be configured to generate a phase correction signal based on a comparison of the reference signal with the generated PWM signal. The phase correction signal may be provided to each phase shift element.

[0021] In an embodiment, the waveform combiner may include at least one edge detector, each edge detector being coupled to at least one flip-flop. The flip-flop may be configured to generate a PWM signal based on a rising edge of at least one generated phase-shifted signal and a rising edge of at least another generated phase-shifted signal.

[0022] In another aspect of the concepts, systems and techniques described herein, a device for generating a dynamically controlled pulse width modulation (PWM) signal is provided. These devices may include a first phase shift element having an input and an output. The input of the first phase shift element may be coupled to a reference signal. The device may also include a second phase shift element that may have an input and an output. The input of the second phase shift element may be coupled to the output of the first phase shift element. The device may also include a waveform combiner that may be electrically coupled to the outputs of the first and second phase shift elements. The first phase shift element may be configured to generate a first phase shift signal at its output based on a reference signal and a corresponding predetermined phase shift. The second phase shift element may be configured to generate a second phase shift signal at its output based on the first phase shift signal and a corresponding predetermined phase shift. The waveform combiner may be configured to generate a PWM signal having a pulse width and a pulse shift based on the first and second phase shift signals.

[0023] With this particular arrangement, a cascade architecture for generating a desired PWM signal is provided. In this arrangement, each phase shift element can receive a different, unrelated phase shift parameter. Therefore, fewer phase shift parameters may need to be adjusted to achieve the desired pulse width and phase shift of the generated PWM signal relative to the reference signal.

[0024] In an embodiment, each predetermined phase shift parameter may include at least a predetermined phase shift or a predetermined pulse width.

[0025] In an embodiment, at least one of the phase shift elements may include an in-phase / quadrature modulator. The apparatus may further include a control circuit coupled to the at least one in-phase / quadrature modulator, the control circuit being configured to provide a control signal to the at least one in-phase / quadrature modulator. In an embodiment, the control signal may include a corresponding predetermined phase shift parameter for the in-phase / quadrature modulator.

[0026] In an embodiment, at least one of the phase shifting elements comprises a phase locked loop.

[0027] In an embodiment, the apparatus may further include a phase detector that may be coupled to the reference signal and the generated PWM signal. The phase detector may be configured to generate a phase correction signal based on a comparison of the reference signal and the generated PWM signal. In an embodiment, each phase shift element may be further configured to generate a phase shift signal based on the phase correction signal.

[0028] In an embodiment, the waveform combiner may include at least one logic gate. The logic gate may be configured to compare the first and second phase shifted signals.

[0029] In another aspect of the concepts, systems and techniques described herein, a device for generating a dynamically controlled pulse width modulation (PWM) signal is described. The device may include a first group of phase shift elements, which are electrically coupled in parallel and each have an input and an output. The inputs of the first group of phase shift elements can each be electrically coupled to a reference signal. The device may also include a second group of phase shift elements, which are electrically coupled in parallel and each have an input and an output. The inputs of the second group of phase shift elements can each be electrically coupled to the output of at least one phase shift element in the first group. The device may also include a waveform combiner electrically coupled to the outputs of the first and second groups of phase shift elements. Each phase shift element in the first group can be configured to generate a corresponding phase shift signal at its output based on a reference signal and a corresponding predetermined phase shift. Each phase shift element of the second group can be configured to generate a corresponding phase shift signal at its output based on at least one phase shift signal generated by the phase shift element of the first group and a corresponding predetermined phase shift. The waveform combiner can be configured to generate a dual-pulse PWM signal having a first pulse with a pulse width and a pulse shift based on a phase-shifted signal generated by a first set of phase-shifted elements. The PWM signal can also have a second pulse with a pulse width and a pulse shift based on a phase-shifted signal generated by a second set of phase-shifted elements.

[0030] With this particular arrangement, an architecture for generating a dual pulse PWM signal is provided. The dual pulse PWM signal can have two pulse widths and a phase shift relative to a reference signal that can be dynamically adjusted. By having two pulse widths and a phase shift, multiple phase switching reactive elements can be driven at once.

[0031] In an embodiment, the phase shift elements of the first set may be electrically coupled in a parallel architecture.An input of each phase shift element of the first set may be coupled to a reference signal.

[0032] In an embodiment, the first set of phase shifting elements may be coupled in a cascade architecture.

[0033] In yet another aspect of the concepts, systems, and techniques described herein, a method for generating a dynamically controlled pulse width modulation (PWM) waveform is provided. The method may include receiving a reference signal at one or more phase shift elements. Each phase shift element may have a corresponding predetermined phase shift parameter. The method may also include generating a corresponding phase shift signal at the output of the one or more phase shift elements based on the reference signal and the corresponding predetermined phase shift parameter. The method may further include combining the generated phase shift signals to obtain a PWM waveform having a pulse width and phase shift based on the predetermined phase shift parameters of the phase shift elements.

[0034] With this particular arrangement, a method for generating a PWM signal with dynamically controlled pulse width and phase shift relative to a reference signal is provided.By adjusting the phase shift parameter, the pulse width and phase shift of the PWM signal can be dynamically controlled.

[0035] In an embodiment, each respective predetermined phase shift parameter may include at least one of a respective predetermined phase shift or a respective predetermined pulse width.

[0036] In an embodiment, the method may further comprise providing a corresponding control signal to each phase shift element. The control signal may comprise a corresponding predetermined phase shift parameter.

[0037] In an embodiment, the method may further include generating a phase correction signal based on a comparison of the reference signal and the PWM waveform.

[0038] In an embodiment, the method may further include adjusting the generated phase shifted signal based on the phase correction signal.

[0039] In another aspect of the concepts, systems and techniques described herein, a power generation and delivery system having an input port and an output port is provided. The power generation and delivery system may include a pulse width modulation (PWM) signal generator, which may include one or more phase shift elements. The PWM signal generator may be used to generate a PWM signal based on a phase shift parameter associated with one or more phase shift elements. The power generation and delivery system may also include a phase-switched tunable impedance network coupled to the output port. The phase-switched tunable impedance network may be configured to receive the generated PWM signal from the PWM signal generator, and in response, may change its impedance to modulate the impedance presented to the output port.

[0040] With this particular arrangement, a phase-switched tunable impedance (PSIM) network driven by a PWM signal is provided. Because the PWM signal generated by the PWM generator can have its pulse width or phase shift relative to a dynamically adjusted reference signal, these parameters can be adjusted to change the impedance presented by the PSIM.

[0041] In an embodiment, one or more phase shifting elements are electrically coupled in a parallel architecture or a cascade architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Other aspects, features, and advantages of the broad concepts sought to be protected herein will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings, in which like reference numerals identify similar or identical elements. Reference numerals introduced in the specification in connection with a drawing may be repeated in one or more subsequent drawings without additional description in the specification in order to provide context for other features.

[0043] Figure 1 is a block diagram of an illustrative tunable impedance matching network (TMN) in accordance with the described embodiments;

[0044] Figure 2 yes Figure 1 Schematic diagram of an illustrative phase-switching variable capacitance element of a TMN;

[0045] Figure 3 is relative to Figure 2 A graph showing the relationship between the current and voltage of the control signal of the phase-switching variable capacitance element and the phase;

[0046] Figure 4 yes Figure 1 Schematic diagram of an illustrative phase-switched variable inductance element of a TMN;

[0047] Figure 5 is relative to Figure 4 A graph showing the relationship between the current and voltage of the control signal of the phase-switching variable inductance element and the phase;

[0048] Figure 6 yes Figure 2 and Figure 4 A relationship diagram of the normalized effective capacitance (or inductance) of the phase switching element versus the control angle of the phase switching element;

[0049] Figure 7 yes Figure 2 and Figure 4 A graph showing the relationship between the total harmonic distortion of a phase switching element and the control angle of the phase switching element;

[0050] Figure 8is a graph of current and voltage versus phase relative to a control signal for a full-wave switched variable capacitance element;

[0051] Fig. 9 is a graph of current and voltage versus phase relative to a control signal for a full-wave switched variable inductor element;

[0052] Fig. 10A -D is a schematic diagram of an illustrative switching reactive element according to the described embodiment;

[0053] Fig.11 is a schematic diagram of an illustrative phase-switched tunable matching network (TMN) employing a digital switched capacitor matrix;

[0054] Fig.12 is a schematic diagram of an illustrative phase-switched TMN employing a digital switched inductor matrix;

[0055] Fig.13 is a schematic diagram of an illustrative phase-switched TMN in accordance with the described embodiments;

[0056] Fig.14 It can be done by Fig.13 Smith chart of the load impedance range matched by the tuning network for an illustrative operating range;

[0057] Fig.15 yes Fig.13 A schematic diagram of additional details of the tuning network;

[0058] Fig.16 is a block diagram of an illustrative topology of a phase-switched impedance modulated amplifier in accordance with the described embodiments;

[0059] Fig.17 is a block diagram of another illustrative topology of a phase-switched impedance modulated amplifier in accordance with the described embodiments;

[0060] Fig.18A -E is a schematic diagram of an illustrative three-switch phase-switched impedance modulated amplifier in accordance with the described embodiments;

[0061] Fig.19 and Fig. 20 is a schematic diagram of an illustrative two-switch phase-switched impedance modulated amplifier in accordance with the described embodiments;

[0062] Fig.21 is a schematic diagram of an illustrative phase-switched impedance-modulated amplifier within an illustrative operating range;

[0063] Fig. 22 and Fig.23 is a Smith chart, which shows that Fig.21The phase-switched impedance modulated amplifier is matched to a load impedance range for an illustrative operating range;

[0064] Fig.24 is a flow chart of an illustrative process for operating a TMN;

[0065] Fig.25A is a system block diagram for generating a pulse width modulated (PWM) signal having a predetermined phase shift and pulse width;

[0066] Fig.25B is a relationship diagram of a pulse width modulation (PWM) waveform having a pulse width w and a phase shift φ relative to a reference signal, wherein the PWM signal is in phase and frequency locked with the reference signal;

[0067] Fig.26 is a block diagram of a PWM generation circuit having a parallel architecture;

[0068] Fig. 27 is a block diagram of a PWM generation circuit having a cascade architecture;

[0069] Fig.28 is a block diagram of a PWM generator circuit having a dual-pulse PWM generation architecture;

[0070] Fig.29 is a block diagram of a PWM generation circuit having a parallel PWM generation architecture with two phase shift elements and a phase detector feedback loop;

[0071] Fig.30 is a system block diagram having an architecture capable of generating multiple PWM waveforms that are phase-locked and frequency-locked to a common reference signal;

[0072] Fig.31 is a block diagram of a PWM generation circuit having an in-phase / quadrature-phase (IQ) modulator;

[0073] Fig.32 is a phase diagram showing a phase shift according to a baseband input of an IQ modulator;

[0074] Fig.33 is a block diagram of a PWM generation circuit having a parallel PWM generation architecture with two phase shifters implemented as IQ modulators;

[0075] Fig.34 is a graph of the phase shift command versus the measured phase shift error for a pair of output signals from Fig.33 a corresponding IQ modulator in an IQ modulator of a PWM generating circuit;

[0076] Fig.35is a plot of the phase shift command versus the measured phase shift standard deviation for a pair of output signals from Fig.33 a corresponding IQ modulator in an IQ modulator of a PWM generating circuit;

[0077] Fig.36 is a block diagram of a cascaded PWM waveform generator having phase shift elements implemented using a phase locked loop (PLL) module coupled to a waveform combiner;

[0078] Fig.37 is a waveform combiner with a D-type flip-flop and edge detector Fig.36 Block diagram of cascade phase-locked PWM generator;

[0079] Fig.38 It is a block diagram of a PWM signal generation system implemented using PLL;

[0080] Fig.39 is a block diagram of a PWM generation system having a nested PLL architecture with feedback;

[0081] Fig.40 is a flow chart of a method of generating a PWM signal having a desired phase shift and pulse width;

[0082] Fig.41A is a block diagram of an impedance matching system including a plurality of phase switched impedance (PSIM) elements driven by a PWM generator;

[0083] Fig.41B is a block diagram of a radio frequency ("RF") amplifier having a phase-switching tunable impedance network coupled to a system for generating a PWM signal having a desired phase shift and pulse width;

[0084] Fig.42 is a block diagram of a system having a phase-switched tunable impedance network having a phase-switched tunable impedance element coupled to a PWM generator; and

[0085] Fig.43 is a block diagram of a system having a phase-switching tunable impedance network with two phase-switching tunable impedance elements coupled to two PWM generators. DETAILED DESCRIPTION

[0086] Table 1 summarizes a list of acronyms used throughout this specification to aid in understanding the described embodiments:

[0087]

[0088] The described embodiments are directed to a phase-switched tunable matching network (PS-TMN) and a phase-switched impedance modulated amplifier (PSIM). Both the phase-switched tunable matching network and the phase-switched impedance modulated amplifier include a phase-switched variable network reactance element. When configured in the context of the PS-TMN and the phase-switched impedance modulated amplifier, such a phase-switched variable network reactance element provides fast, high bandwidth, continuous impedance matching over a wide impedance range while operating efficiently at high power levels without requiring high bias voltages or currents. The PS-TMN may be employed alone or in combination with other matching techniques (e.g., discrete switched reactance groups).

[0089] PS-TMN can be used in a variety of reconfigurable and adaptive RF systems, such as RF front-ends for software-defined radio (SDR) and cognitive radio (CR) applications, which operate over a wide frequency range, at different bandwidths, and in compliance with various communication standards. PS-TMN can also be used in other RF applications, such as drivers for RF plasma loads that compensate for rapid load changes, or in wireless power transfer (WPT) systems to compensate for impedance mismatches between transmitters and receivers, thereby maximizing the transmitted power and / or efficiency.

[0090] The PSIM can function as a zero voltage switching (ZVS) radio frequency (RF) amplifier. Such a PSIM amplifier can use the PS-TMN to operate over a large frequency range by efficiently modulating the output power over a wide frequency range and / or matching to a highly variable load (e.g., a load that is variable over a wide impedance range).

[0091] refer to Figure 1 , a radio frequency (RF) system 100 includes a coupled circuit having an impedance Z S The source 102 has an impedance Z L The source 102, the control circuit 106, and the PS-TMN 112 (as well as other elements of the RF system 100) are coupled to a power supply voltage (e.g., V DC) and ground. The control circuit 106 is coupled to the PS-TMN 112 and provides control signals to the PS-TMN 112 to control the operation of the PS-TMN 112. In response to such control signals, the PS-TMN 112 provides the desired impedance transformation characteristics. It should be understood that the control circuit 106 can be an internal component of the PS-TMN 112, or can be an external component coupled to the PS-TMN 112 or some parts of the control circuit 106 (or the functions provided by the control circuit 106 can be inside the PS-TMN 112, while other parts of the control circuit 106 can be outside the PS-TMN 112).

[0092] In some embodiments, control circuit 106 controls operation of PS-TMN 112 based at least in part on information received from optional feed-forward circuit 104 coupled to source 102 and / or optional feedback circuit 110 coupled to load 114. In some embodiments, optional feed-forward circuit 104 includes adaptive pre-distortion circuit 107, and control circuit 106 includes look-up table (LUT) 108. For example, as will be described in more detail below, some embodiments may employ one or more nonlinear control techniques (e.g., by control circuit 106) to determine appropriate control signals for PS-TMN 112, such as employing a fixed or adaptable look-up table (e.g., LUT 108) to store predetermined control signal information, feedback (e.g., by feedback circuit 110), and / or feed-forward compensation (e.g., by feed-forward circuit 104) to adaptively adjust the control signal information; or performing digital pre-distortion of the control signal (e.g., by pre-distortion circuit 107); or other similar techniques.

[0093] PS-TMN 112 includes one or more phase-switching reactive elements 116(1)-116(N). As will be described in more detail below, phase-switching reactive elements 116(1)-116(N) may be implemented using one or more capacitive elements (e.g., capacitors), one or more inductive elements (e.g., inductors), or a combination of both. Phase-switching reactive elements 116(1)-116(N) may be controlled to adjust the effective impedance (Z) presented to the PS-TMN 112 terminals at a desired frequency. S,IN and Z L,IN The phase-switched reactive elements 116(1)-116(N) are switched, for example, by shunts or series switches, and the effective impedance of the phase-switched reactive elements is controlled by adjusting the phase and / or duty cycle of the shunts or series switches. In some embodiments, the desired frequency may be the RF frequency of operation of the RF source 102 (e.g., the frequency of a signal provided from the RF source 102 to the PS-TMN 112).

[0094] By modulating the effective impedance at a desired operating frequency of RF system 100 (e.g., by adjusting the impedance of phase-switched reactive elements 116(1)-116(N)), it is possible to adjust, tune, change, or otherwise manipulate the impedance presented by PS-TMN 112 to source 102 and / or load 114. For example, phase-switched reactive elements 116(1)-116(N) allow PS-TMN 112 to present a desired impedance (Z) from source 102 to PS-TMN 112. S,IN ), and presents the desired impedance (Z L,IN ).

[0095] The control signals provided to the PS-TMN 112 operate to control the timing of switching on and / or off the switches of the phase-switched reactive elements 116(1)-116(N) relative to the RF signal provided from the source 102. The switches provide effective reactance values ​​of the phase-switched reactive elements 116(1)-116(N) that affect a desired impedance transformation of the PS-TMN 112. The feed-forward information may include information regarding the effective input impedance of the PS-TMN 112, the timing of the RF waveform, a specified signal level and / or impedance level, etc. The feedback information may include measured information regarding the effective load impedance and / or power reflected from the load, the timing of the RF waveform, etc.

[0096] Thus, in some embodiments, PS-TMN 112 may be used to provide a desired impedance transformation between source 102 and load 114. For example, PS-TMN 112 may provide impedance matching between source 102 and load 114. Alternatively, the impedance of PS-TMN 112 may be adjusted to compensate for the impedance (Z) of load 114. L ) changes so that source 102 is coupled to a more stable impedance (e.g., Z S,IN ).

[0097] refer to Figure 2 , a sinusoidal current source 202 having a current I drives an illustrative phase-switched variable reactance 200. The phase-switched variable reactance is shown here as comprising a parallel combination of a capacitor 204 and a switch 206 to provide a phase-switched variable reactance as the phase-switched variable capacitor 200. The capacitor 204 has a physical capacitance C0 and a voltage V C. The state of switch 206 is controlled by the characteristics of signal Q. For example, when signal Q has a logic high value, switch 206 provides a low impedance signal path between its terminals (e.g., switch 206 is "on" or "closed"), and when signal Q has a logic low value, switch 206 provides a high impedance signal path between its terminals (e.g., switch 206 is "off" or "open"). Therefore, switch 206 can be thought of as switching capacitor 204 into the circuit when the switch is open (current I flows into capacitor 204) and switching capacitor 204 out of the circuit when the switch is closed (current I flows through the closed switch and bypasses capacitor 204).

[0098] If switch 206 is always off (open), the effective capacitance C of phase-switched variable capacitor 200 presented to source 202 is EFF = is equal to the physical capacitance C0 of capacitor 204. Alternatively, if switch 206 is always on (closed), the low impedance path between the terminals of switch 206 effectively "shorts out" capacitor 204, and phase-switched variable capacitor 200 behaves as an infinite capacitor in the sense that the voltage across capacitor 204 remains zero regardless of current I. By controlling the conduction angle of switch 206 between 0 and 2π during the AC cycle of sinusoidal current source 202, the effective capacitance C0 of capacitor 204 can theoretically be reduced to EFF As used herein, the conduction angle is the angle of the sinusoidal signal when the switch 206 is turned on. The conduction angle of the switch can be determined entirely by the switch signal Q (e.g., the switch angle), or determined in part by the switch signal Q and by a voltage V C The circuit waveform part such as the current I is determined.

[0099] refer to Figure 3 , shows the current I and capacitor voltage V relative to the switch control signal Q C illustrative waveforms of (e.g., the voltage of capacitor 204) as a function of cycle angle θ. In particular, for a half-wave switched capacitor, curve 302 shows I(θ) and curve 306 shows V C (θ), and curve 304 shows Q(θ). Figure 3 As shown, in each cycle of I(θ), α radians after I(θ) transitions from negative to positive (e.g., switch 206 is turned off (opened) until α radians into the positive half-cycle of I(θ)). Switch 206 remains off (opened) until after the capacitor voltage rings down to zero. Biasing the switch to its on state (e.g., turning the switch on or closing the switch) after the capacitor voltage rings down to zero ensures zero voltage switching (ZVS) of switch 206.

[0100] If the switch includes a diode that naturally prevents the voltage from going negative, the timing of actively turning on switch Q can be relaxed because it will naturally commutate "ON" when the switch voltage reaches zero and the active turn-on signal can be issued while the diode is conducting. The capacitor C0 across the switch provides buffering of the turn-off transition, thereby providing zero voltage switching (ZVS) turn-off of switch 206.

[0101] like Figure 3 As shown, when I(θ) is a pure sinusoidal current source, switch 206 remains off (open) until the conduction angle of the switch is reached (e.g., 2α). Therefore, for a half-wave switched capacitor, switch 206 is turned on and off once per cycle of the RF signal from source 102 (e.g., I(θ) as shown by curve 302).

[0102] Adjusting α sets the position at which switch 206 turns on and off in a cycle (eg, controls the conduction angle of switch 206), and thus controls the voltage at which the capacitor reaches its peak. Thus, at the switching frequency, the switching angle (α) and V C There is a relationship between the magnitudes of the fundamental components of (θ). Therefore, the effective capacitance C of capacitor 204 is EFF can be expressed as a function of α:

[0103]

[0104] refer to Figure 4 It is also possible to implement the phase-switching variable reactance as a switched inductor network that allows its effective inductance to be continuously controlled at the switching frequency. Figure 4 is shown as a phase-switched variable inductor 400, and corresponds to Figure 2 The topological duality of the switched capacitor network 200 is shown. Figure 4 As shown, the illustrative phase-switched variable inductor 400 includes a series combination of an inductor 404 and a switch 406 driven by a sinusoidal voltage source 402 having a voltage V. The inductor 404 has a physical inductance L0 and an inductor current I L The state of the switch 406 is controlled by the signal Q. For example, when the signal Q has a logic high value, the switch 406 may be turned on (e.g., closed), and when the signal Q has a logic low value, the switch 406 may be turned off (e.g., open). Therefore, the switch 406 may be considered as: when the switch is closed, the inductor 404 is switched into the circuit (the voltage V is applied to the inductor 404), and when the switch is open, the inductor 404 is switched out of the circuit (no voltage is applied to the inductor 404).

[0105] Similar to About Figure 2The described embodiment of the phase-switched variable reactance switched capacitor can be used to change the effective inductance L of the phase-switched variable inductor 400 at the switching frequency. EFF Modulate from base value L0 to infinity. For example, if switch 406 is always on (closed), the effective inductance L of phase-switched variable inductor 400 seen by source 402 is EFF is equal to the physical inductance L0 of the inductor 404. Alternatively, if the switch 406 is always off (open), the inductor 404 behaves as an infinite inductor in the sense that the current through the inductor 404 remains zero regardless of the voltage V. By controlling the conduction angle of the switch 406 to be between 0 and 2π during the AC cycle of the sinusoidal voltage source 402, the effective inductance L0 of the inductor 404 is EFF Can be ideally controlled between L0 and infinity.

[0106] refer to Figure 5 , shows the current I and voltage V of capacitor 204 relative to the switch control signal Q C Illustrative waveform of as a function of the period angle θ. Due to the nature of topological duality, Figure 3 The voltage waveform of the switched capacitor network shown is similar to Figure 5 The current waveform of the switched inductor network is shown and vice versa.

[0107] In particular, for a half-wave switched inductor, curve 502 shows I L (θ), curve 506 shows V(θ), and curve 504 shows Q(θ). Figure 5 As shown, in each cycle of V(θ), switch 406 is turned on (closed) α radians after the transition of V(θ) from negative to positive (e.g., switch 406 is turned off / open until α radians into the positive half-cycle of V(θ)). Switch 406 remains on (closed) until after the inductor current rings down to zero. Since the switch has an inductor in series with it, zero current switching (ZCS) turn-on of the switch can be achieved. Turning off the switch when the inductor current rings down to zero ensures zero current switching (ZCS) turn-off of switch 406. Dual to the capacitive circuit, using a diode as part of the switch Q can achieve natural commutation (turn-off) of the switch and relax the detailed active timing (active timing) of the turn-off moment of the switch control waveform. As shown Figure 5 As shown, when V(θ) is a pure sinusoidal voltage source, the switch 406 remains on (closed) until the conduction angle of the switch is reached (eg, 2α).

[0108] Adjusting α sets the position at which switch 406 turns on and off in a cycle (eg, controls the conduction angle of switch 406), and thus controls the current at which the capacitor peaks. Thus, similar to the case with respect to Figure 2The described embodiment of the phase-switched variable reactance switched capacitor, at the switching frequency, the switching angle (α) and I L There is a relationship between the magnitude of the fundamental component of (θ). Therefore, the effective inductance L of inductor 404 is EFF can be expressed as a function of α:

[0109]

[0110] Due to topological duality, the expression (1b) for the effective inductance is identical to the expression (1a) for the effective capacitance. When the switch is always on (α = π), expression (1a) agrees with the intuitive expectation of infinite effective capacitance, and when the switch is permanently off (α = 0), expression (1a) predicts C EFF When the switch is always off (α = 0), expression (1b) is similarly consistent with the intuitive expectation of infinite effective inductance, and when the switch is permanently on (α = π), expression (1b) predicts L EFF Therefore, according to expressions (1a) and (1b), the effective capacitance C at the switching frequency can be modulated by controlling the conduction angle of the switch associated with the capacitor or inductor. EFF Or effective inductance L EFF .

[0111] refer to Figure 6 , the normalized effective capacitance C is shown by curve 602 at the switching frequency EFF / C0 or normalized effective inductance L EFF / L0. For capacitive circuits, this is related to the normalized admittance Y EFF / Y0 is the same as for an inductive circuit, which is the same as the normalized reactance X EFF / X0 is the same. Due to topological duality, Figure 2 The normalized effective admittance Y of the phase-switched capacitor circuit is EFF / Y0 and Figure 4 The normalized reactance X of the phase-switching inductor network is shown EFF / Same as X0.

[0112] like Figure 6 As shown, the normalized effective capacitance C EFF (or inductance L EFF ) increases rapidly with α and approaches infinity as α approaches π (e.g., 180 degrees).

[0113] refer to Figure 7 , curve 702 shows the relationship between the total harmonic distortion of the capacitor voltage (inductor current) and α for a pure sinusoidal current (voltage) excitation source. EFF or L EFFThe actual range that can be modulated depends on the amount of harmonic distortion that may be present in the network. As α increases toward π (ie, the conduction angle of the switch increases), the capacitor voltage V C (e.g., curve 306) or the inductor current I L The ringing of (e.g., curve 502) is limited to a shorter period of time. Figure 7 As shown, for larger Y EFF / Y0 or X EFF / X0 (for example, C EFF / C0 or L EFF / L0) ratio, which causes significant harmonic content in the capacitor voltage (e.g., total harmonic distortion increases as α increases). The amount of harmonic distortion allowed in a given system depends on the specified limits on harmonic content allowed into the source and / or load and the amount of filtering necessary or desired.

[0114] Notice, Figure 7 The harmonic distortion of the phase-switched variable reactance (e.g., the harmonic distortion of the capacitor voltage of the phase-switched variable capacitor 200 or the harmonic distortion of the inductor current of the phase-switched variable inductor 400) is shown, rather than the harmonic content actually injected into the source and / or load (e.g., source 102 and load 114) of the RF system. In some embodiments, the phase-switched variable reactance (e.g., the phase-switched variable capacitor 200 or the phase-switched variable inductor 400) includes additional filtering components ( Figure 2 and Figure 4 ), to reduce the harmonic content injected into the source and / or load (eg, source 102 and load 114).

[0115] As about Figure 3 and Figure 5 As described, the phase-switched variable reactance (eg, the phase-switched variable capacitor 200 or the phase-switched variable inductor 400) is half-wave switched, wherein the switch is operated so that the capacitor voltage ( Figure 3 curve 306) and the inductor current ( Figure 5 The curve 502) is unipolar. However, other switching schemes are also possible. For example, Figure 8 and Fig. 9 For Figure 3 The switched capacitor network shown and Figure 5 A switched inductor network is shown, showing illustrative waveforms of current I and voltage V relative to a switch control signal Q as a function of cycle angle θ.

[0116] In particular, if Figure 8 As shown, for a full-wave switched capacitor, curve 802 shows I(θ) and curve 806 shows V C (θ), and curve 804 shows Q(θ). Fig. 9 As shown, for a full-wave switched inductor, curve 902 shows I L (θ), curve 906 shows V(θ), and curve 904 shows Q(θ). When the phase-switched variable capacitor 200 is full-wave switched, the switch (e.g., switch 206) is turned off twice in each cycle of I(θ) (e.g., Q(θ) is zero), where the off cycle is centered at the time when the current I(θ) is zero. For a pure sinusoidal excitation current I(θ), this results in a bipolar capacitor voltage waveform V C (θ). Capacitor voltage V C (θ) has a zero DC average value. Similarly, when the phase-switched variable inductor 400 is full-wave switched, the switch (e.g., switch 406) is turned on twice (e.g., Q(θ) has a logic high value) during each cycle of V(θ), where the on-cycle is centered at the time when the voltage V(θ) is zero. For a pure sinusoidal excitation voltage V(θ), this results in a bipolar inductor current waveform I L (θ), which also has a zero DC average. Thus, for a full-wave switched capacitor (or inductor), switch 206 is switched on and off twice per cycle of the RF signal from source 102 (eg, I(θ) as shown by curve 802).

[0117] As with half-wave switching (e.g. Figure 3 and Figure 5 As shown in Figure 2), the effective capacitance C at the switching frequency can be modulated by controlling the switching angle α of the switch. EFF and effective inductance L EFF For full-wave switching capacitors, the effective capacitance C of capacitor 204 is EFF can be expressed as a function of α:

[0118]

[0119] Similarly, the effective inductance L of the inductor 404 is EFF can be expressed as a function of α:

[0120]

[0121] Therefore, for a given switching angle α, the effective capacitance / inductance that can be obtained using a full-wave switching network (e.g., relationships (2a) and (2b)) is half of the effective capacitance / inductance that can be obtained using a half-wave switching network (e.g., relationships (1a) and (1b)). However, the full-wave switching network inherently causes a reduction in the harmonic content of the capacitor voltage and the inductor current compared to a half-wave switching network for the same switching angle α (i.e., the switching angle that controls the total switch conduction angle). On the other hand, achieving full-wave switching requires that the switch must operate at twice the operating frequency (e.g., switching twice per cycle). In addition, for capacitive modulation, a bidirectional blocking switch is required, which may complicate the switch implementation with a typical semiconductor switch.

[0122] The above relations (1) and (2) show that for a pure sinusoidal excitation signal, Figure 2 and Figure 4 The effective capacitance and inductance of the switching network shown can be based on the switch angle α. For excitation signals that are not pure sinusoidal, although the exact value of α cannot be calculated by equations (1) and (2), the effective reactance can be controlled by appropriately selecting the timing of the switch turning off (or on) or the switch angle α. Together with the circuit waveform that determines the zero voltage (or zero current) point (for the switch turning on (or off)), the switch angle α determines the total conduction angle of the switch during the cycle. For excitation signals that are not pure sinusoidal, an adaptable lookup table (e.g., LUT 108), feedback circuit 110, or feedforward circuit 104 (including optional digital pre-distortion circuit 107) can be used to determine the required α value for a given desired effective reactance.

[0123] The phase-switched variable capacitor 200 and the phase-switched variable inductor 400 can be used as building blocks for implementing phase-switched variable reactance and other adjustable circuits, such as TMN. In particular, some applications can substantially benefit from a variable reactance whose value can be controlled over a range spanning both capacitive and inductive reactances, and / or by modulating the effective reactance over a more limited range. Enhancing the phase-switched variable capacitor 200 and / or the phase-switched variable inductor 400 with additional reactive elements can provide a wider range of variable reactance.

[0124] Figures 10A-10D An illustrative embodiment of a phase-switched reactance circuit including both capacitive and inductive elements is shown, thereby Figure 2 and Figure 4 The range over which the impedance of the phase-switching reactance circuit can be tuned is expanded compared to the single-element circuit shown.

[0125] For example, Fig. 10AA phase switching reactance circuit 1002 is shown, which includes an inductor 1012 connected in series with a phase switching capacitor 1013. The phase switching capacitor 1013 includes a switch 1016 connected in parallel with a capacitor 1014, similar to the Figure 2 as described. Fig. 10B A phase switching reactance circuit 1004 is shown, which includes an inductor 1024 in series with a capacitor 1022, wherein the series combination of the inductor 1024 and the capacitor 1022 is arranged in parallel with a phase switching capacitor 1025. The capacitor 1022 is not phase switched and is therefore shown as C DC Phase switching capacitor 1025 includes switch 1028 connected in parallel with capacitor 1026, similar to the Figure 2 as described. Fig. 10C Phase switching reactance circuit 1006 is shown, which includes capacitor 1032 connected in parallel with phase switching inductor 1033. Phase switching inductor 1033 includes switch 1036 connected in series with inductor 1034, similar to the Figure 4 as described. Fig. 10D A phase-switched reactance circuit 100 is shown that includes an inductor 1042 in parallel with a capacitor 1044, wherein the parallel combination of the inductor 1042 and the capacitor 1044 is arranged in series with a phase-switched capacitor 1045. The inductor 1042 is not phase-switched and is therefore shown as L DC The phase switching inductor 1045 includes a switch 1048 connected in series with an inductor 1046, similar to the Figure 4 as described.

[0126] As will be appreciated by those skilled in the art, in addition to Figures 10A-10D Circuit variations other than those shown are possible. For example, placing a capacitor in series with the phase switching capacitor provides a net effective impedance having a maximum capacitance equal to the series combination of the physical capacitance of the capacitor and the phase switching capacitor, and a minimum capacitance equal to the series combination of the capacitor and the phase switching capacitance value.

[0127] As about Figure 6 and Figure 7 As described, for phase-switched variable capacitor 200 and phase-switched variable inductor 400, there is a tradeoff between their variable reactance range and the amount of harmonic content injected into the rest of the system. In other words, the range within which the effective reactance can be controlled is limited by the amount of harmonic content that can be accommodated within the system (e.g., by source 102 and / or load 114). Some embodiments may employ additional or external filtering components to reduce the harmonic content injected into source 102 and / or load 114. However, in some embodiments, it may not be possible to employ additional filtering components.

[0128] refer to Fig.11 and Fig.12 , without employing additional filtering components, harmonic content can be reduced by combining the phase-switched variable capacitor 200 and the phase-switched variable inductor 400 with one or more non-phase-switched digitally controlled capacitor or inductor matrices. Such a hybrid switch network includes RF switches that operate at the RF frequency of operation and have a controlled phase and duty cycle relative to the RF waveform. The hybrid switch network also includes digital switches associated with one or more capacitors or inductors in the switch matrix. Digital switches typically operate at frequencies much lower than the RF frequency, but can operate at frequencies as high as the effective reactance C EFF or L EFF The controller operates at an RF frequency determined by a control bandwidth (e.g., on a cycle-by-cycle basis).

[0129] refer to Fig.11 , the hybrid switch network 1100 includes a phase-switched reactance (e.g., capacitor C0 1116 and parallel switch 1118) and a digitally controlled capacitor network 1102. Although illustrated as a phase-switched variable capacitor (e.g., capacitor C0 1116 and parallel switch 1118) coupled in parallel with the digitally controlled capacitor network 1102 and the load 114, in other embodiments, the phase-switched reactance may be implemented as a phase-switched variable inductance (e.g., as shown in FIG. 1 ) coupled in series with the digitally controlled capacitor network 1102 and the load 114. Figure 4 ), or implemented as Fig. 10A -D, or other equivalent circuits.

[0130] Digitally controlled capacitor network 1102 includes a plurality of capacitors and associated switches (shown as capacitors 1104, 1108, and 1112, and switches 1106, 1110, and 1114). In some embodiments, each of capacitors 1104, 1108, and 1112 has a unique capacitance value to allow the capacitance value of digitally controlled capacitor network 1102 to vary over a large capacitance range. For example, Fig.11 As shown, capacitors 1104, 1108, and 1112 may be increased from a phase switching capacitor base value (eg, C0) in increments of C0 until a maximum capacitance value (eg, (2·2 N -1)·C0, where N is the number of capacitors in the digitally controlled capacitor network 1102).

[0131] Switches 1106, 1110, and 1114 are coupled in series with corresponding ones of capacitors 1104, 1108, and 1112, and are operable to adjust the capacitance of the digitally controlled capacitor network 1102 by connecting (or disconnecting) the corresponding capacitors. Switches 1106, 1110, and 1114 may be operated based on one or more control signals from control circuit 106. As described, switches 1106, 1110, and 1114 are typically operated at a frequency less than the RF frequency to adjust the capacitance value of the digitally controlled capacitor network 1102.

[0132] refer to Fig.12 , the hybrid switch network 1200 includes a phase-switched reactance (e.g., inductor L0 1216 and series switch 1218) and a digitally controlled inductor network 1202. Although shown as a phase-switched variable inductance (e.g., inductor L0 1216 and series switch 1218) coupled in series with the digitally controlled inductor network 1202 and coupled in parallel with the load 114, in other embodiments, the phase-switched reactance can be implemented as a phase-switched variable capacitor (e.g., as Figure 2 ), or implemented as Fig. 10A -D, or other equivalent circuits.

[0133] Digitally controlled inductor network 1202 includes a plurality of inductors and associated switches, shown as inductors 1206, 1210, and 1214 and switches 1204, 1208, and 1212. In some embodiments, each of inductors 1206, 1210, and 1214 has a unique inductance value to allow the inductance value of digitally controlled inductor network 1202 to vary over a large inductance range. For example, Fig.12 As shown, inductors 1206, 1210, and 1214 and 1218 may be increased from a phase switching inductor base value (eg, L0) in increments of L0 until a maximum inductance value is reached.

[0134] Switches 1204, 1208, and 1212 are coupled in parallel with corresponding ones of inductors 1206, 1210, and 1214 and are operable to adjust the inductance of digitally controlled inductor network 1202 by connecting (or shorting, e.g., providing a low impedance path to bypass the inductor) the corresponding inductor. Switches 1204, 1208, and 1212 may be operated based on one or more control signals from control circuit 106. As described, switches 1204, 1208, and 1212 typically operate at a frequency less than the RF frequency to adjust the capacitance value of digitally controlled inductor network 1202.

[0135] The digitally controlled capacitor network 1102 and the digitally controlled inductor network 1202 extend the range over which the reactance of the phase switching reactance (e.g., capacitor C0 1116 and parallel switch 1118 or inductor L0 1216 and series switch 1218) can be continuously varied without introducing excessive harmonic content to the source 102 and / or the load 114. For example, Fig.11 and Fig.12 The illustrated embodiment uses a digitally controlled capacitor network 1102 (or a digitally controlled inductor network 1202) to control the base value C0 (or L0) of the switch network 1100 (or 1200). The switch of the phase-switched reactance (e.g., switch 1118 or switch 1218) can be operated to boost the base capacitance C0 (or inductance L0) by the coefficient determined by the relationships (1) and (2) described above.

[0136] For example, you can use Figure 3 The switching angle α shown as varying from 0 to about π / 2 performs half-wave switching of the RF switch to adjust the effective capacitance C of the hybrid switched capacitor network 1100 at the switching frequency to EFF Controlled between the lower capacitance value C0 and the higher capacitance value. Figure 7 As shown, RF switch operation with a switch angle α less than π / 2 (90 degrees) corresponds to a peak harmonic distortion of less than about 35%. Therefore, the hybrid switch network (e.g., 1100 and 1200) allows continuous control of the effective reactance at the switching frequency over a wide capacitive (or inductive) range, where harmonic distortion is minimized and no adjustable bias voltage or current is required.

[0137] In various embodiments, the RF switch (e.g., switch 206 or switch 406) of the TMN 112 may be implemented as one or a combination of various types of switch elements, for example, based on the RF frequency or other operating parameters of the RF system 100. For example, lateral or vertical FETs, HEMTs, thyristors, diodes, or other similar circuit elements may be employed.

[0138] Although other network topologies are possible (e.g., L-network, T-network, or other similar networks), the phase-switched variable capacitor 200 and the phase-switched variable inductor 400 can be used as circuit elements within a more complex phase-switched tunable matching network (PS-TMN) (e.g., a Pi-network topology PS-TMN (Pi-TMN)). Fig.131 shows a schematic diagram of an illustrative RF system 1300 including an RF source 1301 coupled to a Pi-TMN 1302, which is coupled to an RF load 1303. The Pi-TMN 1302 includes two variable shunt capacitive susceptances B1 1310 and B2 1314. In the illustrative embodiment, the RF source 1301 is typically a power amplifier, or the output of another RF system. Fig.13 As shown, the RF source 1301 can be represented by its Norton equivalent circuit as including the source resistance R S 1306 and source susceptance B S 1308 is connected in parallel with the current source 1304. Similarly, the RF load 1303 can be represented as including the load susceptance B L 1316 parallel load resistance R L 1318. Source impedance and load impedance Z S and Z L They can be expressed as:

[0139] Z S =(R S -1 +jB S ) -1 (3)

[0140] Z L =(R L -1 +jB L ) -1 (4)

[0141] Therefore, it can be shown that the load impedance Z L With source impedance Z S The susceptances B1 and B2 required for matching are given by:

[0142]

[0143]

[0144] Thus, the Pi-TMN 1302 can be used to adjust the load impedance Z by adjusting the values ​​of the variable shunt capacitive susceptances B1 1310 and B2 1314. L With source impedance Z S Match.

[0145] like Fig.13As shown, the embodiment of the Pi-TMN 1302 includes two variable shunt capacitive susceptances B1 1310 and B2 1314, and a fixed inductive reactance X 1312, although many other implementations of the Pi-TMN are possible, such as using variable shunt inductive susceptances and fixed capacitive reactances to implement all three reactance branches as variable components, etc. Of course, it should be understood that it is also possible to implement an L-shaped cross-section TMN with one variable shunt path element and one variable series path element. Other types of networks may also be used. As described in more detail below, ground-referenced variable capacitors are well suited for implementation with phase-switched variable reactance networks at RF frequencies.

[0146] refer to Fig.14 , an illustrative range of load impedances that can be matched by Pi-TMN 1302 is shown in Smith chart 1400 as shaded area 1402 (normalized to R S ). For example, the impedance value represented by the shaded area 1402 may be achieved by an illustrative Pi-TMN with X=R S , at 1 / R S To 4 / R S The variable susceptance B1 within the range of 1 / R S To 2 / R S The susceptance B2 is variable within the range of Fig.14 As shown, Pi-TMN 1302 is capable of matching the impedance of RF source 1301 to a load impedance that varies over a resistance range of approximately 10:1 and a reactance range of 5:1 (capacitively and inductively). To this end, Pi-TMN 1302 modulates B1 over a 1:4 range and modulates B2 over a 1:2 range, which can be achieved by employing a phase-switched variable reactance network (e.g., Figure 2 and Figure 4 shown) to achieve this.

[0147] Fig.15 Shown is a method for implementing Fig.14 The values ​​shown are for a 50Ω source impedance (e.g., R S 1506) is an illustrative embodiment of a phase-switched Pi-TMN circuit 1502 for matching the range of the inductive reactance X. The inductive reactance X is selected to have a value equal to the Norton equivalent source resistance R S (For example, 50Ω). Fig.15 As shown, variable capacitive susceptances B1 and B2 are implemented as half-wave phase switching capacitors (eg, Figure 2 The variable capacitive susceptance B1 includes a phase switching capacitor C P21514 and a FET switch 1512, the FET switch 1512 being controlled by a switch control signal q2 having a switch angle α2. The variable capacitive susceptance B2 comprises a phase switching capacitor C P1 1520 and a FET switch 1522, the FET switch 1522 is controlled by a switch control signal q1 having a switching angle α1.

[0148] In the illustrative embodiment, by appropriately adjusting the switching angles (α1 and α2) of the switches and the phase shift therebetween (e.g., by adjusting the switch control signals q1 and q2), the phase-switched Pi-TMN circuit 1502 operates at 27.12 MHz and is capable of matching a 50Ω source impedance to a load impedance that varies (capacitively and inductively) over a resistive range of approximately 10:1 and a reactance range of 5:1.

[0149] Implementing the variable capacitive susceptances B1 and B2 as a half-wave FET switched capacitor network provides zero voltage switching (ZVS) operation of the switches and allows each variable reactance to be implemented with a single ground-referenced switch (e.g., FET 1512 for variable capacitive susceptance B1 and FET 1522 for variable capacitive susceptance B2). ZVS operation is desirable in switching systems because it reduces switching power losses and improves overall system efficiency. In addition, the output (drain to source) capacitance of FETs 1512 and 1522 is proportional to the phase switching capacitor C. P1 and C P2 in parallel, and can therefore be added to the shunt capacitor and used as part of the TMN.

[0150] In the illustrative Pi-TMN circuit 1502, Fig.13 The inductive reactance X 1312 shown is implemented as a series resonant circuit comprising an inductor L arranged in series between variable susceptances B1 and B2. S2 1516 and capacitor C S2 1518, the variable susceptances B1 and B2 are arranged as shunt elements (eg, coupled to ground). Select the inductor L S2 1516 and capacitor C S2 1518 to have an inductive impedance approximately equal to the source impedance (e.g., 50Ω) at the desired frequency.

[0151] exist Fig.15 In the illustrated embodiment, two additional series resonant circuits are included, one as an input filter and one as an output filter of the Pi-TMN circuit 1502 to limit the amount of harmonic content injected into the source and load due to switching.S1 1508 and inductor L S1 1510 acts as a series resonant input filter between source 1504 and Pi-TMN circuit 1502. Similarly, inductor L S3 1524 and capacitor C S3 1526 acts as a series resonant output filter between load 1528 and Pi-TMN circuit 1502.

[0152] L S2 1516 and C S2 The quality factor Q of the series resonant circuit of 1518 controls the phase switching capacitor C P1 1520 and phase switching capacitor C P2 1514. For example, increasing the quality factor Q (e.g., by increasing L S2 1516 and C S2 1518) reduces the phase switching capacitor C P1 1520 and phase switching capacitor C P2 1514 interactions, but increasing the quality factor Q also reduces the effective bandwidth of the network.

[0153] For example, to implement the phase-switched Pi-TMN circuit 1502 at an illustrative desired frequency in the range of approximately 27 MHz Fig.14 The values ​​shown are for a 50Ω source impedance (e.g., R S 1506) matching range, phase switching capacitor C P1 1520 may have a physical value C0 of 130 pF, and the phase switching capacitor C P2 1514 may have a physical value C0 of 100 pF. In order to switch the capacitor C P1 1520 and phase switching capacitor C P2 The series resonant circuit between 1514 realizes the desired quality factor Q, capacitor C S2 1518 can have a value of 0.01μF, and the inductor L S2 1516 may have a value of 297nH. To achieve the desired input and output filtering through the series resonant circuit, capacitor C S1 1508 and C S3 1526 can have a value of 23.4pF, while the inductor L S1 1510 and L S3 1524 may have a value of 1.47 μ H. In addition, FETs 1512 and 1522 may have an on-state resistance of 10 mΩ, and the body diode of each FET may have a forward voltage of 0.4 V and an on-state resistance of 10 mΩ.

[0154] The switching of FETs 1512 and 1522 is synchronized with their drain currents based on a switching angle α which is based on the capacitance of capacitor C P1 and C P2 As described above for the half-wave phase switching capacitor, FET 1512 and FET 1522 are turned off after their drain currents cross from negative to positive, and then turned on again once their respective drain voltages ring down to zero. The desired load impedance Z can be determined by determining the desired load impedance Z given by relations (5) and (6) L The required B1 and B2 susceptances of FETs 1512 and 1522 are used to calculate the appropriate α value for each of FETs 1512 and 1522. Once each capacitive susceptance B1 and B2 is known, this value can be inserted as C according to relationship (1a) (for half-wave phase switching capacitors) or relationship (2a) (for full-wave phase switching capacitors). EFF (C0 is a known value as the physical capacitance of a capacitor) to determine the value of α that corresponds to the desired susceptance value.

[0155] As described, for phase switching networks with non-pure sinusoidal current excitation, relationships (1) and (2) may not yield an accurate value of α to achieve the desired susceptance. In addition, the nonlinearity of the drain-to-source switch capacitance and the interaction of the two switch networks (e.g., capacitive susceptances B1 and B2) may also cause inaccurate calculations of α. Therefore, some embodiments employ nonlinear control techniques (e.g., via control circuit 106) to determine an appropriate value of α, such as a fixed or adaptable lookup table (e.g., LUT 108), feedback (e.g., via feedback circuit 110), feedforward compensation (e.g., via feedforward circuit 104), digital predistortion of the switching angle (e.g., via predistortion circuit 107), or other similar techniques.

[0156] In order to set the correct value of the switch control parameter α for each of the FETs 1512 and 1522 of the Pi-TMN circuit 1502 to achieve a given impedance, the LUT 108 can store predetermined switch angles (e.g., α1 and α2) corresponding to various load impedances. For example, Table 2 shows an illustrative list of possible load impedances that the Pi-TMN circuit 1502 can match to a 50Ω source, and the corresponding values ​​of the switch angles α1 and α2 of the switch control signals q1 and q2:

[0157]

[0158] Table 2 shows that the Pi-TMN circuit 1502 can match a 50Ω source impedance to a load impedance that varies resistively over a range of at least a 10:1 factor. Based on the switching angles (α1 and α2) listed in Table 2 and Figure 6 The effective reactance shown (e.g., C EFF / C0 or L EFF The relationship diagram of the effective capacitance (L0) versus α shows that the 2:1 modulation of the effective capacitance can achieve impedance matching when the load impedance changes resistively in the range of 10:1.

[0159] Other types of systems may also employ the phase switching network described herein. For example, a wide range of systems may benefit from an RF power amplifier (PA) that delivers power at a specific frequency or over a specific frequency band. Such a PA can beneficially control output power over a wide range and maintain high efficiency over its operating range. Conventional linear amplifiers (e.g., Class A, Class B, Class AB, etc.) provide the benefits of wide-range dynamic output power control and high-fidelity amplification, but have limited peak efficiency that decreases rapidly with power backoff. On the other hand, a switching PA (e.g., an inverter such as Class D, Class E, Class F, Class Φ, etc.) provides high peak efficiency, but only generates a constant envelope signal (at a constant supply voltage) while remaining in switching mode.

[0160] One technique for output power control in a switching PA is through load modulation, where the load of the PA is modulated by an external network. In the described embodiment, the load of the PA is modulated by a phase-switched tunable matching network (TMN) (e.g., a network including one or more phase-switched variable capacitors 200 or phase-switched variable inductors 400, such as Pi-TMN circuit 1502). For example, the impedance transformation of the phase-switched TMN may control the output power of the PA.

[0161] refer to Fig.16 , such a phase-switched impedance modulation (PSIM) amplifier is shown as PSIM amplifier 1600. PSIM amplifier 1600 includes an RF power amplifier (or inverter) 1602 that generates RF power at a specific frequency or within a specific frequency range. RF PA 1602 is coupled to a power source (e.g., voltage V DC and ground) and phase switching TMN 1604. Phase switching TMN 1604 is coupled to a load impedance Z L The phase-switched TMN 1604 is coupled to a controller 1608, which controls the operation of the TMN, for example by providing control signals to the switches of the TMN based on a switching angle (eg, α), to achieve a desired impedance. Fig.16 Not shown, in some embodiments, the controller 1608 is coupled to the RF PA 1602 and also controls the operation of the PA. The phase switching TMN 1604 adaptively controls the load impedance Z LThe phase-switched TMN 1604 can be configured to transform the impedance presented to the PA 1602 by modulating the load (e.g., Z TMN ) and / or compensate for frequency and / or load impedance changes to control the output power of PA 1602 to provide high efficiency and desired power to the load.

[0162] In various embodiments, PA 1602 is (1) a switching inverter, (2) an amplitude modulated linear PA, or (3) a combination of these (e.g., depending on the desired output). Fig.17 A block diagram of an illustrative PSIM amplifier 1700 is shown, which includes a switching PA 1702 (e.g., a Class E, Class F, or Class Φ PA, etc.) that includes a single switch (e.g., FET 1706). In other embodiments, other types of PAs may be employed, such as linear PAs (e.g., Class A, Class B, Class AB, or Class C) or other switching PAs that use more than one switch to convert DC power to RF power (e.g., Class D, Inverse Class D, etc.).

[0163] As described, the effective load impedance Z seen by the PA looking toward the phase-switched TMN (eg, TMN 1604 or 1710) is modulated. TMN The output power is controlled within the operating power range of the PSIM amplifiers (eg, amplifiers 1602 and 1702). Additionally, the operating power range of the PSIM amplifiers may be further extended by also employing amplitude modulation on the PA drive signal to achieve large output power back-off.

[0164] Some embodiments may also employ other power modulation techniques, such as discrete or continuous drain modulation of a power amplifier. Drain modulation of a PA modulates (e.g., switches) a bias voltage applied to a bias terminal of the PA. For example, a drain modulation technique may switch the bias voltage between multiple discrete voltage levels, or continuously adjust the bias voltage within a voltage range.

[0165] In addition to performing impedance modulation and output power control of the RF PA, the phase-switched TMN (e.g., TMN 1604 or 1710) can also compensate for the load impedance Z L For example, for a given output power level, by employing a phase-switching TMN to compensate for changes in the amplifier load network impedance as the operating frequency changes and thus maintain ZVS operation, the phase-switching TMN can be continuously tuned to match the variable load impedance to the desired RF inverter load impedance Z TMNThus, a PSIM amplifier (eg, PSIM amplifiers 1600 and 1700) dynamically controls its output power delivered to widely varying load impedances (eg, RF plasma loads) across a large frequency range.

[0166] Thus, PSIM amplifiers (e.g., PSIM amplifiers 1600 and 1700) allow (1) efficient dynamic control of output power over a wide power range; (2) the ability to impedance match and deliver power to a wide range of loads; and (3) full zero voltage switching (ZVS) operation for frequency agile operation across a frequency range.

[0167] although Fig.16 and Fig.17 The block diagrams of the illustrated PSIM amplifiers 1600 and 1700 illustrate the PSIM amplifier as a cascaded combination of an RF PA (e.g., RF PAs 1602 and 1702) and a phase-switched TMN (e.g., phase-switched TMNs 1604 and 1710), but other embodiments integrate the PS-TMN into the design of the RF PA. Thus, such an integrated PSIM amplifier may be viewed as an RF amplifier comprising two or more switches, wherein a first switch (or switch group) is primarily responsible for generating RF power from a DC input power, and a second switch (or switch group) is primarily responsible for modulating the effective impedance presented to the RF amplifier by the load network. Although in some embodiments, the second switch may convert some power from DC to RF or from RF to DC, in most embodiments, the second switch (or switch group) will not convert DC power to RF power (e.g., the second switch provides zero power conversion from DC to RF).

[0168] In most embodiments, the PSIM amplifier may be a zero voltage switching (ZVS) amplifier, in which the switching transistors operate substantially in switch mode and are turned on and off at zero voltage switching, thereby enabling high efficiency to be achieved. In other implementations, the PSIM amplifier may provide switch mode operation (e.g., saturated operation) within a portion of its operating range (e.g., while delivering high output power) and utilize linear mode operation within other portions of its range.

[0169] For example, Fig.18A A schematic diagram of an illustrative topology for PSIM amplifier 1800A is shown. As shown, PSIM amplifier 1800A is coupled to an inductor L F A DC source 1802 coupled in series, an inductor L F is in turn coupled to transistor 1804 and capacitor C F The parallel combination of inductor L F 、Capacitor C Fand FET 1804 are normally operated to generate RF output power from the DC source to the rest of the network. Branch reactance X1 is coupled across capacitor C F and node N2, node N2 is coupled to the Pi-TMN, the Pi-TMN includes a first phase switching reactance (eg, FET 1806, branch reactance X S2 and phase switching variable reactance X P2 ) and the second phase switching reactance (eg, FET 1808, branch reactance X S3 and phase switching variable reactance X P3 ) between the reactance X2. The branch reactance X1 is coupled between Pi-TMN at node N1 and the load impedance Z L Depending on the required design function, branch reactance X1, X2, X3, X S2 , X S3 And the phase switching variable reactance X P2 and X P3 Can be implemented as a variety of different reactance networks.

[0170] Fig.18B Shows Fig.18A An illustrative design of the PSIM amplifier topology is shown in 1800B. Fig.18B As shown, using a half-wave phase switching capacitor network (for example, about Figure 2 and Figure 3 as described) to implement the phase switching variable reactance (including FET switches 1806 and 1808 and phase switching capacitor C P2 and C P3 ).like Fig.18B As shown, the three switches 1814, 1816 and 1818 are isolated from each other at DC (for example, respectively through capacitors C S1 , C S2 and C S3 ). FET switch 1814 is responsible for generating all RF power, while FET switches 1816 and 1818 are responsible for transforming and modulating the power supplied by load Z L The impedance presented to the DC to RF portion of the circuit (eg, at the output port of switch 1814 at node N2).

[0171] Fig.18C Shows Fig.18A An illustrative design 1800C of a PSIM amplifier topology is shown. Network 1800C is similar to network 1800B, but in network 1800C, the phase-switched capacitor network (e.g., FET 1826 and capacitor C P2 and FET 1828 and capacitor C P3 ) are respectively connected to capacitor C P4and C P5 This reduces the sensitivity of the PSIM amplifier to changes in the effective reactance of the switched capacitor network.

[0172] Fig.18D Shows Fig.18A An illustrative design 1800D of a PSIM amplifier topology is shown, in which FET switches 1834 and 1836 are DC coupled (eg, via inductor L S1 ), and thus, potentially, one or both of the FET switches 1834 and 1836 can be used to convert DC power to RF power, or vice versa. On the other hand, the FET switch 1838 is DC isolated (e.g., by a capacitor C S2 and C S3 ), and therefore only for load impedance Z L Impedance matching.

[0173] Fig.18E Shows Fig.18A An illustrative design 1800E of a PSIM amplifier topology is shown in which all three FET switches 1844, 1846, and 1848 are DC coupled (eg, via inductor L S2 ), while only the load is DC isolated (e.g., by capacitor C S3 ). Thus, in such an embodiment, all three FET switches 1844, 1846, and 1848 can potentially be used to convert between DC power and RF power and / or to provide impedance matching of the network to the load, although it is not necessary for all three switches to provide every function.

[0174] like Fig.18E As shown, capacitor C F and the switched capacitor network of FET switch 1844 and capacitor C P2 , inductor L2, and the phase switching network of FET switch 1846 are connected in parallel. Therefore, some embodiments may combine these two networks into a single switched reactance network that has an input current that matches the sum of the input currents of the two switched reactance networks associated with FETs 1844 and 1846. Therefore, in some embodiments, Fig.18E The three-switch PSIM shown can be implemented as a two-switch PSIM, for example Fig.19 and Fig. 20 shown.

[0175] refer to Fig.19 , shows a schematic diagram of an illustrative topology for a two-switch PSIM 1900. The two-switch PSIM 1900 is coupled to an inductor L F The RF source 1902 is coupled in series, the inductor LF is in turn coupled to FET 1904 and capacitor C F The branch reactance X1 is coupled to the capacitor C F and including reactance X S2 The phase switching reactance network, reactance X S2 With phase switching reactance X P2 The branch reactance X2 is coupled in series with the parallel combination of FET 1906. The branch reactance X2 is coupled between the phase switching reactance network and the load impedance Z L Depending on the desired function of the design, the branch reactances X1, X2 and X S2 And the phase switching variable reactance X P2 It can be implemented as a variety of different reactance networks. One of the switch FETs 1904 and 1906, or both of the switches 1904 and 1906, can be used to switch between DC power and RF power.

[0176] refer to Fig. 20 , an illustrative embodiment of a two-switch PSIM 2000 is shown with an inductor L implemented as S1 and capacitor C S1 The branch reactance X1. Capacitor C S1 DC isolation is provided between FET switches 2004 and 2006. Thus, FET switch 2004 generates RF power and FET switch 2006 modulates the impedance presented to the source.

[0177] Fig.21 An illustrative embodiment of a three-switch PSIM amplifier 2100 is shown. The PSIM amplifier 2100 operates in a frequency range of 20.86 MHz to 27.12 MHz (1.3 times the frequency). In addition, the PSIM amplifier 2100 provides the ability to dynamically control the output power delivered to the load, which has an impedance Z of 50 Ω. L , with an impedance variation (resistance and reactance) of ±10%.

[0178] The PSIM amplifier 2100 includes an RF PA (inverter) 2102, a Pi-TMN 2104, a branch filter 2106, and a load impedance Z L RF PA 2102 includes FET switch 2108, inductor L F and capacitor C F and C S1 And the inductor L S1 The output network is formed. Fig.21In the illustrated embodiment, the RF PA 2102 is a modified class E inverter that uses a FET switch 2108 to switch between DC power and RF power. The Pi-TMN 2104 includes a first phase switching capacitor (e.g., C P2 and FET 2110 and a second phase switching capacitor (eg, C P1 and FET 2112). The branch filter 2106 includes a coupling between Pi-TMN 2104 and the load Z L The inductor L between S3 and capacitor C S3 .

[0179] When Pi-TMN 2104 loads the inverter impedance Z at the operating frequency of RF PA 2102 TMN When the load is kept approximately resistive, the RF PA 2102 maintains zero voltage switching (ZVS) and high efficiency at different output power levels. TMN 50Ω (for example, matching load impedance Z L ), the RF PA 2102 generates peak RF power. Z can be modulated by Pi-TMN 2104 TMN To achieve dynamic control of the power back-off of RF PA 2102.

[0180] To operate in the frequency range of 20.86MHz to 27.12MHz, Fig.21 The illustrative embodiment of the PSIM amplifier 2100 shown employs an inductor L having a value of 113 nH. F , capacitor C with a value of 180pF F , capacitor C with a value of 15.2pF S1 , the inductor L has a value of 3.81μH S1 , a phase switching capacitor C having a physical value C0 of 152 pF P2 , an inductor L having a value of 381nH S2 , a capacitor C having a value of 0.01 μF S2 , a phase switching capacitor C having a physical value C0 of 152 pF P1 , the inductor L has a value of 3.81μH S3 , and a capacitor C having a value of 15.2 pF S3 In some embodiments, Pi-TMN 2104 employs a half-wave switched capacitor network (eg, capacitor C P2 and FET 2110 and capacitor C P1 and FET 2112).

[0181] By capacitor C S2and inductor L S2 The series reactance network branch formed has an inductive impedance of 50Ω at a frequency of 20.86MHz and also DC isolates the two switch networks (e.g., capacitor C P2 and FET 2110 and capacitor C P1 and FET 2112). Capacitor C S2 and inductor L S2 The impedance setting can modulate the Z of the Pi-TMN 2104 TMN The resistance range of capacitor C S3 and inductor L S3 The series resonant network formed provides the load current I L additional filtering and prevents DC current and high frequency harmonic content from being coupled to the load Z L The Pi-TMN 2104 can modulate the impedance Z presented to the RF PA 2102 by appropriately driving the FET switches 2110 and 2112, for example by adjusting the conduction angle of the FETs. TMN By modulating the impedance Z presented to the RF PA2102 TMN , Pi-TMN 2104 can control the power delivered from RF PA 2102 to load Z L output power.

[0182] Fig. 22 An illustrative impedance range (e.g., shaded area 2202) is shown within which the Z of the Pi-TMN 2104 can be adjusted at 20.86 MHz. TMN . Fig.23 It is shown that the Z of Pi-TMN 2104 can be adjusted at 27.12MHz TMN The Smith charts 2200 and 2300 are normalized to 50Ω. The shaded areas 2202 and 2302 show that the Pi-TMN 2104 can be switched by changing the phase of the capacitor C within a 1:6 impedance range. P1 (e.g., changing the switching angle α1 of FET 2112 within a range of approximately 0 to 125 degrees) and changing the phase switching capacitor C within a 1:10 impedance range P1 (e.g., by varying the switching angle α2 of FET 2110 within a range of approximately 0 degrees to 135 degrees) to match the load impedance Z within a range of 10:1 L In addition, Z TMN Modulation is performed to resolve the load impedance Z at the operating frequency of the RF PA 2102 L ±10% variation of (resistance and reactance).

[0183] In order to set the correct values ​​of the switching angle α1 of the FET 2112 and the switching angle α2 of the FET 2110 of the Pi-TMN 2104 to achieve a given impedance, the LUT 108 may store predetermined switching angles (e.g., α1 and α2) corresponding to various impedances. For example, Table 3 shows the switching angles that can be used with a 50Ω load impedance Z. L Possible impedance Z that matches the corresponding switching angle (e.g., α1 and α2) TMN The values ​​of Table 3 may be determined based on a simulation of PSIM amplifier 2100, where FETs 2110 and 2112 are modeled as having an on-state resistance of 10 mΩ and a body diode with a forward voltage drop of 0.4 V. The output powers listed in Table 3 include the power delivered at the fundamental frequency and at higher frequencies when the PSIM amplifier is provided with a 48 VDC supply.

[0184]

[0185] As described, the PSIM amplifier 2100 maintains zero voltage switching of all FET switches across a wide range of output powers, load impedances, and operating frequencies. For example, to provide an illustrative PSIM amplifier 2100 with a supply voltage of 48 VDC at 20.86 MHz to a 50Ω load Z L To deliver 58.6W of output power, the TMN 2102 is required to provide a near 1:1 impedance match (e.g., Z L =Z TMN =50Ω). Under this operating condition, the effective shunt capacitance required at nodes N1 and N2 is equal to C P1 and C P2 The capacitor, and therefore the FET switches 2110 and 2112 are turned off during the entire cycle, and the drain voltage waveform of the FET switches 2110 and 2112 will be sinusoidal.

[0186] As another example, to provide an illustrative PSIM amplifier 2100 with a power supply voltage of 48 VDC at 27.12 MHz to a 50Ω load Z L To deliver 3.50W output power, the TMN2102 is required to provide an impedance Z of approximately 50Ω TMN (As shown in Table 3). Under this operating condition, the effective shunt capacitance required at nodes N1 and N2 is higher than C P1 and C P2 Capacitors, and thus while maintaining ZVS, FET switches 2110 and 2112 are turned on at a certain portion of the cycle. Although the high-frequency harmonic content of the drain voltage waveform of FET switches 2110 and 2112 is high, the current flowing through load Z L The load current I Lshould remain close to sinusoidal.Thus, the PSIM amplifier 2100 is able to provide dynamic output power control while matching to variable loads across the switching frequency range.

[0187] Reference now Fig.25A , a pulse width modulation (PWM) generator 2500 includes a phase shift circuit 2504, which includes one or more phase shift elements 2504a-2504N, wherein each phase shift element has an input and an output. The PWM shift circuit 2504 receives one or more reference signals from a reference signal source 2502 and provides one or more phase shifted signals 2510 at its output. The PWM generator further includes a PWM waveform combiner 2506, which is configured to: receive signals provided thereto from the phase shift circuit 2504, combine such signals, and provide a PWM signal at its output. Therefore, the PWM generator 2500 receives one or more reference signals 2508 and generates one or more PWM signals 2508, which have the ability to dynamically control the pulse width and phase relative to the reference signal 2502. In particular, the PWM generator 2500 is configured to generate one or more PWM signals 2508 having a predetermined pulse width and phase shift relative to the reference signal 2502. The reference signal source 2502 and the PWM signal 2508 are shown here in dashed lines since they are not properly part of the PWM generator 2500 .

[0188] The reference signal provided by 2502 can be provided as any arbitrary periodic waveform, including but not limited to periodic voltage and current waveforms having various waveform shapes, including but not limited to sinusoidal waveforms (e.g., sine waves, cosine waves or portions thereof, etc.), rectangular waves, square waves, triangular waves, or any combination thereof. Although reference is sometimes made below to a reference signal as a voltage waveform for purposes of clarity, it will be understood by those of ordinary skill in the art that a current waveform may also be used in accordance with the concepts described. In addition, any other signal derived from the current and / or voltage signal may also be used as a reference.

[0189] In an embodiment, the input of at least one phase shift element in the phase shift circuit 2504 is configured to receive at least one reference signal 2502. In other embodiments, the inputs of two or more phase shift elements 2504 may be configured to receive at least one reference signal 2502. Fig.26 and Fig. 27 Examples of different phase shifting circuit architectures are discussed.

[0190] As will be apparent from the description below, each phase shift element of the phase shift circuit 2504 is configured to generate a phase shift signal 2510 at its respective output relative to the received reference signal 2502 based on a respective phase shift parameter. The phase shift parameters are provided from a controller 2509, which is shown here in dashed lines because it is not properly part of the PWM generator 2500. Each phase shift element may include analog and / or digital circuitry configured to apply a phase shift to a signal received at its input to generate a phase shift signal at its output. The phase shift element may include, for example, any of an in-phase / quadrature ("IQ") circuit, a phase-locked loop ("PLL") circuit, or any combination thereof.

[0191] In an embodiment, the phase shift parameters may include a predetermined phase shift and / or a predetermined pulse width for generating a signal having a specific phase shift (e.g., used in the generation of the phase shift signal 2510). According to some embodiments, each phase shift element 2504 is configured to receive a corresponding predetermined phase shift parameter from a controller 2509. For example, the controller 2509 may be provided as any type of processing circuit including, but not limited to, a digital signal processor ("DSP"), a computer, a microprocessor, a microcontroller, or any combination thereof.

[0192] As follows, at least Fig. 27 Described in detail, in some embodiments, the first phase-shift element 2504a can be configured to receive at least one reference signal 2502 at its input, and the second phase-shift element 2504b can be configured to receive at its input a generated phase-shifted signal (e.g., one of the signals 2510) from another (i.e., different) phase-shift element (e.g., the first phase-shift element 2504a).

[0193] In an embodiment, each phase shift element 2504a-2504N is configured to shift the phase of a signal received at its input based on a corresponding phase shift parameter to generate a corresponding one of phase shift signals 2510a-2510N, generally indicated as 2510. In an embodiment, some phase shift elements may be configured to shift the phase of a received reference 2502 to generate the phase shift signal 2510, while other phase shift elements may be configured to shift the phase of the generated phase shift signal 2510 received from another phase shift element 2504. For example, a phase shift element 2504 may receive a phase shift parameter including a phase shift φ. This phase shift element 2504 may then generate a phase shift signal 2510 at its output by shifting the phase of a signal received at its input (e.g., a reference signal 2502 or a generated phase shift signal) according to the phase shift φ.

[0194] The waveform combiner 2506 is configured to receive one or more generated phase shifted signals 2510A-2510N generated by the phase shift elements 2504A-2504N. The waveform combiner 2506 is configured to combine the phase shifted signals provided thereto (e.g., the phase shifted signal 2510) and generate a PWM signal 2508. The waveform combiner 2506 may include analog / digital circuits configured to generate, compare, sum, combine, detect, or amplify the PWM signal 2508. Such circuits may include, but are not limited to, edge detectors, analog or digital logic gates, operational amplifiers, comparators, or any combination thereof. In some embodiments, the waveform combiner 2506 is configured to generate one or more PWM signals 2508 based on the received phase shifted signals 2510, while in other embodiments, the waveform combiner 2506 may be configured to generate two or more PWM signals 2508 based on the received phase shifted signals 2510.

[0195] By generating a PWM signal 2508 based on the received phase shift signal 2510, the generated PWM signal 2508 has a phase shift and pulse width relative to the reference signal 2502. These phase shift and pulse width adjusted signals are determined based on the phase shift parameters applied by the phase shift element 2504 when generating the phase shift signal 2510. In some embodiments, the phase shift parameters are determined and stored in a memory or other storage device (for example, a memory of the controller 2509 that can be part of the controller 2509 or a separate form). It should be understood that in some embodiments, the phase shift parameters are determined based on the PWM signal duty cycle and phase shift required for a specific application of the PWM generator. These parameters can be pre-stored in the controller 2509 or in a separate external controller / memory. Generally, it is necessary to dynamically adjust the phase shift parameters depending on the specific application, and therefore, the external system controller can be assigned the task of estimating / calculating these parameters based on various inputs from the system and passing them to the PWM controller 2509.

[0196] Thus, one of ordinary skill in the art will appreciate that the desired phase shift and pulse width of the generated PWM signal 2508 relative to the reference signal 2502 can be achieved by selecting the phase shift parameters necessary to achieve the desired phase shift and pulse width.

[0197] In an embodiment, the controller 2509 may be configured to determine the phase shift parameters of the corresponding phase shift element 2504 based on the desired phase shift and pulse width of the generated PWM signal 2508. For example, the controller 2509 may be configured to determine the desired phase shift and pulse width of the generated PWM signal 2508 relative to the reference signal 2502. Based on the desired phase shift and pulse width, the controller 2509 may determine the phase shift parameters using empirical or analytical techniques. In more detail, for one or more phase shift elements 2504, the phase shift parameters may be determined based on feedback or feedforward techniques or a combination of both, so that the phase shift element generates a phase shift signal 2510, which in turn may be used to generate a PWM signal 2508 having a desired phase shift and pulse width relative to the reference signal 2502.

[0198] In addition, as will be described in detail below, the PWM signals 2508 are generated based on the received phase shift signal 2510, and the pulse width and phase of each generated PWM signal 2508 can be independently adjusted within a range of 0° to 360° with arbitrarily fine resolution that is not affected by the operating frequency (e.g., the frequency of the reference signal 2508). The generated PWM signals 2508 are capable of maintaining phase and frequency lock to the reference signal 2502 over a wide modulation range of the reference signal frequency. In an embodiment, the PWM generator 100 is suitable for generating accurate and dynamically adjustable PWM waveforms for high frequency and ultra-high frequency applications. The PWM generator 100 has particular value in applications where the reference signal 2508 is derived from a radio frequency ("RF") input source, and precise timing of the PWM signal must be maintained with respect to the reference signal 2508, such applications including PSIM-based tunable matching networks and PSIM amplifiers.

[0199] Reference now Fig.25B , by a PWM generator (e.g., combined with Fig.25A A portion of an illustrative PWM signal Q(θ) 2508 generated by a PWM generator 2500 as described above has a pair of pulses 2508a, 2508b. Each of the pulses 2508a, 2508b has a pulse width w 2512 and is locked in phase and frequency to a reference signal V REF (θ) 2502. The PWM signal Q(θ) 2508 can be combined as above Fig.25A is generated as discussed.

[0200] exist Fig.25B In the example embodiment of FIG. 5 , the generated PWM signal Q(θ) 2508 has a relative to the reference signal V REFThe phase shift φ (indicated by reference numeral 2514) of the PWM signal Q(θ) 2502 is defined as the phase shift φ 2514 between the rising edge of the PWM signal Q(θ) 2508 and the reference signal V REF It should be noted that this definition of PWM phase shift is used throughout this disclosure. Fig.25B The phase shift 2514 shown is considered a positive phase shift. It should also be noted that the definition of phase shift is only truly unique between two sinusoidal signals at the same frequency. When describing, for example, Fig.25B When describing the relationship between the PWM and sinusoidal signals in , the definition of phase shift is arbitrary. The definition of phase shift used in this article is chosen for convenience only. However, if desired, the phase shift can be defined in any other way as long as the definition uniquely describes Fig.25B If that is the case, then a phase shift based on one definition can always be converted to a phase shift based on the other definition without loss of generality. The phase shift definition has no effect on the circuit implementation. As discussed above, one of ordinary skill in the art will appreciate that a desired pulse width w 2512 and phase shift φ 2514 relative to reference signal 2502 can be achieved via selected values ​​of phase shift parameters provided to PWM generator 2504 that are required for phase shift element 2504 to achieve the desired phase shift.

[0201] Reference now Fig.26 , the PWM generator circuit 2600 includes a pair of phase shift elements 2016, 2018 that are coupled such that processing of the reference signal 2602 occurs in parallel. This architecture is referred to herein as a "parallel architecture."

[0202] The phase shift elements 2620, 2622 may be the same or similar to the phase shift elements 2504a-2504N described above in conjunction with FIG. 25. In a parallel architecture, the inputs of at least two phase shift elements are configured to receive a common reference signal (here, reference signal 2602), which may be the same or similar to reference signal 2502. Each phase shift element 2616, 2618 is configured to generate a corresponding phase shift signal at its output based on the received reference signal 2602 and a received predetermined phase shift parameter provided from a control signal 2620, 2632, which may be provided from one or more controllers (e.g., controller 2509 described above in conjunction with FIG. 25). The phase shift elements 2616, 2618 are each configured to generate a phase shift signal by applying a phase shift to the received reference signal 2602 according to a corresponding phase shift parameter included in a corresponding controller signal in the controller signals 2620, 2622.

[0203] According to an embodiment, each phase shift element 2616, 2618 may be configured to receive a corresponding one of the control signals 2620, 2622. The control signals 2620, 2622 may include one or more predetermined phase shift parameters for each of the corresponding phase shift elements 2616, 2618. In an embodiment, the control signals 2620, 2622 may be generated by a processing circuit (e.g., but not limited to, a DSP, a computer, a microprocessor, a microcontroller, or any combination thereof).

[0204] exist Fig.26 In the illustrative embodiment of , the phase shift element 2616 is configured to receive a control signal 2620 including a phase shift parameter including a phase shift φ. In addition, the phase shift element 2618 can be configured to receive a control signal 2622 including a phase shift parameter including a phase shift φ and a pulse width w. The phase shift elements generate phase shift signals A, B at their respective outputs.

[0205] The waveform combiner 2606 is configured to receive the phase shifted signals A, B generated at the outputs of the phase shift elements 2616, 2618. The waveform combiner 2606 can be coupled to the waveform combiner 2506 ( Fig.25A ) are the same or similar. In response to the phase shift signals A, B provided thereto, the waveform combiner 2606 generates a PWM signal 2608. The PWM signal 2608 has phase shift and pulse width characteristics according to the received phase shift signal A generated by the phase shift element 2616 and the phase shift signal B generated by the phase shift element 2618.

[0206] exist Fig.26 In the illustrative embodiment of , the phase shift signals A and B are phase locked to the reference signal 2602 and phase shifted according to the respective phase shift values ​​(φ and w+φ) of the phase shift elements that generate them. In an embodiment, the phase shift signals A and B can then be appropriately combined, for example, via a waveform combiner 2606, to synthesize a PWM signal 2608 having a pulse width w and a phase φ that is phase locked to the reference signal 2602. It should be understood by those of ordinary skill in the art that the amount of phase shift necessary for the phase shift elements 2616, 2618 to generate the desired PWM waveform 2608 is highly dependent on the actual implementation of the waveform combiner 2608.

[0207] It should also be understood that although Fig.26A parallel architecture with only two phase shift elements is shown, but it should be noted that a parallel architecture can be implemented using three or more phase shift elements. The number of phase shift elements to be included in the phase shifter circuit is selected based on the needs of the particular application. Factors to consider when selecting the number of phase shift elements to be included in the PWM generator include, but are not limited to, the number of rising / falling edges that the PWM waveform must have during a single cycle. In the simplest terms, each phase shift element controls the position of one rising or falling edge of the PWM waveform relative to the beginning of its cycle. For example, in Fig.26 In , the PWM waveform has a single pulse per cycle, and therefore, it has only one rising edge and one falling edge; phase shift element 2616 sets the position of the rising edge, and phase shift element 2618 sets the position of the falling edge. In more complex PWM waveforms (where more than one pulse per cycle may be required), more falling and rising edges are required, and more phase shift elements are required to control all edges. For example, in Fig.28 In , Q has two pulses that repeat every single cycle, and has a total of four edges in one cycle. Therefore, in order to control the relative position of each of these edges, four phase shift elements are required.

[0208] Another reason to have more phase-shifting elements than the minimum required is system redundancy and reliability. Fig.26 In , additional redundant phase shift elements (same as 2616) can be implemented to generate another copy of signal A. In the event that one of the phase shift elements fails, the waveform combiner can automatically select the other copy of signal A.

[0209] Reference now Fig. 27 , the PWM generator circuit 2700 or more simply the PWM generator comprises a pair of phase shift elements 2716, 2718, wherein a first of the phase shift elements (here, phase shift element 2716) has an input configured to receive a reference signal 2702, and has an output coupled to both an input of a waveform combiner 2706 and an input of a second phase shift element (here, phase shift element 2718). The output of the second phase shift element is coupled to a second input of the waveform combiner 2706. This architecture is referred to herein as a "cascade architecture".

[0210] In a cascaded architecture, it can be combined with the phase shift element 2504 ( Figure 1 ) is configured to receive the reference signal 2702 at its input. The first phase shift element 2716 is configured to generate a phase shift signal A at its output (e.g., by a combination of the above) based on the reference signal 2702 and the corresponding predetermined phase shift parameters. Fig.25AFor example, the phase shift element 2716 may be configured to generate the phase shift signal A by shifting the phase of the reference signal 2702 according to a predetermined phase shift parameter.

[0211] As referenced above Fig.26 As discussed, the phase shift element may be configured to receive a control signal including a predetermined phase shift parameter. Fig. 27 In the illustrative embodiment of , phase shift element 2716 is configured to receive a control signal 2720 including a phase shift parameter φ.

[0212] The cascade architecture further includes a second phase shift element 2718, which is configured to receive at its input the phase shift signal A generated by the phase shift element 2716. The second phase shift element 2718 is configured to generate at its output a phase shift signal B based on the phase shift signal A and the corresponding phase shift parameter. Fig. 27 In the illustrative embodiment of , the phase shift element 2718 is configured to generate the phase shift signal B by shifting the phase of the phase shift signal B according to a predetermined phase shift parameter (shown here as (φ+w)).

[0213] Waveform combiner 2706 (which can be combined with waveform combiner 2506 ( Fig.25A ) is configured to receive the phase-shifted signals generated at the outputs of the phase-shift elements 2716 , 2718 and generate a PWM signal 2708 having a desired pulse width and phase shift relative to the reference signal 2702 .

[0214] exist Fig. 27 In the illustrative embodiment of , the phase shift elements 2716, 2718 are configured to generate phase shifted signals A and B that are phase locked to the reference signal 2702 and phase shifted by phase shifts φ and φ+w, respectively, relative to the reference signal 2702. However, the phase shift elements 2716, 2718 in the cascaded architecture only introduce phase shifts of φ and w (i.e., the phase shift element 2716 introduces a phase shift φ, while the phase shift element 2718 introduces a phase shift w). On the other hand, in the parallel architecture, the phase shift elements phase shift the reference signal by φ and φ+w (e.g., in Fig.26 In FIG. 1 , phase shift element 2616 introduces a phase shift φ, while phase shift element 2618 introduces a phase shift φ+w).

[0215] Generally speaking, in order to generate the same PWM waveform, the phase shift element in the parallel architecture needs to be able to introduce a larger phase shift and operate within a wider phase shift range than the phase shift element in the cascade architecture.

[0216] On the other hand, a PWM waveform generated by a cascaded architecture may suffer from more jitter than a PWM waveform generated with a shunt architecture. The choice of one system architecture over another depends on a variety of factors, including but not limited to the specific application and the requirements for the generated PWM waveform, as well as the characteristics of the circuits available to implement them. While the range of phase shifts that each phase shift element can produce is an important determining factor in choosing a cascaded or shunt architecture, the dynamic behavior and transient response of the PWM generator is also highly dependent on the generator architecture.

[0217] The parallel architecture allows one to independently control the dynamics with which one can adjust the rising and falling edges of the PWM waveform. On the other hand, in the cascade architecture, the dynamics with which one can control the PWM waveform pulse is the combination of the dynamic responses of all phase shift elements.

[0218] In order to generate Fig.25B For a single pulse PWM waveform such as the waveform shown (i.e., one PWM pulse per period of the periodic reference signal 2502), an architecture with two phase shift elements is sufficient (see Fig.26 and Fig. 27 ). However, by employing more phase-shifting elements, one can generate more complex PWM signals, including waveforms with multiple pulses and multiple correlated PWM signals (e.g., as can be used to drive multiple switches in a multi-switch amplifier or converter).

[0219] Reference now Fig.28 , the PWM generator 2800 is configured to generate a dual-pulse PWM waveform 2808 and includes at least four phase-shift elements 2824-2830, each having an output coupled to an input of the waveform combiner 2806. The first set of phase-shift elements 2824, 2826 are each configured to receive a reference signal 2802 at their respective inputs. The phase-shift elements 2824, 2826 are each configured to generate a phase-shifted signal at their respective outputs based on the reference signal 2802 and a corresponding phase-shift parameter. For example, in Fig.28 In the illustrative embodiment of , the phase shift element 2824 is configured to generate a phase shift signal at its output by operating as follows: shifting the phase of the reference signal 2802 according to the corresponding phase shift parameter (φ) of the phase shift element 2824. Similarly, the phase shift element 2826 is configured to generate a phase shift signal at its output by operating as follows: shifting the phase of the reference signal 2802 according to the corresponding phase shift parameter (φ+α+γ) of the phase shift element 2826.

[0220] The second set of phase shift elements 2828, 2830 are each configured to receive at their inputs the phase shifted signals generated by the corresponding phase shift elements in the first set of phase shift elements 2824, 2826. Fig.28 In the illustrative embodiment of , phase shift element 2828 is configured to receive at its input the phase shifted signal generated by phase shift element 2824 , while phase shift element 2830 is configured to receive at its input the phase shifted signal generated by phase shift element 2826 .

[0221] The second set of phase shift elements 2828, 2830 are each configured to generate a phase shift signal at its respective output based on the phase shift signal generated by the first set of phase shift elements and the respective phase shift parameters. Fig.28 In the illustrative embodiment of , phase shift element 2828 is configured to generate a phase shifted signal by further shifting the phase of the phase shifted signal generated by phase shift element 2824 provided to the input of phase shift element 2828. Phase shift element 2828 shifts the phase of the signal provided thereto by a phase of (∝).

[0222] Similarly, the phase shift element 2830 is configured to generate a phase shift signal by shifting the phase of the phase shift signal generated by the phase shift element 2826 according to the corresponding phase shift parameter (β) of the phase shift element 2830 .

[0223] The waveform combiner 2806 receives at its input the phase-shifted signals generated at the outputs of the phase-shifting elements 2824-2830, combines the signals provided thereto, and generates a PWM signal 2808 based on the received phase-shifted signals. In an embodiment, the PWM signal 2808 is a dual-pulse PWM waveform (i.e., a pair of pulses occurring within a single cycle of the reference signal waveform) having a first pulse width and phase shift relative to the reference signal 2802 and a second pulse width and phase shift relative to the reference signal 2802.

[0224] By using two sets of phase shift elements to generate the PWM signal 2808, a double pulse PWM waveform can be generated. Fig.28 In the illustrative embodiment of , PWM waveform 2808 includes a dynamically and independently controlled phase φ with pulse widths α and β and an interval γ between pulses, while maintaining phase and frequency lock to reference signal 2802 .

[0225] One possible way to achieve this behavior is to design the waveform combiner in this example to switch its output Q whenever one of its four inputs undergoes a negative-to-positive transition. For example, assume that when REF undergoes a negative-to-positive transition at θ=0, Q is a logic low. The level of the output signal Q remains low until the output of the phase shift element 2824 undergoes a negative-to-positive transition at θ=0 (at which point the output signal Q switches to a logic high level). The output signal Q remains at a logic high level within (∝) degrees (the negative-to-positive transition of the output of the phase shift element 2828 resets Q at this point). Similarly, a negative-to-positive transition on the output of phase shift elements 2826 and 2830 causes another pulse of width β to follow the first pulse with a pulse interval γ. In this way, very complex multi-pulse PWM waveforms can be generated that remain phase- and frequency-locked to the reference signal input. Note that in Fig.28 In the example of , both parallel and cascade connection of phase shifting elements are adopted, that is, it is a hybrid architecture.

[0226] Reference now Fig.29 , the PWM generator 2900 includes a pair of phase shift elements 2916, 2918 coupled in a parallel architecture. The phase shift elements 2916, 2918 can be combined with the above FIG. Fig.26 The PWM generator 2900 also includes a phase detector 2932 that receives a portion of the reference signal at its input. The phase detector 2932 also receives a feedback signal from the output of the waveform combiner 2906 at its input. The output of the phase detector 2932 is coupled to the phase shift elements 2916, 2918.

[0227] In an embodiment, the phase detector 2932 is configured to receive a portion of the reference signal 2902 and a portion of the PWM output signal 2908, and is configured to monitor (i.e., measure, detect, calculate, or otherwise determine) the phase between the PWM signal 2908 and the reference signal 2902. The phase detector 2932 may include analog and / or digital circuits configured to detect and compare the phases of two or more signals, and may include a DSP, a microprocessor, a computer, a microcontroller.

[0228] The waveform combiner 2908 may be the same as or similar to the waveform combiner 2508 ( FIG. 25 ). In an embodiment, there may be significant propagation delays associated with the circuitry of the waveform combiner 2908 . Such propagation delays cause phase modulation of the output of the waveform combiner 2908 (i.e., the phase of the output signal of the waveform combiner may have a frequency variation that may disrupt the phase lock between the reference signal 2902 and the PWM waveform 2902 . In an embodiment, the phase detector 2932 may be configured to compare the phase between the PWM signal 2908 and the reference signal 2902 to a phase threshold. The phase threshold corresponds to a phase value indicating that the phase between the PWM signal 2908 and the reference signal 2902 has become too large. In other words, the phase threshold may include a value indicating that the PWM signal 2908 and the reference signal 2902 are no longer in phase lock.

[0229] In an embodiment, when it is determined that the PWM signal 2908 and the reference signal 2902 are no longer in phase lock, the phase detector 2932 can be configured to generate one or more phase correction signals. The phase correction signal can include data indicating an adjustment of one or more phase shift parameters of the corresponding phase shift element to place the PWM signal 2908 and the reference signal 2902 in phase lock. Thus, the phase correction signal includes data for correcting the propagation delay such that the PWM signal 2908 and the reference signal 2902 are no longer in phase lock.

[0230] In an embodiment, each phase shift element 2916, 2918 is configured to receive a phase correction signal and adjust its phase shift parameter in response to the phase correction signal. By adjusting the phase shift parameters of the phase shift elements 2916, 2918, the phase shift signals generated by the phase shift elements 2916, 2918 are also adjusted. Because the PWM signal 2902 is generated by the waveform combiner 2908 based on the received phase shift signal, adjusting the phase shift parameters allows the PWM signal 2902 generated by the waveform combiner 2906 to be corrected.

[0231] Reference now Fig.30 The PWM generation system 3000 includes a plurality of PWM generators 3036a-3036N, each of which can be combined with the above Fig.25A , 26 , 27, 28 and 29. Each PWM generator 3036a-N is configured to receive a reference signal 3002.

[0232] exist Fig.30In the illustrative embodiment of , each PWM generator 3036a-N includes at least two phase shift elements 3016a-N, 3018a-N that are configured to generate one or more phase shift signals based on a reference signal 3002 and phase shift parameters associated with each phase shift element 3016a-N, 3018a-N.

[0233] For example, the PWM generator 3036a includes phase shift elements 3016a, 3018a, which are configured to generate two or more phase shift signals based on the reference signal 3002 and phase shift parameters associated with the phase shift elements 3016a, 3018a. Each phase shift signal generated by the phase shift elements AN 3016a-N, 3018a-N is provided to a corresponding waveform combiner 3006a-N to generate a corresponding PWM signal 3008a-N.

[0234] In this manner, a plurality of PWM signals 3008 a -N may be generated that are frequency and phase locked to the reference signal 3002 , wherein each PWM signal 3008 a -N has a respective pulse width and phase shift relative to the reference signal 3002 .

[0235] In an embodiment, each phase shift element 3016a-N, 3018a-N is configured to receive a phase shift parameter from a controller 3034. The controller 3034 may include a processing circuit, such as, but not limited to, a DSP, a computer, a microprocessor, a microcontroller, or any combination thereof. In an embodiment, the controller 3034 is configured to receive an input including a desired pulse width and phase shift relative to the reference signal 3002 for one or more desired PWM signals 3008. It should be understood that the desired PWM pulse width / phase may also be an input provided by a user, or be predetermined and stored in a lookup table in memory.

[0236] Typically, however, the desired pulse width and phase will be determined by the controller with respect to some system feedback, whether it be impedance level or some other measured voltage / current / power signal within the system. In an embodiment, the controller 3034 may receive inputs including desired pulse widths and phase shifts relative to the reference signal 3002 from a computer, microcontroller, processor, graphical user interface, interactive device (i.e., keyboard, mouse, touch screen, etc.), or any combination thereof, to name a few. Based on these desired pulse widths and phase shifts relative to the reference signal 3002, the controller 3034 is configured to determine the phase shift parameters of each phase shift element necessary to achieve the desired pulse width and phase shift, and provide them to the corresponding phase shift elements.

[0237] Each PWM waveform 3008A-N generated by the PWM generation system 300 can be dynamically and independently adjusted by the controller 3034 by having the controller 3034 determine the phase shift parameters and provide them to the phase shift elements necessary to achieve the desired pulse width and phase shift. In many applications, there is a need to generate multiple PWM waveforms that are properly synchronized with respect to each other. This is particularly important in many types of converters that require accurate commutation between two or more switches. For example, driving the switches with a half-bridge would require generating two PWM waveforms with controllable duty cycles and individually controlled dead times for each transition. Both the phase φ and the pulse width w of each PWM waveform can be dynamically and independently adjusted by the controller.

[0238] It will be understood by those skilled in the art that although Fig.30 The illustrative embodiment shows that all N PWM generators 3036a-N are based on a parallel architecture ( Fig.26 ), but other architectures can be used, such as a cascade architecture or any combination of the two. Depending on the specific requirements of the application, PWM generators with different architectures and / or implementations can be connected together and fed with a common reference signal.

[0239] Those skilled in the art will note that the characteristics of a particular PWM generation architecture are highly dependent on the implementation details of the phase shift element and the waveform combiner. As discussed below, the PWM generation architecture with a phase shift element implementation is based on both an IQ modulator and a phase locked loop. Designs based on IQ modulators and phase locked loops often allow one to control the phase shift over a wide operating frequency range while preventing phase shift modulation with frequency variation. Those of ordinary skill will note that there are other possible methods for implementing a phase shift element (e.g., a programmable / voltage controlled delay line and a delay locked loop).

[0240] about Figure 31-35 , an embodiment of a PWM generator is provided based on a phase shifting element implemented using an IQ modulator. In an embodiment, the IQ modulator allows the RF carrier signal to be modulated according to different ranges of amplitude, frequency and phase modulation operations.

[0241] Reference now Fig.31 , the PWM generation circuit 3100 implemented as an IQ modulator includes an amplitude and phase shifting circuit 3152 having a first input configured to receive a local oscillator (LO) signal 3140. The PWM generation circuit further includes a pair of optional amplifiers 3144, 3146. In this illustrative embodiment, the first of the amplifiers is configured to receive an in-phase signal component I (also referred to herein as I BB, and identified by reference numeral 3138), and the second of the pair of amplifiers is configured to receive a quadrature phase signal component Q (also referred to herein as Q BB , and are identified by reference numeral 3140). Amplifiers 3144, 3146 receive respective ones of the IQ signals provided thereto and provide appropriately amplified signals to the inputs of respective ones of a pair of mixers (or multipliers) 3148, 3150. Mixers 3148, 3150 receive appropriately phase and amplitude adjusted LO signals from amplitude and phase shifting circuit 3152 on their second inputs. The outputs of mixers 3148, 3150 are coupled to the inputs of summing circuit 3154. Summing circuit 3154 appropriately sums the signals provided thereto to provide phase shifted signal 3110 (combined with the above Fig.25B Examples of which are shown and described).

[0242] Thus, the IQ modulator is configured to receive a local oscillator ("LO") 3140, which may be a signal that is the same as or similar to the reference signal 2502. The IQ modulator 3100 is configured to split the LO 3140 into two quadrature signal components I 3138 and Q 3132. Signal component I 3138 represents an in-phase component relative to the LO 3140, in other words, component I 3138 and LO 3140 have the same phase. Component Q 3132 represents a quadrature component of the LO 3140 that has a phase shift relative to the LO 3140. For example, component Q 3132 may have a phase shift of 90° or π / 2 radians relative to the LO 3140.

[0243] In an embodiment, one or more signals derived from LO 3140 may be generated by amplitude and phase shifting circuit 3152. Amplitude and phase shifting circuit 3152 may include analog and / or digital circuitry configured to shift the phase and / or amplitude of LO 3140 to generate one or more signals derived from LO 3140. In an embodiment, amplitude and phase shifting circuit 3152 is configured to generate a phase and / or amplitude shifted signal derived from LO 3140 to be applied to component I 3138 (I BB ) and the signal derived from LO 3140 will be applied to component Q 3132 (Q BB In an embodiment, the amplitude and phase shifting circuit 3152 is configured to generate a baseband signal so as to achieve the desired phase shift of the LO 3140.

[0244] In an embodiment, component I 3138 is provided to multiplier 3148. In some embodiments, component I 3138 may first be provided to amplifier 3144 before being provided to multiplier 3148. It should be understood that amplifiers 3144, 3146 may generally be used for any input signal conditioning, buffering, or amplification / attenuation. It should be understood that although circuits 3144, 3146 are schematically shown as amplifiers in this illustrative embodiment, the actual functionality of circuits 3144 / 3146 is highly dependent on the specific implementation of the IQ modulator. In addition, a signal derived from LO 3140 generated by amplitude and phase shift circuit 3152 is also provided to multiplier 3148. Multiplier 3148 is configured to multiply component I 3138 and a signal derived from LO 3140 and provide the product to adder 3154. Similarly, component Q 3142 is provided to multiplier 3150. In some embodiments, component Q 3142 may be provided to an amplifier 3146 before being provided to a multiplier 3150. Additionally, a second signal derived from LO 3140 generated by an amplitude and phase shifting circuit 3152 is provided to the multiplier 3150. The multiplier 3150 is configured to multiply component Q 3142 and the signal derived from LO 3140 and provide the product to an adder 3154. Each multiplier 3148, 3150 includes analog and / or digital circuitry configured to multiply two or more signals together.

[0245] The adder 3154 includes analog and / or digital circuits configured to sum two or more signals together. The adder 3154 is configured to generate a phase shift signal 3110 by summing the products provided by the multiplier 3148 and the multiplier 3150. In other words, the adder 3154 is configured to generate a phase shift signal 3110 based on the phase shift signal of the LO 3140 and the generated baseband signal I BB and Q BB to generate a phase shift signal.

[0246] In an embodiment, the output of the IQ modulator may be expressed as:

[0247] [EQ 1]

[0248] Here, RF(t) represents the phase shifted signal generated by the IQ modulator.

[0249] For simplicity, it can be assumed that LO 3140 is split into two orthogonal cos(ωt) and -sin(ωt) signals. Any absolute phase offset in LO 3140 will produce the same absolute phase offset in the phase shifted signal.

[0250] As shown in EQ 1, by making IBB 2 +Q BB 2 Keep constant and adjust Q BB with I BB The ratio of θ can control the phase shift θ between the local oscillator input and the RF output while maintaining a constant RF amplitude. In embodiments, using an IQ modulator (strictly as a phase modulator) in this way is particularly suitable for implementing the phase shift elements required for PWM generation.

[0251] Reference now Fig.32 , provides a phasor diagram (i.e., polar plot) of an example I / Q modulation. In the polar plot, Q is represented along the Y axis of the diagram. BB 3242, I along the X-axis of the graph BB 3238, wherein the phase shift signal 3210 generated by the I / Q modulator is represented as a phasor between the two. Fig.32 It can be seen that I BB 3238 actually controls the real part of the phase shift signal phasor, and Q BB Therefore, it will be understood by those skilled in the art that by appropriately controlling the two baseband signals I BB and Q BB , both the amplitude and the phase of the phase shifted signal 3210 can be modulated independently. In an embodiment, frequency modulation is also possible by appropriately modulating the phase of the output.

[0252] As from Fig.32 It can be seen that by keeping I BB 2 +Q BB 2 Constant and adjustable Q BB with I BB The phase shift θ can be controlled between the LO 3240 input and the phase shift signal output 3110 while maintaining a constant phase shift signal amplitude. Using an IQ modulator (strictly as a phase modulator) in this manner is particularly suitable for implementing the phase shift elements required for PWM generation.

[0253] It should be noted that although the phase of the PWM waveform may vary with frequency for a fixed set of baseband inputs I and Q, the pulse width 11' (in electrical degrees) remains constant and is not affected by the frequency modulation. This is primarily due to Fig.33 The architecture (referred to as the parallel architecture in this article) has a symmetrical structure and balanced path delays.

[0254] It should also be understood that if Fig.33If the bandpass filters of the two IQ modulators in have the same frequency-phase response, then a frequency change will produce the same phase shift for both IQ1 and IQ2. However, the pulse width of the PWM waveform is equal to the differential phase of the two logic gate inputs relative to the REF signal. Therefore, if the propagation delays from IQ1 and IQ2 to the output Q are also matched, the frequency modulation only causes a common-mode phase shift to the logic gate inputs and therefore does not affect the pulse width w. This is one reason to use comparators with matched propagation delays in a common package (i.e., the comparators are implemented in the same integrated circuit package and therefore they are exposed to similar manufacturing process variables and temperature, resulting in nearly matched propagation delays) for implementing the waveform combiner.

[0255] Those skilled in the art will appreciate that if modulating the PWM waveform phase φ with frequency for constant baseband inputs I and Q is undesirable for a particular application, a variety of approaches can be pursued to mitigate this problem. For example, I and Q can be tuned in response to frequency changes to correct for any phase error in φ. However, this approach requires accurate measurement of the frequency phase response of the IQ modulator and the propagation delay associated with the waveform combiner circuit. In addition, the controller that combines the I and Q signals must track the operating frequency - which may be undesirable and cumbersome for some applications.

[0256] To achieve accurate phase control of the phase shift element, a lookup table is implemented in a controller that is the same as or similar to controller 3034, which maps a set of baseband I and Q values ​​to a phase shift between the IQ output of the phase shift element and its reference signal.

[0257] In the exemplary embodiment, the I and Q values ​​are synthesized using 12-bit OAC and therefore they can only take one of 4096 discrete values. To create the lookup table, one of the baseband inputs is scanned through its entire digital range, while the other input is adjusted so that I 2 +Q 2 The amplitude of REF remains approximately constant, as shown in (I). The phase shift between REF and IQ is measured for each of the 4096 pairs of baseband inputs and stored in a lookup table. This control method corrects for any nonlinearity in the DAC transfer function, mismatch in the baseband channel gain of the IQ modulator, and the insertion phase of the output bandpass filter at a specific operating frequency.

[0258] Reference now Fig.33, the PWM generator 3300 includes one or more phase shifting elements implemented as a pair of IQ modulators, as shown. A reference signal to which the PWM waveform is synchronized is fed to both IQ modulators and serves as their local oscillator input. A pair of DACs controlled by a microcontroller can be used to synthesize appropriate values ​​for the I and Q signals of each IQ modulator, and thus control the phase shift of its outputs IQ1 and IQ2 relative to the REF signal.

[0259] exist Fig.33 In the illustrative embodiment of , the PWM generator 3300 includes a waveform combiner 3306, which is implemented with a pair of comparators and a single logic gate (shown here as a gate, and provided here as an AND gate). It should be understood that in Fig.33 In the example implementation shown, the logic AND gate has one inverting input. The gate is shown like this simply to simplify the circuit complexity. However, in practice, the circuit can be implemented using an AND gate with two non-inverting inputs and a NOT gate at one of its inputs.

[0260] Another way to achieve the same circuit functionality is to invert (i.e., flip) the + / - connections of comparator 3368 (negate its outputs) and feed the outputs of both comparators to an AND gate with two non-inverting inputs. In fact, the latter is the actual circuit implementation that we have used in our prototype construction. The output Q of waveform combiner 3306 is asserted (logic high) only during the time when signal IQ1 is positive and signal IQ2 is negative. Therefore, in order to generate a PWM waveform with pulse width w and phase φ, the IQ modulator outputs IQ1 and IQ2 must be phase shifted by φ and φ+w, respectively, relative to the REF signal.

[0261] It should be understood that the resolution with which w and φ can be controlled depends on the resolution with which the DAC can synthesize the I and Q inputs of the two IQ modulators. Fig.33 The implementation of the waveform combiner in limits the pulse width of the output PWM waveform to a maximum of 1800, which corresponds to IQ1 and IQ2 being 1800 out of phase. However, as described below, this limitation can be alleviated using a different implementation of the waveform combiner.

[0262] In one embodiment, a single phase shift element based IQ modulator implementation utilizes the LTC5598 (Analog Devices Inc.) chip, which provides an integrated implementation of an IQ modulator with differential baseband I and Q inputs and differential LO inputs. The differential voltage at the I and Q inputs is converted to current, which in turn drives a double-balanced mixer. The outputs of these mixers are summed and applied to a buffer that converts the differential mixer signal to a 50n single-ended buffered RF output. The LTC5598 allows operation over a local oscillator frequency range of 5MHz to 1600MHz while supporting a baseband bandwidth of over 400MHz, which enables very fast adjustment of the PWM waveform. The I and Q inputs are synthesized using a pair of 12-bit DACs (AD5624, Analog Devices Inc.); their single-ended outputs are buffered and converted to differential signals using a pair of fully differential operational amplifiers (LTC6362, Linear Technology). The DACs are controlled by a microcontroller via a standard SPI serial interface. A passive impedance matching network and a 1:1 balun (TC II TG2+, Mini-Circuits) convert the differential LO input of the IQ modulator to a single-ended 50n reference input REF.

[0263] Reference now Fig.34 , a plot of the phase shift command versus the measured phase shift error shows a good correspondence between the commanded phase shift and the phase shift achieved in response to such a commanded phase shift. In some embodiments, in order to control the phase shift produced by the IQ modulator based phase shift element, appropriate I and Q inputs must be provided to the IQ modulator. One method of determining these inputs is through the use of a lookup table. A predetermined lookup table stored in the memory of the controller lists the I and Q signal values ​​required to produce a certain commanded phase shift. This lookup table can be pre-calculated or measured empirically. As Fig.34 As shown, using this lookup table approach, one can control the phase of the phase shift element output (e.g., Fig.33 The phase shift signals IQ1 and IQ2 in the circuit can be controlled to within 0.5° over the entire 360° range of the commanded phase shift). If desired, the control accuracy can be further improved by synthesizing the I and Q inputs using a DAC with a higher number of bits.

[0264] Reference now Fig.35 , a graph of phase shift command versus measured phase shift standard deviation (STD) shows the standard deviation of the measured phase error achieved in the prototype circuit. Fig.35 The standard deviation of the measured phase error in can be viewed as an indirect measure of the jitter in the output of the phase shift element based on the prototype IQ modulator. Fig.35shows the full -180° to 180° range for a given commanded phase shift. Fig.34 The certainty of the phase error measurement in .

[0265] Fig.35 Act as verification Fig.34 An important metric for phase error measurements.

[0266] As mentioned above, Fig.35 The standard deviation of the measured phase error in can be viewed as a measure of the jitter in the phase shift element output, and it is primarily due to jitter in the reference signal and in the oscilloscope acquisition system that performs the phase measurement. Fig.35 For verification Fig.34 The measurement results of the phase error in . Fig.35 Basically it shows Fig.34 The measured phase error shown is accurate to within approximately ±0.1°. In other words, Fig.34 shows the measured phase error, and Fig.35 The certainty of the measurement results (the so-called standard deviation) is shown.

[0267] Described next is the use of a phase-locked loop (PLL) in implementing a phase-shifting element for PWM waveform generation. Also described is a design example of a cascaded PWM generation architecture with multiple phase-shifting elements including a PLL.

[0268] In general, a PLL-based approach to generating a variable duty cycle waveform allows both angular pulse width and phase φ (relative to a reference signal) to be dynamically controlled independently of frequency, i.e., frequency modulation affects neither w nor φ. Angular pulse width refers here to the pulse width of the PWM waveform, expressed in degrees out of a 360° period (one complete cycle).

[0269] For example, a PWM waveform with a 100nsec period and a 25nsec pulse width has a 90° angular pulse width (one quarter of a single period). By using this concept of angular pulse width, it is possible to describe the width of a pulse in relation to its period without specifying the frequency. This is somewhat similar to the concept of using a 0-100% duty cycle to describe a PWM waveform.

[0270] Reference now Fig.36, a circuit 3600 capable of generating a variable duty cycle waveform includes a phase shift circuit 3604, which includes a pair of phase shift elements 3604a, 3604b. The phase shift elements 3604a, 3604b each include a PLL 3616, 3618, wherein the first of the PLLs 3616 has an input 3616a configured to receive a reference signal 3602. The PLL 3616 provides a phase shift signal A at its output 3616b. The PLL output 3616b is coupled to a first input of a waveform combiner 3606 via a signal path. A portion of the PLL output signal A is also coupled to an input 3618a of a second PLL 3618 and to a feedback input 3616c of the PLL 3616 via a time delay circuit 3674. Thus, the first phase shift element 3604a and the second phase shift element 3604b are coupled such that the phase shifted output signal generated by the first phase shift element 3604a serves as a reference signal (i.e., input signal) for the second phase shift element 3604b. Thus, the phase shift elements 3604a, 3604b are said to be coupled in a so-called "cascade" architecture.

[0271] Time delay element 3674 introduces a time delay τ in the feedback path of PLL 3616. The time delay τ is selected to match the time delay τ received from input 3606a (i.e., Fig.36 signal A input) to output 3606C (i.e., Fig.36 The propagation delay of the signal Q output in (Q output). Such delays may include switch gate driver delays as well as any other delays. As will be described in detail below, time delay element 3674 introduces a time delay τ that is selected to significantly reduce (and ideally eliminate) the dependence of the phase shift φ on the frequency modulation.

[0272] In response to the signal provided to its input 3618a, PLL 3618 provides a phase shifted signal B at its output 3618b. The output 3618b of PLL 3618 is coupled to a second input of waveform combiner 3606 via a signal path. A portion of the PLL output signal B is also coupled to a feedback input 3618c of PLL 3618.

[0273] The waveform combiner 3606 combines the signals provided to it at inputs 3606a, 3606b and provides a PWM signal 3608 having a desired waveform at output 3606c. The waveform combiner 3606 combines the signals provided to it using any of the techniques described herein or any other technique suitable for generating the PWM signal 3608.

[0274] Each PLL module 3616, 3618 generates a respective output signal A, B at a respective output 3616b, 3618b, such that the signal fed back to the respective feedback input is frequency locked to the input signal provided to the respective input 3616a, 3618a and phase shifted relative thereto (i.e., phase shifted relative to the respective input signal) by a certain amount. The PLL modules 3616, 3618 thus allow direct control of the phase shift between the input signal and the feedback signal.

[0275] This phase shift can be digitally controlled (e.g., via a microcontroller (μC) 3662 or via some other control source) and can be adjusted from -180° to +180° with arbitrary resolution. The resolution can depend on, for example, the implementation of the PLL. Depending on the implementation of the PLL-based phase shift element, the phase shift it produces is typically controlled by an analog current or voltage signal. The resolution at which this analog signal can be synthesized ultimately determines the resolution at which the phase shift can be controlled. Typically, the analog control signal is synthesized using a digital-to-analog converter (DAC). The DAC itself can be part of the microcontroller, or can be part of the PLL phase shift element design.

[0276] In the former case, the microcontroller synthesizes the analog control signal directly and in this case it is indeed the resolution of the microcontroller that determines the resolution with which the phase shift can be controlled.

[0277] However, in the latter case, the microcontroller can digitally control the DAC as part of the PLL phase shift element. In this case, it is the PLL implementation that determines the resolution with which the phase shift can be controlled.

[0278] Fig.36 Thus is an example of a cascaded PWM waveform generator with phase shift elements implemented using a phase locked loop module coupled to a waveform combiner. In an embodiment, the waveform combiner may be implemented using one or more logic gates (e.g., a single AND gate). This approach allows for the generation of PWM waveforms with dynamically adjustable duty cycle and phase φ. It should be noted that with a waveform combiner provided from a single logic gate, the angular pulse width w of the PWM waveform may be limited to a maximum value of 180°.

[0279] consider Fig.36In the circuit 3600 of FIG. 3601 , if the time delay element τ in the feedback path of PLL 3616 is zero and PLL 3616 (PLL1) is commanded to provide a phase shift φ between its input and the feedback signal, this causes the output signal A (i.e., the output of PLL 3616) to be frequency locked to the reference input REF and phase shifted φ relative to the reference input REF (assuming τ=0). In this example, the phase shift φ between the reference signal REF and the output signal A means that the rising edge of the output signal pulse lags the negative to positive transition in the reference signal by a phase φ.

[0280] Similarly, assume that PLL 3618 (PLL2) is commanded to provide a phase shift of w between its input and the feedback signal. Since the output of PLL1 serves as the input to PLL2, signal B has a phase shift of w relative to signal A and therefore lags the reference signal REF by a phase shift of φ+w.

[0281] In one embodiment, signals A and B may be combined with a logic AND gate to produce an output signal Q having an angular pulse width w and a phase shift φ between its rising edge and the negative-to-positive transition of the REF signal. It should be noted that in this case, signal B is first inverted before being logically combined with signal A (i.e., via the AND logic gate). It should also be noted that due to the propagation delay of the waveform combiner circuit, any frequency modulation of the REF signal will cause a corresponding change in the phase shift φ of the PWM waveform. By tuning the time delay τ in the feedback path of PLL1 to match the propagation delay of the waveform combiner logic gate (e.g., AND gate), the dependence of the PWM waveform phase on frequency can be significantly reduced (and ideally eliminated).

[0282] To further clarify this point, suppose the command Fig.36 PLL1 in the circuit provides a phase shift φ between its input and the feedback signal. The time delay τ in the feedback path of PLL1 will cause the output signal A to lead the feedback input 3616c (at Fig.36 3616c (FB). If the time delay τ matches the propagation delay of the waveform combiner, the signal Q will be in phase with the signal at the feedback input 3616c (FB), and therefore, the output signal Q will lag the reference signal REF by a phase φ corresponding to the commanded phase shift. Thus, the phase of the PWM waveform will be set by the commanded phase shift of the PLL 3616 and will not be affected by frequency changes.

[0283] It should be noted that the amount of propagation delay that can be compensated by the feedback loop in this way while maintaining PLL stability depends on the phase margin and bandwidth of the PLL feedback loop. A PLL design with a high loop bandwidth can only accommodate a small amount of loop delay, and therefore requires the use of logic circuits in the waveform combiner that have sufficient operation speed to support such operation. On the other hand, in order to be able to fully compensate for the propagation delay of a waveform combiner with a large propagation delay (which may be the case when using transistor gate drivers as logic gates), a PLL design with a slow loop bandwidth is required, and therefore limits the speed at which the PWM waveform phase can be adjusted.

[0284] Although a waveform combiner comprising only a single logic gate (e.g., a single AND logic gate with an inverting input coupled to the PLL output 3618b) is relatively simple to implement, it only allows the generation of a PWM waveform with a maximum angular pulse width of 180 degrees (50% duty cycle), which corresponds to signals A and B being 180 degrees out of phase. Furthermore, this is only possible if both signals A and B have a 50% duty cycle. However, many applications require the ability to control the duty cycle of the PWM waveform over a wider range. Therefore, the following combined Fig.37 Alternative implementations of the waveform combiner are described that alleviate the above limitations.

[0285] In general, Fig.37 is a cascaded phase-locked PWM generator 3700 having a waveform combiner provided from an edge detector coupled to a D-type flip-flop. This approach allows for dynamic adjustment of the PWM phase φ and angular pulse width w over a 360° range. As discussed above, the time delay element τ included in the feedback path of the first PLL receiving the reference signal is selected to substantially match the propagation delay from input A to output Q through the waveform combiner circuit and thus eliminate the dependency of φ on frequency modulation.

[0286] Reference now Fig.37 , an illustrative circuit for PWM waveform generation includes a pair of phase shift elements 3704, 3704 coupled to a waveform combiner 3706. Phase shift elements 3704, 3704 can be combined with the above Fig.36The waveform combiner 3706 includes a pair of edge detectors 3778, 3780, each of which receives an input from a corresponding phase shift element in the phase shift elements 3704, 3704. The edge detectors 3778, 3780 are implemented here with logic gates (shown here as AND logic gates having an inverter coupled to one of their inputs). Of course, it will be understood by those of ordinary skill in the art that any type of circuit can be used to implement the edge detector. It will be further understood by those of ordinary skill in the art that any type of circuit capable of detecting a signal edge (e.g., a rising edge and / or a falling edge of a signal) can also be used.

[0287] The output of a first one of the edge detectors (here, edge detector 3778) is coupled to the clock input CLK of a D-type flip-flop 3782. The output of a second one of the edge detectors (here, edge detector 3780) is coupled to the reset input RESET of the D flip-flop 3782. The D input of the flip-flop 3782 is coupled to a reference signal (here, a logic signal having a value of logic 1).

[0288] This D-type flip-flop arrangement alleviates Fig.36 Since the D input of the flip-flop is coupled to a signal having a logic high signal level, a rising edge on the CLK input sets the output signal Q to a high level (i.e., a logic high signal level), and a rising edge on the RES input clears Q (i.e., sets the output signal Q to a logic low signal level). When a rising edge occurs on signal A or B, the edge detectors 3778, 3780 at the combiner input generate pulses to drive the flip-flop.

[0289] Of course, it should also be understood that, depending on the implementation of the flip-flop, it may not be necessary to use an edge detector.

[0290] For a flip-flop with an asynchronous reset input, the output signal Q will be forced to a logic low signal level as long as RES is logic high regardless of the CLK input. In such a case, it is important to use an edge detector to prevent the flip-flop from "skipping" the rising edge of signal A when signal B is logic high. When an edge detector is used, the maximum PWM pulse width that can be obtained is approximately equal to the time period of the REF signal minus the pulse width of the edge detector output. It should therefore be understood that the waveform combiner 3706 allows the angular pulse width and phase of the PWM waveform to be controlled over a range of almost 360°.

[0291] In some applications, it may be desirable or necessary to generate multiple related "single pulse" PWM waveforms. Generally speaking, a PWM waveform may include multiple pulses in a single cycle, with various pulse widths and intervals between pulses. In such a "multi-pulse" PWM waveform, the pulse pattern repeats at the PWM waveform frequency every cycle. For example, in Fig.28 In the example, each 360° period of the generated PWM waveform has two pulses with widths of α and β.

[0292] A PWM waveform that includes only a single pulse per 360° period (one complete cycle) is referred to herein as a "single-pulse PWM waveform". For example, circuits and systems capable of generating multiple such single-pulse PWM waveforms may be used to drive complementary switches in a half-bridge with controllable duty cycles and individually controllable dead times between switches. In other applications, it may be desirable or necessary to provide a controllable overlap in time rather than providing a controllable dead time or more than two related single-pulse waveforms. Fig.38 An exemplary design of a PWM generation system is shown, which can generate multiple (here two) PWM waveforms that are phase- and frequency-locked to a common reference signal REF.

[0293] Reference now Fig.38 , the PWM generation system 3800 includes a reference signal source 3802 that generates a reference signal. The reference signal is provided to the input of each of a plurality of PLL-based PWM generators 3836a-3836N. The PLL-based PWM generators 3836a-3836N can be combined with the above Fig.37 The PWM generator 3700 described is the same or similar.

[0294] PWM generator 3836a is taken as a representative of PWM generators 3836a-3836N, and the PWM generator includes a pair of PLLs 3816a, 3816b coupled in a cascade configuration. As described above, in the cascade configuration, the first of the PLLs 3816a receives a reference signal from a reference signal source 3802 at its input, and the output of the PLL 3816a is coupled to the input of a second, different PLL 3818, so that the phase-shifted output signal from the PLL 3816a serves as a reference signal (i.e., input signal) of the PLL 3818a. As described above, the output of the PLL 3816a is coupled to the feedback input of the PLL 3816a through a time delay circuit 3874a. The phase-shifted signal generated by the PLLs 3816a, 3818a is provided to the input of the waveform combiner to generate a PWM output signal Q at the output 3808a of the PWM generator 3836a.

[0295] The PWM generation system 3800 further includes a controller 3834. The controller 3834 provides a phase shift parameter value to a phase shift element in each of the PWM generators 3836a-3836N. In particular, the controller 3834 provides the phase shift parameter values ​​3812a-3812N to a corresponding PLL in the PLLs 3816a-3816N, 3838a-3838N.

[0296] Thus, where the system 3800 includes two of the PLL-based PWM generators 3836 fed with the same reference signal, the system is able to independently control the phase shifts φ1, φ2 and pulse widths w1, w2 of the two PWM waveforms Q1 and Q2, respectively.

[0297] For example, Fig.38 The circuit can be used to generate drive signals for two complementary switches in a half-bridge circuit with controllable duty cycle and dead time. In an embodiment with two PWM generators 3836 and a reference signal frequency that can vary in the range of 5 MHz to 20 MHz, PWM waveforms Q1 and Q2 with approximately 25% duty cycle and 25% symmetrical dead time can be provided, that is, the dead time of each transition is approximately 25% of the PWM period. The rising edges of Q1 and Q2 can be 180° apart and aligned with the maximum and minimum values ​​of the reference signal, respectively. In such an embodiment, the PWM duty cycle, dead time, and phase shift are not affected as the frequency varies throughout the range of 5 MHz to 20 MHz.

[0298] Reference now Fig.39 , the illustrative PWM generation system 3900 includes first and second phase shift elements 3904a, 3904b, which are coupled so that the phase shifted output signal generated by the first PLL 3916 serves as the reference signal (input) of the second PLL 3918. Therefore, the PLLs 3916, 3918 are combined with the above Fig.36 The so-called cascade architecture described is coupled.

[0299] However, combined with the above Fig.36 In contrast to the cascade arrangement described in Fig.39 In the illustrative embodiment of , the feedback signal provided to the FB input 3916c of the PLL 3916 is taken directly from the output of the waveform combiner 3906 (i.e., a portion of the output signal Q is provided to the feedback input 3916c of the PLL 3916).

[0300] The system controller 3934 provides phase shift parameters to the phase shift elements 3904a, 3904b, and in particular to the PLLs 3916, 3918. The phase shift parameters include at least one or more phase shift values. Fig.39In the example of FIG. 3 , system controller 3934 provides a phase shift value φ to phase shift element 3904a and provides a phase shift value of w to phase shift element 3904b.

[0301] Providing a predetermined phase shift value φ to phase shift element 3904a forces PLL 3916 to adjust its output signal (i.e., Fig.39 ) until the phase shift between the reference signal REF and the feedback signal provided to the FB input of the PLL 3916 is a phase φ. As described above, since the phase shift elements 3916, 3918 are coupled in a so-called cascade configuration, this causes the phase shift element 3904b to produce a phase shifted signal B having a phase shift of φ+w. The phase shifted signals produced by the phase shift elements 3904a, 3904b are combined in the waveform combiner 3906 to generate a PWM signal 3908 (i.e., output signal Q) having a phase shift φ and a pulse width w. Therefore, the phase of the PWM waveform relative to the reference signal REF can be directly controlled when the frequency is changed without the need to compensate for the propagation time delay in the waveform combiner circuit.

[0302] Reference now Fig.40 , a flowchart of a process of generating a PWM signal having a desired pulse width and phase shift relative to a reference signal begins at processing block 4002, wherein a PWM generator receives a reference signal. Such a PWM generator may be the same as or similar to any of the PWM generators described herein and is configured to receive at least one reference signal. The reference signal may be the same as any of the reference signals described herein (including but not limited to the above in combination with Fig.25B In an embodiment, the PWM generator may include at least one phase shift element, which may be the same as or similar to the phase shift element 2504. The phase shift element of the PWM generator may have a parallel architecture, a cascade architecture, or both, as described above with reference to FIG. Fig.26 and Fig. 27 discussed.

[0303] Processing then proceeds to processing block 4004, where at least one phase shift element of the PWM generator generates a phase shift signal at its output. This phase shift signal may be combined with Fig.25BThe phase shift signal 2508 described above may be the same or similar. The phase shift of the phase shift signal may be based on the reference signal provided in the processing block 4002 and based on the corresponding predetermined phase shift parameters. The phase shift parameters may include a predetermined phase shift and / or a predetermined pulse width used in the generation of the phase shift signal. For example, the predetermined phase shift parameters may include a desired phase shift for a corresponding phase shift element to be applied to the reference signal in order to generate the phase shift signal. In an embodiment, some phase shift elements may be configured to generate a phase shift signal by phase shifting the reference signal according to the predetermined phase shift parameters, while other phase shift elements may be configured to generate a phase shift signal by phase shifting a phase shift signal generated by another phase shift element.

[0304] In an embodiment, the predetermined phase shift parameters may be generated by a controller, which may be the same or similar to any of the controllers described herein. The controller may be configured to generate the predetermined phase shift parameters based on a desired pulse width and phase of a reference signal relative to a PWM signal generated by a PWM generator. In an embodiment, the controller is configured to provide the generated predetermined phase shift parameters to the corresponding phase shift elements.

[0305] Processing then proceeds to processing block 4006, where the phase shifted signals generated in processing block 4004 are combined to generate one or more PWM signals. The phase shifted signals generated in processing block 4004 may be combined using various techniques including any of the techniques described herein. For example, the phase shifted signals may be combined by providing the phase shifted signals to a waveform combiner, which may be the same or similar to any of the waveform combiners described herein. For example, the waveform combiner may be operable to compare, sum, detect, divide (or any combination thereof) the received shifted signals to generate the PWM signals. In an embodiment, based on predetermined phase shift parameters of the phase shift elements, the generated PWM signals have a desired pulse width and phase shift relative to a reference signal.

[0306] Reference now Fig.41A , an illustrative power generation and delivery system 4100 having first and second ports 4127 , 4129 includes a phase switching and tunable impedance matching network 4188 (PSIM TMN) having an input coupled to port 4127 and having an output coupled to port 4129 .

[0307] A unit for monitoring impedance at port 4127 is coupled between port 4127 and PSIM TMN input 4188a, and a unit for monitoring impedance 4196 is coupled between PSIM TMN output 4188b and port 4129. The unit for monitoring impedance 4194, 4196 may measure, detect, calculate, or otherwise determine the impedance at one or both of ports 4127, 4129. Using such a unit allows the impedance to be determined dynamically.

[0308] The PSIM TMN 4188 includes one or more phase-switched impedance (PSIM) elements having N PSIM elements 4190a-N shown here. In an embodiment, the PSIM elements 4190a-N may be coupled to the phase-switched elements described herein (e.g., as described above with reference to Figure 1 Each PSIM element 4190a-N is coupled to a PWM generation circuit 4136, which includes at least one PWM generator. In an embodiment, the PWM generator in the PWM generation circuit 4136 can be the same or similar to the PWM generator described herein.

[0309] PSIM elements 4190a-N are configured to respond to PWM signals provided by PWM generation circuit 4136. In particular, in response to the PWM signals generated by PWM generation circuit 4136, PSIM TMN 4088 adjusts the impedance presented to (i.e., looking at) one or both of first and second ports 4127, 4129.

[0310] In an embodiment, a portion of the signals provided to and from the PSIM TMN 4188 are coupled to the PWM generator 4136. It should be understood that Fig.41A The input / output signals of the TMN in the PSIM can be used as reference signals for the PWM generator to synchronize the switching of the PSIM elements appropriately with the current / voltage in the TMN network. Fig.41A As indicated, an external SYNC signal can also be used as a reference for the PWM generator.

[0311] The PWM generators 4136 are each configured to receive at least one reference signal and at least one control signal. The control signal may be provided, for example, by a controller 4184, which may be the same or similar to any of the controllers described herein. Fig.41A In the illustrative embodiment of , M reference signals designated as SYNC 1-M (where M≤N) are shown, where N refers to the number of PSIM elements.

[0312] Of course, it should be understood that, in general, the PWM generator may acquire any number M of SYNC signals, and there is no real need to constrain M ≤ N (i.e., in some embodiments, M>N may be desirable or even necessary). For example, the PWM generator may acquire more SYNC signals than PSIM elements, and dynamically switch which SYNC signal is used for which PSIM element based on internal control or some command from the system controller.

[0313] In response to the signal provided thereto, the PWM generator, circuit 4136 generates at least one PWM signal having a pulse width and a phase shift relative to a reference signal. The reference signal may include a signal that is the same or similar to the reference signal described herein (e.g., the reference signal 2502 described above in conjunction with FIG. 25 ). The PWM signal generated by the PWM signal generator 4136 is provided to at least one PSIM element 4190a-N. Each PWM generator 4136 may include one or more phase shift elements configured to generate a phase shift signal (based at least in part on a phase shift parameter provided from the controller 4184), and one or more waveform combiners configured to generate at least one PWM signal based on the generated phase shift signal.

[0314] In an embodiment, the PSIM TMN 4188 is configured to adjust the impedance presented at Port 1 and / or Port 2 based on the pulse width and phase shift of the reference signal relative to the PWM signal generated by the PWM signal generator 4136. In other words, the impedance presented at Port 1 and / or Port 2 is determined based on the pulse width and phase shift (relative to the reference signal) of the PWM signal generated by the PWM signal generator circuit 4136.

[0315] The desired impedance value presented at port 1 and / or port 2 can be achieved by appropriately selecting the pulse width and phase shift values ​​of the PWM signal provided to the PSIM TMN. After reading the description provided herein, a person of ordinary skill in the art will further understand that the desired value of the impedance presented at port 1 and / or port 2 can be achieved by selecting appropriate phase shift parameters of the phase shift element of the PWM generator included in the PWM generation circuit 4136.

[0316] In embodiments, the predetermined phase shift parameters may be provided to the phase shift elements of the PWM generator by the system controller 4184. The system controller 4184 may include a DSP, a processor, a microprocessor, a computer, a microcontroller, or any combination thereof, to name a few. In some embodiments, the system controller 4184 is configured to generate the predetermined phase shift parameters based on desired values ​​of pulse width and phase shift of a reference signal relative to the PWM signal generated by the PWM generator 4136. In other embodiments, the system controller 4184 is configured to generate the predetermined phase shift parameters based on desired values ​​of impedance presented at port 1 and / or port 2.

[0317] In some embodiments, the means for monitoring impedance 4149, 4196 may be provided as one or more current and / or voltage (IV) probes, wherein at least one IV probe is coupled to port 1 and at least one IV probe is coupled to port 2. Each IV probe is configured to monitor (e.g., measure, detect, calculate, or otherwise determine) load impedance and / or impedance loading of ports 1 and 2 and provide a signal representative of the monitored load impedance and / or impedance loading to the system controller 4184.

[0318] In an embodiment, the system controller 4184 is configured to adjust the generated predetermined phase shift parameters provided to the phase shift elements 4190a-4190N to adjust the impedance value at Port 1 and / or Port 2 to a desired value. Thus, the system controller 4184 can control the PWM generator and the PSIM TMN 4188 based on the monitored load impedance and / or the impedance load monitored (e.g., measured, detected, or otherwise determined) at Port 1 and / or Port 2.

[0319] Reference now Fig.41B , the illustrative RF power generation and delivery system 4100 includes a system controller having a first output coupled to the RF input of an inverter 4186, and a second output coupled to the input of a PWM generation circuit 4136. The PWM generation circuit 4136 includes one or more PWM generators, each of which may be the same or similar to any of the PWM generators described herein. The output of the RF inverter 4186 is coupled to the input of a PSIM TMN 4188. The output of the PSIM TMN 4188 is coupled to a load 4192.

[0320] PSIM TMN 4188 includes a plurality of PSIM elements 4190a-N. Each PSIM element 4190a-N is coupled to at least one PWM generator of PWM generation circuit 4136. The PWM generator in PWM generation circuit 4136 is configured to generate a PWM signal having a pulse width and a phase shift relative to a reference signal. Fig.41B The PWM generator in the can get reference signals from the control system, the input / output of the TMN, any internal current / voltage signal from the TMN, or get similar Fig.41A any other externally provided SYNC signal (as indicated by the dashed line).

[0321] The specific width and phase shift provided by the PWM generator is based on the phase shift parameters provided by the system controller 4184. Some of the phase shift parameters provided by the control system are responsible for controlling the phase of the generated PWM waveform relative to the reference signal, while other phase shift parameters control the pulse width of the PWM waveform.

[0322] Generally speaking, the phase shift parameters that control the PWM pulse width must be adjusted dynamically and are usually determined by some kind of feedback (e.g., measurement of the TMN input / load impedance, reflected power at the TMN port, etc.) These can also be controlled / overridden directly by the user.

[0323] The phase shift parameters that control the phase of the PWM waveform generally do not need to be dynamically adjusted and may be pre-stored in a lookup table that may be obtained through system calibration. However, in general, these phase shift parameters may also be determined based on feedback (e.g., voltage and current waveforms in the TMN, power losses in the PSIM device, etc.) and may be dynamically adjusted by the control system (or overridden by the user) to meet the needs of the system. In response to signals provided to and / or from the PWM generation circuitry, the PSIM TMN 4188 adjusts the impedance presented at its input and output.

[0324] Thus, with the RF inverter coupled to the input of 4188 and the load coupled to the output of PSIM TMN 4188, the impedance presented to the RF inverter 4186 and / or the load 4092 can be adjusted in response to the PWM signal generated by the PWM generator 4136. In an embodiment, the system controller 4184 can generate values ​​of predetermined phase shift parameters provided to the PWM generation circuit 4136 so that the desired value of the impedance presented to the RF inverter 4186 and / or the load 4092 can be achieved. It will be understood by those of ordinary skill in the art that the desired value of the impedance presented to the RF inverter 4186 and / or the load 4092 will depend on the operation, use, design, etc. of the RF power generation and delivery system.

[0325] Reference now Fig.42 , the illustrative RF power generation and delivery system 4200 includes an RF inverter or amplifier 4286 having an output coupled to an input of a PSIM TMN 4288. The PSIM TMN 4288 includes at least one PSIM element. The RF inverter 4286 is shown here as a voltage source 4203 and a resistor R S 4205. IV probe 4294 is coupled between the RF inverter and the PSIM TMN. With load impedance Z L A load 4298 is coupled to the output of the PSIM TMN 4288. An IV probe is coupled between the PSIN TMN 4288 and the load 4298.

[0326] The system further includes a PWM waveform generator 4236 (including phase shift element A 4216, phase shift element B 4218, and waveform combiner 4206), IV probes 4294, 4296, and a system controller 4284. Thus, in this illustrative embodiment, the PSIM TMN 4288 is coupled at its input to the RF inverter or amplifier 4286 and at its output to the load 4298, and is configured to adjust the impedance presented to the RF inverter or amplifier 4286 and the impedance presented to the load 4298.

[0327] In an embodiment, the PSIM element includes a capacitor C S1 4207、C S2 4217 and C P1 , inductor L S1 4209 and L S2 4215, and transistor q1. Transistor q1 is configured to receive a drive signal 4208 from a PWM generator 4236 and, in response thereto, adjust the impedance presented at the input and / or output terminals of the PSIM TMN 4288 (i.e., adjust the impedance presented to the RF inverter or amplifier 4286 and / or the load 4298). The drive signal may be provided as a PWM signal generated by the PWM generator 4236 using any of the techniques described herein.

[0328] The input of the PSIM TMN 4288 is coupled to the input of the PWM generator 4236 (here through a level adjust circuit 4233, which may include, for example, an attenuator) such that a signal (e.g., a voltage signal) at the input of the PSIM TMN 4288 is provided to the PWM 4236 as a reference signal 4202. In an embodiment, the signal at the input of the PSIM TMN 4288 may first be provided to the attenuator 4284 and then provided as the reference signal 4202 to ensure compatibility with the internal circuitry of the PWM generator 4236. In this illustrative embodiment, a PWM generator 4236 having a parallel architecture is provided. Thus, the reference signal 4202 is provided to both phase shift elements A, B 4216, 4218, wherein each phase shift element is configured to generate a phase shift signal 4210A, 4210B based on a corresponding predetermined phase shift parameter. In an embodiment, the predetermined phase shift parameter may be provided to the phase shift elements 4216, 4218 by the system control 4284. Of course, it should be understood that in other embodiments, it may be desirable or necessary to provide the PWM generator 4236 with a cascade architecture.

[0329] The IV probes 4294, 4296 are configured to monitor (e.g., detect, measure, calculate, or otherwise determine) the impedance presented to the load 4298 and the RF inverter 4286, and provide the monitored impedance to the system control 4284. In an embodiment, the system control 4284 is configured to generate predetermined phase shift parameters based on the monitored impedance to achieve a desired value of the monitored impedance presented to the load 4298 and the RF inverter 4286.

[0330] Reference now Fig.43 , the illustrative RF power generation and delivery system 4300 includes a PSIM TMN 4388 having input and output terminals and two PSIM elements; an RF inverter or amplifier 4386 (including a voltage source 4303 and a resistor R S 4305); PWM waveform generators A, B 4236A, 4326B (each including first phase shift elements 4316A, B and second phase shift elements 4318A, B and waveform combiners 4306A, B); IV probes 4394, 4396 and system controller 4384. In an embodiment, PSIM TMN 4388 is coupled at its input to RF inverter or amplifier 4386 and at its output to load 4398 and is configured to adjust the impedance presented to RF inverter or amplifier 4386 and the impedance presented to load 4298.

[0331] The first PSIM element includes a transistor q1 4321 configured to receive a drive signal and in response thereto adjust the impedance presented at the output terminal of the PSIM TMN 4288 (i.e., adjust the impedance presented to the load 4398). In an embodiment, the drive signal of q1 4321 may be provided as a PWM signal generated by a PWM generator 4336A. The second PSIM element includes a transistor q2 4311 configured to receive a drive signal and in response thereto adjust the impedance presented at the input terminal of the PSIM TMN 4388 (i.e., adjust the impedance presented to the RF inverter or amplifier 4386). In an embodiment, the drive signal of q2 4311 may be provided as a PWM signal generated by a PWM generator 4336B.

[0332] Each PWM generator 4336 is configured to generate a PWM signal based on predetermined phase shift parameters provided to its phase shift elements 4316, 4318. In an embodiment, these phase shift parameters may be generated by a system control 4384, wherein the system control 4384 is configured to generate the predetermined phase shift parameters based on expected values ​​of impedance presented at the input and output of the PSIM TMN 4388.

[0333] Each PWM signal generated by the PWM generators 4336A, B has a pulse width and a phase shift relative to a corresponding reference signal provided to the PWM generator. In an embodiment, the reference signal provided to PWM generator A 4336A may include one or more signals (e.g., voltage signals) at the output of PSIM TMN 4388, and the reference signal provided to PWM generator B 4336B may include one or more signals (e.g., voltage signals) at the input of PSIM TMN 4388. Thus, PWM generator A 4336A generates a PWM signal having a pulse width and a phase shift relative to the signal at the output of PSIM TMN 4388, while PWM generator B 4336B generates a PWM signal having a pulse width and a phase shift relative to the signal at the input of PSIM TMN 4388.

[0334] In an embodiment, IV probes 4396, 4398 on the input and output ports of the PSIM TMN 4338 monitor the impedance presented at the input and output of the PSIM TMN 4338, and the system control 4384 can control the operation (e.g., operating frequency, output power) of each PWM generator 4336 and RF inverter or amplifier 4386 based on the impedance.

[0335] References to "one embodiment" or "embodiment" herein mean that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the claimed subject matter. The phrase "in one embodiment" appearing in various places in the specification does not necessarily all refer to the same embodiment, and separate or alternative embodiments are not necessarily mutually exclusive with other embodiments. The same applies to the term "implementation".

[0336] As used in this application, the words "exemplary" and "illustrative" are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" or "illustrative" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Instead, the use of the words "exemplary" and "illustrative" is intended to present concepts in a concrete way.

[0337] Additionally, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless specified otherwise or clear from the context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the foregoing instances. Additionally, the articles "a" and "an" used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from the context to be directed to the singular form.

[0338] To the extent that directional terms (e.g., up, down, parallel, perpendicular, etc.) are used in the specification and claims, these terms are intended only to assist in describing the embodiments and are not intended to limit the claims in any way. Such terms do not require precision (e.g., exact perpendicular or exact parallel, etc.), but are intended to apply normal tolerances and ranges. Similarly, unless expressly stated otherwise, each value and range should be interpreted as approximate, as if the words "about," "substantially," or "approximately" preceded the value or range value.

[0339] Some embodiments may be implemented in the form of methods and devices for practicing those methods. In addition, as will be apparent to those skilled in the art, the various functions of the circuit elements may also be implemented as processing blocks in a software program. The described embodiments may also be implemented in the form of program code embodied in a tangible medium (e.g., a magnetic recording medium, a hard disk drive, a floppy disk, a tape medium, an optical recording medium, a compact disk (CD), a digital versatile disk (DVD), a solid-state memory, a hybrid magnetic and solid-state memory, or any other machine-readable storage medium), wherein, when the program code is loaded into and executed by a machine (e.g., a computer), the machine becomes a device for practicing the claimed invention. The described embodiments may also be implemented in the form of program code, for example, whether stored in a storage medium, loaded into and / or executed by a machine, or transmitted through some transmission medium or carrier (e.g., by wire or cable), by optical fiber, or via electromagnetic radiation, wherein, when the program code is loaded into and executed by a machine such as a computer, the machine becomes a device for practicing the claimed invention. When implemented on a processing device, the program code segments are combined with a processor to provide a unique device similar to a specific logic circuit. Such processing devices may include, for example, general purpose microprocessors, digital signal processors (DSPs), reduced instruction set computers (RISCs), complex instruction set computers (CISCs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), microcontrollers, embedded controllers, multi-core processors, and / or other, including combinations of the above. The described embodiments may also be implemented in the following forms: bit streams or other sequences of signal values ​​transmitted electrically or optically through a medium, magnetic field changes stored in a magnetic recording medium, etc., generated using the methods and / or apparatus as recited in the claims.

[0340] Also for the purposes of this description, the terms "coupled," "linked," "coupled," "connected," "connected," or "linked" refer to any means known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the insertion of one or more additional elements is contemplated, but not required. Conversely, the terms "directly coupled," "directly connected," and the like connote the absence of such additional elements. A signal and a corresponding node or port may be referred to by the same name and are interchangeable for purposes herein.

[0341] It should be understood that the steps of the method described herein are not necessarily required to be performed in the order described, and the order of the steps of such method should be understood to be merely illustrative. Likewise, in methods consistent with various embodiments, additional steps may be included in such methods, and certain steps may be omitted or combined.

[0342] It will be further understood that those skilled in the art may make various changes in the details, materials and arrangements of components which have been described and illustrated herein without departing from the scope of the appended claims.

Claims

1. A pulse width modulation (PWM) generator, comprising: a phase shift circuit having at least one input and a plurality of outputs, the phase shift circuit being configured to receive a reference signal and in response thereto provide a phase shifted signal at each of the two or more outputs, each phase shifted signal having a predetermined phase shift relative to the reference signal; as well as a waveform combiner having a plurality of inputs, wherein each input is coupled to a respective one of the plurality of outputs of the phase shift circuit, the waveform combiner being configured to receive at its input a phase shifted signal from the phase shift circuit and in response thereto generate a pulse width modulated signal having a predetermined pulse width and phase shift relative to the reference signal, wherein the predetermined phase shift is defined between a rising edge of the pulse width modulated signal and a negative to positive transition of the reference signal.

2. The pulse width modulation generator according to claim 1, wherein: The phase shift circuit includes a plurality of phase shift elements coupled in a parallel architecture.

3. The pulse width modulation generator according to claim 1, wherein: The phase shift circuit includes a plurality of phase shift elements coupled in a cascade architecture.

4. The pulse width modulation generator according to claim 1, wherein: The phase shift circuit includes at least one in-phase / quadrature-phase (IQ) modulator having at least three inputs and at least one output, wherein at least one of the inputs is configured to receive the reference signal and at least two of the inputs are configured to receive a baseband signal derived from the reference signal, the IQ modulator including an adder coupled between the output and at least two inputs.

5. The pulse width modulation generator according to claim 1, wherein: The waveform combiner includes at least one of: an edge detector; a logic gate; a flip-flop; or an amplifier.

6. The pulse width modulation generator according to claim 5, wherein: The waveform combiner comprises: a plurality of amplifiers having inputs and outputs, each input of the amplifier being configured to receive a phase-shifted signal; and A logic gate having a plurality of inputs and at least one output, each input of the waveform combiner being configured to be coupled to an output of at least one amplifier.

7. The pulse width modulation generator according to claim 1, wherein: The phase shift circuit is configured to generate two or more phase shifted signals based on at least one predetermined phase shift parameter.

8. The pulse width modulation generator according to claim 7, wherein: The phase shift circuit is further configured to receive the at least one predetermined phase shift parameter from a controller.

9. The pulse width modulation generator according to claim 8, wherein: The controller is configured to generate the at least one predetermined phase shift parameter based on the pulse width and the phase shift of the reference signal relative to the generated pulse width modulated signal.

10. The pulse width modulation generator according to claim 1, wherein: The pulse width modulation generator is implemented in an integrated circuit.

11. An apparatus for generating a dynamically controlled pulse width modulation (PWM) signal, comprising: two or more phase shift elements, each phase shift element having an input and an output, wherein the input of each phase shift element is configured to receive a reference signal, wherein each phase shift element is configured to generate a respective phase shifted signal at its output based on the reference signal and a phase shift parameter provided thereto, each phase shifted signal having a predetermined phase shift relative to the reference signal; a waveform combiner having an input coupled to the output of the phase shift element and configured to combine the phase shifted signals provided thereto from the output of the phase shift element to generate a pulse width modulated signal having a pulse width and a phase shift based on a characteristic of the reference signal and the phase shift parameter, wherein the predetermined phase shift is defined between a rising edge of the pulse width modulated signal and a negative-to-positive transition of the reference signal.

12. The device according to claim 11, wherein Each predetermined phase shift parameter includes at least one of the following: a predetermined phase shift; or Predetermined pulse width.

13. The device according to claim 11, wherein: At least one of the phase shifting elements includes an in-phase / quadrature-phase (IQ) modulator.

14. The device according to claim 11, wherein: At least one of the phase shifting elements comprises a phase locked loop.

15. The device according to claim 11, wherein Each phase shift element is coupled to receive a respective one of a plurality of control signals, each respective control signal including a respective predetermined phase shift parameter.

16. The device according to claim 15, wherein: The apparatus further includes a phase detector coupled to the reference signal and the generated pulse width modulated signal.

17. The device according to claim 16, wherein: The phase detector is configured to generate a phase correction signal based on a comparison of the reference signal and the generated pulse width modulated signal, and wherein the phase correction signal is provided to each phase shifting element.

18. The device according to claim 11, wherein The waveform combiner includes at least one edge detector, each edge detector being coupled to at least one flip-flop.

19. The device according to claim 18, wherein: The at least one flip-flop is configured to generate the pulse width modulated signal based on a rising edge of at least one generated phase-shifted signal and a rising edge of at least another generated phase-shifted signal.

20. A method for generating a dynamically controlled pulse width modulation (PWM) waveform, comprising: receiving a reference signal at one or more phase shift elements, each phase shift element having a corresponding predetermined phase shift parameter; generating respective phase-shifted signals at outputs of the one or more phase-shifting elements based on the reference signal and the respective predetermined phase-shifting parameters, each phase-shifted signal having a predetermined phase shift relative to the reference signal; The generated phase shifted signals are combined to obtain a pulse width modulated waveform having a pulse width and a phase shift based on the predetermined phase shift parameter of the phase shift element, wherein the predetermined phase shift is defined between a rising edge of the pulse width modulated waveform and a negative to positive transition of the reference signal.

21. The method according to claim 20, wherein: Each respective predetermined phase shift parameter comprises at least one of a respective predetermined phase shift or a respective predetermined pulse width.

22. The method according to claim 20, further comprising: A respective control signal is provided to each phase shift element, the control signal comprising the respective predetermined phase shift parameter.

23. The method of claim 20, further comprising: A phase correction signal is generated based on a comparison of the reference signal and the pulse width modulated waveform.

24. The method according to claim 23, further comprising: The generated phase shifted signal is adjusted based on the phase correction signal.

25. A power generation and delivery system having an input port and an output port, the power generation and delivery system comprising: a pulse width modulated (PWM) signal generator comprising one or more phase shift elements and a waveform combiner having an input coupled to an output of the phase shift element, the pulse width modulated signal generator being configured to generate a pulse width modulated signal based on phase shift parameters associated with the one or more phase shift elements; as well as a phase-switching tunable impedance network coupled to the output port and configured to receive the generated pulse width modulated signal from the pulse width modulated signal generator, the phase-switching tunable impedance network being configured such that in response to the generated pulse width modulated signal, the phase-switching tunable impedance network changes its impedance to modulate the impedance presented to the output port.

26. The power generation and delivery system of claim 25, wherein: The one or more phase shifting elements are coupled in a parallel architecture.

27. The power generation and delivery system of claim 25, wherein: The one or more phase shifting elements are coupled in a cascade architecture.

28. The power generation and delivery system of claim 25, further comprising a controller coupled to the pulse width modulation signal generator, the controller configured to store phase shift parameters and configured to provide one or more phase shift parameters to the pulse width modulation to generate a pulse width modulated signal having at least one of a predetermined phase shift or a predetermined pulse width.

29. The power generation and delivery system of claim 25, wherein: At least one of the phase shift elements comprises one of the following: a. In-phase / quadrature (IQ) modulator; and b. Phase-locked loop.

30. The power generation and delivery system of claim 25, wherein: The waveform combiner includes at least one of the following: a. one or more logic gates, the at least one logic gate being configured to compare the first phase-shifted signal and the second phase-shifted signal; b. two or more mixers configured to receive respective ones of the I and Q signals, and having outputs coupled to respective inputs of a summing circuit; or c. Two or more edge detector circuits having inputs configured to receive respective ones of the two or more phase-shifted signals and having outputs coupled to different inputs of the flip-flop.

Images