A digital-to-analog converter (DAC) circuit employing a resistor rotator circuit configured to be included in an analog-to-digital converter (ADC) circuit

Abstract

A digital-to-analog converter (DAC) circuit is disclosed that employs a resistor rotator circuit configured to be included in an analog-to-digital converter (ADC) circuit. In one aspect, a DAC circuit includes a plurality of DAC stages, wherein each DAC stage can be configured to generate one or more DAC analog signals corresponding to a selected resistance within the DAC stage. Each DAC stage is configured to receive a corresponding top voltage and a bottom voltage. Each DAC stage is configured to generate a number of DAC analog signals based on the corresponding top voltage and the corresponding bottom voltage and a selected resistance of the DAC stage. Each DAC stage includes an adjustment circuit that includes a resistor configured to adjust the resistance of the corresponding DAC stage so that a parallel combination of the resistance of the adjustment circuit and the resistance of the next DAC stage is maintained at an ideal resistance level.

Description

[0001] Priority claim

[0002] This patent application claims priority to application Ser. No. 16 / 135,985, filed on Sep. 19, 2018, and entitled “DIGITAL-TO-ANALOG CONVERTER (DAC) CIRCUIT EMPLOYING A RESISTOR ROTATOR CIRCUIT CONFIGURED TO BE INCLUDED IN AN ANALOG-TO-DIGITAL CONVERTER (ADC) CIRCUIT,” which is assigned to the present assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technology of the present disclosure generally relates to digital-to-analog converter (DAC) circuits, and more particularly to DAC circuits employing resistor circuits configured to be included in analog-to-digital converter (ADC) circuits. Background Art

[0004] A digital-to-analog converter (DAC) circuit is a device that converts digital codes into a representative analog signal. For example, the converted analog signal can be a reproduction of a native analog signal that was previously converted to digital code by an analog-to-digital converter (ADC) circuit. A common use of DAC circuits is to convert audio and video signals used in media devices (e.g., televisions, cell phones, MP3 players, etc.) from analog to digital representation, and vice versa.

[0005] In addition to converting the digital signal generated by the ADC circuit back into a native analog signal, a DAC circuit is also employed within the ADC circuit to assist in the analog-to-digital conversion. For example, one type of ADC circuit is a successive approximation (SA) flash ADC circuit, which includes: a plurality of comparators cascaded to perform a comparison of an input voltage signal with a series of analog signals generated during the conversion process. Each analog signal used in such a comparison is generated by a DAC circuit employed by the SA flash ADC circuit. Each comparison result of the input voltage signal with the analog signal is used to generate a final value of the digital output signal by the SA flash ADC circuit. Another type of ADC circuit is a successive approximation register (SAR) ADC circuit, which includes: performing a continuous comparison of an analog input signal with a series of analog signals generated during the conversion process. Similar to the SA flash ADC circuit, the series of analog signals used in the comparison is generated by a DAC circuit. Each comparison result of the analog input signal with the series of generated analog signals is used to generate a final value of the digital signal by the SAR ADC circuit.

[0006] As the functional complexity of devices employing ADC circuits continues to increase, the length (i.e., the number of bits) of the digital signals generated by such ADC circuits also increases. This increase in digital signal length typically results in the ADC circuits and the DAC circuits employed by the ADC circuits employing more circuitry, resulting in greater area consumption. However, this increased area consumption reduces the space available for other circuitry within the device. Summary of the Invention

[0007] Various aspects disclosed in the specific embodiments include a digital-to-analog converter (DAC) circuit that employs a resistor rotator circuit that is configured to be included in an analog-to-digital converter (ADC) circuit. In one aspect, a DAC circuit includes multiple DAC stages, wherein each DAC stage can be configured to generate one or more DAC analog signals that correspond to a selected resistance of the DAC stage. In particular, each DAC stage is configured to receive a corresponding top voltage and a corresponding bottom voltage. Each DAC stage is configured to generate a certain number of DAC analog signals based on the corresponding top voltage and the corresponding bottom voltage. Additionally, one or more DAC stages include an adjustment circuit that includes a resistor that is configured to adjust the resistance of the corresponding DAC stage so that the parallel combination of the resistance of the adjustment circuit and the resistance of the next DAC stage is maintained at an ideal resistance level. Compared to traditional DAC circuits, employing multiple DAC stages and adjustment circuits in this manner results in the DAC circuit employing less circuitry and therefore consuming less area.

[0008] In this regard, in one aspect, a multi-bit parallel SAR ADC circuit is provided, comprising a plurality of SAR controller circuits. Each of the plurality of SAR controller circuits includes a number of SAR register circuits. Each SAR register circuit is configured to receive a clock signal and, in response to a corresponding cycle of the clock signal, provide a digital signal representing a digital bit of a digital output signal. Each SAR register circuit is further configured to receive a corresponding digital bit, store the digital bit, and provide a digital signal associated with the digital bit in response to a corresponding next cycle of the clock signal. The digital bit is based on a comparison of an analog input signal and a corresponding DAC analog signal. The multi-bit parallel SAR ADC circuit also includes a multi-output DAC circuit comprising a plurality of DAC stages. Each of the plurality of DAC stages is configured to receive a corresponding top voltage and a corresponding bottom voltage, wherein a voltage range of the corresponding top voltage and the corresponding bottom voltage is based on a reference voltage; and generate a number of DAC analog signals based on the corresponding top voltage, the corresponding bottom voltage, and a resistance of the DAC stage. Each DAC stage in the plurality of DAC stages includes an adjustment circuit, the adjustment circuit including a resistor configured to adjust the resistance of the corresponding DAC stage so that a parallel combination of the resistance of the adjustment circuit and the resistance of the next DAC stage is maintained at a desired resistance level. The multi-bit parallel SAR ADC circuit also includes a comparison circuit. The comparison circuit is configured to receive the number of DAC analog signals, receive an analog input signal, and generate a digital bit corresponding to each SAR controller circuit in the plurality of SAR controller circuits based on a comparison of each DAC analog signal with each analog input signal. Each generated digital bit collectively forms a digital output signal, which is a digital representation of the analog input signal.

[0009] In another aspect, a method for converting an analog input signal into a digital output signal is provided, wherein a plurality of digital bits of the digital output signal are generated in parallel. The method includes receiving a reference voltage; receiving a clock signal; and providing a digital signal in response to a corresponding cycle of the clock signal. The method also includes receiving a corresponding digital bit in response to a corresponding next cycle of the clock signal, wherein the digital bit is based on a comparison of the analog input signal and a corresponding DAC analog signal. The method also includes storing the digital bit in response to the corresponding next cycle of the clock signal; and providing a digital signal associated with the digital bit in response to the corresponding next cycle of the clock signal. The method also includes receiving a corresponding top voltage and a corresponding bottom voltage, wherein a voltage range of the corresponding top voltage and the corresponding bottom voltage is based on the reference voltage. The method also includes: generating a certain number of DAC analog signals based on the corresponding top voltage, the corresponding bottom voltage and the resistance of the DAC stage, wherein the number of DAC analog signals is equal to the number of digital signals; adjusting the resistance of the corresponding DAC stage so that the parallel combination of the resistance of the adjustment circuit and the resistance of the next DAC stage is maintained at an ideal resistance level; and generating corresponding digital bits based on the comparison of each corresponding DAC analog signal with the analog input signal, wherein each generated digital bit collectively forms a digital output signal, which is a digital representation of the analog input signal.

[0010] In another aspect, a multi-bit parallel SA flash ADC circuit is provided, comprising a multi-output DAC circuit including a plurality of DAC stages. Each DAC stage in the plurality of DAC stages corresponds to a parallel comparator stage in a plurality of parallel comparator stages. Each DAC stage in the plurality of DAC stages is configured to receive a corresponding top voltage and a corresponding bottom voltage, wherein a voltage range of the corresponding top voltage and the corresponding bottom voltage is based on a reference voltage; and to generate a certain number of DAC analog signals based on the corresponding top voltage, the corresponding bottom voltage, and the resistance of the DAC stage, wherein the number of DAC analog signals is equal to the number of comparator circuits in each corresponding parallel comparator stage. Each DAC stage in the plurality of DAC stages includes an adjustment circuit, the adjustment circuit including a resistor, the resistor being configured to adjust the resistance of the corresponding DAC stage so that the parallel combination of the resistance of the adjustment circuit and the resistance of the next DAC stage is maintained at an ideal resistance level. The multi-bit parallel SA flash ADC circuit also includes a system comparison circuit, which includes a plurality of parallel comparator stages. Each parallel comparator stage in the plurality of parallel comparator stages includes a number of comparator circuits, wherein the number of comparator circuits in each parallel comparator stage is equal to two (2) multiplied by itself by the number of digital bits of the corresponding parallel comparator stage, minus one (1). Each comparator circuit is configured to receive an analog input signal, receive a corresponding DAC analog signal, and generate a digital signal. If the voltage of the analog input signal is greater than the voltage of the corresponding DAC analog signal, the digital signal has a logic high value; and if the voltage of the analog input signal is less than the voltage of the corresponding DAC analog signal, the digital signal has a logic low value. The system comparison circuit is configured to generate one or more digital bits corresponding to each parallel comparator stage based on each corresponding digital signal, wherein the one or more digital bits collectively form a digital output signal, which is a digital representation of the analog input signal.

[0011] In another aspect, a method for converting an analog input signal into a digital output signal is provided, wherein multiple digital bits of the digital output signal are determined in parallel. The method includes: receiving a reference voltage; receiving a corresponding top voltage and a corresponding bottom voltage, wherein a voltage range of the corresponding top voltage and the corresponding bottom voltage is based on the reference voltage; and generating a number of DAC analog signals based on the corresponding top voltage, the corresponding bottom voltage, and the resistance of a DAC stage, wherein the number of DAC analog signals equals the number of digital signals. The method also includes: adjusting the resistance of the corresponding DAC stage so that the parallel combination of the resistance of the adjustment circuit and the resistance of the next DAC stage is maintained at an ideal resistance level; receiving an analog input signal; and generating one or more digital signals in a plurality of parallel comparator stages. Each digital signal is generated by comparing the analog input signal with a corresponding DAC analog signal. Each digital signal has a logic high value if the voltage of the analog input signal is greater than the voltage of the corresponding DAC analog signal; and each digital signal has a logic low value if the voltage of the analog input signal is less than the voltage of the corresponding DAC analog signal. The method also includes generating one or more digital bits corresponding to each parallel comparator stage based on one or more digital signals of a corresponding parallel comparator stage in the plurality of parallel comparator stages, wherein the one or more digital bits collectively form a digital output signal that is a digital representation of the analog input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram of an exemplary digital-to-analog converter (DAC) circuit configured to generate one or more DAC analog signals;

[0013] Figure 2 is a diagram of an exemplary multi-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuit;

[0014] Figure 3 This diagram shows that Figure 2 a flowchart of an exemplary process performed by a multi-bit parallel SAR ADC circuit to convert an analog input signal into a digital output signal, wherein multiple digital bits of the digital output signal are generated in parallel;

[0015] Figure 4A and Figure 4B illustrates a circuit diagram of an exemplary two (2)-bit parallel ten (10)-bit SAR ADC circuit employing an exemplary multi-output DAC circuit;

[0016] Figure 5 Yes, you can Figure 4B a circuit diagram of an exemplary resistor rotator circuit employed in each DAC stage of a multi-output DAC circuit;

[0017] Figures 6A to 6C illustrates a circuit diagram of another exemplary two (2)-bit parallel ten (10)-bit SAR ADC circuit employing an exemplary multi-output DAC circuit;

[0018] Figure 7 Yes, you can Figure 6B a circuit diagram of an exemplary resistor rotator circuit employed in each DAC stage of a multi-output DAC circuit;

[0019] Figures 8A to 8C illustrates a circuit diagram of an exemplary three (3)-bit parallel twelve (12)-bit SAR ADC circuit employing an exemplary multi-output DAC circuit;

[0020] Figure 9 Yes, you can Figure 8B a circuit diagram of an exemplary resistor rotator circuit employed in each DAC stage of a multi-output DAC circuit;

[0021] Figure 10A is a circuit diagram of an exemplary multi-bit parallel SA flash ADC circuit employing a multi-output DAC circuit;

[0022] Figure 10B It can be used for Figure 10A a circuit diagram of an exemplary resistor rotator circuit for each DAC stage of a multi-output DAC circuit;

[0023] Figure 11 This diagram shows that Figure 10A A flowchart of an exemplary process performed by a multi-bit parallel SA flash ADC circuit to convert an analog input signal into a digital output signal;

[0024] Figure 12 is a circuit diagram of an exemplary successive approximation (SA) flash ADC circuit employing a multi-output DAC circuit;

[0025] Figure 13A Yes, you can Figure 12 a circuit diagram of an exemplary resistor rotator circuit employed in each DAC stage of a multi-output DAC circuit;

[0026] Figure 13B Yes, you can Figure 12 a circuit diagram of another exemplary resistor rotator circuit employed in each DAC stage of a multi-output DAC circuit;

[0027] Figure 14A is a circuit diagram of another exemplary SA flash ADC circuit employing another type of multi-output DAC circuit;

[0028] Figure 14Bis a circuit diagram of another exemplary SA flash ADC circuit employing another type of multi-output DAC circuit;

[0029] Figure 15 is a circuit diagram of an exemplary three (3) column single output DAC circuit using "resistor rotators" as the first two resistor columns;

[0030] Figure 16 It is from Figure 15 A circuit diagram of an exemplary three (3) column multi-output DAC circuit developed from the three (3) column single output DAC circuit in;

[0031] Figure 17 is a circuit diagram of an exemplary resistor rotator circuit employing an "insertion" approach that may be employed in each DAC stage of a multi-output DAC circuit;

[0032] Figure 18 is a circuit diagram of an exemplary resistor rotator circuit employing a "short circuit" path that may be employed in each DAC stage of a multi-output DAC circuit;

[0033] Figure 19 is a circuit diagram of an exemplary resistor rotator circuit employing a "reshuffle" approach that may be employed in each DAC stage of a multi-output DAC circuit;

[0034] Figure 20A and Figure 20B illustrates a circuit diagram of an exemplary single-output DAC circuit;

[0035] Figure 20C is a circuit diagram of another exemplary single-output DAC circuit;

[0036] Figure 20D is a circuit diagram of another exemplary single-output DAC circuit;

[0037] Figure 21 is a circuit diagram of an exemplary multi-output DAC circuit that may be employed in a SAR ADC circuit;

[0038] Figure 22A and Figure 22B illustrates a circuit diagram of an exemplary multi-bit parallel SAR ADC circuit employing a multi-output DAC circuit and a SA flash-based comparison circuit;

[0039] Figure 23 It can be used for Figure 22A and Figure 22B a circuit diagram of an exemplary resistor rotator circuit for each DAC stage of a multi-output DAC circuit;

[0040] Figure 24is a circuit diagram of another exemplary resistor rotator circuit employing a "short circuit" approach that may be employed in each DAC stage of a multi-output DAC circuit;

[0041] Figure 25 can include the use of Figure 1 A block diagram of an exemplary processor-based system of elements of a DAC circuit; and

[0042] Figure 26 is a block diagram of an exemplary wireless communication device including radio frequency (RF) components formed in an integrated circuit (IC), wherein the RF components may include a Figure 1 components of the DAC circuit. DETAILED DESCRIPTION

[0043] Now, with reference to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0044] Various aspects disclosed in the specific embodiments include a digital-to-analog converter (DAC) circuit that employs a resistor rotator circuit that is configured to be included in an analog-to-digital converter (ADC) circuit. In one aspect, a DAC circuit includes multiple DAC stages, each of which can be configured to generate one or more DAC analog signals corresponding to a selected resistance of the DAC stage. In particular, each DAC stage is configured to receive a corresponding top voltage and a corresponding bottom voltage. Each DAC stage is configured to generate a certain number of DAC analog signals based on the corresponding top voltage and the corresponding bottom voltage. Additionally, one or more DAC stages include an adjustment circuit that includes a resistor that is configured to adjust the resistance of the corresponding DAC stage so that the parallel combination of the resistance of the adjustment circuit and the resistance of the next DAC stage is maintained at an ideal resistance level. Compared to traditional DAC circuits, employing multiple DAC stages and adjustment circuits in this manner results in the DAC circuit employing less circuitry and therefore consuming less area.

[0045] In this regard, Figure 1An exemplary DAC circuit 100 is illustrated that is configured to generate a plurality of DAC analog signals 102(1)(1) to 102(N)(M). In particular, the DAC circuit 100 includes DAC stages 104(1) to 104(N), wherein each DAC stage 104(1) to 104(N) can be configured to generate one or more DAC analog signals 102(1)(1) to 102(N)(M). Each DAC stage 104(1) to 104(N) is configured to receive a corresponding top voltage VTOP(1) to VTOP(N) and a corresponding bottom voltage VBOT(1) to VBOT(N) at input ports Rtop(1) to Rtop(N), Rbot(1) to Rbot(N), respectively. Voltage ranges of the corresponding top voltages VTOP(1) to VTOP(N) and the corresponding bottom voltages VBOT(1) to VBOT(N) are based on a reference voltage VREF. Each DAC stage 104(1) to 104(N) has resistors R(1) to R(N) that control the respective top voltages VTOP(1) to VTOP(N) and the corresponding bottom voltages VBOT(1) to VBOT delivered to the next DAC stage 104(1) to 104(N). In this regard, each DAC stage 104(1) to 104(N) divides the voltage received by it between the respective received top voltages VTOP(1) to VTOP(N) and the corresponding bottom voltages VBOT(1) to VBOT(N) into sub-ranges of voltages divided across the respective plurality of resistors 106(1)(1) to 106(N)(S) in each DAC stage 104(1) to 104(N). Each DAC stage 104(1) to 104(N-1) is then configured to select a particular resistor 106(1)(1) to 106(N)(S) to provide a selected voltage sub-range to provide a top voltage VTOP(2) to VTOP(N) and a corresponding bottom voltage VBOT(2) to VBOT(N) to the next DAC stage 104(2) to 104(N). The DAC stages 104(1) to 104(N-1) are configured to select a voltage sub-range between the corresponding received top voltage VTOP(1) to VTOP(N) and the corresponding bottom voltage VBOT(1) to VBOT(N) based on a received control signal CTL and a select signal SEL. The control signal CTL determines in which operating state the DAC stages 104(1) to 104(N) operate. The selection signal SEL determines which of the corresponding resistors 106(1)(1) to (106)(N)(S) in the DAC stages 104(1) to 104(N) are selected to control the resistances R(1) to R(N) between the corresponding top voltages VTOP(1) to VTOP(N-1) and the corresponding bottom voltages VBOT(1) to VBOT(N-1) delivered to the next DAC stage 104(2) to 104(N).For example, as described in more detail below, each DAC stage 104(1) to 104(N) may include a resistor rotator circuit in which a select signal SEL activates / deactivates a certain combination of switches such that the corresponding DAC stage 104(1) to 104(N) selects a corresponding resistor 106(1)(1) to 106(N)(S) in the DAC stage 104(1) to 104(N).

[0046] Continue to refer Figure 1 , each DAC stage 104(1) to 104(N) is configured to generate M DAC analog signals 102(1)(1) to 102(N)(M) based on corresponding top voltages VTOP(1) to VTOP(N), corresponding bottom voltages VBOT(1) to VBOT(N), and selected resistors 106(1)(1) to 106(N)(S). Additionally, each DAC stage 104(1) to 104(N) is configured to generate top voltages VTOP(2) to VTOP(N) and bottom voltages VBOT(2) to VBOT(N) for each subsequent DAC stage 104(2) to 104(N) based on a control signal CTL and a select signal SEL. For example, the DAC stage 104(1) is configured to generate the DAC analog signals 102(1)(1) to 102(1)(M), a top voltage VTOP(2) on the output node Ra(1), and a bottom voltage VBOT(2) on the output node Rb(1). The DAC stage 104(2) is configured to generate DAC analog signals 102(2)(1) to 102(2)(M), a top voltage VTOP(3) at the output node Ra(2), and a bottom voltage VBOT(3) at the output node Rb(2). The DAC stage 104(N-1) is configured to generate DAC analog signals 102(N-1)(1) to 102(N-1)(M), a top voltage VTOP(N) at the output node Ra(N-1), and a bottom voltage VBOT(N) at the output node Rb(N-1). Further, the DAC stage 104(N) is configured to generate DAC analog signals 102(N)(1) to 102(N)(M), a top voltage VTOP(N+1) at the output node Ra(N), and a bottom voltage VBOT(N+1) at the output node Rb(N). The control signal CTL may be configured to electrically couple the corresponding top bypass nodes RbypA(1) to RbypA(N) to the corresponding output nodes Ra(1) to Ra(N) and to electrically couple the corresponding bottom bypass nodes RbypB(1) to RbypB(N) to the corresponding output nodes Rb(1) to Rb(N).

[0047] Continue to refer Figure 1In this aspect, because each DAC stage 104(1) to 104(N) is configured to generate M DAC analog signals 102(1)(1) to 102(N)(M), the DAC circuit 100 is referred to as a multi-output DAC circuit 100. However, other aspects may be configured to generate a single DAC analog signal 102, in which case these aspects are referred to as a single-output DAC circuit 100. Additionally, while each DAC stage 104(1) to 104(N) is configured to generate M DAC analog signals 102(1)(1) to 102(N)(M), other aspects may include DAC stages 104(1) to 104(N) that generate a different number of DAC analog signals 102. The number M of DAC analog signals 102(1)(1) to 102(N)(M) generated by the corresponding DAC stages 104(1) to 104(N) is equal to the number of times the number of bits i of the corresponding selection signal SEL is multiplied by two (2) minus one (1) (i) (i) - 1). Additionally, in this example, the number of resistors 106(1)(1) to 106(N)(S) (e.g., resistors 106(1)(1) to 106(N)(S)) employed in each DAC stage 104(1) to 104(N) is equal to the number M of DAC analog signals 102(1)(1) to 102(N)(M) generated by the corresponding DAC stages 104(1) to 104(N) plus one (1) (e.g., S=M+1).

[0048] Continue to refer Figure 1, each resistor 106(1)(1) to 106(N)(S) within each corresponding DAC stage 104(1) to 104(N) has an equal value. Additionally, each DAC stage 104(1) to 104(N) includes an adjustment circuit 108(1) to 108(N) including a corresponding resistor RADJ(1) to RADJ(N) configured to adjust the resistance of the corresponding DAC stage 104(1) to 104(N). Each corresponding resistor RADJ(1) to RADJ(N) is adjusted so that the parallel combination of the resistance RADJ(1) to RADJ(N) of the adjustment circuit 108(1) to 108(N) and the input impedance REQ(2) to REQ(N) of the next DAC stage 104(2) to 104(N) (each of which may be equal or unequal) is maintained at an ideal resistance. In this aspect, the ideal resistance is equal to the value of each resistor 106(1)(1) to 106(N)(S) within each corresponding DAC stage 104(1) to 104(N) to which each corresponding adjustment circuit 108(1) to 108(N) is coupled. Utilizing multiple DAC stages 104(1) to 104(N) and adjustment circuits 108(1) to 108(N) in this manner results in the DAC circuit 100 utilizing less circuitry and, therefore, consuming less area, compared to conventional DAC circuits.

[0049] Figure 2 is a diagram of an exemplary multi-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuit 200 that may employ a DAC circuit 202 that is Figure 1 One aspect of the DAC circuit 100. Although Figure 2 The individual components of the DAC circuit 202 are not shown or labeled in FIG. 1 , but it is assumed that the DAC circuit 202 includes Figure 11 through 108(N). In particular, the multi-bit parallel SAR ADC circuit 200 is configured to convert an analog input signal VIN into a digital output signal DOUT, wherein X digital bits DG(X) through DG(1) of the digital output signal DOUT are generated in parallel. In various aspects described herein, the digital bit DG(Y) (e.g., the highest numbered digital bit DG) is the most significant bit (MSB) of the digital output signal DOUT, and the digital bit DG(1) (e.g., the lowest numbered digital bit DG) is the least significant bit (LSB) of the digital output signal DOUT. To perform this conversion, the multi-bit parallel SAR ADC circuit 200 includes X SAR controller circuits 204(1) through 204(X). In this example, each of the SAR controller circuits 204(1) to 204(X) includes P SAR register circuits 206(1)(1) to 206(X)(P), where X*P=Y. The SAR register circuits can be any type of circuit that can generate a digital signal corresponding to a received digital bit. The SAR register circuits 206(1)(P) to 206(1)(1) are located in the SAR controller circuit 204(1). The SAR register circuits 206(X-1)(P) to 206(X-1)(1) are located in the SAR controller circuit 204(X-1). The SAR register circuits 206(X)(P) to 206(X)(1) are located in the SAR controller circuit 204(X).

[0050] Further, each of the SAR register circuits 206(1)(1) to 206(X)(P) is configured to receive a clock signal CLK. In response to a corresponding cycle of the clock signal CLK, each of the SAR register circuits 206(1)(1) to 206(X)(P) provides a digital signal 208(1)(1) to 208(X)(P). In response to a corresponding next cycle of the clock signal CLK, one of the SAR register circuits 206(1)() to 206(X)(P) in each corresponding SAR controller circuit 204(1) to 204(X) receives and stores a digital bit DG(1) to DG(X) corresponding to the SAR controller circuit 204(1) to 204(X) based on a comparison of the analog input signal VIN with the corresponding DAC analog signal 210(1) to 210(A). Each SAR register circuit 206(1)(1) to 206(X)(P) also provides a digital signal 208(1)(1) to 208(X)(P) associated with digital bits DG(1) to DG(Y) during the next cycle referenced above.

[0051] Continue to refer Figure 2 The multi-bit parallel SAR ADC circuit 200 includes a DAC circuit 202 that receives a reference voltage VREF and digital signals 208(1)(1) to 208(X)(P). As discussed in more detail below by way of example, the DAC circuit 202 generates a plurality of DAC analog signals 210(1) to 210(A) based on the reference voltage VREF and the digital signals 208(1)(1) to 208(X)(P) and a control signal CONTROL. The SAR register circuits 206(1)(1) to 206(X)(P) of the SAR controller circuits 204(1) to 204(X) generate the control signal CONTROL that conveys timing information to the DAC circuit 202 for passing the designated corresponding digital signals 208(1)(1) to 208(X)(P) from the SAR controller circuits 204(1) to 204(3) to the comparison circuit 214. The control signal CONTROL may be generated by another controller that controls the timing. Additionally, the comparison circuit 214 receives the DAC analog signals 210(1) to 210(A) and the analog input signal VIN. Using the DAC analog signals 210(1) to 210(A) and the analog input signal VIN, the comparison circuit 214 generates digital bits DG(1) to DG(X) corresponding to each SAR controller circuit 204(1) to 204(X), such that the comparison circuit 214 generates X digital bits of the Y digital bits DG(1) to DG(Y) during each cycle of the clock signal CLK (i.e., in parallel), which are stored in the corresponding SAR register circuit 206(1)(1) to 206(X)(P) during the conversion process. Each of the generated digital bits DG(1) to DG(Y) collectively forms a digital output signal DOUT, which is a digital representation of the analog input signal VIN. In this manner, the digital output signal DOUT includes Y digital bits DG(1) to DG(X), where the number Y is equal to the number X of SAR controller circuits 204(1) to 204(X) multiplied by the number P of bits stored in the SAR register circuits 206(1)(1) to 206(X)(P) in each SAR controller circuit 204(1) to 204(X) (i.e., Y=X*P). As used herein, the numbers X, Y, and P are positive integers. As described above, even if the number of digital bits DG(1) to DG(Y) in the digital output signal DOUT increases, generating the digital output signal DOUT by generating the X digital bits DG(1) to DG(Y) in parallel provides a faster conversion time compared to a conventional SAR ADC circuit.

[0052] Figure 3 The diagram shows that Figure 2An exemplary process 300 is provided for performing by a multi-bit parallel SAR ADC circuit 200 to convert an analog input signal VIN into a digital output signal DOUT, wherein X digital bits DG(1) to DG(X) (i.e., DG(1) to DG(X)) of an X-bit width digital output signal DOUT are generated in parallel. The process 300 includes: the multi-bit parallel SAR ADC circuit 200 receives a reference voltage VREF (block 302). The process 300 includes: each SAR register circuit 206(1)(1) to 206(X)(P) receives a clock signal CLK (block 304). Additionally, the process 300 includes: in response to a corresponding cycle of the clock signal CLK, each corresponding SAR register circuit 206(1)(1) to 206(X)(P) provides a digital signal 208(1)(1) to 208(X)(P) (block 306). For example, during each clock cycle i, where i increments between 1 and P for each clock cycle, one SAR register circuit 206(1)(i) to 206(X)(i) in each corresponding SAR controller circuit 206(1) to 204(X) provides a corresponding digital signal 208(1)(i) to 208(X)(i). The process 300 further includes: in response to a corresponding next cycle of the clock signal CLK, each SAR register circuit 206(1)(1) to 206(X)(P) receives a corresponding digital bit DG(1) to DG(X), wherein the digital bit DG(1) to DG(X) is based on a comparison of the analog input signal VIN and the corresponding DAC analog signal 210(1) to 210(A) (where A=2 X-1)(box 308). The process 300 also includes: in response to the corresponding next cycle of the clock signal CLK, each SAR register circuit 206(1)(1) to 206(X)(P) stores the digital bits DG(1) to DG(X) (box 310). The process 300 also includes: in response to the corresponding next cycle of the clock signal CLK, each SAR register circuit 206(1)(1) to 206(X)(P) provides a digital signal 208(1)(1) to 208(X)(P) related to the digital bits DG(1) to DG(X) (box 312). Further, the process 300 includes: the DAC circuit 202 receives the corresponding top voltage VTOP(1) to VTOP(N) and the corresponding bottom voltage VBOT(1) to VBOT(N) (box 314). The voltage range of the corresponding top voltage VTOP(1) to VTOP(N) and the corresponding bottom voltage VBOT(1) to VBOT(N) is based on the reference voltage VREF. The process 300 also includes: the DAC circuit 202 generates a number of DAC analog signals 210(1) to 210(A) based on the received corresponding top voltages VTOP(1) to VTOP(N) and the corresponding bottom voltages VBOT(1) to VBOT(N) (block 316). The process 300 also includes: using the adjustment circuit 108(1) to 108(N) to adjust the resistance 106(1)(1) to 106(N)(S) of the corresponding DAC stage 104(1) to 104(N) so that the parallel combination of the resistance of the adjustment circuit 108(1) to 108(N) and the resistance of the next DAC stage 104(2) to 104(N) is maintained at a desired resistance level (block 318). The process 300 further includes generating, by the comparison circuit 214, a digital bit DG(1) to DG(X) corresponding to each SAR controller circuit 204(1) to 204(X) based on the comparison of each DAC analog signal 210(1) to 210(A) with the analog input signal VIN (block 320). In this manner, each of the generated digital bits DG(1) to DG(X) collectively form a digital output signal DOUT that is a digital representation of the analog input signal VIN.

[0053] Figure 4A and Figure 4B An exemplary two (2)-bit parallel ten (10)-bit SAR ADC circuit 400 (also referred to as "multi-bit parallel SAR ADC circuit 400") employing an exemplary multi-output DAC circuit 402 is illustrated. The multi-bit parallel SAR ADC circuit 400 may also be referred to as a two (2)-bit parallel ten (10)-bit SAR ADC circuit 400. The multi-bit parallel SAR ADC circuit 400 includes Figure 2 The common elements of the multi-bit parallel SAR ADC circuit 200 are Figure 2 as well as Figure 4A and Figure 4B Common element symbols are used to refer to the components, and therefore they are not described again in this document.

[0054] Continue to refer Figure 4A and Figure 4B , the multi-output DAC circuit 402 includes DAC stages 404(1) to 404(4), switches 406(1) to 406(10), and a voltage divider circuit 408 using resistors 410(1) to 410(4). Additionally, in this aspect, the SAR controller circuit 204(2) is configured to provide enable signals 412(1) to 412(5) and DAC select signals 414(1) to 414(5) corresponding to each SAR register circuit 206(2)(1) to 206(2)(5). In particular, the enable signals 412(1) to 412(5) are generated by the SAR register circuits 206(2)(1) to 206(2)(5). DAC select signals 414(1) to 414(4) correspond to the value of each select input node SEL provided to each corresponding SAR register circuit 206(2)(1) to 206(2)(4), while DAC select signal 414(5) is provided as the output of OR gate 416, which receives enable signal 412(5) and select signal SEL provided to SAR register circuit 206(2)(5). OR gate 416 combines enable signal 412(5) with select signal SEL so that at the end of the conversion process, voltage divider 408 remains connected to DAC stage 404(4) through switches 406(5) and 406(10). Multi-bit parallel SAR ADC circuit 400 also includes SAR register circuit 417, which is configured to generate a test signal TRIAL and a completion signal DONE.

[0055] Continue to refer Figure 4A and Figure 4BEach DAC stage 404(1) to 404(4) is configured to receive a corresponding top voltage VTOP(1) to VTOP(4), a corresponding bottom voltage VBOT(1) to VBOT(4), and a corresponding digital bit DG(1) to DG(10). Each DAC stage 404(1) to 404(4) is further configured to generate a corresponding top output voltage VTO(1) to VTO(4) and a bottom output voltage VBO(1) to VBO(4) by dividing a voltage range of each corresponding top voltage VTOP(1) to VTOP(4) and each bottom voltage VBOT(1) to VBOT(4) based on a value of the digital bit DG(1) to DG(10). For example, the DAC stage 404(1) is configured to receive a reference voltage VREF as the top voltage VTOP(1), a ground signal as the bottom voltage VBOT(1), and the digital bits DG(10) and DG(9). The top output voltage VTO(1) and the bottom output voltage VBO(1) of the DAC stage 404(1) are generated by dividing the voltage range between the reference voltage VREF and the ground signal based on the values of the digital bits DG(10), DG(9).

[0056] Continue to refer Figure 4A and Figure 4B, the top output voltage VTO(1) and the bottom output voltage VBO(1) are provided to the DAC stage 404(2) as the top voltage VTOP(2) and the bottom voltage VBOT(2), respectively. The DAC stage 404(2) is further configured to receive the digital bits DG(8), DG(7). Therefore, the top output voltage VTO(2) and the bottom output voltage VBO(2) of the DAC stage 404(2) are generated by dividing the voltage range between the top output voltage VTO(1) and the bottom output voltage VBO(1) based on the values of the digital bits DG(8), DG(7). Additionally, the top output voltage VTO(2) and the bottom output voltage VBO(2) are provided to the DAC stage 404(3) as the top voltage VTOP(3) and the bottom voltage VBOT(3), respectively. The DAC stage 404(3) is further configured to receive the digital bits DG(6), DG(5). Therefore, by dividing the voltage range between the top output voltage VTO(2) and the bottom output voltage VBO(2) based on the value of the digital bits DG(6), DG(5), the top output voltage VTO(3) and the bottom output voltage VBO(3) of the DAC stage 404(3) are generated. Further, the top output voltage VTO(3) and the bottom output voltage VBO(3) are provided to the DAC stage 404(4) as the top voltage VTOP(4) and the bottom voltage VBOT(4), respectively. The DAC stage 404(4) is also configured to receive the digital bits DG(4), DG(3). Therefore, by dividing the voltage range between the top output voltage VTO(3) and the bottom output voltage VBO(3) based on the value of the digital bits DG(4), DG(3), the top output voltage VTO(4) and the bottom output voltage VBO(4) of the DAC stage 404(4) are generated.

[0057] Continue to refer Figure 4A and Figure 4B , DAC select signals 414(1) to 414(5) are provided to switches 406(1) to 406(10), respectively. Based on the values of the DAC select signals 414(1) to 414(5), some combination of the reference voltage VREF and the top output voltages VTO(1) to VTO(4) is provided to the input node 418(1) of the voltage divider circuit 408. It should be noted that, alternatively, the DAC stages 404(1) to 404(4) may include (or represent) a circuit designed with Figure 4B4. The voltage divider circuit 408 of FIG. 2 is similar in design to the voltage divider circuit 408 of FIG. 2. Additionally, based on the values of the DAC select signals 414(1) to 414(5) that activate a certain combination of switches 406(6) to 406(10), a certain combination of the ground signal and the bottom output voltage VBO(1) to VBO(4) is provided to the input node 418(2) of the voltage divider circuit 408. In this aspect, the resistors 410(1) to 410(4) each have equal resistance (e.g., two (2) kilo-ohms (kΩ)) such that the voltage divider circuit 408 generates DAC analog signals 419(1) to 419(3) as equal divisions (e.g., divisions of corresponding voltage ranges) of the voltage provided to the voltage divider circuit 408. The comparison circuit 214 uses the DAC analog signals 419(1) to 419(3) to generate a digital output signal DOUT having digital bits DG(1) to DG(10) within five (5) cycles of the clock signal. In this aspect, the comparison circuit 214 includes comparator circuits 420(1) to 420(3) and a thermometer-to-binary (TTB) circuit 422. Specifically, the TTB circuit 422 includes AND gates 424(1), 424(2), inverters 426(1), 426(2), and OR gates 428(1), 428(2). The signals H, M, and L generated by the OR gates 428(1), 428(2) generate digital bits DG(X), DG(X-1) of the corresponding period. The multi-output DAC circuit 402 is used to replace three separate DACs to consume less chip area.

[0058] Figure 5 The diagram shows that Figure 4A and Figure 4B The exemplary resistor rotator circuit 500 employed in each DAC stage 404(1) to 404(4) of FIG. The resistor rotator circuit 500 is configured to receive a top voltage VTOP on a top voltage input node TOP and a bottom voltage VBOT on a bottom voltage input node BOT. The resistor rotator circuit 500 also includes a decoder circuit 502 configured to receive a top voltage VTOP on a top voltage input node TOP and a bottom voltage VBOT on a bottom voltage input node BOT. Figure 4A and Figure 4BDAC stages 404(1) to 404(4) described in the embodiment of the present invention receive digital bits DG(X), DG(X-1) at their respective input nodes S1, S0 and generate decoded signals DS(1) to DS(4) based on the digital bits DG(X), DG(X-1). In this aspect, decoder circuit 502 is a one-hot decoder, wherein only one of the decoded signals DS(1) to DS(4) has a logic high "1" value. For example, decoded signals DS(1) to DS(4) are generated according to the following logic functions: DS(1) = (inverted DG(X) AND inverted DG(X-1)); DS(2) = (inverted DG(X) AND DG(X-1)); DS(3) = (DG(X) AND inverted DG(X-1)); and DS(4) = DG(X) AND DG(X-1)). Each decoded signal DS(1) to DS(4) is provided to a corresponding AND gate 506(1) to 506(4). Each AND gate 506(1) to 506(4) also receives an enable signal via an enable input node EN. Figure 4A and Figure 4B 4 and 508 ( 4 ) corresponding to the DAC stages 404 ( 1 ) to 404 ( 4 ) described above.

[0059] Continue to refer Figure 5, the resistor rotator circuit 500 also includes switches 510(1) to 510(8), wherein a logic high "1" value closes the switches 510(1) to 510(8), and a logic low "0" value opens the switches 510(1) to 510(8). The switches 510(1) to 510(8) are used in conjunction with resistors 512(1) to 512(6) to generate top output voltages VTO(1) to VTO(4) and bottom output voltages VBO(1) to VBO(4) at respective voltage output nodes RA, RB of corresponding DAC stages 404(1) to 404(4). In particular, the resistor 512(1) includes a first node 514(1)(1) electrically coupled to the switch 510(1); and a second node 514(1)(2) electrically coupled to the switch 510(2). Resistor 512(2) includes a first node 514(2)(1) electrically coupled to switch 510(2); and a second node 514(2)(2) electrically coupled to switch 510(3). Resistor 512(3) includes a first node 514(3)(1) electrically coupled to switch 510(3); and a second node 514(3)(2) electrically coupled to switch 510(4). Further, resistor 512(4) includes a first node 514(4)(1) electrically coupled to switch 510(5); and a second node 514(4)(2) electrically coupled to switch 510(6). Resistor 512(5) includes a first node 514(5)(1) electrically coupled to switch 510(6); and a second node 514(5)(2) electrically coupled to switch 510(7). Resistor 512 ( 6 ) includes a first node 514 ( 6 )( 1 ) electrically coupled to switch 510 ( 7 ) and a second node 514 ( 6 )( 2 ) electrically coupled to switch 510 ( 8 ).

[0060] Continue to refer Figure 5, switches 510(1), 510(5) are configured to receive resistor select signal 508(1), and switches 510(2), 510(6) are configured to receive resistor select signal 508(2). Further, switches 510(3), 510(7) are configured to receive resistor select signal 508(3), and switches 510(4), 510(8) are configured to receive resistor select signal 508(4). Also included is a resistor 516, wherein a first node 518(1) is electrically coupled to a top voltage output node RA, and a second node 518(2) is electrically coupled to a bottom voltage output node RB. The resistance RADJ of resistor 516 can be adjusted so that the parallel combination of resistor 516 and a desired resistance R_NEXT of the next DAC stage 404 is maintained at a desired constant value so that the resistor rotator circuit 500 generates a desired output. In this manner, the above configuration causes the resistor rotator circuit 500 to generate corresponding top output voltages VTO(1) to VTO(4) and bottom output voltages VBO(1) to VBO(4) depending on which of the switches 510(1) to 510(8) are opened or closed based on the digital bits DG(X), DG(X-1).

[0061] Figures 6A to 6C FIG2 shows a circuit diagram of another exemplary two (2)-bit parallel ten (10)-bit SAR ADC circuit 600 employing a multi-output DAC circuit 602. The two (2)-bit parallel ten (10)-bit SAR ADC circuit 600 may also be referred to as a multi-bit parallel SAR ADC circuit 600. The multi-bit parallel SAR ADC circuit 600 includes Figure 4A and Figure 4B The common elements of the multi-bit parallel SAR ADC circuit 400 are Figure 4A and Figure 4B as well as Figures 6A to 6C Common element symbols are used to refer to the components, and therefore they are not described again in this document.

[0062] Continue to refer Figures 6A to 6C , the multi-output DAC circuit 602 is functionally equivalent to Figure 4B4. In this manner, the multi-output DAC circuit 602 includes DAC stages 604(1) to 604(4), switches 606(1) to 606(8), and a voltage divider circuit 608 employing resistors 610(1) to 610(4). Each DAC stage 604(1) to 604(4) is configured to receive a respective enable signal 612(1) to 612(4) generated by an AND gate 614 that receives an enable signal 616 from the SAR register circuit 417 and an inverted completion signal 618 from an inverter 619. Additionally, the DAC stage 604(1) is configured to generate stage signals 620(1) to 620(3). Further, as discussed in more detail below, in this example, Figure 6B The DAC stage 604(1) of the multi-output DAC circuit 602 in FIG. Figure 7 700 in the resistor rotator circuit. In this example, the other DAC stages 604(2) to 604(4) of the multi-output DAC circuit 602 are Figure 5 The resistor rotator circuit 500 in FIG. 2 is a circuit diagram of a two (2) bit parallel ten (10) bit SAR ADC circuit 600. The two (2) bit parallel ten (10) bit SAR ADC circuit 600 also includes a selection circuit 622 that employs multiplexer circuits 624 (1) to 624 (3) as analog multiplexers. Each multiplexer circuit 624 (1) to 624 (3) is configured to receive a corresponding level signal 620 (1) to 620 (3) and a corresponding DAC analog signal 628 (1) to 628 (3). Additionally, each multiplexer circuit 624 (1) to 624 (3) is configured to receive a DAC select signal 630 that selects between input values of the corresponding multiplexer circuit 624 (1) to 624 (3). In particular, the DAC select signal 630 is the output of an OR gate 632 that receives a signal 633 from a complement output node 634 of a D flip-flop circuit 636 and receives as input a done signal DONE of the multi-bit parallel SAR ADC circuit 600. Multiplexer circuits 624(1) to 624(3) provide corresponding selected DAC analog signals 638(1) to 638(3) to the comparison circuit 214, wherein the output of the comparison circuit 214 is provided to the TTB circuit 422, which is configured to generate digital bits DG(X), DG(X-1) in corresponding cycles until all digital bits DG(1) to DG(10) are calculated. Figures 6A to 6C The SAR ADC circuit 600 is Figure 4A and Figure 4B The difference is: Figures 6A to 6CThe SAR ADC circuit 600 in FIG. 6 allows for different reference voltage load resistances than those allowed by the basic resistor rotator. Regardless of the state of the SAR ADC circuit 600, Figure 6A The SAR ADC circuit 600 in FIG. 6 , which includes the flip-flop 636 and gates 619 , 614 , 632 , all provide a uniform (constant) resistance to the VREF driver circuit. Figure 7 The diagram shows that Figure 6B An exemplary resistor rotator circuit 700 is employed in a DAC stage 604(1) of a multi-output DAC circuit 602. The resistor rotator circuit 700 is configured to receive a top voltage VTOP on a top voltage input node TOP and a bottom voltage VBOT on a bottom voltage input node BOT. The resistor rotator circuit 700 further includes a decoder circuit 702 configured to receive a top voltage VTOP and a bottom voltage VBOT. Figure 6A and Figure 6B The DAC stage 604(1) described in Figure 6B , and generates decoded signals DS(1) to DS(4) based on digital bits DG(10) and DG(9) in the decoded state. In this aspect, the decoder circuit 702 is a one-hot decoder, wherein only one of the decoded signals DS(1) to DS(4) has a logic high "1" value. For example, the decoded signals DS(1) to DS(4) are generated according to the following logic functions: DS(1) = (inverted DG(X) AND inverted DG(X-1)); DS(2) = (inverted DG(X) AND DG(X-1)); DS(3) = (DG(X) AND inverted DG(X-1)); and DS(4) = DG(X) AND DG(X-1)). Each decoded signal DS(1) to DS(4) is provided to a corresponding AND gate 706(1) to 706(4). Each AND gate 706(1) to 706(4) also receives an enable signal via an enable input node EN. Figure 6A and Figure 6B 6. The DAC stages 604(1) to 604(4) described in the preceding claims are enabled by one of the enable signals 612 corresponding to the DAC stages 604(1) to 604(4) described in the preceding claims, and corresponding resistor select signals 708(1) to 708(4) are generated.

[0063] Continue to refer Figure 7, the resistor rotator circuit 700 also includes inverters 710(1) to 710(4), which are configured to receive corresponding decoded signals DS(1) to DS(4) and generate corresponding inverted decoded signals DSI(1) to DSI(4). OR gates 712(1) to 712(4) are configured to receive phase signal 714 and corresponding inverted decoded signals DSI(1) to DSI(4) and generate resistor select signals 708(5) to 708(8). The resistor rotator circuit 700 also includes switches 716(1) to 716(15), wherein a logic high "1" value closes the switches 716(1) to 716(15), and a logic low "0" value opens the switches 716(1) to 716(15). Switches 716(1) to 716(15) are used in conjunction with resistors 718(1) to 718(4) to generate a top output voltage VTOP and a bottom output voltage VBOT(1) at respective voltage output nodes RA, RB of DAC stage 604(1). Other DAC stages 604(2) to 604(4) may be used. Figure 5 5. When the phase signal 714 is logic high, the DAC voltages VDAC(1) to VDAC(3) are used by the multi-output DAC 602 and passed to the comparator circuits 420(1) to 420(3) through the multiplexer circuits 624(1) to 624(3).

[0064] Figures 8A to 8C An exemplary three (3)-bit parallel twelve (12)-bit SAR ADC circuit 800 (also referred to as "multi-bit parallel SAR ADC circuit 800") employing an exemplary multi-output DAC circuit 802 is illustrated. The three (3)-bit parallel twelve (12)-bit SAR ADC circuit 800 includes Figure 4A and Figure 4B as well as Figures 6A to 6C The multi-bit parallel SAR ADC circuits 400 and 600 have common elements that use Figure 4A and Figure 4B 、 Figures 6A to 6C and Figures 8A to 8C The common element symbols in the figure are used to refer to the components, and therefore they are not described again in this article.

[0065] Continue to refer Figures 8A to 8C, a three (3) bit parallel twelve (12) bit SAR ADC circuit 800 includes SAR controller circuits 204 (1) to 204 (3), wherein each SAR controller circuit includes four (4) SAR register circuits 206 (1) (1) to 206 (3) (4). In this manner, the SAR register circuits 206 (1) (1) to 206 (1) (4) correspond to digital bits DG (1), DG (4), DG (7) and DG (10), the SAR register circuits 206 (2) (1) to 206 (2) (4) correspond to digital bits DG (2), DG (5), DG (8) and DG (11), and the SAR register circuits 206 (3) (1) to 206 (3) (4) correspond to digital bits DG (3), DG (6), DG (9) and DG (12). Additionally, the DAC select signals 806(1) to 806(4) correspond to the value of each select input node SEL provided to each corresponding SAR register circuit 206(3)(1) to 206(3)(4).

[0066] Continue to refer Figures 8A to 8C , the multi-output DAC circuit 802 includes DAC stages 808(1) to 808(3) and a voltage divider circuit 810. Figure 9 As discussed in greater detail at the outset, the DAC stages 808(1) to 808(3) are configured to internally multiplex the DAC analog signals 812(1) to 812(7). Additionally, the voltage divider circuit 810 includes switches 814(1) to 814(7) that multiplex the DAC analog signals 812(1) to 812(7) using resistors 816(1) to 816(8). A comparison circuit 818, similar to the comparison circuit 214 (except that the comparison circuit 214 employs three (3) comparator circuits rather than seven (7) comparator circuits as employed in the comparison circuit 818), receives the DAC analog signals 812(1) to 812(7) and the analog input signal VIN. Comparison circuit 818 employs a TTB circuit 820 similar to TTB circuit 422, wherein TTB circuit 820 generates signals O7 to O1 used by OR gates 428(1) to 428(3) to generate digital bits DG(1) to DG(12). Specifically, digital bits DG(1), DG(5), and DG(9) are generated during a cycle of clock signal CLK, while digital bits DG(2), DG(6), and DG(10) are generated during another cycle of clock signal CLK. Furthermore, digital bits DG(3), DG(7), and DG(11) are generated during a cycle of clock signal CLK, while digital bits DG(4), DG(8), and DG(12) are generated during another cycle of clock signal CLK.

[0067] Figure 9 The diagram shows that Figure 8BAn exemplary resistor rotator circuit 900 is employed in each DAC stage 808(1) to 808(3) of the multi-output DAC circuit 802. The resistor rotator circuit 900 is configured to receive a top voltage VTOP on a top voltage input node TOP and a bottom voltage VBOT on a bottom voltage input node BOT. The resistor rotator circuit 900 also includes a decoder circuit 902 configured to receive digital bits DG(X) to DG(X-2) on input nodes S2, S1, and S0, and to generate decoded signals DS(1) to DS(8) based on the digital bits DG(X) to DG(X-2). The resistor rotator circuit 900 also includes switches 904(1) to 904(16). The decoded signals DS(1) to DS(8) are provided to corresponding switches 904(1) to 904(8) and 904(9) to 904(16), respectively. The resistor rotator circuit 900 is configured to provide a top output voltage VTO and a bottom output voltage VBO at respective voltage output nodes RA, RB. Additionally, switches 904(17) to 904(23) are configured to receive a phase signal 908 so as to provide DAC analog signals 812(1) to 812(7).

[0068] Figure 10A An exemplary multi-bit parallel SA flash ADC circuit 1000 employing a multi-output DAC circuit 1002 is illustrated. In particular, the multi-bit parallel SA flash ADC circuit 1000 is configured to convert an analog input signal VIN into a digital output signal DOUT having digital bits DG(8) to DG(1), wherein two (2) of the digital bits DG(8) to DG(1) are generated in parallel. The multi-output DAC circuit 1002 includes DAC stages 1004(1) to 1004(4) configured to provide corresponding DAC analog signals 1006(1)(1) to (4)(3) based on a reference voltage VREF and a subset of the digital bits DG(8) to DG(1) generated by parallel comparator stages 1008(1) to 1008(4) of a system comparison circuit 1010. The DAC analog signals 1006(1)(1) to 1006(4)(3) are provided to each corresponding parallel comparator stage 1008(1) to 1008(4). The multi-output DAC circuit 1002 further includes a resistor 1011. Alternatively, the DAC stage 1004(4) can be replaced by a four (4) resistor voltage divider between the terminals of the voltage VTOP(4) and VBOT(4), wherein the DAC analog signals 1006(4)(1) to 1006(4)(3) are connected to three (3) tap points of the voltage divider. The voltage divider has the same resistance between the terminals of the voltage VTOP(4) and VBOT(4) as the DAC stage 1004(4).

[0069] Continue to refer Figure 10A, each of the parallel comparator stages 1008(1) to 1008(4) includes three (3) corresponding comparator circuits 1012(1)(1) to 1012(4)(3). In particular, the number of comparator circuits 1012(1)(1) to 1012(4)(3) in each of the parallel comparator stages 1008(1) to 1008(4) is equal to the number of digital bits DG(8) to DG(1) of the corresponding parallel comparator stage 1008(1) to 1008(4) (i.e., 2 b -1, where b is the number of parallel digital bits (two (2) in this example), i.e., for example, DG(8) and DG(7), or DG(6) and DG(5), or DG(4) and DG(3), or DG(2) and DG(1)). Each comparator circuit 1012(1)(1) to 1012(4)(3) receives an analog input signal VIN and a corresponding DAC analog signal 1006(1)(1) to 1006(4)(3), and generates a digital signal 1014(1)(1) to 1014(4)(3) based on comparing the analog input signal VIN and the DAC analog signal 1006(1)(1) to 1006(4)(3). The system comparison circuit 1010 is configured to generate a digital bit DG(8) to DG(1) corresponding to each parallel comparator stage 1008(1) to 1008(4), wherein the digital bits DG(8) to DG(1) collectively form a digital output signal DOUT (not shown). In this aspect, the system comparison circuit 1010 includes a TTB circuit 1016 configured to receive the digital signals 1014(1)(1) to 1014(4)(3) and generate a digital bit DG(8) to DG(1) corresponding to each parallel comparator stage 1008(1) to 1008(4) to form the digital output signal DOUT. In particular, TTB circuit 1016 employs AND gates 1018(1)(1) to 1018(4)(2), inverters 1020(1)(1) to 1020(4)(2), and OR gates 1022(1)(1) to 1022(4)(2) to generate digital bits DG(8) to DG(1).

[0070] Continue to refer Figure 10A, each DAC stage 1004(1) to 1004(4) is configured to generate a corresponding DAC analog signal 1006(1)(1) to 1006(4)(3), wherein each DAC analog signal 1006(1)(1) to 1006(4)(3) of each DAC stage 1004(1) to 1004(4) is provided to a corresponding comparator circuit 1012(1)(1) to 1012(4)(3) in each corresponding parallel comparator stage 1008(1) to 1008(4). In particular, each DAC stage 1004(1) to 1004(4) is configured to receive a corresponding top voltage VTOP(1) to VTOP(4) and a corresponding bottom voltage VBOT(1) to VBOT(4). Each DAC stage 1004(1) to 1004(4) is further configured to generate each DAC analog signal 1006(1)(1) to 1006(4)(3) (as a signal provided to the DAC) by dividing the voltage range of each corresponding top voltage VTOP(1) to VTOP(4) and each bottom voltage VBOT(1) to VBOT(4) Figure 10B DAC voltages VDAC(1) to VDAC(3) of the resistor rotator circuit 1024 in FIG. 1 . For example, a reference voltage VREF is provided to the DAC stage 1004(1) as a top voltage VTOP(1), while a ground signal is provided to the DAC stage 1004(1) as a bottom voltage VBOT(1). Therefore, the DAC analog signals 1006(1)(1) to 1006(1)(3) of the DAC stage 1004(1) are divisions of a range between the reference voltage VREF and the ground signal. In this manner, the parallel comparator stage 1008(1) generates digital signals 1014(1)(1) to 1014(1)(3) based on each division of the reference voltage VREF, such that digital bits DG(8), DG(7) are generated based on whether the analog input signal VIN is greater than or less than each corresponding DAC analog signal 1006(1)(1) to 1006(4)(3).

[0071] Continue to refer Figure 10A, digital bits DG(8) to DG(3) are used to determine the top voltages VTOP(2) to VTOP(4) and the bottom voltages VBOT(2) to VBOT(4) of subsequent DAC stages 1004(2) to 1004(4). For example, in response to digital bits DG(8), DG(7) reaching a stable state, DAC stage 1004(1) provides the top voltage VTOP(2) and the bottom voltage VBOT(2) of DAC stage 1004(2) from output nodes RA(1), RB(1). Additionally, digital bits DG(6) to DG(5) are used by DAC stage 1004(2) to determine the top voltage VTOP(3) and the bottom voltage VBOT(3) provided from output nodes RA(2), RB(2) to DAC stage 1004(3). Further, digital bits DG(4), DG(3) are used by DAC stage 1004(3) to determine the top voltage VTOP(4) and the bottom voltage VBOT(4) provided to DAC stage 1004(4) from output nodes RA(3), RB(3). Using digital bits DG(8), DG(7) in this manner causes the top voltage VTOP(2) and the bottom voltage VBOT(2) to have a voltage range within which the analog input signal VIN falls. Thus, the top voltages VTOP(1) to VTOP(4) and the bottom voltages VBOT(1) to VBOT(4) are generated, enabling the multi-bit parallel SA flash ADC circuit 1000 to use successive approximation when generating digital bits DG(8) to DG(1). Additionally, digital bits DG(6) to DG(5) are used by DAC stage 1004(2) to determine the top voltage VTOP(3) and the bottom voltage VBOT(3) provided to DAC stage 1004(3) from output nodes RA(2), RB(2). Furthermore, digital bits DG(4) and DG(3) are used by DAC stage 1004(3) to determine the top voltage VTOP(4) and the bottom voltage VBOT(4) provided from output nodes RA(3) and RB(3) to DAC stage 1004(4). Because DAC stage 1004(4) (i.e., the final DAC stage 1004(4) of multi-output DAC circuit 1002) does not provide voltages to subsequent DAC stages, digital bits DG(2) and DG(1) are not provided to DAC stage 1004(4). Instead, in this aspect, resistor 1011 is electrically coupled to output nodes RA(4) and RB(4) of DAC stage 1004(4) to provide the same resistance as that which may be provided by subsequent DAC stage 1004.

[0072] Figure 10B The diagram shows the Figure 10AAn exemplary resistor rotator circuit 1024 for each DAC stage 1004(1) to 1004(4) of the multi-output DAC circuit 1002 is shown. The resistor rotator circuit 1024 is configured to receive a top voltage VTOP on a top voltage input node TOP and a bottom voltage VBOT on a bottom voltage input node BOT. The resistor rotator circuit 1024 also includes a decoder circuit 1026 configured to receive digital bits DG(2), DG(1) of the corresponding parallel comparator stage 1008 and generate decoded signals DS(1) to DS(4) based on the digital bits DG(2), DG(1). In this aspect, the decoder circuit 1026 is a one-hot decoder in which only one of the decoded signals DS(1) to DS(4) has a logic high "1" value. For example, decoded signals DS(1) to DS(4) are generated according to the following logic functions: DS(1) = (inverted DG(2) AND inverted DG(1)); DS(2) = (inverted DG(2) AND DG(1)); DS(3) = (DG(2) AND inverted DG(1)); and DS(4) = (DG(2) AND DG(1)). Resistor rotator circuit 1024 also includes inverters 1028(1) to 1028(4) configured to receive corresponding decoded signals DS(1) to DS(4) and generate corresponding inverted decoded signals DS'(1) to DS'(4).

[0073] Continue to refer Figure 10B , resistor rotator circuit 1024 further includes switches 1030(1) to 1030(12). Switches 1030(1) to 1030(4) are configured to receive corresponding inverted decoded signals DS'(1) to DS'(4). Additionally, switches 1030(5) and 1030(7) are configured to receive decoded signal DS(1), switches 1030(6) and 1030(9) are configured to receive decoded signal DS(2), switches 1030(8) and 1030(11) are configured to receive decoded signal DS(3), and switches 1030(10) and 1030(12) are configured to receive decoded signal D(4). Additionally, resistor rotator circuit 1024 includes resistors 1032(1) to 1032(4) alternately coupled in series with corresponding switches 1030(1) to 1030(4) and coupled in parallel with switches 1030(5) to 1030(12). Resistor rotator circuit 1024 also includes an adjustment circuit 1034 having a resistor RADJ.

[0074] Continue to refer Figure 10B, the above configuration causes the resistor rotator circuit 1024 to generate DAC voltages VDAC(1) to VDAC(3), where each DAC voltage is in a voltage range between a top voltage VTOP and a bottom voltage VBOT. In this aspect, resistors 1032(1) to 1032(4) each have equal resistance (e.g., 2 kilo-ohms (kΩ)) such that the DAC voltages VDAC(1) to VDAC(3) are equal divisions of the voltage range between the top voltage VTOP and the bottom voltage VBOT. For example, if the reference voltage VREF is equal to one (1.0) volt (V), the DAC voltages VDAC(3) to VDAC(1) can be equal to 0.75V, 0.5V, and 0.25V, respectively, regardless of the value of the digital bits DG(2), DG(1). Additionally, the above configuration causes the resistor rotator circuit 1024 to generate a next-level top voltage VTOP' on the top voltage output node TOP_OUT and a next-level bottom voltage VBOT' on the bottom voltage output node BOT_OUT, where the next-level top voltage VTOP' and bottom voltage VBOT' (i.e., RA and RB of the next DAC stage 1004) are determined based on which of the switches 1030(1) to 1030(12) are opened or closed based on the digital bits DG(2), DG(1).

[0075] Figure 11 An exemplary process 1100 is illustrated, which may be performed by Figure 10AThe multi-bit parallel SA flash ADC circuit 1000 is executed to convert an analog input signal VIN into a digital output signal DOUT. The process 1100 includes: receiving a reference voltage VREF (box 1102). The process 1100 also includes: receiving corresponding top voltages VTOP(1) to VTOP(4) and corresponding bottom voltages VBOT(1) to VBOT(4) (box 1104). The voltage range of the corresponding top voltages VTOP(1) to VTOP(4) and the corresponding bottom voltages VBOT(1) to VBOT(4) is based on the reference voltage VREF. The process 1100 also includes: generating a certain number of DAC analog signals 1006(1)(1) to 1006(4)(3) based on the corresponding top voltages VTOP(1) to VTOP(4), the corresponding bottom voltages VBOT(1) to VBOT(4), and the resistance of the DAC stages 1004(1) to 1004(4) (box 1106). The number of DAC analog signals 1006(1)(1) to 1006(4)(3) is equal to the number of digital signals 1014(1)(1) to 1014(4)(3). Process 1100 also includes adjusting the resistance of the corresponding DAC stage 1004(1) to 1004(4) so that the parallel combination of the resistance of the adjustment circuit 1030 and the resistance R_NEXT of the next DAC stage 1004(2) to 1004(4) is maintained at a desired resistance level (block 1108). Process 1100 also includes receiving an analog input signal VIN (block 1110).

[0076] Continue to refer Figure 11The process 1100 further includes generating one or more digital signals 1014(1)(1) to 1014(4)(3) in a plurality of parallel comparator stages 1008(1) to 1008(1) (block 1112). Each digital signal 1014(1)(1) to 1014(4)(3) is generated by comparing the analog input signal VIN with a corresponding DAC analog signal 1006(1)(1) to 1006(4)(3). Further, each digital signal 1014(1)(1) to 1014(4)(3) has a logic high "1" value if the voltage of the analog input signal VIN is greater than the voltage of the corresponding DAC analog signal 1006(1)(1) to 1006(4)(3), and each digital signal 1014(1)(1) to 1014(4)(3) has a logic low "0" value if the voltage of the analog input signal VIN is less than the voltage of the corresponding DAC analog signal 1006(1)(1) to 1006(4)(3). Process 1100 also includes generating one or more digital bits DG(1) to DG(8) corresponding to each parallel comparator stage 1008(1) to 1008(4) based on the one or more digital signals 1014(1)(1) to 1014(4)(3) of the corresponding parallel comparator stage 1008(1) to 1008(4) (block 1114). One or more digital bits DG(1) to DG(8) collectively form a digital output signal DOUT, which is a digital representation of the analog input signal VIN.

[0077] Apart from Figure 10A In addition to the multi-bit parallel SA flash ADC circuit 1000, other types of flash ADC circuits can also use multi-output DAC circuits. In this regard, Figure 12An exemplary non-parallel SA flash ADC circuit 1200 employing a multi-output DAC circuit 1202 (i.e., generating one digital bit DG at a time) is illustrated. In this aspect, the multi-output DAC circuit 1202 includes DAC stages 1204(1) to 1204(8), wherein each DAC stage is configured to generate a corresponding DAC analog signal 1206(1) to 1206(8). Each DAC stage 1204(1) to 1204(8) generates a corresponding DAC analog signal 1206(1) to 1206(8) by receiving a corresponding top voltage VTOP(1) to VTOP(8), a corresponding bottom voltage VBOT(1) to VBOT(8), and a corresponding digital signal 1208(1) to 1208(8) from a corresponding comparison circuit 1210(1) to 1210(8). In this example, each digital signal 1208(1) to 1208(8) is output from a corresponding buffer 1212(1) to 1212(8) that receives a corresponding digital bit DG(1) to DG(8) generated by each comparison circuit 1210(1) to 1210(8) that compares the corresponding DAC analog signal 1206(1) to 1206(8) with the analog input signal VIN. The buffer 1212(1) to 1212(8) provides gain between the digital bit DG(1) to DG(8) generated by the comparison circuit 1210(1) to 1210(8) and the input node S0 of the corresponding DAC stage 1204(1) to 1204(8). Additionally, in this aspect, the multi-output DAC circuit 1202 includes a resistor 1214 corresponding to the DAC stage 1204(1).

[0078] Figure 13A The diagram shows that Figure 12 An exemplary resistor rotator circuit 1300A is employed in each DAC stage 1204(1) to 1204(8) of the multi-output DAC circuit 1202. The resistor rotator circuit 1300A is configured to receive a top voltage VTOP on a top voltage input node TOP, a bottom voltage VBOT on a bottom voltage input node BOT, and a corresponding digital signal 1208 on an input node S0. The resistor rotator circuit 1300A includes an inverter 1302A configured to receive the digital signal 1208 and generate a corresponding inverted digital signal 1208'. The resistor rotator circuit 1300A also includes switches 1304A(1) to 1304A(6) and resistors 1306A(1), 1306A(2). Based on Figure 13A As shown in the illustrated design, the resistor rotator circuit 1300A is configured to generate Figure 12 The corresponding DAC analog signal 1206. In particular, based on Figure 13ADue to the connection of the components shown, the resistor rotator circuit 1300A is referred to as a "short-circuit" type resistor rotator circuit, wherein the DAC analog signal 1206 is equal to the average of the top voltage VTOP and the bottom voltage VBOT. An adjustment circuit 1308A having a resistor RADJ is also employed. Additionally, the digital signal 1208 determines whether the effective resistance between RA and RB is placed at the bottom or top of the voltage divider provided by the two (2) resistors 1306A(1), 1306A(2) coupled to the respective terminals TOP and BOT.

[0079] Figure 13B The diagram shows that Figure 12 Another exemplary resistor rotator circuit 1300B employed in each DAC stage 1204(1) to 1204(8) of the multi-output DAC circuit 1202 of FIG. The resistor rotator circuit 1300B is configured to receive a top voltage VTOP on a top voltage input node TOP, a bottom voltage VBOT on a bottom voltage input node BOT, and a corresponding digital signal 1208 on an input node S0. The resistor rotator circuit 1300B includes an inverter 1302B configured to receive the digital signal 1208 and generate a corresponding inverted digital signal 1208'. The resistor rotator circuit 1300B also includes switches 1304B(1) to 1304B(8) and a resistor 1306B. Based on Figure 13B As shown in the design, the resistor rotator circuit 1300B is configured to generate Figure 12 The corresponding DAC analog signal 1206. In particular, based on Figure 13B Due to the connection of the components shown, the resistor rotator circuit 1300B is referred to as a "replacement" type resistor rotator circuit, wherein the DAC analog signal 1206 is equal to the average of the top voltage VTOP and the bottom voltage VBOT. An adjustment circuit 1308B having a resistor RADJ is also employed. Additionally, the digital signal 1208 determines whether the effective resistance between RA and RB is placed at the bottom or top of the voltage divider provided by the two (2) resistors 1306A(1), 1306A(2) coupled to the respective terminals TOP and BOT.

[0080] Figure 14A Another exemplary non-parallel SA flash ADC circuit 1400A employing another type of multi-output DAC circuit 1402A is illustrated. The non-parallel SA flash ADC circuit 1400A is configured to generate digital bits DG(1) to DG(4) and includes comparator circuits 1404A(1) to 1404A(4) and buffers 1406A(1) to 1406A(4) that are coupled to the DAC circuit 1402A. Figure 121408A(1) to 1412A(3), switches 1414A(1) to 1414A(14), and AND gates 1416A(1) to 1416A(12). As shown in FIG. Figure 14A The use of the elements indicated above results in the generation of DAC analog signals 1408A(1) to 1408A(4) depending on which switches 1414A(1) to 1414A(14) are activated / deactivated by the value of the select signal provided to the non-parallel SA flash ADC circuit 1400A. In other words, the DAC analog signals 1408A(1) to 1408A(4) are generated by dividing the top voltage VTOP and the bottom voltage VBOT and selecting the corresponding divided voltages depending on which switches 1414A(1) to 1414A(14) are activated. It is worth noting that the multi-output DAC circuit 1402A can also be used in a multi-bit parallel SA flash ADC circuit.

[0081] Figure 14B Another exemplary non-parallel SA flash ADC circuit 1400B employing another type of multi-output DAC circuit 1402B is illustrated. The non-parallel SA flash ADC circuit 1400B is configured to generate digital bits DG(1) to DG(4) and includes comparator circuits 1404B(1) to 1404B(4) and buffers 1406B(1) to 1406B(4) that are coupled to the DAC circuit 1402B. Figure 12 The non-parallel SA flash ADC circuit 1200 in FIG. However, the multi-output DAC circuit 1402B is designed as a voltage divider configured to generate DAC analog signals 1408B(1) to 1408B(4) by selecting specific voltages. More specifically, the multi-output DAC circuit 1402B employs resistors 1410B(1) to 1410B(16), inverters 1412B(1) to 1412B(3), and switches 1414B(1) to 1414B(22). Figure 14BThe use of the elements indicated above results in the generation of DAC analog signals 1408B(1) to 1408B(4) depending on which switches 1414B(1) to 1414B(22) are activated / deactivated by the value of the select signal provided to the multi-output DAC circuit 1402B. In other words, the DAC analog signals 1408B(1) to 1408B(4) are generated by dividing the top voltage VTOP and the bottom voltage VBOT and selecting the corresponding divided voltages according to the select signals SEL(1) to SEL(22). It is worth noting that the multi-output DAC circuit 1402B can also be used in a multi-bit parallel SA flash ADC circuit.

[0082] Figure 15An exemplary three (3) column single output DAC circuit 1500 (also referred to as "single output DAC circuit 1500") is illustrated. In particular, single output DAC circuit 1500 is a nine (9) bit triple column direct-connect resistor string DAC circuit that includes columns 1502(1) to 1502(3). Column 1502(1) includes resistors 1504(1) to 1504(16), inner switches 1506(1) to 1506(8), and outer switches 1508(1) to 1508(8), wherein the inner switches 1506(1) to 1506(8) and the outer switches 1508(1) to 1508(8) are activated or deactivated in corresponding pairs by logic circuitry. For example, inner switches 1506(8) and outer switches 1508(1) are activated or deactivated in pairs, as are the other inner switches 1506(1) and outer switches 1508(8) by input switches. Column 1502(1) is configured to receive a top voltage VTOP(1) and a bottom voltage VBOT(1). Based on which inner switches 1506(1) to 1506(8) and outer switches 1508(1) to 1508(8) are activated or deactivated according to a select signal (not shown), column 1502(1) generates a top voltage VTOP(2) and a bottom voltage VBOT(2) that are provided to column 1502(2). Column 1502(2) includes resistors 1504(17) to 1504(32), inner switches 1506(9) to 1506(16), and outer switches 1508(9) to 1508(16). Further, based on which inner switches 1506(9) to 1506(16) and outer switches 1508(9) to 1508(16) are activated or deactivated by a select signal (not shown), column 1502(2) is configured to generate a top voltage VTOP(3) and a bottom voltage VBOT(3) that are provided to column 1502(3). Column 1502(3) includes resistors 1504(33) to 1504(40) and switches 1510(1) to 1510(8). Based on which switches 1510(1) to 1510(8) are activated or deactivated by a select signal (not shown), column 1502(3) is configured to generate a DAC analog signal 1512 as an output of single output DAC circuit 1500.

[0083] Figure 16 An exemplary three (3) column multi-output DAC circuit 1600 (also referred to as "multi-output DAC circuit 1600") is illustrated. In particular, the multi-output DAC circuit 1600 is a nine (9) bit triple column direct-connected resistor string DAC circuit. The multi-output DAC circuit 1600 includes columns 1602(1) to 1602(3). The columns 1602(1) to 1602(3) include Figure 15 Columns 1502(1) to 150(3) have certain elements in common, which are Figure 15 and Figure 16Common element symbols are used in the present invention, so they will not be described again in this article. Figure 15 In addition to the components described, column 1602(1) includes switches 1604(1) and 1604(2), column 1602(2) includes switches 1604(3) and 1604(4), and column 1602(3) includes switches 1604(5) and 1604(6). Switches 1604(1) to 1604(6) are used to position columns 1602(1) to 1602(3) to appropriate positions for operation of the corresponding multi-bit parallel SAR ADC circuit. Additionally, column 1602(3) is configured to generate a plurality of DAC analog signals 1606(1) to 1606(7) as outputs of the multi-output DAC circuit 1600. It should be noted that because the seven (7) DAC analog signals 1606(1) to 1606(7) are all available simultaneously, the multi-output DAC circuit 1600 only requires six (6) bits for controlling the switches 1604(1) to 1604(6).

[0084] Figure 17 An exemplary resistor rotator circuit 1700 employing an "insertion" approach that can be employed in each DAC stage of a multi-output DAC circuit is illustrated. As used in this context, insertion means that equivalent resistors are inserted into appropriate locations in the resistor rotator circuit 1700. The resistor rotator circuit 1700 includes input ports RTOP, RBOT, output ports RA, RB, and a decoding circuit 1702 configured to receive digital bits DG(1), DG(2) and provide digital decoded bits DS(1) to DS(4). The resistor rotator circuit 1700 also includes inverters 1704(1) to 1704(4), resistors 1706(1) to 1706(3), and switches 1708(1) to 1708(12). If the resistor rotator circuit 1700 is used in a multi-output DAC circuit, additional logic circuits and switches may be included to generate the DAC analog output(s). Additionally, in this aspect, adjustable resistors 1710 ( 1 ), 1710 ( 2 ) are illustrated having respective resistances RADJ1 , RADJ2 .

[0085] Figure 18is a circuit diagram of an exemplary resistor rotator circuit 1800 that employs a "short-circuit" approach that may be employed in each DAC stage of a multi-output DAC circuit. In particular, the resistor rotator circuit 1800 includes a decoding circuit 1802 configured to receive digital bits DG(1), DG(2) and provide digital decoded bits DS(1) to DS(4). The resistor rotator circuit 1800 also includes resistors 1804(1) to 1804(6) and switches 1806(1) to 1806(8). The resistor rotator circuit 1800 also includes input ports RTOP, RBOT and output ports RA, RB. If the resistor rotator circuit 1800 is used in a multi-output DAC circuit, additional logic circuitry and switches may be included to generate the output(s). Additionally, in this aspect, adjustable resistors 1808(1), 1808(2) having respective resistances RADJ1, RADJ2 are illustrated.

[0086] Figure 191 is a circuit diagram of an exemplary multi-output DAC circuit 1900 employing a resistor rotator circuit 1902(1) to 1902(4) in each DAC stage 1904(1) to 1904(4), wherein each resistor rotator circuit 1902(1) to 1902(4) uses a "reshuffle" approach. The multi-output DAC circuit 1900 includes input ports RTOP, RBOT, input ports D4 to D1, and output ports VDIV2, VDIV4, VDIV8, and VDIV16. Each resistor rotator circuit 1902(1) to 1902(4) employs a corresponding resistor 1906(1) to 1906(4) and a corresponding switch 1908(1)(1) to 1908(4)(8). In this aspect, the resistor 1906(1) of the DAC stage 1904(1) has a resistance of eight (8) kΩ. The total equivalent resistance after DAC stage 1904(1) is also eight (8) kΩ, which can be inserted above or below resistor 1906(1). In this example, resistor 1906(2) of DAC stage 1904(2) has a resistance of four (4) kΩ, and the total equivalent resistance after DAC stage 1904(2) is also four (4) kΩ, which can be inserted above or below resistor 1906(2). In this example, DAC stages 1904(3), 1904(4) follow a similar resistance pattern, with resistor 1906(3) having a resistance of two (2) kΩ and resistor 1906(4) having a resistance of one (1) kΩ. In this manner, resistors 1904(1) to 1906(4) are binary weighted relative to each other. The DAC stage 1904(4) is terminated by a simple voltage divider 1910 employing resistors 1912(1), 1912(2). The resistor rotator circuit 1902(4) also includes a resistor 1914. Resistor 1914 can be a single resistor or the equivalent resistance of the voltage divider 1910, depending on the application. A single output is taken from the center of the voltage divider 1910. Further, digital selection bits D4 to D1 cause the binary weighted resistors 1906(1) to 1906(4) to be rearranged to generate the desired voltage for the single output DAC analog signal 1916. An alternative to resistor 1904(4) is to replace the voltage divider 1910 across the terminals connecting resistor 1904(4) to the previous resistor rotator stage 1904(3).

[0087] Figure 20A and Figure 20BAnother exemplary single-output DAC circuit 2000A is illustrated, which is also referred to as a ten (10)-bit single-output DAC circuit 2000A. In this aspect, the single-output DAC circuit 2000A includes DAC stages 2002A(1) to 2002(10), wherein DAC stage 2002A(1) is a two (2)-bit resistor rotator circuit, and DAC stages 2002A(2) to 2002A(9) are intercalation-type one (1)-bit resistor rotator circuits. DAC stage 2002A(1) employs a decoding circuit 2004A, inverters 2006A(1) to 2006A(4), resistors 2008A(1) to 2008A(3), and switches 2010A(1) to 2010A(12). Additionally, each of the DAC stages 2002A(2) to 2002A(9) employs inverters 2012A(2) to 2012A(9), resistors 2014A(2) to 2014A(9), switches 2016A(2)(1) to 2016A(9)(6), and adjustable resistors 2017(2) to 2017(9) having respective resistances RADJ2 to RADJ9. DAC stage 2002A(10) includes a voltage divider 2018A employing resistors 2020A(1), 2020A(2) and is configured to provide a DAC analog signal 2022A.

[0088] Figure 20C Another exemplary single output DAC circuit 2000B is illustrated, which is also referred to as a ten (10) bit single output DAC circuit 2000B. In this aspect, the single output DAC circuit 2000B includes DAC stages 2002B(1) to 2002B(6), wherein each DAC stage 2002B(1) to 2002B(6) is a reference Figure 20A and Figure 20B A two (2) bit resistor rotator circuit similar in aspect to that described, wherein each DAC stage comprises a respective decoding circuit 2004B(1) to 2004B(5). The elements of DAC stage 2002B(1) are similar to Figure 20A The elements of DAC stage 2002A(1) are similar but are not renumbered herein for simplicity. For further simplicity, the elements of DAC stages 2002B(2) through 2002B(5) are not illustrated. Additionally, DAC stage 2002B(6) includes a voltage divider 2018B using resistors 2008B(1), 2008B(2). Figure 20C The alternatives are Figure 20DAnother exemplary single output DAC circuit 2000C is shown, which is also referred to as a ten (10) bit single output DAC circuit 2000C. The single output DAC circuit 2000C includes DAC stages 2002C(1) to 2002C(3) and decoding circuits 2004C(1) to 2004C(3), which are respectively connected to Figure 20A DAC stages 2002B(1) to 2002B(3) and decoding circuits 2004B(1) to 2004B(3) are identical. However, DAC stages 2002B(4) to 2002B(6) are replaced by DAC stage 2002C(4), where DAC stage 2002C(4) is a single four (4) bit voltage divider using decoding circuit 2004C(4), resistors 2008C(1) to 2008C(17), and switches 2010C(1) to 2010C(16), the decoding circuit 2004C(4) being configured to generate signals G1-G16. Some of the modularity (particularly, DAC stages 2002B(1) to 2002B(5) and DAC stages 2002C(1) to 2002C(3)) provides the designer with the ability to use Figure 20B 、 Figure 20C This is a common simplified layout option for the single-output DAC circuits 2000B and 2000C.

[0089] Figure 21An exemplary multi-output DAC circuit 2100 that can be employed in a multi-bit parallel SAR ADC circuit is illustrated. The multi-output DAC circuit 2100 employs DAC stages 2102(1) to 2102(4), switches 2104(1) to 2104(8), a voltage divider circuit 2106 for the DAC stages 2102(4) employing resistors 2108(1) to 2108(8), and adjustment circuits 2110(1) to 2110(3) corresponding to the DAC stages 2102(1) to 2102(3). In particular, each adjustment circuit 2110(1) to 2110(3) has a resistor RADJ(1) to RADJ(3) configured to adjust the resistance of the corresponding DAC stage 2102(1) to 2102(3) so that the parallel combination of the resistance of the adjustment circuit 2110(1) to 2110(3) and the resistance of the next DAC stage 2102(2) to 2102(4) is maintained at an ideal resistance level. Further, each DAC stage 2102(1) to 2102(4) is configured to receive a corresponding top voltage VTOP(1) to VTOP(4), a corresponding bottom voltage VBOT(1) to VBOT(4), a corresponding enable signal EN(1) to EN(3), and three (3) corresponding digital bits DG(3) to DG(11). Each DAC stage 2102 ( 1 ) to 2102 ( 4 ) is also configured to divide the voltage range of each corresponding top voltage VTOP( 1 ) to VTOP( 4 ) and each bottom voltage VBOT( 1 ) to VBOT( 4 ).

[0090] Continue to refer Figure 21 Based on the values of the DAC select signals DG(11) to DG(3), certain combinations of the top voltages VTOP(1) to VTOP(4) and the bottom voltages VBOT(1) to VBOT(4) are provided to the input nodes 2112(1), 2112(2) of the voltage divider circuit 2106. In this aspect, the resistors 2108(1) to 2108(8) each have an equal resistance (e.g., two (2) kilo-ohms (kΩ)) such that the voltage divider circuit 2106 generates the DAC analog signals 2114(1) to 2114(7) as equal divisions (e.g., divisions of the corresponding voltage ranges) of the voltage provided to the voltage divider circuit 2106.

[0091] Figure 22A and Figure 22BAn exemplary three (3)-bit parallel twelve (12)-bit SAR ADC circuit 2200 employing a multi-output DAC circuit 2202 and a SA flash-based comparison circuit 2204 is illustrated. The three (3)-bit parallel twelve (12)-bit SAR ADC circuit 2200 is configured to receive a clock signal CLK, a signal of a logic "1" (i.e., high) value, a start signal START, and a reference voltage VREF. The three (3)-bit parallel twelve (12)-bit SAR ADC circuit 2200 includes SAR controller circuits 2206 (1) to 2206 (3), wherein each SAR controller circuit includes four (4) SAR register circuits 2208 (1) (1) to 2208 (3) (4). In this manner, the SAR register circuits 2208 (1) (1) to 2208 (1) (4) correspond to digital bits DG (1), DG (4), DG (7), and DG (10). SAR register circuits 2208(2)(1) to 2208(2)(4) correspond to digital bits DG(2), DG(5), DG(8), and DG(11), and SAR register circuits 2208(3)(1) to 2208(3)(4) correspond to digital bits DG(3), DG(6), DG(9), and DG(12). SAR register circuit 2211 is also included, and is configured to generate a completion signal DONE.

[0092] Continue to refer Figure 22A and Figure 22B, the multi-output DAC circuit 2202 includes a selection circuit 2212 that employs multiplexer circuits 2214(1) to 2214(12) for processing digital signals. The multi-output DAC circuit 2202 also includes DAC stages 2216(1) to 2216(12). In this manner, the number of multiplexer circuits 2214(1) to 2214(12) and the number of DAC stages 2216(1) to 2216(12) are equal to the number of digital bits DG(1) to DG(12) in the digital output signal DOUT (not shown). Further, each multiplexer circuit 2214(1) to 2214(12) is configured to receive a corresponding digital bit DG(1) to DG(12). Multiplexer circuits 2214(1), 2214(4), 2214(7), and 2214(10) are configured to also receive comparator signal 2218(1) from comparison circuit 2220(1), and multiplexer circuits 2214(2), 2214(5), 2214(8), and 2214(11) are configured to also receive comparator signal 2218(2) from comparison circuit 2220(2). Multiplexer circuits 2214(3), 2214(6), 2214(9), and 2214(12) are configured to also receive comparator signal 2218(3) from comparison circuit 2220(3). Multiplexer circuits 2214(1) to 2214(3) are configured to receive a DAC select signal 2210(4), and multiplexer circuits 2214(4) to 2214(6) are configured to receive a DAC select signal 2210(3). Multiplexer circuits 2214(7) to 2214(9) are configured to receive a DAC select signal 2210(2), and multiplexer circuits 2214(10) to 2214(12) are configured to receive a DAC select signal 2210(1). The DAC select signals 2210(1) to 2210(4) select between input values of corresponding multiplexer circuits 2214(1) to 2214(12), such that the multiplexer circuits 2214(1) to 2214(12) provide corresponding resistor select signals 2222(1) to 2222(12).

[0093] Continue to refer Figure 22A and Figure 22B And specific reference Figure 22B, DAC stages 2216(1) to 2216(12) are configured to receive corresponding resistor selection signals 2222(1) to 2222(12) on corresponding input nodes S0. Further, DAC stages 2216(1) to 2216(3) are configured to receive DAC selection signal 2210(4), and DAC stages 2216(4) to 2216(6) are configured to receive DAC selection signal 2210(3) on corresponding selection input nodes SEL. DAC stages 2216(7) to 2216(9) are configured to receive DAC selection signal 2210(2), and DAC stages 2216(10) to 2216(12) are configured to receive DAC selection signal 2210(1) on corresponding selection input nodes SEL. As shown in FIG. Figure 23 As discussed in more detail, each DAC stage 2216(1) to 2216(12) is configured to receive a top voltage VTOP and a bottom voltage VBOT at respective top input nodes TOP and bottom input nodes BOT, and to provide respective output voltages VTO, VBO at respective voltage output nodes RA, RB. As a result, DAC stages 2216(1), 2216(4), 2216(7), and 2216(10) provide a DAC analog signal 2224(1), DAC stages 2216(2), 2216(5), 2216(8), and 2216(11) provide a DAC analog signal 2224(2), and DAC stages 2216(3), 2216(6), 2216(9), and 2216(12) provide a DAC analog signal 2224(3). Furthermore, the DAC analog signals 2224(1) to 2224(3) are provided to corresponding comparison circuits 2220(1) to 2220(3), wherein the comparison circuits 2220(1) to 2220(3) also receive the analog input signal VIN. It is important to note that the SA flash-based comparison circuit 2204 includes a certain number of comparison circuits 2220(1) to 2220(3), which is equal to the number of SAR controller circuits 2206(1) to 2206(3).

[0094] Continue to refer Figure 22A and Figure 22B, each comparison circuit 2220(1) to 2220(3) is configured to generate a corresponding comparator signal 2218(1) to 2218(3), wherein each comparator signal 2218(1) to 2218(3) is a corresponding digital bit DG(1) to DG(12) of a corresponding period of the clock signal CLK. In particular, if the voltage of the analog input signal VIN is greater than the voltage of the corresponding DAC analog signal 2224(1) to 2224(3), each comparator signal 2218(1) to 2218(3) has a logic high "1" value. Alternatively, if the voltage of the analog input signal VIN is less than the voltage of the corresponding DAC analog signal 2224(1) to 2224(3), each comparator signal 2218(1) to 2218(3) has a logic low "0" value.

[0095] Figure 23 It can be used for Figure 22A and Figure 22B FIG2 is a circuit diagram of an exemplary resistor rotator circuit 2300 for each DAC stage 2216(1) to 2216(12) of a multi-output DAC circuit 2202. In this aspect, the resistor rotator circuit 2300 is configured to receive a top voltage VTOP on a top voltage input node TOP and a bottom voltage VBOT on a bottom voltage input node BOT. Additionally, the resistor rotator circuit 2300 is configured to receive corresponding resistor select signals 2222(1) to 2222(12) on an input node SO and corresponding DAC select signals 2210(1) to 2210(4) on a select input node SEL. In this manner, using the inverter 2302, the resistor 2304, the switches 2306(1) to 2306(9), and the resistor 2308 having a resistance RADJ, the corresponding DAC select signals 2210(1) to 2210(4) and the resistor select signals 2222(1) to 2222(12) enable the resistor rotator circuit 2300 to provide corresponding top voltage VTOP and bottom voltage VBOT on the output nodes RA and RB, respectively. Additionally, the output node DAC provides the corresponding VTOP and VBOT. Figure 22A and Figure 22B The corresponding DAC analog signals 2224(1) to 2224(3) are shown.

[0096] Figure 24is a circuit diagram of another exemplary resistor rotator circuit 2400 that employs a "short circuit" approach that can be employed in each DAC stage of a multi-output DAC circuit. The resistor rotator circuit 2400 is configured to receive a top voltage VTOP on a top voltage input node TOP and a bottom voltage VBOT on a bottom voltage input node BOT. The resistor rotator circuit 2400 also includes a decoder circuit 2402 that is configured to receive digital bits DG(1) to DG(3) on input nodes S0, S1, S2 and generate decoded signals DS(1) to DS(8) based on the digital bits DG(1) to DG(3). Each decoded signal DS(1) to DS(8) is provided to a corresponding AND gate 2406(1) to 2406(8). Each AND gate 2406(1) to 2406(8) also receives one of the enable signals 2408 via an enable input node EN and generates a corresponding resistor select signal 2410(1) to 2410(8).

[0097] Continue to refer Figure 24 , the resistor rotator circuit 2400 also includes switches 2412(1) to 2412(16), wherein a logic high "1" value closes the switches 2412(1) to 2412(16), and a logic low "0" value opens the switches 2412(1) to 2412(16). The switches 2412(1) to 2412(16) are used in conjunction with resistors 2414(1) to 2414(14) to generate a top output voltage VTO and a bottom output voltage VBO at respective voltage output nodes RA, RB. An adjustment circuit 2416 having a resistor RADJ is also included. In this manner, the above configuration causes the resistor rotator circuit 2400 to generate corresponding top output voltages VTO and bottom output voltages VBO depending on which of the switches 2412(1) to 2412(16) are opened or closed based on the digital bits DG(1) to DG(3).

[0098] A DAC circuit employing a resistor rotator circuit configured according to various aspects disclosed herein and included in an ADC circuit can be provided or integrated in any processor-based device. Examples include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet computer, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyeglasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter.

[0099] In this regard, Figure 25 The diagram shows that the Figure 1 The DAC circuit 100 shown in FIG. Figure 2 , Figures 4 to 10 and Figures 12 to 24 25. An example of a processor-based system 2500 is provided in accordance with various aspects of the present invention as illustrated in FIG. In this example, the processor-based system 2500 includes one or more central processing units (CPUs) 2502, each of which includes one or more processors 2504. The CPU(s) 2502 may have a cache memory 2506 coupled to the processor(s) 2504 for quickly accessing temporarily stored data. The CPU(s) 2502 are coupled to a system bus 2508 and may couple the master and slave devices included in the processor-based system 2500 to one another. As is well known, the CPU(s) 2502 communicate with these other devices by exchanging address, control, and data information on the system bus 2508. For example, the CPU(s) 2502 may communicate a bus transaction request to a memory controller 2510, which is an example of a slave device. Although Figure 25 Not shown in the figure, but multiple system buses 2508 may be provided, with each system bus 2508 forming a different configuration.

[0100] Other master and slave devices may be connected to the system bus 2508. Figure 25As shown, these devices may include, for example, a memory system 2512, one or more input devices 2514, one or more output devices 2516, one or more network interface devices 2518, and one or more display controllers 2520. The input device(s) 2514 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. The output device(s) 2516 may include any type of output device, including, but not limited to, audio, video, other visual indicators, and the like. The network interface device(s) 2518 may be any device configured to allow data to be exchanged with a network 2522. The network 2522 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) 2518 may be configured to support any desired type of communication protocol. The memory system 2512 may include one or more memory units 2524(0) to 2524(P).

[0101] The CPU(s) 2502 may also be configured to access the display controller(s) 2520 via the system bus 2508 to control information sent to the one or more displays 2526. The display controller(s) 2520 sends information to the display(s) 2526 for display via one or more video processors 2528, which process the information to be displayed into a format suitable for the display(s) 2526. The display(s) 2526 may include any type of display including, but not limited to, cathode ray tubes (CRTs), liquid crystal displays (LCDs), plasma displays, light emitting diode (LED) displays, and the like.

[0102] Figure 26 An exemplary wireless communication device 2600 is illustrated that includes radio frequency (RF) components formed in an integrated circuit (IC) 2602, where the RF components may include a Figure 1 The components of the DAC circuit 100 and Figure 2 , Figures 4 to 10 and Figures 12 to 24 In this regard, the wireless communication device 2600 may be provided in the IC 2602. The wireless communication device 2600 may include or be provided in, for example, any of the devices referenced above. Figure 26As shown, wireless communication device 2600 includes a transceiver 2604 and a data processor 2606. Data processor 2606 may include memory for storing data and program codes. Transceiver 2604 includes a transmitter 2608 and a receiver 2610 that support bidirectional communication. In general, wireless communication device 2600 may include any number of transmitters 2608 and / or receivers 2610 for any number of communication systems and frequency bands. All or a portion of transceiver 2604 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0103] The transmitter 2608 or the receiver 2610 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, for the receiver 2610, the signal is frequency converted between RF and baseband in many stages, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is frequency converted between RF and baseband in one stage. The superheterodyne architecture and the direct conversion architecture may use different circuit blocks and / or have different requirements. Figure 26 In the wireless communication device 2600 in FIG. 2 , the transmitter 2608 and the receiver 2610 are implemented using a direct conversion architecture.

[0104] In the transmit path, the data processor 2606 processes the data to be transmitted and provides an I analog output signal and a Q analog output signal to the transmitter 2608. In the exemplary wireless communication device 2600, the data processor 2606 includes digital-to-analog converters (DACs) 2612(1), 2612(2) for converting the digital signals generated by the data processor 2606 into I analog output signals and Q analog output signals, such as I output current and Q output current, for further processing.

[0105] Within the transmitter 2608, low-pass filters 2614(1) and 2614(2) filter the I analog output signal and the Q analog output signal, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 2616(1) and 2616(2) amplify the signals from the low-pass filters 2614(1) and 2614(2), respectively, and provide an I baseband signal and a Q baseband signal. An up-converter 2618 up-converts the I baseband signal and the Q baseband signal using the I transmit (TX) local oscillator (LO) signal and the Q transmit (TX) local oscillator (LO) signal via mixers 2620(1) and 2620(2) from a TX LO signal generator 2622 to provide an up-converted signal 2624. A filter 2626 filters the up-converted signal 2624 to remove undesired signals caused by the frequency up-conversion and noise in the receive band. A power amplifier (PA) 2628 amplifies the upconverted signal 2624 from the filter 2626 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 2630 and transmitted via an antenna 2632.

[0106] In the receive path, antenna 2632 receives the signal transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 2630 and provided to a low noise amplifier (LNA) 2634. The duplexer or switch 2630 is designed to operate using a specific receive (RX) to TX duplexer frequency spacing so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 2634 and filtered by filter 2636 to obtain the desired RF input signal. Down-conversion mixers 2638 (1), 2638 (2) mix the output of filter 2636 with the I RX LO signal and the Q RX LO signal (i.e., LO_I and LO_Q) from the RX LO signal generator 2640 to generate an I baseband signal and a Q baseband signal. The I baseband signal and the Q baseband signal are amplified by amplifiers (AMPs) 2642 (1) and 2642 (2) and filtered by low-pass filters 2644 (1) and 2644 (2) to obtain I analog input signals and Q analog input signals, which are provided to the data processor 2606. In this example, the data processor 2606 includes ADCs 2646 (1) and 2646 (2) for converting the analog input signals into digital signals for further processing by the data processor 2606.

[0107] exist Figure 26In wireless communication device 2600, TX LO signal generator 2622 generates I TX LO signal and Q TX LO signal for frequency upconversion, while RX LO signal generator 2640 generates I RX LO signal and Q RX LO signal for frequency downconversion. Each LO signal is a periodic signal having a specific fundamental frequency. TX phase-locked loop (PLL) circuit 2648 receives timing information from data processor 2606 and generates control signals for adjusting the frequency and / or phase of the TX LO signal from TX LO signal generator 2622. Similarly, RX PLL circuit 2650 receives timing information from data processor 2606 and generates control signals for adjusting the frequency and / or phase of the RX LO signal from RX LO signal generator 2640.

[0108] Those skilled in the art will also appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the various aspects disclosed herein can be implemented as instructions stored in electronic hardware, memory, or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. The master and slave devices described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be a memory of any type and size and can be configured to store any type of information desired. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally according to their functionality. How to implement this functionality depends on the specific application, design choice, and / or design constraints imposed on the entire system. Technicians can implement the described functionality in a varying manner for each specific application, but such implementation decisions should not be interpreted as departing from the scope of this disclosure.

[0109] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0110] The various aspects disclosed herein may be embodied in hardware and in instructions stored in the hardware and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and can write information to the storage medium. In an alternative embodiment, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative embodiment, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0111] It should also be noted that the operational steps described in any of the exemplary aspects in this article are described to provide examples and discussion. The described operations can be performed in many different sequences in addition to the illustrated sequence. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that it will be apparent to those skilled in the art that the operational steps illustrated in the flow chart can be modified in many different ways. It should also be understood by those skilled in the art that information and signals can be represented using any of a variety of different techniques and technologies. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be cited throughout the above specification can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0112] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuit, comprising: A plurality of SAR controller circuits, wherein each SAR controller circuit of the plurality of SAR controller circuits comprises a number of SAR register circuits, wherein each SAR register circuit is configured to: receiving a clock signal; providing a digital signal in response to corresponding cycles of the clock signal; and In response to a corresponding next cycle of the clock signal: receiving a corresponding digital bit, wherein the digital bit is based on a comparison of an analog input signal and a corresponding digital-to-analog converter (DAC) analog signal; storing the digital bits; and providing said digital signal associated with said digital bits; A multi-output DAC circuit includes a plurality of DAC stages, wherein: Each DAC stage of the plurality of DAC stages is configured to: receiving a corresponding top voltage and a corresponding bottom voltage, wherein a voltage range of the corresponding top voltage and the corresponding bottom voltage is based on a reference voltage; and generating a number of DAC analog signals by dividing the voltage range generated by a voltage divider circuit based on the corresponding top voltage, the corresponding bottom voltage, and a resistance of the DAC stage; and each DAC stage of the plurality of DAC stages includes an adjustment circuit including an additional resistor configured to adjust the resistance of the corresponding DAC stage such that a parallel combination of the resistance of the adjustment circuit and a resistance of a next DAC stage is maintained at a desired resistance level; and The comparison circuit is configured as follows: receiving the number of DAC analog signals; receiving the analog input signal; and The digital bit corresponding to each SAR controller circuit in the plurality of SAR controller circuits is generated based on a comparison of each DAC analog signal with the analog input signal, wherein each generated digital bit collectively forms a digital output signal that is a digital representation of the analog input signal.

2. The multi-bit parallel SAR ADC circuit according to claim 1 , wherein the multi-output DAC circuit comprises a multi-output DAC circuit configured to: receiving the top voltage and the bottom voltage, wherein the voltage ranges of the top voltage and the bottom voltage are based on the reference voltage; and The number of DAC analog signals is generated based on the top voltage and the bottom voltage. 3 . The multi-bit parallel SAR ADC circuit of claim 2 , wherein a value of each of the number of DAC analog signals is a division of the voltage range.

4. The multi-bit parallel SAR ADC circuit of claim 2 , wherein the multi-output DAC circuit comprises a plurality of resistor rotator circuits configured to generate the number of DAC analog signals by generating a plurality of divisions of the voltage range.

5. The multi-bit parallel SAR ADC circuit according to claim 2 , wherein the comparison circuit comprises: a number of comparison circuits, wherein the number M of comparison circuits is equal to (2^i)-1, where i is the number of the plurality of SAR controller circuits, and wherein each comparison circuit is configured as: receiving the analog input signal and a corresponding DAC analog signal; and Generates a comparator signal where: If the analog input signal has a voltage greater than the corresponding DAC analog signal, the comparator signal has a logic high value; and If the analog input signal has a voltage less than the corresponding DAC analog signal, the comparator signal has a logic low value; and Thermometer-to-binary (TTB) circuit, configured as: receiving the comparator signal from each comparison circuit; and The digital bit corresponding to each SAR controller circuit is generated based on the comparator signal from each comparison circuit.

6. The multi-bit parallel SAR ADC circuit of claim 2 , wherein the comparison circuit comprises a number of comparison circuits, the number of comparison circuits being equal to the number of the plurality of SAR controller circuits, wherein each comparison circuit is configured to: receiving the analog input signal and a corresponding DAC analog signal; and Generates a comparator signal where: The comparator signal is the corresponding digital bit; If the analog input signal has a voltage greater than the corresponding DAC analog signal, the comparator signal has a logic high value; as well as If the analog input signal has a voltage less than the corresponding DAC analog signal, the comparator signal has a logic low value.

7. The multi-bit parallel SAR ADC circuit of claim 1, integrated into an integrated circuit (IC).

8. The multi-bit parallel SAR ADC circuit of claim 1 , integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a Session Initiation Protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle (UAV); and a multirotor helicopter.

9. A method for converting an analog input signal into a digital output signal, wherein a plurality of digital bits of the digital output signal are generated in parallel, the method comprising: Receive reference voltage; receiving a clock signal; providing a digital signal in response to corresponding cycles of the clock signal; receiving a corresponding digital bit in response to a corresponding next cycle of the clock signal, wherein the digital bit is based on a comparison of the analog input signal and a corresponding digital-to-analog converter (DAC) analog signal; storing the digital bit in response to the corresponding next cycle of the clock signal; providing the digital signal associated with the digital bit in response to the corresponding next cycle of the clock signal; receiving a corresponding top voltage and a corresponding bottom voltage, wherein a voltage range of the corresponding top voltage and the corresponding bottom voltage is based on the reference voltage; generating a number of DAC analog signals by dividing the voltage range generated by a voltage divider circuit based on the corresponding top voltage, the corresponding bottom voltage, and a resistance of a DAC stage, wherein the number of DAC analog signals is equal to the number of digital signals; adjusting the resistance of the corresponding DAC stage by an adjustment circuit included in the corresponding DAC stage, the adjustment circuit comprising an additional resistor configured such that a parallel combination of the resistance of the adjustment circuit and a resistance of a next DAC stage is maintained at a desired resistance level; as well as The corresponding digital bit is generated based on a comparison of each corresponding DAC analog signal with the analog input signal, wherein each generated digital bit collectively forms the digital output signal, the digital output signal being a digital representation of the analog input signal.

10. The method according to claim 9, further comprising: receiving the top voltage and the bottom voltage, wherein the voltage ranges of the top voltage and the bottom voltage are based on the reference voltage; as well as The number of DAC analog signals is generated based on the top voltage and the bottom voltage.

11. A multi-bit parallel successive approximation (SA) flash analog-to-digital converter (ADC) circuit, comprising: A multiple-output digital-to-analog converter (DAC) circuit includes a plurality of DAC stages, wherein: Each DAC stage in the plurality of DAC stages corresponds to a parallel comparator stage in the plurality of parallel comparator stages; Each DAC stage of the plurality of DAC stages is configured to: receiving a corresponding top voltage and a corresponding bottom voltage, wherein a voltage range of the corresponding top voltage and the corresponding bottom voltage is based on a reference voltage; and generating a number of DAC analog signals by division of the voltage range generated by a voltage divider circuit based on the corresponding top voltage, the corresponding bottom voltage, and a resistance of the DAC stage, wherein the number of DAC analog signals is equal to the number of comparator circuits in each corresponding parallel comparator stage; and each DAC stage of the plurality of DAC stages includes an adjustment circuit including an additional resistor configured to adjust the resistance of the corresponding DAC stage such that a parallel combination of the resistance of the adjustment circuit and a resistance of a next DAC stage is maintained at a desired resistance level; A system comparison circuit comprising the plurality of parallel comparator stages, wherein each of the plurality of parallel comparator stages comprises: A number of comparator circuits, where: The number of comparator circuits of each parallel comparator stage M=(2^i)-1, where i is the number of digital bits of the corresponding parallel comparator stage; and Each comparator circuit is configured as: Receive analog input signal; receiving a corresponding DAC analog signal; and Generates a digital signal where: If the analog input signal has a voltage greater than the corresponding DAC analog signal, Then the digital signal has a logic high value; and If the analog input signal has a voltage less than the corresponding DAC analog signal, the digital signal has a logic low value; and The system comparison circuit is configured to generate one or more digital bits corresponding to each parallel comparator stage based on each corresponding digital signal, wherein the one or more digital bits collectively form a digital output signal that is a digital representation of the analog input signal.

12. The multi-bit parallel SA flash ADC circuit of claim 11 , wherein the multi-output DAC circuit comprises a multi-output DAC circuit including the plurality of DAC stages, wherein: each DAC stage of the plurality of DAC stages corresponds to the parallel comparator stage of the plurality of parallel comparator stages; as well as Each DAC stage of the plurality of DAC stages is configured to: receiving the corresponding top voltage and the corresponding bottom voltage, wherein the voltage range of the corresponding top voltage and the corresponding bottom voltage is based on the reference voltage; as well as The number of DAC analog signals is generated based on the corresponding top voltage and the corresponding bottom voltage, wherein The number of DAC analog signals is equal to the number of comparator circuits in each corresponding parallel comparator stage.

13. The multi-bit parallel SA flash ADC circuit according to claim 12 , wherein the system comparison circuit further comprises a thermometer-to-binary (TTB) circuit, wherein the thermometer-to-binary (TTB) circuit is configured to: receiving the digital signal from the number of comparator circuits of each parallel comparator stage in the plurality of parallel comparator stages; and The one or more digital bits corresponding to each parallel comparator stage are generated, wherein the one or more digital bits collectively form the digital output signal, the digital output signal being the digital representation of the analog input signal. 14 . The multi-bit parallel SA flash ADC circuit of claim 12 , wherein the values of the number of DAC analog signals generated by each of the plurality of DAC stages are divisions of the voltage range.

15. The multi-bit parallel SA flash ADC circuit of claim 12, wherein each of the plurality of DAC stages comprises a resistor rotator circuit configured to generate the number of DAC analog signals by generating a division of the voltage range.

16. The multi-bit parallel SA flash ADC circuit of claim 15 , wherein the resistor rotator circuit of each DAC stage comprises: a top voltage input node configured to receive the corresponding top voltage; a bottom voltage input node configured to receive the corresponding bottom voltage; The decoder circuit is configured as follows: receiving the one or more digital bits of the corresponding parallel comparator stage; and generating a number of decoded signals based on the one or more digital bits, wherein the number of decoded signals M=(2^i), where i is the number of the one or more digital bits; A plurality of inverters, wherein each inverter is configured as: receiving a corresponding decoded signal; and generating a corresponding inverted decoding signal; Multiple switches, including: A number of switches are configured to receive the corresponding inverted decoded signals; and said number of switches being configured to receive said corresponding decoded signals; and a plurality of resistors alternately connected in series with the number of switches configured to receive the corresponding inverted decoded signals, wherein the plurality of resistors are arranged such that the plurality of resistors divide the voltage range into the number of DAC analog signals and into the top voltage and the bottom voltage to be provided to the next DAC stage.

17. The multi-bit parallel SA flash ADC circuit of claim 11, integrated into an integrated circuit (IC).

18. The multi-bit parallel SA flash ADC circuit of claim 11 , integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a Session Initiation Protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle (UAV); and a multirotor helicopter.

19. A method for converting an analog input signal into a digital output signal, wherein a plurality of digital bits of the digital output signal are determined in parallel, the method comprising: Receive reference voltage; receiving a corresponding top voltage and a corresponding bottom voltage, wherein a voltage range of the corresponding top voltage and the corresponding bottom voltage is based on the reference voltage; generating a number of digital-to-analog converter (DAC) analog signals based on the corresponding top voltage, the corresponding bottom voltage, and division of the voltage range generated by a voltage divider circuit, wherein the number of DAC analog signals is equal to the number of digital signals; adjusting the resistance of the corresponding DAC stage by an adjustment circuit included in the corresponding DAC stage, the adjustment circuit including an additional resistor configured such that a parallel combination of the resistance of the adjustment circuit and the resistance of the next DAC stage is maintained at a desired resistance level; receiving the analog input signal; One or more digital signals are generated in multiple parallel comparator stages, where: Each digital signal is generated by comparing the analog input signal with a corresponding DAC analog signal; each digital signal having a logic high value if the analog input signal has a voltage greater than the corresponding DAC analog signal; and each digital signal having a logic low value if the analog input signal has a voltage less than the corresponding DAC analog signal; and One or more digital bits corresponding to each parallel comparator stage are generated based on the one or more digital signals of the corresponding parallel comparator stage among the plurality of parallel comparator stages, wherein the one or more digital bits collectively form the digital output signal, which is a digital representation of the analog input signal.

20. The method according to claim 19, further comprising: receiving the corresponding top voltage and the corresponding bottom voltage, wherein the voltage range of the corresponding top voltage and the corresponding bottom voltage is based on the reference voltage; as well as The number of DAC analog signals is generated based on the corresponding top voltage and the corresponding bottom voltage, wherein the number of DAC analog signals is equal to the number of digital signals.

21. The method of claim 19, wherein the values of the number of DAC analog signals are divisions of the voltage range.

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