Random number generation device and method

Abstract

The present application discloses a random number generation device and method, which relates to the field of hardware encryption and is used to stably generate random numbers. The random number generation device includes: a first physical unclonable function PUF calculation module, including a first resistive random access memory RRAM device and a second RRAM device, the initial state of the first RRAM device and the second RRAM device is a high resistance state; an adaptive separation circuit, which is connected to the first RRAM device and the second RRAM device respectively, and is used to apply a write voltage to the first RRAM device and the second RRAM device, and when it is detected that the first RRAM device switches from a high resistance state to a low resistance state, stop applying the write voltage to the first RRAM device and the second RRAM device; a read circuit, which is connected to the first RRAM device and the second RRAM device respectively, and is used to obtain a first random number according to the difference between the low resistance state of the first RRAM device and the resistance state of the second RRAM device, wherein the resistance state of the second RRAM device is higher than the low resistance state of the first RRAM device.

Description

Technical Field

[0001] The present application relates to the field of hardware encryption, and in particular to a random number generation device and method. Background Art

[0002] Nowadays, Internet of Things (IoT) terminal nodes (such as wearable devices, household appliances and various sensors) are ubiquitous, and the information security of these terminal nodes has gradually attracted widespread attention, making it increasingly necessary to encrypt key information in practical applications.

[0003] The requirements for encryption key generation and storage are: ensuring that the key is unpredictable and has a unique random source; having a protected memory that can reliably store the key. PUF technology can meet both of the above requirements for encryption keys. However, obtaining an efficient and reliable PUF remains a challenge.

[0004] like Figure 1 As shown, a physical unclonable function (PUF) structure includes a first transistor 11, a second transistor 12, a third transistor 13 and a fourth transistor 14. The first transistor 11 and the third transistor 13 are gate transistors, and the PUF structure can be gated by the above-mentioned gate transistors when the word line (WL) is set. The second transistor 12 and the fourth transistor 14 are random source generation devices. When high voltage is applied, the rupture time of the gate oxide layer of these two transistors shows a certain difference, thereby generating a random number, which can be used as a bit of an encryption key. For example, the gate oxide layer rupture of the second transistor 12 corresponds to a random number with a value of "1", and the gate oxide layer rupture of the fourth transistor 14 corresponds to a random number with a value of "0".

[0005] After the PUF structure generates the encryption key, it cannot be reconfigured, that is, it is one-time programmable (OTP), and there is no way to ensure that only one of the second transistor 12 and the fourth transistor 14 has a broken gate oxide layer. For example, if the gate oxide stacks of both transistors are broken, random numbers other than "1" and "0" will appear, so the stability of the random number generation cannot be guaranteed. Summary of the invention

[0006] Embodiments of the present application provide a random number generation device and method for stably generating random numbers.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a random number generating device is provided, comprising: a first physical unclonable function PUF calculation module, comprising a first resistive random access memory RRAM device and a second RRAM device, wherein the initial states of the first RRAM device and the second RRAM device are high-resistance states. An adaptive separation circuit is connected to the first RRAM device and the second RRAM device, respectively, and is used to apply a write voltage to the first RRAM device and the second RRAM device, and when it is detected that the first RRAM device switches from the high-resistance state to the low-resistance state, the write voltage is stopped from being applied to the first RRAM device and the second RRAM device. A read circuit is connected to the first RRAM device and the second RRAM device, respectively, and is used to obtain a first random number according to the difference between the low-resistance state of the first RRAM device and the resistance state of the second RRAM device, wherein the resistance state of the second RRAM device is higher than the low-resistance state of the first RRAM device.

[0009] The random number generating device provided by the embodiment of the present application includes a PUF calculation module, an adaptive separation circuit and a reading circuit. The PUF calculation module includes two RRAM devices whose initial state is a high-resistance state. The adaptive separation circuit applies a write voltage to the two RRAM devices. If one of the RRAM devices changes from a high-resistance state to a low-resistance state, the write voltage is stopped from being applied to the two RRAM devices. Then the reading circuit obtains a random number based on the difference in resistance state between the two RRAM devices. Since there will not be a situation where the resistance state between the two RRAM devices is exactly the same, no random numbers other than "1" and "0" will be generated, so that random numbers can be generated stably.

[0010] In a possible implementation, the first PUF calculation module further includes: a first selector, connected to the first RRAM device and the second RRAM device, respectively, and used to control the current flowing through the first RRAM device and the second RRAM device. The function of the selector is to prevent current turbulence and avoid generating other unnecessary paths.

[0011] In a possible implementation, the first PUF calculation module further includes: a second selector connected to the first RRAM device and used to control the current flowing through the first RRAM device; and a third selector connected to the second RRAM device and used to control the current flowing through the second RRAM device. The function of the selector is to prevent current turbulence and avoid generating other unnecessary paths.

[0012] In a possible implementation, it further includes: a second PUF calculation module, including a third RRAM device and a fourth RRAM device; the read circuit is also connected to the third RRAM device and the fourth RRAM device respectively; wherein the read circuit is connected to the third RRAM device in the same manner as the read circuit is connected to the second RRAM device, and the read circuit is connected to the fourth RRAM device in the same manner as the read circuit is connected to the first RRAM device. By connecting the bit lines in adjacent PUF calculation modules in a mirrored manner, even if there is a system deviation, the setup time of the RRAM device on one side is shorter than the setup time of the RRAM device on the other side, but through the above-mentioned mirror connection method, the probability of the random numbers "0" and "1" read by the read circuit will not deviate from 1 / 2.

[0013] In a possible implementation, the adaptive separation circuit is connected to the third RRAM device and the fourth RRAM device, respectively, and the adaptive separation circuit is further used to: apply the write voltage to the third RRAM device and the fourth RRAM device, wherein the initial state of the third RRAM device and the fourth RRAM device is a high-resistance state; and when it is detected that the third RRAM device switches from the high-resistance state to the low-resistance state, stop applying the write voltage to the third RRAM device and the fourth RRAM device. The read circuit is also used to obtain a second random number according to the difference between the low-resistance state of the third RRAM device and the resistance state of the fourth RRAM device, wherein the resistance state of the fourth RRAM device is higher than the low-resistance state of the third RRAM device.

[0014] Optionally, the first selector, the second selector and the third selector may include any one of the following devices: a transistor, a diode, and a bidirectional diode.

[0015] In a second aspect, a random number generation method is provided, which is performed by a random number generation device including a physical unclonable function PUF calculation module, and the method includes: applying a write voltage to a first RRAM device and a second RRAM device in the PUF calculation module, wherein the initial state of the first RRAM device and the second RRAM device is a high-resistance state; when it is detected that the first RRAM device switches from the high-resistance state to a low-resistance state, stopping applying the write voltage to the first RRAM device and the second RRAM device; and obtaining a first random number according to the difference between the low-resistance state of the first RRAM device and the resistance state of the second RRAM device, wherein the resistance state of the second RRAM device is higher than the low-resistance state of the first RRAM device.

[0016] In a possible implementation, the method further includes: controlling the current flowing through the first RRAM device and the second RRAM device, so as to prevent current turbulence and avoid generating other unnecessary paths. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a physical PUF structure provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of the structure of a random number generation device provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of the structure of another random number generation device provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of a PUF calculation module corresponding to different selectors provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of the setting time and reset time of a tantalum oxide (TaOx) RRAM provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of the structure of an adaptive separation circuit provided in an embodiment of the present application;

[0023] Figure 7 A schematic diagram of a working sequence of a control signal Set_Se l, a control signal DL and a feedback signal FB provided in an embodiment of the present application;

[0024] Figure 8 A schematic diagram of the structure of a reading circuit provided in an embodiment of the present application;

[0025] Fig. 9 A schematic diagram of the working timing of a read circuit provided in an embodiment of the present application;

[0026] Fig.10 A schematic diagram of a RRAM device and a bit line connection method provided in an embodiment of the present application;

[0027] Fig.11 A schematic diagram of the structure of another random number generation device provided in an embodiment of the present application;

[0028] Fig.12 A schematic diagram of another RRAM device and bit line connection method provided in an embodiment of the present application;

[0029] Fig.13 A schematic diagram of a random number generation method provided in an embodiment of the present application;

[0030] Fig.14 A flowchart of another random number generation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] As mentioned above, for a PUF structure that generates random numbers using the difference in the break time of the gate oxide layers of two transistors, random numbers other than "1" and "0" may be generated due to the breakage of both gate oxide layers, and the stability of the generated random numbers cannot be guaranteed.

[0032] The random number generation device and method provided by the embodiments of the present application apply a write voltage to two resistive random access memory (RRAM) devices whose initial state is a high-resistance state. If one of the RRAM devices changes from the high-resistance state to the low-resistance state, the write voltage is stopped from being applied to the two RRAM devices, and then a random number is obtained according to the difference in the resistance state between the two RRAM devices, thereby stably generating random numbers.

[0033] The following first describes some concepts involved in this application:

[0034] PUF: PUF is a "digital fingerprint" defined by the physical unclonable property of materials. PUF is based on the unique physical changes that occur naturally during semiconductor manufacturing as a unique identifier of semiconductor devices (such as microprocessors). PUF is usually implemented in integrated circuits and is often used in applications with high security requirements (such as cryptography). Depending on the application field and scenario, PUF is usually divided into strong PUF and weak PUF. Strong PUF includes, for example, arbitration PUF, optical PUF, lightweight security PUF, bistable ring PUF, etc. Strong PUF has the advantage of a huge number of challenge-response pairs (CRP), but due to resource reuse, it is vulnerable to modeling attacks and is mostly used for authentication. Weak PUF includes, for example, Internet cred it identity (ICID), coating PUF, ring oscillator PUF, SRAM PUF, butterfly PUF, latch PUF, trigger PUF, etc. Weak PUF has the advantage of not being vulnerable to modeling attacks, but the number of CRPs is small and they are mostly used to generate secret keys or product identifications.

[0035] High impedance state and low impedance state: High impedance state refers to a node in the circuit having a relatively higher impedance than other nodes in the circuit, which is equivalent to an open circuit in the circuit. Low impedance state is a concept opposite to high impedance state, that is, the impedance in low impedance state is lower than that in high impedance state, which is equivalent to a short circuit in the circuit.

[0036] The first electrode and the second electrode of the transistor: For the transistor involved in the embodiments of the present application, when the transistor is an N-type metal-oxide-semiconductor (NMOS) transistor, the first electrode refers to the drain and the second electrode is the source; when the transistor is a P-type metal-oxide-semiconductor (PMOS) transistor, the first electrode is the source and the second electrode is the drain.

[0037] like Figure 2 and Figure 3 As shown, the embodiment of the present application provides a random number generating device, which at least includes: an adaptive separation circuit 21, a reading circuit 22, and M*N PUF calculation modules, where M and N are positive integers. In the embodiment of the present application, M represents the number of columns, and N represents the number of rows, that is, the random number generating device includes N rows and M columns of PUF calculation modules, and each PUF calculation module is used to generate a random number.

[0038] It should be noted that, for the convenience of description, the present application may refer to the first column of PUF calculation modules in two adjacent columns as the first PUF calculation module 23 and the second column of PUF calculation modules as the second PUF calculation module 24. The first PUF calculation module 23 and the second PUF calculation module 24 use the same device. In one embodiment, the connection method between the two and the bit line may be the same, and in another embodiment, the connection method between the two and the bit line may be different. In the subsequent description, unless otherwise specified, the relevant description of the first PUF calculation module 23 is also applicable to the second PUF calculation module 24, so the relevant content of the second PUF calculation module 24 will not be repeated, and the differences between the two will be specifically explained.

[0039] In addition, the random number generating device further includes a column gating circuit 25, a controller 26, a row decoder 27, and a word line driving circuit 28. Optionally, Figure 3 As shown, the random number generating device may further include a selection line driving circuit 29 .

[0040] The functions of each part are described below:

[0041] The controller 26 is used to control the timing of the operation of the entire random number generation device. For example, it can control the timing of the operation of the adaptive separation circuit 21, the read circuit 22, the row decoder 27, the column selection circuit 25, etc., so as to realize the functions of random number generation, random number reading and PUF calculation module reset.

[0042] The row decoder 27 is used to select a word line (WL) through the word line driving circuit 28 according to the timing control signal of the controller 26. Since each word line is connected to a row of PUF calculation modules, it is equivalent to selecting a row of PUF calculation modules. Figure 2 and Figure 3 As shown, in the embodiment of the present application, there are N word lines in total, that is, there are N rows of PUF calculation modules.

[0043] The word line driving circuit 28 is optional as a buffer, which is used to accelerate the charging and discharging process of the PUF computing module.

[0044] The column selection circuit 25 is used to select a group of bit lines (BL) according to the timing control signal of the controller 26. Since two bit lines in each group of bit lines are connected to a column of PUF calculation modules, it is equivalent to selecting a column of PUF calculation modules. Each group of bit lines includes two bit lines. For example, the first group of bit lines includes bit line BL (0) and bit line BLB (0). Figure 2 and Figure 3 As shown, there are M groups of bit lines in the present application, that is, there are M columns of PUF calculation modules.

[0045] If a word line is selected through the row decoder 27 and a group of bit lines is selected through the column selection circuit 25, it is equivalent to selecting a PUF calculation module at the intersection of the word line and the group of bit lines.

[0046] The selection line driving circuit 29 is used to select a selection line (SL) according to the timing control signal of the controller 26. Since each selection line is connected to a row of PUF calculation modules, it is equivalent to selecting a row of PUF calculation modules. Figure 3 As shown, there are a total of N selection lines in this application.

[0047] like Figure 2 or Figure 3 As shown, the first PUF calculation module 23 includes a first RRAM device 231 and a second RRAM device 232 .

[0048] The first RRAM device 231 includes a first word line terminal WLT1 and a first bit line terminal BLT1, and the second RRAM device 232 includes a second word line terminal WLT2 and a second bit line terminal BLT2. The first word line terminal WLT1 and the second word line terminal WLT2 are used to connect to the same word line, for example, Figure 2 The first word line terminal WLT1 and the second word line terminal WLT2 shown in A are commonly connected to the word line WL(0). The first bit line terminal BLT1 is used to connect to the first bit line BL, for example, Figure 2The first bit line terminal BLT1 shown in A is connected to the bit line BL(0); the second bit line terminal BLT2 is used to connect to the second bit line BLB, for example, Figure 2 The second bit line terminal BLT2 shown in A is connected to the bit line BLB(0), and the second bit line can also be called a complementary bit line.

[0049] In a possible implementation, Figure 3 As shown in A, the first PUF calculation module 23 may further include: a first selector 233, which is connected to the first RRAM device 231 and the second RRAM device 232, respectively, and is used to control the current flowing through the first RRAM device 231 and the second RRAM device 232. Specifically, the first end SL11 of the first selector 233 is connected to the first word line end WLT1 of the first RRAM device 231, the second end SL12 of the first selector 233 is connected to the second word line end WLT2 of the second RRAM device 232, and the third end SL13 of the first selector 233 is connected to the word line, for example, Figure 3 A third terminal SL13 of the first selector 233 shown in A is connected to the word line WL(0), and a fourth terminal SL14 of the first selector 233 is connected to the selection line SL(0).

[0050] Or, in another possible implementation, as Figure 3 As shown in B, the first PUF calculation module 23 may further include: a second selector 234 and a third selector 235. The second selector 234 is connected to the first RRAM device 231, and is used to control the current flowing through the first RRAM device 231. The third selector 235 is connected to the second RRAM device 232, and is used to control the current flowing through the second RRAM device 232. Specifically, the first end SL21 of the second selector 234 is connected to the first word line end WLT1 of the first RRAM device 231, the second end SL32 of the third selector 235 is connected to the second word line end WLT2 of the second RRAM device 232, and the second end SL22 of the second selector 234 and the second end SL32 of the third selector 235 are connected to the word line, for example, Figure 3 The second end SL22 of the second selector 234 and the second end SL32 of the third selector 235 shown in FIG. 2 are connected to the word line WL(0). The third end SL23 of the second selector 234 and the third end SL33 of the third selector 235 are connected to the selection line, for example, Figure 3 The third terminal SL23 of the second selector 234 and the third terminal SL33 of the third selector 235 shown in FIG. 2B are connected to the selection line SL( 0 ).

[0051] The selector can be a transistor, a diode, a bidirectional diode or other different devices. According to the number of selectors used in the PUF calculation module, the following can be formed: Figure 4The PUF structures of different structures such as 2T2R / 2D2R / 1T2R / 1D2R / 0T2R / 0D2R are shown, where T represents a transistor, D represents a diode or a bidirectional diode, and R represents an RRAM device. When there is no selector, a PUF computing module with the smallest area can be obtained, thereby improving the density of the PUF computing module.

[0052] The function of the selector is to prevent current turbulence and avoid generating other unnecessary paths. For example, when the row decoder 27 and the column selection circuit 25 select the first PUF calculation module 23, the selection line driving circuit 29 can select the selection line SL0, and can only control the current flowing through the first RRAM device 231 and the second RRAM device 232 of the first PUF calculation module 23, without affecting the current flowing through the RRAM devices of other PUF calculation modules.

[0053] The initial state of the first RRAM device 231 and the second RRAM device 232 is a high impedance state. When the row decoder 27 applies a reset voltage to a word line through the word line driving circuit 28, the two RRAM devices of a row of PUF calculation modules connected to the word line can be restored to the initial state. Alternatively, when the selection line driving circuit 29 applies a reset voltage to a selection line, the two RRAM devices of a row of PUF calculation modules connected to the word line can be restored to the initial state.

[0054] The number of adaptive separation circuits 21 is not limited to one. For example, each column of PUF calculation modules may correspond to one adaptive separation circuit, or all PUF calculation modules may share one adaptive separation circuit to save circuit area. This application takes all PUF calculation modules sharing one adaptive separation circuit as an example, but is not intended to be limited to this.

[0055] The adaptive separation circuit 21 is respectively connected to the first RRAM device 231 and the second RRAM device 232. Specifically, the first end S of the adaptive separation circuit 21 is connected to the first RRAM device 231 through the column selection circuit 25 and the first bit line BL, and is connected to the second RRAM device 232 through the column selection circuit 25 and the second bit line BLB.

[0056] The adaptive separation circuit 21 is used to apply a write voltage (also referred to as a set voltage) to the first RRAM device 231 and the second RRAM device 232. When it is detected that the first RRAM device 231 switches from a high resistance state to a low resistance state, the write voltage is stopped from being applied to the first RRAM device 231 and the second RRAM device 211.

[0057] As described above, the initial states of the first RRAM device 231 and the second RRAM device 232 are high-resistance states. After the write voltage is applied to the first RRAM device 231 and the second RRAM device 232, the first RRAM device 231 and the second RRAM device 232 respectively begin to enter their respective set (Set) times. When the set (Set) time of the first RRAM device 231 ends (i.e., the setting is completed), the first RRAM device 231 switches from the high-resistance state to the low-resistance state; due to the difference in the set time between RRAM devices, the set time of the second RRAM device 232 has not yet ended (i.e., the setting has not been completed), so the resistance state of the second RRAM device 232 is still higher than the low-resistance state of the first RRAM device 231. At this time, the write voltage is stopped from being applied to the first RRAM device 231 and the second RRAM device 232, and the resistance state of the second RRAM device 232 stops decreasing and remains.

[0058] The present application utilizes the difference in the set time of two RRAM devices in the first PUF calculation module as a random source, and obtains a random number by reading the difference in the resistance states of the two RRAM devices through the read circuit 22 .

[0059] like Figure 5 , which is a schematic diagram of the setup time and reset time of a tantalum oxide (TaOx) RRAM, wherein A corresponds to the setup time and B corresponds to the reset time.

[0060] If the same write voltage is applied to the two RRAM devices in the first PUF computing module, the write voltage is stopped after one RRAM device switches from a high-resistance state to a low-resistance state. Figure 5 As shown in A, since the setting process of the RRAM device is abrupt, it is extremely rare to form a conductive filament (CF) on two RRAM devices at the same time, thereby ensuring that one of the last two RRAM devices is in a low resistance state and the other is in a high resistance state.

[0061] If the difference in reset time is used as a random source, the same reset voltage is applied to two RRAM devices, and the reset voltage is stopped after one RRAM device switches from a low-resistance state to a high-resistance state. Figure 5 As shown in Figure B, since the reset process is gradual, the CF in the two RRAM devices may experience different degrees of rupture, resulting in one of the two RRAM devices being in a higher high-resistance state and the other being in a lower high-resistance state. Therefore, by selecting the difference in the setup time of the two RRAM devices as the random source, a larger resistance difference between the two RRAM devices can be obtained, which is conducive to the read circuit to accurately read the random number.

[0062] For example, Figure 6 As shown, an embodiment of the present application provides an adaptive separation circuit, which includes: transistors M1-transistor M7. The first electrode of transistor M1 is connected to the set voltage Vset, the gate A of transistor M1 is used to connect the gates of transistors at the same position of other adaptive separation circuits, and the second electrode of transistor M1 is connected to the first electrode of transistor M2. The gate of transistor M2 is connected to the second electrode of transistor M4, the first electrode of transistor M5 and the gate of transistor M7, and the feedback signal FB is derived here; the second electrode of transistor M2 is connected to the second electrode of transistor M3, the gate of transistor M4, the gate of transistor M5 and the first electrode of transistor M6, where the node corresponds to the control signal DL. The first electrode of transistor M3 is connected to the set voltage Vset, and the gate of transistor M3 inputs the control signal Set_Se l. The first electrode of transistor M4 is connected to the power supply voltage Vdd. The second electrode of transistor M5 is connected to the first electrode of transistor M7. The gate of transistor M6 is connected to the control signal Rst, and the second electrode of transistor M6 is grounded. The second electrode of transistor M7 is grounded.

[0063] In the above circuit, the transistor M1 acts as a current limiter. The node of the control signal DL acts as the first terminal S of the adaptive separation circuit 21, and the first terminal S is connected to the first RRAM device 231 through the column selection circuit 25 and the first bit line BL, and is connected to the second RRAM device 232 through the column selection circuit 25 and the second bit line BLB. The adaptive separation circuit 21 applies a write voltage to the first RRAM device 231 and the second RRAM device 232 through the control signal DL on the first terminal S, and determines that any one of the two RRAM devices changes from a high resistance state to a low resistance state by monitoring the voltage drop of the write voltage, that is, as long as one RRAM device changes from a high resistance state to a low resistance state, the voltage drop of the write voltage will drop to 0.

[0064] Optionally, the adaptive separation circuit may further include a current limiting generator LG. The current limiting generator LG includes a transistor M8 and a current source I comp. The first electrode of the transistor M8 is connected to the set voltage Vset, the gate of the transistor M8 is connected to the second electrode of the transistor M8 and the gate of the transistor M1, and the second electrode of the transistor M8 is grounded through the constant current source I comp. In actual use, the current limiting generator LG may not be used to reduce the circuit area, but if the current limiting generator LG is used, the separation speed of the adaptive separation circuit can be accelerated and the power consumption of the circuit can be reduced.

[0065] The working process of the adaptive separation circuit is as follows:

[0066] The working sequence of the control signal Set_Se l, the control signal DL and the feedback signal FB is as follows: Figure 7As shown. First, the control signal Set_Se l is set to a low level, and the control signal DL of the adaptive separation circuit becomes a high level, and its voltage is pulled up to a level close to the set voltage Vset. After passing through the inverter composed of transistors M4, M5 and M7, the voltage of the feedback signal FB changes from a high level to a low level. When an RRAM device in the first PUF calculation module 23 changes from a high-resistance state to a low-resistance state, the voltage of the control signal DL on the first bit line BL or the second bit line BLB begins to drop. Due to the positive feedback effect of the inverter composed of transistors M4, M5 and M7, the voltage of the control signal DL drops rapidly to 0, preventing another RRAM device in the first PUF calculation module 23 from changing to a low-resistance state, and at the same time, the voltage of the feedback signal FB changes from a low level to a high level.

[0067] It should be noted that the first RRAM device 231 and the second RRAM device 232 in this document can be replaced with each other, and no special description will be given later. For example, the adaptive separation circuit 21 can also stop applying the write voltage to the first RRAM device 231 and the second RRAM device 211 when it is detected that the second RRAM device 232 switches from a high-resistance state to a low-resistance state. When the first RRAM device 231 changes from a high-resistance state to a low-resistance state, it can correspond to a random number "0", and when the second RRAM device 232 changes from a high-resistance state to a low-resistance state, it can correspond to a random number "1"; or, when the first RRAM device 231 changes from a high-resistance state to a low-resistance state, it can correspond to a random number "1", and when the second RRAM device 232 changes from a high-resistance state to a low-resistance state, it can correspond to a random number "0", which is not limited in this application.

[0068] By adopting the above-mentioned adaptive separation circuit, on the one hand, it can be ensured that only one RRAM device in the first PUF computing module 23 changes from a high-resistance state to a low-resistance state during separation, thereby ensuring that the PUF correctly outputs a random number; on the other hand, during separation, two RRAM devices in the same PUF computing module are connected to the same end of the adaptive separation circuit, so that the mismatch of the adaptive separation circuit will not affect the randomness of the PUF output.

[0069] The read circuit 22 may be a sense amplifier (SA), which is connected to the first RRAM device 231 and the second RRAM device 232, respectively, and is used to obtain a first random number according to the difference between the low resistance state of the first RRAM device 231 and the resistance state of the second RRAM device 232. As described above, when the first RRAM device 231 changes from a high resistance state to a low resistance state, the resistance state of the second RRAM device 232 is higher than the low resistance state of the first RRAM device 231.

[0070] Specifically, the first terminal T of the read circuit 22 is connected to the first RRAM device 231 through the column selection circuit 25 and the first bit line BL, and the second terminal V of the read circuit 22 is connected to the second RRAM device 232 through the column selection circuit 25 and the second bit line BLB.

[0071] For example, Figure 8 As shown, an embodiment of the present application provides a read circuit, which includes: transistors M0-transistor M10. The gate of transistor M0 is connected to the input signal SAE, the second electrode of transistor M0 is grounded, and the first electrode of transistor M0 is connected to the second electrode of transistor M1 and the second electrode of transistor M2. The gate of transistor M1 is connected to the gate of transistor M3, the first electrode of transistor M2, the second electrode of transistor M4, the second electrode of transistor M6 and the first electrode of transistor M8, and the output signal QB is derived here. The first electrode of transistor M1 is connected to the second electrode of transistor M5, the first electrode of transistor M7, the second electrode of transistor M3, the second electrode of transistor M4 and the second electrode of transistor M2, and the output signal Q is derived here. The first electrode of transistor M3 is connected to the first electrode of transistor M5, the first electrode of transistor M4 and the first electrode of transistor M6, and is connected to the power supply voltage Vdd. The gate of transistor M5 and the gate of transistor M6 are connected to the input signal PCH. The second electrode of transistor M7 is connected to the first electrode of transistor M9 and the first bit line BL, and the second electrode of transistor M8 is connected to the first electrode of transistor M10 and the second bit line BLB. The gate of the transistor M7 and the gate of the transistor M8 are connected to the input signal VCL. The second electrode of the transistor M9 and the second electrode of the transistor M10 are grounded. The gate of the transistor M9 and the gate of the transistor M10 are connected to the input signal DCH.

[0072] Among them, transistor M0 is a start tube, transistors M1-M4 form a latch, transistors M5 and M6 are pre-charging tubes, transistors M7 and M8 are clamping tubes, and transistors M9 and M10 are discharge tubes for the first bit line BL and the second bit line BLB respectively.

[0073] In the above circuit, the second electrode of the transistor M7 and the first electrode of the transistor M9 correspond to the first input terminal of the read circuit 22 described above, and are used to connect the first RRAM device 231 through the column selection circuit 25 and the first bit line BL; the second electrode of the transistor M8 and the first electrode of the transistor M10 correspond to the second input terminal of the read circuit 22 described above, and are used to connect the second RRAM device 232 through the column selection circuit 25 and the second bit line BLB.

[0074] The working process of the read circuit is as follows:

[0075] like Fig. 9As shown, at the beginning, the input signal DCH is at a high level, and the first bit line BL and the second bit line BLB are discharged to a low level. Then the input signal PCH is set to a low level, and the first bit line BL and the second bit line BLB begin to precharge. Due to the clamping effect of transistors M7 and M8, the charging voltage of the first bit line BL and the second bit line BLB will not be particularly high. Then the input signal SAE is set to a high level. Since one of the two RRAM devices of the first PUF calculation module is in a high-resistance state and the other is in a low-resistance state, the discharge current of the first bit line BL and the second bit line BLB is different. The RRAM device in the high-resistance state discharges slowly, and the voltage drop of the bit line connected to it is also slow. The RRAM device in the low-resistance state discharges quickly, and the voltage drop of the bit line connected to it is also fast. Due to the amplification effect of the latch formed by transistors M1-transistor M4, one of the output signals Q and QB of the latch is high, and the other is low.

[0076] The first RRAM device is connected to the first bit line BL, and the second RRAM device is connected to the second bit line BLB. Assuming that the first RRAM device is in a high-resistance state and the second RRAM device is in a low-resistance state, the voltage of the first bit line BL drops slowly, and the voltage of the second bit line BLB drops quickly. The output signal Q corresponding to the first bit line BL is a high level, and the output signal QB corresponding to the second bit line BLB is a low level. At this time, a random number 1 can be obtained.

[0077] Assuming that the first RRAM device is in a low-resistance state and the second RRAM device is in a high-resistance state, the voltage of the first bit line BL drops faster, and the voltage of the second bit line BLB drops slower. The output signal Q corresponding to the first bit line BL is a low level, and the output signal QB corresponding to the second bit line BLB is a high level. At this time, a random number 0 can be obtained.

[0078] like Fig.10 As shown, for two PUF computing modules located in the same row, it is assumed that the connection mode of the read circuit and the RRAM devices on the same side in different PUF computing modules is the same, that is, the RRAM devices on one side are connected to the read circuit 22 through the first bit line BL, and the RRAM devices on the other side are connected to the read circuit 22 through the second bit line BLB. At this time, if there is a system deviation, that is, the setup time of the RRAM device on one side is shorter than the setup time of the RRAM device on the other side, then the side that ends the setup time faster (exemplarily, the right side in the figure) is more likely to change from a high-resistance state to a low-resistance state first, so the read circuit 22 is more likely to read a specific random number (exemplarily, the random number "1" in the figure) from this side, so that the probability of the entire random number generation device generating random numbers "0" and "1" deviates from 1 / 2.

[0079] The second PUF calculation module 24 provided in the embodiment of the present application may refer to an adjacent PUF calculation module located in the same row as the first PUF calculation module 23. Fig.11 As shown, the second PUF calculation module 24 includes a third RRAM device 241 and a fourth RRAM device 242 , and the initial states of the third RRAM device 241 and the fourth RRAM device 242 are high-impedance states.

[0080] The adaptive separation circuit 21 is connected to the third RRAM device 241 and the fourth RRAM device 242, respectively, and is further used to: apply a write voltage to the third RRAM device 241 and the fourth RRAM device 242. When it is detected that the third RRAM device 241 switches from a high-resistance state to a low-resistance state, stop applying the write voltage to the third RRAM device 241 and the fourth RRAM device 242.

[0081] The read circuit 22 is also connected to the third RRAM device 241 and the fourth RRAM device 242, and is used to obtain a second random number according to the difference between the low resistance state of the third RRAM device 241 and the resistance state of the fourth RRAM device 242, wherein the resistance state of the fourth RRAM device 242 is higher than the low resistance state of the third RRAM device 241.

[0082] The connection mode of the read circuit 22 and the third RRAM device 241 is the same as the connection mode of the read circuit 22 and the second RRAM device 232, and the connection mode of the read circuit 22 and the fourth RRAM device 242 is the same as the connection mode of the read circuit 22 and the first RRAM device 231. That is, the read circuit 22 connects the fourth RRAM device 242 and the first RRAM device 231 through the first bit line BL, and connects the third RRAM device 241 and the second RRAM device 232 through the second bit line BLB.

[0083] like Fig.12 As shown, by connecting the bit lines in adjacent PUF computing modules in a mirrored manner, even if there is a system deviation, the setup time of the RRAM device on one side is shorter than the setup time of the RRAM device on the other side, but through the above-mentioned mirror connection method, the probability of the random numbers "0" and "1" read by the read circuit 22 will not deviate from 1 / 2.

[0084] The working process of the random number generation device provided in the embodiment of the present application includes: random number generation, random number reading and PUF calculation module reset, which is as follows:

[0085] In the random number generation process, the controller 26 controls the row decoder 27 to select a word line (for example, WLx) through the word line driving circuit 28, and the controller 26 controls the column gating circuit 25 to select a pair of bit lines BLy and BLBy, so that the PUF calculation module located at the intersection of the word line WLx and the bit line BLy / BLBy is selected. Then, the adaptive separation circuit 21 applies a write voltage to the two RRAM devices of the selected PUF calculation module through the column gating circuit 25, and stops applying the write voltage to the two RRAM devices when it is detected that any one of the two RRAM devices switches from a high-resistance state to a low-resistance state.

[0086] In the random number reading process, the controller 26 controls the row decoder 27 to select a word line (for example, WLx) through the word line driving circuit 28, and the controller 26 controls the column selection circuit 25 to select a pair of bit lines BLy and BLBy, so that the PUF calculation module located at the intersection of the word line WLx and the bit line BLy / BLBy is selected. Then, the read circuit obtains the random number according to the difference in the resistance state of the two RRAM devices in the selected PUF module. Each PUF calculation module corresponds to a random number. If multiple random numbers need to be obtained, the PUF calculation modules of the corresponding number of bits can be read.

[0087] During the reset process, the controller 26 controls the row decoder 27 to select a word line (e.g., WLx) through the word line driving circuit 28. If there is no selection line driving circuit 29 and each PUF calculation module does not include a selector, the PUF calculation module corresponding to the word line can be reset by applying a reset voltage to the selected word line. If there is a selection line driving circuit 29 and each PUF calculation module includes a selector, the PUF calculation module corresponding to the selection line can be reset by applying a reset voltage to the selection line (e.g., SLx) of the selection line driving circuit 29 and setting all bit lines to a low level. In addition, the control signal Rst of the adaptive separation circuit is set to a high voltage to reset the adaptive separation circuit. The reset of the PUF calculation module refers to the two RRAM devices of the PUF calculation module being in a high impedance state, and all BLs and BLBs are set to a low level at the same time, so that the PUF unit can be reset.

[0088] The random number generating device provided by the embodiment of the present application includes a PUF calculation module, an adaptive separation circuit and a reading circuit. The PUF calculation module includes two RRAM devices whose initial state is a high-resistance state. The adaptive separation circuit applies a write voltage to the two RRAM devices. If one of the RRAM devices changes from a high-resistance state to a low-resistance state, the write voltage is stopped from being applied to the two RRAM devices. Then the reading circuit obtains a random number based on the difference in resistance state between the two RRAM devices. Since there will not be a situation where the resistance state between the two RRAM devices is exactly the same, no random numbers other than "1" and "0" will be generated, so that random numbers can be generated stably.

[0089] like Fig.13 As shown, the embodiment of the present application provides a random number generation method, which can be performed by the random number generation device including the PUF calculation module. The method includes:

[0090] S1301. Apply a write voltage to a first RRAM device and a second RRAM device in a PUF computing module, wherein an initial state of the first RRAM device and the second RRAM device is a high-impedance state.

[0091] This step can refer to the description of the adaptive separation circuit, which will not be repeated here.

[0092] S1302 : When it is detected that the first RRAM device switches from the high resistance state to the low resistance state, stop applying the write voltage to the first RRAM device and the second RRAM device.

[0093] This step can refer to the description of the adaptive separation circuit, which will not be repeated here.

[0094] S1303 , obtaining a first random number according to a difference between the low resistance state of the first RRAM device and the resistance state of the second RRAM device.

[0095] The resistance state of the second RRAM device is higher than the low resistance state of the first RRAM device.

[0096] This step can refer to the description of the read circuit and will not be repeated here.

[0097] Optional, such as Fig.14 As shown, the method may also include:

[0098] S1401, controlling the current flowing through the first RRAM device and the second RRAM device to prevent current turbulence and avoid generating other unnecessary paths.

[0099] This step can refer to the description of the selector and will not be repeated here.

[0100] It should be understood that the devices and methods disclosed in the several embodiments provided in the present application can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0101] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0102] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0103] It should be noted that the embodiments provided in this application are merely illustrative. Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above embodiments, the descriptions of each embodiment have their own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. The features disclosed in the embodiments, claims, and drawings of the present invention may exist independently or in combination. The features described in the embodiment of the present invention in the form of hardware may be executed by software, and vice versa. This is not limited here.

[0104] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application shall be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A random number generating device, characterized in that: include: A first physical unclonable function PUF calculation module includes a first resistive random access memory RRAM device and a second RRAM device, wherein the initial states of the first RRAM device and the second RRAM device are high-resistance states; the first RRAM device includes a first word line terminal and a first bit line terminal, the second RRAM device includes a second word line terminal and a second bit line terminal, the first word line terminal and the second word line terminal are connected to the same word line, the first bit line terminal is connected to the first bit line, and the second bit line terminal is connected to the second bit line; the word line is used to select the first PUF calculation module; A second PUF computing module, comprising a third RRAM device and a fourth RRAM device, wherein the initial states of the third RRAM device and the fourth RRAM device are high impedance; the third RRAM device comprises a third word line terminal and a third bit line terminal, the fourth RRAM device comprises a fourth word line terminal and a fourth bit line terminal, the third word line terminal and the fourth word line terminal are connected to the same word line, the third bit line terminal is connected to the second bit line, and the fourth bit line terminal is connected to the first bit line; the word line is also used to select the second PUF computing module; the first PUF computing module and the second PUF computing module are adjacent PUF computing modules, the first RRAM device is located on a side away from the second PUF computing module, the second RRAM device is located on a side close to the second PUF computing module, the third RRAM device is located on a side close to the first PUF computing module, and the fourth RRAM device is located on a side away from the first PUF computing module; an adaptive separation circuit, connecting the first RRAM device and the fourth RRAM device through the first bit line, and connecting the second RRAM device and the third RRAM device through the second bit line; and used to apply a write voltage to the first RRAM device and the second RRAM device, and, when detecting that the first RRAM device switches from the high-resistance state to the low-resistance state, stop applying the write voltage to the first RRAM device and the second RRAM device; Alternatively, applying a write voltage to the third RRAM device and the fourth RRAM device, and, when detecting that the third RRAM device switches from the high-resistance state to the low-resistance state, stopping applying the write voltage to the third RRAM device and the fourth RRAM device; A read circuit is connected to the first RRAM device and the fourth RRAM device through the first bit line, and to the second RRAM device and the third RRAM device through the second bit line, and is used to obtain a first random number generated by the first PUF calculation module or a second random number generated by the second PUF calculation module according to a level of the first bit line and a level of the second bit line.

2. The random number generating device according to claim 1, characterized in that: The first PUF calculation module also includes: The first selector is connected to the first RRAM device and the second RRAM device, respectively, and is used to control current flowing through the first RRAM device and the second RRAM device.

3. The random number generating device according to claim 1, characterized in that: The first PUF calculation module also includes: a second selector, connected to the first RRAM device, and configured to control a current flowing through the first RRAM device; The third selector is connected to the second RRAM device and is used to control the current flowing through the second RRAM device.

4. The random number generating device according to claim 2, characterized in that: The first selector includes any one of the following devices: a transistor, a diode, and a bidirectional diode.

5. The random number generating device according to claim 3, characterized in that: The second selector and the third selector include any one of the following devices: a transistor, a diode, and a bidirectional diode.

6. A random number generation method, characterized in that: The method is performed by a random number generating device including a physical unclonable function PUF calculation module, and the method includes: Applying a write voltage to a first RRAM device and a second RRAM device in a first PUF computing module, wherein the initial states of the first RRAM device and the second RRAM device are high impedance; a first word line terminal of the first RRAM device and a second word line terminal of the second RRAM device are connected to the same word line, a first bit line terminal of the first RRAM device is connected to a first bit line, and a second bit line terminal of the second RRAM device is connected to a second bit line; When it is detected that the first RRAM device switches from the high resistance state to the low resistance state, stopping applying the write voltage to the first RRAM device and the second RRAM device; Obtaining a first random number generated by the first PUF calculation module according to a level of the first bit line and a level of the second bit line; Applying a write voltage to a third RRAM device and a fourth RRAM device in a second PUF computing module, wherein the initial states of the third RRAM device and the fourth RRAM device are high impedance states; a third word line terminal of the third RRAM device and a fourth word line terminal of the fourth RRAM device are connected to the same word line, a third bit line terminal of the third RRAM device is connected to the second bit line, and a fourth bit line terminal of the fourth RRAM device is connected to the first bit line; the first PUF computing module and the second PUF computing module are adjacent PUF computing modules, the first RRAM device is located on a side away from the second PUF computing module, the second RRAM device is located on a side close to the second PUF computing module, the third RRAM device is located on a side close to the first PUF computing module, and the fourth RRAM device is located on a side away from the first PUF computing module; When it is detected that the third RRAM device switches from the high resistance state to the low resistance state, stopping applying the write voltage to the third RRAM device and the fourth RRAM device; A second random number generated by the second PUF calculation module is obtained according to the level of the first bit line and the level of the second bit line.

7. The method according to claim 6, characterized in that The method further comprises: A current flowing through the first RRAM device and the second RRAM device is controlled.

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