Display panel and display device

Abstract

The present application relates to a display panel and a display device. The display panel includes a first display area and a second display area. The display panel includes a plurality of first pixel groups in the first display area, a plurality of second pixel groups in the second display area, and a plurality of scan lines connected to the first pixel groups and the second pixel groups. The second display area includes a plurality of light emitting areas and a plurality of opening areas, the second pixel groups are arranged in the plurality of light emitting areas respectively, and the second pixel groups are not arranged in the plurality of opening areas. A scan line of a second pixel group of an nth row is cut and does not overlap with an opening area adjacent to the second pixel group of the nth row of the nth row, and is connected to a scan line of a second pixel group of an (n-1)th row or a scan line of a second pixel group of an (n+1)th row in the second display area.

Description

TECHNICAL FIELD

[0001] The disclosure herein relates to a display panel and a display apparatus, and more particularly, to a display apparatus having improved sensing sensitivity of an electronic module. BACKGROUND

[0002] A display apparatus can include various electronic components, such as a display panel for displaying an image, an input sensing member for sensing an external input, and an electronic module. The electronic components can be electrically connected to each other by signal lines disposed in various ways. The display panel includes a light emitting element for generating light.

[0003] The input sensing member can include a sensing electrode for sensing an external input. The electronic module can include a camera, an infrared sensor, a proximity sensor, etc. The electronic module can be disposed under the display panel. SUMMARY

[0004] The disclosure provides a display panel having improved sensing sensitivity of an electronic module, and a display apparatus including the same.

[0005] In an embodiment of the disclosure, a display panel includes a first display area having a first light transmittance value and a second display area having a second light transmittance value higher than the first light transmittance value. In such an embodiment, the display panel includes a plurality of first pixel groups in the first display area, wherein each of the plurality of first pixel groups includes a first pixel, a plurality of second pixel groups in the second display area, wherein each of the plurality of second pixel groups includes a second pixel, and a plurality of scan lines connected to the plurality of first pixel groups and the plurality of second pixel groups.

[0006] In such an embodiment, the second display area includes a plurality of light emitting areas and a plurality of opening areas, the plurality of second pixel groups are respectively arranged in the plurality of light emitting areas, and the plurality of second pixel groups are not arranged in the plurality of opening areas.

[0007] In such an embodiment, a scan line of an nth row of second pixel groups among the plurality of second pixel groups is cut and does not overlap with an opening area of the nth row adjacent to the nth row of second pixel groups, and is connected to a scan line of an (n-1)th row of second pixel groups or a scan line of an (n+1)th row of second pixel groups in the second display area. Herein, n is an integer greater than 1.

[0008] In an embodiment of the present invention, a display apparatus includes a display panel and an electronic module. In such an embodiment, the display panel includes a first display area having a first resolution value, a second display area having a second resolution value lower than the first resolution value, a plurality of first pixel groups in the first display area, a plurality of second pixel groups in the second display area, and a plurality of scan lines connected to the plurality of first pixel groups and the plurality of second pixel groups, wherein each of the plurality of first pixel groups includes first pixels, and wherein each of the plurality of second pixel groups includes second pixels. In such an embodiment, the electronic module is disposed under the second display area.

[0009] In such an embodiment, the second display area includes a plurality of light emitting areas and a plurality of opening areas, the second pixels are disposed in the plurality of light emitting areas, and the second pixels are not disposed in the plurality of opening areas.

[0010] In such an embodiment, a scan line of an nth row of the plurality of second pixel groups is cut and does not overlap with an opening area of the nth row adjacent to the nth row of the second pixel groups, and is connected to a scan line of an (n-1)th row of the second pixel groups or a scan line of an (n+1)th row of the second pixel groups in the second display area. Herein, n is an integer greater than 1. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present invention and together with the description serve to describe the principles of the present invention. In the drawings:

[0012] FIG. 1A is a perspective view of a display apparatus according to an embodiment of the present invention;

[0013] FIG. 1B is an exploded perspective view of a display apparatus according to an embodiment of the present invention;

[0014] FIG. 2 is a block diagram of a display apparatus according to an embodiment of the present invention;

[0015] FIG. 3A is a cross-sectional view of a display module according to an embodiment of the present invention;

[0016] FIG. 3B is a cross-sectional view of a display module according to an alternative embodiment of the present invention;

[0017] FIG. 4A is a plan view of a display panel according to an embodiment of the present invention;

[0018] FIG. 4Bis a plan view of a display panel according to an alternative embodiment of the present application;

[0019] FIG. 4C is a plan view of a display panel according to another alternative embodiment of the present application;

[0020] FIG. 5 is an enlarged plan view of a portion of a display panel according to an embodiment of the present application;

[0021] FIG. 6 is FIG. 5 is an enlarged plan view of region I of

[0022] FIG. 7 is FIG. 6 is an equivalent circuit diagram of the first red pixel illustrated in

[0023] FIG. 8 is FIG. 6 is a sectional view of some elements of the first display region illustrated in

[0024] FIG. 9 is FIG. 5 is an enlarged plan view of region II of

[0025] FIG. 10 is a plan view illustrating FIG. 9 the connection relationship between the pixel circuit portion and the wiring illustrated in

[0026] FIG. 11 is FIG. 10 is an enlarged plan view of region III of

[0027] FIG. 12A is FIG. 11 is a sectional view of one of the opening regions illustrated in

[0028] FIG. 12B is a sectional view taken along FIG. 11 the line IV-IV' illustrated in

[0029] FIG. 12C is a sectional view taken along FIG. 11 the line V-V' illustrated in

[0030] FIG. 13 is an enlarged plan view of a portion of a display panel according to an alternative embodiment of the present application;

[0031] FIG. 14 is FIG. 13 is an enlarged plan view of region VI of

[0032] FIG. 15 is a plan view illustrating FIG. 14The diagram shows the connection relationship between the pixel circuit section and the wiring.

[0033] FIG. 16 This is an equivalent circuit diagram of the first red pixel according to an embodiment of the present invention; and

[0034] FIG. 17 This is a plan view illustrating the connection relationship between the pixel circuit portion and the wiring according to an embodiment of the present invention. Detailed Implementation

[0035] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of the invention to those skilled in the art.

[0036] It will be understood that when a component or layer is referred to as being "on," "connected to," or "coupled to" another component or layer, it can be directly on, directly connected to, or directly coupled to that other component or layer, or there can be intermediate components or layers. Conversely, when a component is referred to as being "directly" on, directly connected to, or directly coupled to another component, there are no intermediate components.

[0037] Throughout this specification, the same reference numerals refer to the same elements. In the figures, for the purpose of effectively describing the technical content, the thickness, scale, and dimensions of the elements are exaggerated.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to include the plural forms that include “at least one”, unless the context clearly indicates otherwise. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” or “including” specify the presence of the stated features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or groups thereof.

[0039] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section without departing from the teachings of the invention.

[0040] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the equipment in use or operation.

[0041] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the relevant field context and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0042] This document describes embodiments with reference to cross-sectional views as schematic illustrations of idealized examples. Therefore, variations in the illustrated shapes are contemplated as a result of, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions illustrated herein, but should include, for example, deviations in shape due to manufacturing processes. For example, regions illustrated or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the sharp corners illustrated may be rounded. Therefore, the regions illustrated in the figures are schematic in nature and their shapes are not intended to represent the precise shapes of the illustrated regions and are not intended to limit the scope of the claims of this invention.

[0043] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0044] FIG. 1A This is a perspective view of a display device according to an embodiment of the present invention. FIG. 1B This is an exploded perspective view of a display device according to an embodiment of the present invention. FIG. 2 This is a block diagram of a display device according to an embodiment of the present invention.

[0045] Reference FIG. 1A , FIG. 1B and FIG. 2An embodiment of the display device DD can be a device activated by an electrical signal. The display device DD can include various devices, such as tablet computers, laptop computers, personal computers, televisions, etc. In the following description, for ease of description, an embodiment in which the display device DD is a smartphone will be described in detail.

[0046] The display device DD can display an image IM on a display surface FS that is parallel to the first direction DR1 and intersects (or is perpendicular to) the first direction DR1, facing a third direction DR3. The display surface FS on which the image IM is displayed can correspond to the front side of the display device DD and the front side FS of the window 100. Hereinafter, the display surface and front side of the display device DD, as well as the front side of the window 100, can be indicated by the same reference numeral FS. In addition to moving images, the image IM can include static images. In embodiments, such as... FIG. 1A As shown in the illustration, the image IM can include a clock window and application icons.

[0047] In such an embodiment, the front (or top surface) and back (or bottom surface) of each component are defined relative to the direction in which the image IM is displayed. The front and back can be opposite each other on a third direction DR3, and the normal direction of each of the front and back can be parallel to the third direction DR3. In this document, the directions indicated by the first direction DR1 to the third direction DR3 are relative and can be converted to different directions.

[0048] In an embodiment, such as FIG. 1B As shown, the display device DD may include a window 100, a display module 200, a driving circuit unit 300, a housing 400, and an electronic module 500. In such an embodiment, the window 100 and the housing 400 may be combined to form the appearance of the display device DD.

[0049] Window 100 may include an optically transparent insulating material. In one embodiment, for example, window 100 may include glass or plastic. Window 100 may have a multilayer structure or a single-layer structure. In one embodiment, for example, window 100 may include multiple plastic films bonded together by an adhesive, or it may include a glass substrate and plastic films bonded together by an adhesive.

[0050] When viewed in a plane, window 100 can be divided into a transmission region TA and a border region BZA. In this document, the term "when viewed in a plane" can mean the view from a planar view on a third-party DR3. Furthermore, "thickness direction" can mean the third-party DR3.

[0051] The transmissive region TA can be an optically transparent region. The border region BZA can be a region with lower light transmittance compared to the transmissive region TA. The border region BZA can define the shape of the transmissive region TA. The border region BZA can be adjacent to and surround the transmissive region TA.

[0052] The border region BZA may have a predetermined color. The border region BZA may cover the peripheral region NAA of the display module 200 to prevent the peripheral region NAA from being viewed from the outside. In an alternative embodiment, the border region BZA may be omitted in the window 100.

[0053] The display module 200 can be arranged below the window 100. In this document, "below" can mean a direction opposite to the direction in which the display module 200 provides the image, or a direction opposite to the third direction DR3. The display module 200 can display the image IM and sense external input TC. The display module 200 includes a front IS comprising an active region AA and a peripheral region NAA. The active region AA can be a region activated according to an electrical signal.

[0054] In an embodiment, the active region AA can be the region in which the image IM is displayed and the external input TC is sensed. The transmission region TA overlaps at least with the active region AA. In one embodiment, for example, the transmission region TA overlaps entirely or at least partially with the active region AA. Therefore, a user can view the image IM or provide the external input TC through the transmission region TA.

[0055] The peripheral region NAA can be the area covered by the border region BZA. The peripheral region NAA is adjacent to the active region AA. The peripheral region NAA can surround the active region AA. The drive circuitry, drive wiring, etc., used to drive the active region AA can be arranged in the peripheral region NAA.

[0056] In this embodiment, the display module 200 is assembled in a flat state with its active region AA and peripheral region NAA facing the window 100. However, this is merely exemplary and alternative; a portion of the peripheral region NAA may be bent. In such an embodiment, a portion of the peripheral region NAA may be bent to face the back of the display device DD, and thus the surface area of ​​the bezel region BZA on the front of the display device DD can be reduced. Alternatively, the display module 200 may be assembled with a portion of its active region AA bent. Alternatively, the peripheral region NAA may be omitted from the display module 200.

[0057] The active area AA of the display module 200 may include multiple display areas. These multiple display areas may have different transmittance values ​​than each other. In embodiments of the present invention, such as... FIG. 1BAs shown, the active area AA of the display module 200 includes a first display area DA1 and a second display area DA2. The second display area DA2 may have a higher light transmittance than the first display area DA1.

[0058] The driving circuit unit 300 can be electrically connected to the display module 200. The driving circuit unit 300 may include a main circuit board MB and a flexible film CF.

[0059] The flexible film CF is electrically connected to the display module 200. The flexible film CF can be connected to the pads PD of the display module 200 located in the peripheral area NAA. The flexible film CF provides electrical signals for driving the display module 200. These electrical signals can be generated either within the flexible film CF or in the main circuit board MB. The main circuit board MB may include various drive circuits for driving the display module 200, connectors for supplying power, etc.

[0060] Electronic module 500 may include a first electronic module 501 and a second electronic module 502. When viewed in a flat surface, the first electronic module 501 and the second electronic module 502 may overlap with the second display area DA2. The first electronic module 501 and the second electronic module 502 may be arranged below the display module 200. The first electronic module 501 and the second electronic module 502 may receive external input transmitted through the second display area DA2, or output signals through the second display area DA2. In such an embodiment, as described above, the second display area DA2 has a higher light transmittance than the first display area DA1, allowing the electronic module 500 to effectively transmit and / or receive signals through the second display area DA2.

[0061] The housing 400 and window 100 are combined. The housing 400 and window 100 are combined to provide internal space. The display module 200 and electronic module 500 can be accommodated in the internal space.

[0062] The housing 400 may comprise a material with relatively high rigidity. In one embodiment, for example, the housing 400 may comprise multiple frames and / or panels made of glass, plastic, metal, or a combination thereof. The housing 400 can safely protect the components of the display device DD housed within the internal space from external impacts.

[0063] Reference FIG. 2 The display device DD may include a display module 200, a power module PM, a first electronic module EM1, and a second electronic module EM2. The display module 200, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other.

[0064] The display module 200 may include a display panel 210 and an input sensing unit 220.

[0065] The display panel 210 can be a component that essentially generates an image IM. The image IM generated by the display panel 210 is displayed on the front IS and viewed by the user from the outside through the transmissive area TA.

[0066] Input sensing unit 220 senses external input TC applied from the outside. In one embodiment, for example, input sensing unit 220 may sense external input TC provided to window 100. External input TC may be user input. User input includes various types of external input, such as touch, light, heat, pen, and pressure from a part of the user's body. In an embodiment, such as FIG. 1A As shown, the external input TC can be a touch of a user's hand on the front FS. However, this is merely exemplary, and the external input TC can be provided in various forms as described above. In embodiments, the input sensing unit 220 can sense the external input TC applied to the side surface or back surface of the display device DD, depending on the structure of the display device DD, but is not limited thereto.

[0067] The power module PM supplies power for the entire operation of the display device DD. The power module PM may include a battery module.

[0068] The first electronic module EM1 and the second electronic module EM2 may include various functional modules for operating the display device DD.

[0069] The first electronic module EM1 can be directly mounted on the motherboard that is electrically connected to the display module 200, or it can be mounted on a discrete board and electrically connected to the motherboard via a connector (not shown) or the like.

[0070] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, a voice input module AIM, a memory MM, and an external interface IF. Some of these modules may not be mounted on the motherboard, but can be electrically connected to the motherboard via a flexible circuit board.

[0071] The control module CM controls the entire operation of the display device DD. The control module CM may be a microprocessor. In one embodiment, for example, the control module CM activates or deactivates the display module 200. The control module CM may control other modules such as the image input module IIM and the sound input module AIM based on touch signals received from the display module 200.

[0072] The wireless communication module TM can use Bluetooth or Wi-Fi channels to send radio signals to or receive radio signals from another terminal. The wireless communication module TM can also use common communication channels to send / receive voice signals. The wireless communication module TM may include a transmitting section TM1 for modulating and transmitting the signal to be transmitted, and a receiving section TM2 for demodulating the received signal.

[0073] The image input module IIM processes image signals and converts them into image data to be displayed on the display module 200. The sound input module AIM uses a microphone to receive external sound signals in recording mode, voice recognition mode, etc., and converts the received external sound signals into electronic voice data.

[0074] The external interface IF can be used as an interface for connecting external chargers, wired / wireless data ports, card (e.g., memory cards and SIM / UIM card) slots, etc.

[0075] The second electronic module EM2 may include a sound output module AOM, a light emitting module LM, a light receiving module LRM, a camera module CMM, etc. These components can be directly mounted on the motherboard, mounted on a discrete board for electrical connection to the display module 200 via connectors (not shown), or electrically connected to the first electronic module EM1.

[0076] The audio output module AOM converts audio data received from the wireless communication module TM or audio data stored in the memory MM, and outputs the converted audio data to the outside.

[0077] A light emitting module (LM) generates and outputs light. The LM can output infrared light. The LM may include light-emitting diode (LED) elements. A light receiving module (LRM) detects infrared light. The LRM can be activated when infrared light of a predetermined level or higher is detected. The LRM may include a complementary metal-oxide-semiconductor (CMOS) sensor. After the infrared light generated by the LM is output, it can be reflected by an external object (e.g., a user's finger or face), and the reflected infrared light can be incident on the LRM. A camera module (CMM) can capture external images.

[0078] In an embodiment, FIG. 1B Each of the first electronic module 501 and the second electronic module 502 shown may include FIG. 2At least one of the components of the first electronic module EM1 and the second electronic module EM2 shown. In one embodiment, for example, each of the first electronic module 501 and the second electronic module 502 may include at least one of the following: a sound output module AOM, a light emitting module LM, a light receiving module LRM, a camera module CMM, and a thermal sensing module. The first electronic module 501 and the second electronic module 502 can detect through the second display area DA2 ( FIG. 1B (As illustrated in the diagram) The external object received, or the sound signal such as voice or the light such as infrared light can be provided to the outside through the second display area DA2.

[0079] FIG. 3A This is a cross-sectional view of a display module according to an embodiment of the present invention.

[0080] Reference FIG. 3A An embodiment of the display module 200 may include a display panel 210, an input sensing unit 220, and a bonding member SLM. The input sensing unit 220 may be referred to as the input sensing panel.

[0081] In this embodiment, the display panel 210 may be a light-emitting display panel, and is not specifically limited thereto. In one embodiment, for example, the display panel 210 may be an organic light-emitting display panel or a quantum dot light-emitting display panel.

[0082] The display panel 210 may include a substrate BL, a display circuit layer ML, and a light-emitting element layer EML. The input sensing unit 220 may include a cover substrate CBL and a sensing circuit layer ML-T.

[0083] Each of the substrate BL and the cover substrate CBL may have a stacked structure including a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or multiple insulating layers.

[0084] The display circuit layer ML can be disposed on the substrate BL. The display circuit layer ML may include multiple insulating layers, multiple conductive layers, and semiconductor layers. The multiple conductive layers of the display circuit layer ML can constitute the signal wiring or control circuitry of a pixel.

[0085] A light-emitting element layer (EML) can be disposed on a display circuit layer (ML). The EML may include a light-emitting layer for generating light. In one embodiment, for example, the light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of a quantum dot light-emitting display panel may include at least one selected from quantum dots and quantum rods.

[0086] A cover substrate CBL can be disposed on a light-emitting element layer EML. A predetermined space can be defined between the cover substrate CBL and the light-emitting element layer EML. This space can be filled with air or an inert gas. In embodiments of the invention, this space can also be filled with fillers such as silicone polymers, epoxy resins, and acrylic resins.

[0087] The sensing circuit layer ML-T can be disposed on the cover substrate CBL. The sensing circuit layer ML-T may include multiple insulating layers and multiple conductive layers. The multiple conductive layers may form sensing electrodes for sensing external inputs, sensing wiring connected to the sensing electrodes, and sensing pads connected to the sensing wiring.

[0088] A bonding member SLM can be disposed between a substrate BL and a cover substrate CBL. The bonding member SLM can bond the substrate BL and the cover substrate CBL. The bonding member SLM may include organic materials such as photocurable resins and photoplastic resins, or may include inorganic materials such as glass frit sealants, but is not limited thereto.

[0089] FIG. 3B This is a cross-sectional view of a display module according to an alternative embodiment of the present invention.

[0090] Reference FIG. 3B An embodiment of the display module 200-F may include a display panel 210-F and an input sensing unit 220-F. The input sensing unit 220-F may be referred to as an input sensing layer.

[0091] The display panel 210-F may include a substrate BL, a display circuit layer ML, a light-emitting element layer EML, and a thin-film encapsulation layer TFE. The input sensing unit 220-F may include a substrate BS and a sensing circuit layer ML-T. The substrate BS may be disposed on the thin-film encapsulation layer TFE. FIG. 3B The diagram illustrates a discrete layer structure where the substrate layer (BS) and the thin-film encapsulation layer (TFE) are formed. However, embodiments of the present invention are not limited thereto. In alternative embodiments, the substrate layer (BS) and the thin-film encapsulation layer (TFE) can be integrally formed as a single unit.

[0092] According to an embodiment of the present invention, the display panel 210-F and the input sensing unit 220-F can be formed in a continuous process. In such an embodiment, the substrate layer BS (or the sensing circuit layer ML-T) can be formed directly on the thin-film encapsulation layer TFE.

[0093] FIG. 4A This is a plan view of a display panel according to an embodiment of the present invention.

[0094] Reference FIG. 4AThe first display area DA1 and the second display area DA2 can be defined within the display panel 210. The first display area DA1 and the second display area DA2 can be connected to the display module 200 (see [link]). FIG. 1B The active region AA (see) FIG. 1B Corresponding to.

[0095] Electronic Module 500 (see) FIG. 1B The first display area DA1 can be arranged below the second display area DA2. The transmittance of the second display area DA2 can be higher than that of the first display area DA1. Therefore, the electronic module 500 can easily send and / or receive signals through the second display area DA2. In an embodiment, some components in the second display area DA2 can be omitted to improve transmittance. In one embodiment, for example, some pixels disposed in the second display area DA2 can be omitted.

[0096] The first display area DA1 and the second display area DA2 may be adjacent to each other in the second direction DR2. The boundary between the first display area DA1 and the second display area DA2 may extend in the first direction DR1. When viewed in a plane, the second display area DA2 may be defined at the upper part of the display panel 210.

[0097] A first pixel PX1 can be disposed in a first display area DA1, and a second pixel PX2 can be disposed in a second display area DA2. The first pixel PX1 and the second pixel PX2 can be pixels that generate light. The number of first pixels PX1 and the number of second pixels PX2 in the same unit area can be different from each other. In one embodiment, for example, the number of second pixels PX2 in the same unit area can be less than the number of first pixels PX1 in the same unit area. Therefore, the light transmittance of the second display area DA2 can be higher than that of the first display area DA1. In such an embodiment, the resolution of the second display area DA2 can be lower than that of the first display area DA1.

[0098] The first pixel PX1 and the second pixel PX2 can have the same configuration. The configuration of the first pixel PX1 and the second pixel PX2 will be described in more detail later.

[0099] FIG. 4B This is a plan view of a display panel according to an alternative embodiment of the present invention. FIG. 4B In the middle, refer to the above FIG. 4A Components that are identical or similar to those described are indicated by the same or similar reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0100] Reference FIG. 4BIn this embodiment, the first display area DA1a and the second display area DA2a can be defined within the display panel 210. Electronic module 500 (see...) FIG. 1B It can be placed below the second display area DA2a.

[0101] In one embodiment, for example, such as FIG. 4B As shown, the second display area DA2a can be defined at the upper left corner, but the position of the second display area DA2a can be modified differently based on the position of the electronic module 500. In an alternative embodiment of the invention, for example, the second display area DA2a can be defined at the upper right corner of the display panel 210. In another alternative embodiment, the second display area DA2a can be defined at both the upper left and upper right corners of the display panel 210.

[0102] FIG. 4C This is a plan view of a display panel according to another alternative embodiment of the present invention. FIG. 4C In the middle, refer to the above FIG. 4A Components that are identical or similar to those described are indicated by the same or similar reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0103] Reference FIG. 4C In this embodiment, the first display area DA1b and a plurality of second display areas DA2b may be defined in the display panel 210.

[0104] Electronic Module 500 (see) FIG. 1B The multiple second display areas DA2b can be arranged below each other. When viewed in a plane, each of the multiple second display areas DA2b can have a surface area corresponding to the size of the corresponding one in the electronic module. In one embodiment, for example, in two electronic modules 501 and 502 ( FIG. 1B In the arrangement shown in the diagram, two second display areas DA2b can be provided within the active area AA. In such an embodiment, the two second display areas DA2b can be spaced apart from each other. In such an embodiment, each of the two second display areas DA2b can be surrounded by a first display area DA1b.

[0105] In one embodiment, for example, the two second display areas DA2b may have the same transmittance value. Herein, the transmittance value (or transmittance value) of an area means the value of light transmittance (or transmittance value) when light passes through the area. However, embodiments of the invention are not limited thereto. In alternative embodiments, the two second display areas DA2b may have different transmittance values.

[0106] FIG. 5This is an enlarged plan view of a portion of the display panel according to an embodiment of the present invention.

[0107] Reference FIG. 4A and FIG. 5 An embodiment of the display panel 210 includes a first display area DA1 and a second display area DA2. The first display area DA1 includes a plurality of first pixel groups PG1, and the second display area DA2 includes a plurality of second pixel groups PG2. Each of the first pixel groups PG1 includes one or more first pixels PX1, and each of the second pixel groups PG2 includes one or more second pixels PX2. The structure and shape of the first pixels PX1 included in the first pixel group PG1 may be the same as or different from the structure and shape of the second pixels PX2 included in the second pixel group PG2. For ease of description, reference will be made later. FIG. 6 to FIG. 12C An embodiment in which the pixels of the first pixel group PG1 and the second pixel group PG2 have the same pixel structure as each other is described in more detail, but is not limited thereto.

[0108] In the first display area DA1, a plurality of first pixel groups PG1 can be arranged in a matrix form, which may include, for example, rows and columns in a first direction DR1 and a second direction DR2 respectively in different directions, or rows and columns in two diagonal directions that intersect each other. Here, the two diagonal directions may be a fifth direction DR5 located between the first direction DR1 and the second direction DR2, and a fourth direction DR4 perpendicular to the fifth direction DR5.

[0109] The second display area DA2 includes a plurality of light-emitting areas EA in which a plurality of second pixel groups PG2 are respectively arranged, and a plurality of opening areas OA in which the second pixel groups PG2 are not arranged. The light-emitting areas EA and the opening areas OA can be alternately arranged in the first direction DR1 and the second direction DR2. One of the opening areas OA is arranged between two adjacent light-emitting areas EA in the first direction DR1, and another one of the opening areas OA is arranged between two adjacent light-emitting areas EA in the second direction DR2. In embodiments of the invention, the number of light-emitting areas EA in the second display area DA2 and the number of opening areas OA in the second display area DA2 can be the same. Therefore, in the same surface area of ​​the first display area DA1 and the second display area DA2, the number of second pixel groups PG2 can be half the number of first pixel groups PG1. As a result, the light transmittance of the second display area DA2 can be higher than that of the first display area DA1. In such embodiments, the resolution of the second display area DA2 can be lower than that of the first display area DA1.

[0110] In an embodiment, such as FIG. 5As shown, multiple light-emitting regions EA and multiple opening regions OA are illustrated as being arranged in a matrix in the fourth direction DR4 and the fifth direction DR5, but embodiments of the present invention are not limited thereto. In an alternative embodiment, for example, the multiple light-emitting regions EA and multiple opening regions OA may be arranged in a matrix in the first direction DR1 and the second direction DR2.

[0111] FIG. 6 yes FIG. 5 An enlarged plan view of region I. FIG. 7 yes FIG. 6 The equivalent circuit diagram of the first red pixel shown in the figure is as follows: FIG. 8 yes FIG. 6 The figure shows a cross-sectional view of some components in the first display area.

[0112] Reference FIG. 5 and FIG. 6 A plurality of first pixel groups PG1 are disposed in a first display area DA1 along a first direction DR1 and a second direction DR2. Each of the plurality of first pixel groups PG1 includes a plurality of pixels. In one embodiment, for example, each of the first pixel groups PG1 may include eight pixels. In such an embodiment, four of the eight pixels are included in a first sub-pixel group SPG1, and the remaining four pixels are included in a second sub-pixel group SPG2. In an embodiment of the invention, the four pixels included in the first sub-pixel group SPG1 may be a first red pixel PXR1, a first green pixel PXG1, a first blue pixel PXB1, and a second green pixel PXG2. The four pixels included in the second sub-pixel group SPG2 may be a second blue pixel PXB2, a third green pixel PXG3, a second red pixel PXR2, and a fourth green pixel PXG4. The first sub-pixel groups SPG1 and the second sub-pixel groups SPG2 may be arranged to be adjacent to each other along the second direction DR2. The four pixels included in each of the sub-pixel groups may be set to be adjacent to each other along the first direction DR1.

[0113] The first red pixel PXR1 includes a first pixel circuit portion CC1 and a first red pixel R1, and the first green pixel PXG1 includes a second pixel circuit portion CC2 and a first green pixel G1. The first blue pixel PXB1 includes a third pixel circuit portion CC3 and a first blue pixel B1, and the second green pixel PXG2 includes a fourth pixel circuit portion CC4 and a second green pixel G2. The configuration or shape of the first pixel circuit portions CC1 to the fourth pixel circuit portion CC4 can be substantially the same as each other. The first red pixel R1 and the first blue pixel B1 can overlap with the first pixel circuit portion CC1 and the third pixel circuit portion CC3, respectively, and the first green pixel G1 and the second green pixel G2 can overlap with the second pixel circuit portion CC2 and the fourth pixel circuit portion CC4, respectively. In embodiments of the invention, the first blue pixel B1 can have a larger size than the first red pixel R1, and the first red pixel R1 can have a larger size than the first green pixel G1 and the second green pixel G2. The first green pixel G1 and the second green pixel G2 can have the same size. The size of the color pixels is not limited thereto and can be modified and applied differently.

[0114] The second blue pixel PXB2 includes a fifth pixel circuit portion CC5 and a second blue pixel B2, and the third green pixel PXG3 includes a sixth pixel circuit portion CC6 and a third green pixel G3. The second red pixel PXR2 includes a seventh pixel circuit portion CC7 and a second red pixel R2, and the fourth green pixel PXG4 includes an eighth pixel circuit portion CC8 and a fourth green pixel G4. The fifth pixel circuit portions CC5 to CC8 can be configured identically, and their shapes can be identical. The second blue pixel B2 and the second red pixel R2 can overlap with the fifth pixel circuit portion CC5 and the seventh pixel circuit portion CC7, respectively, and the third green pixel G3 and the fourth green pixel G4 can overlap with the sixth pixel circuit portion CC6 and the eighth pixel circuit portion CC8, respectively. In embodiments of the present invention, the second blue pixel B2 can have a larger size than the second red pixel R2, and the second red pixel R2 can have a larger size than the third green pixel G3 and the fourth green pixel G4. The third green pixel G3 and the fourth green pixel G4 can have the same size. The size of the color pixels is not limited to this, and can be modified and applied in different ways.

[0115] The display panel 210 includes multiple scan lines SLI1, SLW1, SLI2, SLW2, SLI3, SLW3, SLI4, and SLW4 connected to a plurality of first pixel groups PG1. In such an embodiment, the first to fourth scan lines SLI1, SLW1, SLI2, and SLW2 are connected to a plurality of first pixel groups PG1 disposed in the same row in a first display area DA1. The first to fourth scan lines SLI1, SLW1, SLI2, and SLW2 extend in a first direction DR1 and are sequentially arranged in a second direction DR2. The first scan line SLI1 and the second scan line SLW1 are connected to a first sub-pixel group SPG1, and the third scan line SLI2 and the fourth scan line SLW2 are connected to a second sub-pixel group SPG2. In an embodiment, the first pixel circuit portion to the fourth pixel circuit portion CC1, CC2, CC3 and CC4 are connected to the first scan line SLI1 and the second scan line SLW1, and the fifth pixel circuit portion to the eighth pixel circuit portion CC5, CC6, CC7 and CC8 are connected to the third scan line SLI2 and the fourth scan line SLW2.

[0116] The third scan line SLI2 can be connected to the second scan line SLW1 outside the first display area DA1 (that is, in the peripheral area NAA). Therefore, the second scan line SLW1 is also electrically connected to the second sub-pixel group SPG2 via the third scan line SLI2. In an embodiment, as... FIG. 6 As illustrated, the second scan line SLW1 can be connected to the fifth to eighth pixel circuit sections CC5, CC6, CC7, and CC8 via the third scan line SLI2. In such an embodiment, the same signal can be applied to both the second scan line SLW1 and the third scan line SLI2.

[0117] The display panel 210 includes first data lines to fourth data lines DL1, DL2, DL3, and DL4 connected to a plurality of first pixel groups PG1 and arranged in the same column in a first display area DA1. The first data lines to fourth data lines DL1, DL2, DL3, and DL4 extend in a second direction DR2 and are sequentially arranged in a first direction DR1. A first pixel circuit portion CC1 and a fifth pixel circuit portion CC5 are connected to the first data line DL1, and a second pixel circuit portion CC2 and a sixth pixel circuit portion CC6 are connected to the second data line DL2. A third pixel circuit portion CC3 and a seventh pixel circuit portion CC7 are connected to the third data line DL3, and a fourth pixel circuit portion CC4 and an eighth pixel circuit portion CC8 are connected to the fourth data line DL4.

[0118] The display panel 210 may further include a first light-emitting control line EL1, a second light-emitting control line EL2, a third light-emitting control line EL3, and a fourth light-emitting control line EL4. The first light-emitting control lines EL1 to EL4 are connected to a first pixel group PG1. The first light-emitting control lines EL1 to EL4 may extend in a first direction DR1. The first light-emitting control line EL1 and the third light-emitting control line EL3 may be connected to a first sub-pixel group SPG1, and the second light-emitting control line EL2 and the fourth light-emitting control line EL4 may be connected to a second sub-pixel group SPG2.

[0119] The display panel 210 may further include power supply voltage lines, initialization voltage lines, etc., connected to the first pixel group PG1.

[0120] In the following text, reference will be made to FIG. 7 The configuration of the first red pixel PXR1 is described. In such an embodiment, the other pixels have the same configuration as the first red pixel PXR1, and for ease of description, any repeated detailed descriptions of the configurations of the other pixels will be omitted.

[0121] Reference FIG. 7 The first pixel circuit portion CC1 of the first red pixel PXR1 may include multiple transistors T1 to T7, a capacitor CP, and a light-emitting element LD. The multiple transistors T1 to T7 and the capacitor CP of the first pixel circuit portion CC1 can control the amount of current flowing into the light-emitting element LD in response to data signals and scan signals.

[0122] Each of the plurality of transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In the following text, for ease of description, one of the input electrode and the output electrode may be referred to as the first electrode, and the other of the input electrode and the output electrode may be referred to as the second electrode.

[0123] The first electrode of the first transistor T1 can be connected to the first power supply voltage line PL1 via the fifth transistor T5. The first power supply voltage line PL1 can be a wiring that provides the first power supply voltage ELVDD. The second electrode of the first transistor T1 is connected to the anode of the light-emitting element LD via the sixth transistor T6.

[0124] The first transistor T1 can control the amount of current flowing into the light-emitting element LD in response to the voltage applied to the control electrode of the first transistor T1.

[0125] The second transistor T2 is connected between the first data line DL1 and the first electrode of the first transistor T1. The control electrode of the second transistor T2 is connected to the second scan line SLW1. When the second scan signal is provided to the second scan line SLW1, the second transistor T2 is turned on to electrically connect the first data line DL1 to the first electrode of the first transistor T1.

[0126] The third transistor T3 is connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the second scan line SLW1. When the second scan signal is provided to the second scan line SLW1, the third transistor T3 is turned on to electrically connect the second electrode of the first transistor T1 to the control electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in the form of a diode.

[0127] A fourth transistor T4 is connected between node ND and the initialization voltage line VIL. The control electrode of the fourth transistor T4 is connected to the first scan line SLI1. Node ND can be the node where the control electrodes of the fourth transistor T4 and the first transistor T1 are connected to each other. When the first scan signal is provided to the first scan line SLI1, the fourth transistor T4 is turned on to provide the initialization voltage Vint to node ND. The first scan signal can be generated before the second scan signal is generated.

[0128] The fifth transistor T5 is connected between the first power supply voltage line PL1 and the first electrode of the first transistor T1. The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the anode of the light-emitting element LD. The control electrodes of the fifth transistor T5 and the sixth transistor T6 are connected to the first light-emitting control line EL1.

[0129] A seventh transistor T7 is connected between the initialization voltage line VIL and the anode of the light-emitting element LD. The control electrode of the seventh transistor T7 is connected to the second scan line SLW1. When the second scan signal is provided to the second scan line SLW1, the seventh transistor T7 is turned on to provide the initialization voltage Vint to the anode of the light-emitting element LD. In such an embodiment, as... FIG. 6 As shown, the second scan line SLW1 is connected to the third scan line SLI2. Therefore, the second scan signal provided to the second scan line SLW1 can be sent to the fourth transistor T4 of the fifth pixel circuit section to the eighth pixel circuit section CC5, CC6, CC7, and CC8 via the third scan line SLI2. When the scan signal provided via the third scan line SLI2 is defined as the third scan signal, the second scan signal and the third scan signal can be the same signal.

[0130] The seventh transistor T7 can improve the black display capability of the first red pixel PXR1. In such an embodiment, when the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the light-emitting element LD discharges. Then, when black illumination is achieved, the light emission of the light-emitting element LD, which can be caused by the leakage current from the first transistor T1, will not occur, and thus the black display capability can be improved.

[0131] In an embodiment, such as FIG. 7 As shown, the control electrode of the seventh transistor T7 can be connected to the second scan line SLW1, but embodiments of the invention are not limited thereto. In an alternative embodiment of the invention, the control electrode of the seventh transistor T7 can be connected to an additional scan line for providing a scan signal different from the second scan signal.

[0132] In an embodiment, such as FIG. 7 As shown, the first transistor T1 to the seventh transistor T7 can be P-type transistors, such as P-type metal-oxide-semiconductor (PMOS) transistors, but are not limited thereto. In an alternative embodiment of the invention, some or all of the first transistors T1 to the seventh transistor T7 constituting the first pixel circuit portion CC1 can be N-type transistors, such as N-type metal-oxide-semiconductor (NMOS) transistors.

[0133] A capacitor CP is positioned between the first power supply voltage line PL1 and node ND. The capacitor CP stores the voltage corresponding to the data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing in the first transistor T1 can be determined based on the voltage stored in the capacitor CP.

[0134] The light-emitting element (LD) can be electrically connected to the sixth transistor T6 and the second power supply voltage line PL2. The anode of the LD is connected to the sixth transistor T6, and the cathode is connected to the second power supply voltage line PL2. The second power supply voltage ELVSS can be applied to the second power supply voltage line PL2. The second power supply voltage ELVSS is lower than the first power supply voltage ELVDD. Therefore, the LD can emit light corresponding to the voltage difference between the signal transmitted through the sixth transistor T6 and the second power supply voltage ELVSS received through the second power supply voltage line PL2.

[0135] In embodiments of the present invention, the configuration of the first red pixel PXR1 is not limited to... FIG. 7 The configuration is illustrated in the figure. In an alternative embodiment of the invention, the first red pixel PXR1 can be modified to have a configuration for emitting light in the light-emitting element LD.

[0136] Reference FIG. 7 and FIG. 8In one embodiment, a first insulating layer 10 is disposed on a substrate BL. The first insulating layer 10 may include a barrier layer and / or a buffer layer. The barrier layer may include an inorganic material. The barrier layer can effectively prevent oxygen or moisture introduced through the substrate BL from penetrating into the pixel. The buffer layer may include an inorganic material. The buffer layer can provide a lower surface energy than the substrate BL so that the pixel can be stably formed on the substrate BL.

[0137] exist FIG. 8 For ease of illustration, only one transistor TR of the pixel circuit CC1 is shown in the diagram. The transistor TR can be... FIG. 7 The first transistor T1 is shown in the figure.

[0138] A transistor TR can be disposed on a first insulating layer 10. The transistor TR includes a semiconductor pattern SP, a control electrode CE, a first electrode IE, and a second electrode OE. The semiconductor pattern SP is disposed on the first insulating layer 10. The semiconductor pattern SP may include a semiconductor material. The control electrode CE is spaced apart from the semiconductor pattern SP, and a second insulating layer 20 is located between the control electrode CE and the semiconductor pattern SP.

[0139] The first electrode IE and the second electrode OE pass through the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40, respectively, and are connected to one side and the other side of the semiconductor pattern SP. In embodiments, the stack-up structure of the transistor TR can be modified in various ways and is not limited to specific designs. FIG. 8 The embodiment is illustrated in the figure.

[0140] A fifth insulating layer 50 is disposed on the fourth insulating layer 40 to cover the first electrode IE and the second electrode OE. The fifth insulating layer 50 may include organic and / or inorganic materials and may have a single-layer structure or a multi-layer structure (e.g., a stacked structure).

[0141] The light-emitting element (LD) may include a pixel electrode E1, a light-emitting layer EL, and a common electrode E2. The pixel electrode E1 is disposed on a fifth insulating layer 50. The pixel electrode E1 can be electrically connected to a transistor TR through the fifth insulating layer 50. Although the pixel electrode E1 is illustrated as being electrically connected to... FIG. 8 The transistor TR in the middle, but as FIG. 7 As illustrated, pixel electrode E1 can be electrically connected to transistor TR via sixth transistor T6.

[0142] A sixth insulating layer 60 may be disposed on the fifth insulating layer 50. An opening may be defined in the sixth insulating layer 60, and the opening may expose at least a portion of the pixel electrode E1. The sixth insulating layer 60 may be a pixel defining film. The opening may correspond to the light-emitting area of ​​the first red pixel PXR1.

[0143] A light-emitting layer EL can be disposed on a pixel electrode E1 exposed by an opening defined in a sixth insulating layer 60. The light-emitting layer EL may include a light-emitting material. In one embodiment, for example, the light-emitting layer EL may include at least one of a material emitting red, green, and blue light, or be formed of at least one of a material emitting red, green, and blue light. The light-emitting layer EL may include a fluorescent or phosphorescent material. The light-emitting layer EL may include an organic or inorganic light-emitting material. The light-emitting layer EL may emit light in response to a potential difference between the pixel electrode E1 and the common electrode E2.

[0144] The common electrode E2 can be disposed on the light-emitting layer EL. The common electrode E2 can have a source region AA (see [reference]). FIG. 1B ) to the outer area NAA (see FIG. 1B The overall shape extends. The common electrode E2 can be provided to multiple pixels.

[0145] The common electrode E2 may comprise a transmissive conductive material or a transmissive-reflective conductive material. Therefore, light generated in the light-emitting layer EL can be effectively emitted onto the third-party DR3 via the common electrode E2. However, this is merely exemplary. In embodiments, the light-emitting element LD may be driven by its design in a bottom-emission method where the pixel electrode E1 comprises a transmissive or transmissive-reflective material, or in a double-sided emission method where light is emitted towards both the front and back sides, and is not limited to any single embodiment.

[0146] FIG. 9 yes FIG. 5 Enlarged plan view of Region II, FIG. 10 It is a diagram. FIG. 9 The diagram shows a plan view of the connection relationship between the pixel circuit section and the wiring. FIG. 11 yes FIG. 10 The enlarged plan view of region III shown in the figure.

[0147] Reference FIG. 5 , FIG. 9 and FIG. 10 The second display area DA2 includes multiple light-emitting areas EA in which multiple second pixel groups PG2 are respectively arranged, and multiple opening areas OA in which the second pixel groups PG2 are not arranged. The light-emitting areas EA and the opening areas OA can be alternately arranged on the first direction DR1 and the second direction DR2.

[0148] Each of the plurality of second pixel groups PG2 comprises a plurality of pixels. Each of the plurality of second pixel groups PG2 has the same structure as each of the first pixel group PG1. Therefore, the same or similar elements of the second pixel groups PG2 have been adopted as described above for reference. FIG. 6The same or similar reference numerals describing the pixels that constitute the first pixel group PG1 are used for labeling.

[0149] In embodiments of the invention, each of the second pixel group PG2 may include eight pixels. Four of the eight pixels are included in the first sub-pixel group SPG1, and the remaining four pixels are included in the second sub-pixel group SPG2. In one embodiment, for example, the four pixels included in the first sub-pixel group SPG1 may be a first red pixel PXR1, a first green pixel PXG1, a first blue pixel PXB1, and a second green pixel PXG2. In such an embodiment, the four pixels included in the second sub-pixel group SPG2 may be a second blue pixel PXB2, a third green pixel PXG3, a second red pixel PXR2, and a fourth green pixel PXG4. The first sub-pixel group SPG1 and the second sub-pixel group SPG2 may be arranged to be adjacent to each other in the second direction DR2. The four pixels included in each of the sub-pixel groups may be arranged to be adjacent to each other in the first direction DR1.

[0150] The first red pixel PXR1 includes a first pixel circuit portion CC1 and a first red pixel R1, and the first green pixel PXG1 includes a second pixel circuit portion CC2 and a first green pixel G1. The first blue pixel PXB1 includes a third pixel circuit portion CC3 and a first blue pixel B1, and the second green pixel PXG2 includes a fourth pixel circuit portion CC4 and a second green pixel G2. The configuration and shape of the first pixel circuit portions CC1 to the fourth pixel circuit portion CC4 can be identical to each other. The first red pixel R1 and the first blue pixel B1 can overlap with the first pixel circuit portion CC1 and the third pixel circuit portion CC3, respectively, and the first green pixel G1 and the second green pixel G2 can overlap with the second pixel circuit portion CC2 and the fourth pixel circuit portion CC4, respectively. In embodiments of the present invention, the first blue pixel B1 can have a larger size than the first red pixel R1, and the first red pixel R1 can have a larger size than the first green pixel G1 and the second green pixel G2. The first green pixel G1 and the second green pixel G2 can have the same size as each other. The size of the color pixels is not limited thereto and can be modified and applied differently.

[0151] The second blue pixel PXB2 includes a fifth pixel circuit portion CC5 and a second blue pixel B2, and the third green pixel PXG3 includes a sixth pixel circuit portion CC6 and a third green pixel G3. The second red pixel PXR2 includes a seventh pixel circuit portion CC7 and a second red pixel R2, and the fourth green pixel PXG4 includes an eighth pixel circuit portion CC8 and a fourth green pixel G4. The configuration and shape of the fifth pixel circuit portions CC5 to the eighth pixel circuit portions CC8 can be identical to each other. The second blue pixel B2 and the second red pixel R2 can overlap with the fifth pixel circuit portion CC5 and the seventh pixel circuit portion CC7, respectively, and the third green pixel G3 and the fourth green pixel G4 can overlap with the sixth pixel circuit portion CC6 and the eighth pixel circuit portion CC8, respectively. In embodiments of the invention, the second blue pixel B2 can have a larger size than the second red pixel R2, and the second red pixel R2 can have a larger size than the third green pixel G3 and the fourth green pixel G4. The third green pixel G3 and the fourth green pixel G4 can have the same size as each other. The size of the color pixels is not limited thereto and can be modified and applied differently.

[0152] The display panel 210 includes multiple scan lines GLI1, GLW1, GLI2, GLW2, GLI3, GLW3, GLI4, and GLW4 connected to multiple second pixel groups PG2. In an embodiment, the first to fourth scan lines GLI1, GLW1, GLI2, and GLW2 of the multiple scan lines are connected to multiple second pixel groups PG2 that are arranged in the same row in the second display area DA2. The first scan line GLI1 and the second scan line GLW1 are connected to a first sub-pixel group SPG1, and the third scan line GLI2 and the fourth scan line GLW2 are connected to the second sub-pixel group SPG2. In an embodiment, the first pixel circuit portion to the fourth pixel circuit portion CC1, CC2, CC3, and CC4 are connected to the first scan line GLI1 and the second scan line GLW1, and the fifth pixel circuit portion to the eighth pixel circuit portion CC5, CC6, CC7, and CC8 are connected to the third scan line GLI2 and the fourth scan line GLW2.

[0153] The third scan line GLI2 can be connected to the second scan line GLW1 outside the second display area DA2 (that is, in the peripheral area NAA). Therefore, the second scan line GLW1 is also electrically connected to the second sub-pixel group SPG2 via the third scan line GLI2. In an embodiment, as... FIG. 10As illustrated, the second scan line GLW1 can be connected to the fifth to eighth pixel circuit sections CC5, CC6, CC7, and CC8 via the third scan line GLI2. In such an embodiment, the same signal can be applied to both the second scan line GLW1 and the third scan line GLI2.

[0154] In an embodiment, such as FIG. 10 and FIG. 11 As illustrated, the first scan line GLI1 and the second scan line GLW1 extend in the first direction DR1 to overlap with the first pixel circuit portions CC1 to the fourth pixel circuit portions CC4. The first scan line GLI1, connected to the second pixel group PG2 in the nth row of a plurality of second pixel groups PG2, can be connected to the fourth scan line GLW2 in the second display area DA2. The fourth scan line GLW2 is connected to the second pixel group PG2 in the (n-1)th row. The fourth scan line GLW2, connected to the second pixel group PG2 in the nth row, is connected to the first scan line GLI3 in the second display area DA2. The first scan line GLI3 is connected to the second pixel group PG2 in the (n+1)th row. The first scan line GLI1 in the nth row can be connected to the fourth scan line GLW2 in the (n-1)th row in the second display area DA2 via a first bridging wire BL1. In an embodiment, the fourth scan line GLW2, connected to the second pixel group PG2 in the nth row, can be connected to the first scan line GLI3 in the second display area DA2. The first scan line GLI3 is connected to the second pixel group PG2 in the (n+1)th row via a first bridging wire BL1. In such an embodiment, the first bridge cable BL1 can be arranged in the second display area DA2.

[0155] The third scan line GL12 and the fourth scan line GLW2 extend in the first direction DR1 to overlap with the fifth pixel circuit portion CC5 to the eighth pixel circuit portion CC8. One end of the second scan line GLW1, which connects to the second pixel group PG2 in the nth row of a plurality of second pixel groups PG2, is connected in the second display area DA2 to the third scan line GL12, which in turn connects to the second pixel group PG2 in the nth row. One end of the second scan line GLW1 in the nth row can be connected to the third scan line GL12 in the nth row via a second bridging wire BL2 in the second display area DA2. In such an embodiment, the second bridging wire BL2 can be arranged in the second display area DA2.

[0156] A third scan line GLI2 connected to the second pixel group PG2 in each row may extend in a first direction to overlap with one of the plurality of opening regions OA located in the same row. In such an embodiment, the third scan line GLI2 may be bent and extend along the lower edge of the opening region OA. A second scan line GLW1 connected to the second pixel group PG2 in each row may have a structure that is cut within the opening region. In such an embodiment, the second scan line GLW1 may not overlap with the opening region OA.

[0157] The display panel 210 may further include first light-emitting control lines EL1 to fourth light-emitting control lines EL4, which are connected to a plurality of second pixel groups PG2 arranged in the same row. The first light-emitting control lines EL1 to fourth light-emitting control lines EL4 may extend in a first direction DR1. The first light-emitting control line EL1 and the third light-emitting control line EL3 may be connected to a first sub-pixel group SPG1, and the second light-emitting control line EL2 and the fourth light-emitting control line EL4 may be connected to the second sub-pixel group SPG2. The first light-emitting control line EL1 and the second light-emitting control line EL2 may extend in the first direction DR1 to overlap with an opening region OA located in the same row among a plurality of opening regions OA. In such an embodiment, the first light-emitting control line EL1 may be bent and extend along the upper edge of the opening region OA, and the second light-emitting control line EL2 may be bent and extend along the lower edge of the opening region OA.

[0158] The display panel 210 includes first to fourth data lines DL1, DL2, DL3, and DL4, which are connected to a plurality of second pixel groups PG2 disposed in the same column in a second display area DA2. The first to fourth data lines DL1, DL2, DL3, and DL4 extend in a second direction DR2 and are sequentially arranged in a first direction DR1. A first pixel circuit portion CC1 and a fifth pixel circuit portion CC5 are connected to the first data line DL1, and a second pixel circuit portion CC2 and a sixth pixel circuit portion CC6 are connected to the second data line DL2. A third pixel circuit portion CC3 and a seventh pixel circuit portion CC7 are connected to the third data line DL3, and a fourth pixel circuit portion CC4 and an eighth pixel circuit portion CC8 are connected to the fourth data line DL4.

[0159] The first data line DL1 to the fourth data line DL4 may extend in the second direction DR2 to overlap with the open area OA located in the same column. In one embodiment, for example, the first data line DL1 and the second data line DL2 may be bent and extend along the left edge of the open area OA, and the third data line DL3 and the fourth data line DL4 may be bent and extend along the right edge of the open area OA.

[0160] FIG. 12A yes FIG. 11 The diagram shows a cross-sectional view of one of the opening regions. FIG. 12B It is along FIG. 11 The cross-sectional view taken by line IV-IV' shown in the figure, and FIG. 12C It is along FIG. 11 The diagram shows a cross-section taken by line V-V'.

[0161] Reference FIG. 12A Pixels may not be arranged in each of the opening regions OA. Therefore, the substrate BL and the first insulating layer 10 to the fourth insulating layer 40 can be arranged in the opening region OA. However, this is merely exemplary, and embodiments of the present invention are not limited thereto.

[0162] In an alternative embodiment, portions of the substrate BL and some of the first insulating layers 10 to the fourth insulating layers 40 in the opening region OA can be removed to improve transmittance. In an alternative embodiment, FIG. 8 The fifth insulating layer 50 and the sixth insulating layer 60, as well as the common electrode E2, shown in the figure, can be further arranged in the opening region OA.

[0163] Reference FIG. 11 and FIG. 12B The first bridge wire BL1 electrically connects the fourth scan line GLW2 to the first scan line GLI3. The fourth scan line GLW2 is connected to the second pixel group PG2 in the nth row, and the first scan line GLI3 is connected to the second pixel group PG2 in the (n+1)th row.

[0164] The fourth scan line GLW2 in the nth row and the first scan line GLI3 in the (n+1)th row are disposed on the second insulating layer 20 and covered by the third insulating layer 30 and the fourth insulating layer 40. In such an embodiment, a first contact hole CNT1 for exposing one end of the fourth scan line GLW2 in the nth row and a second contact hole CNT2 for exposing a portion of the first scan line GLI3 in the (n+1)th row can be defined or formed in the third insulating layer 30 and the fourth insulating layer 40. A first bridging wire BL1 is disposed on the fourth insulating layer 40 and is connected to the fourth scan line GLW2 in the nth row and the first scan line GLI3 in the (n+1)th row through the first contact hole CNT1 and the second contact hole CNT2, respectively.

[0165] Therefore, the fourth scan line GLW2 in the nth row can have a structure that is cut within the opening region OA. However, as illustrated in the accompanying drawings, the fourth scan line GLW2 in the nth row is connected to the first scan line GLI3 in the (n+1)th row via the first bridge wire BL1, and thus the fourth scan line GLW2 in the nth row can receive the scan signal through the first scan line GLI3 in the (n+1)th row. Therefore, the fifth pixel circuit section CC5 to the eighth pixel circuit section CC8 can receive the scan signal from the fourth scan line GLW2 in the nth row and operate normally.

[0166] In an embodiment where the fourth scan line GLW2 of the nth row is removed from the aperture region OA, the aperture ratio of the aperture region OA can be improved, thereby improving the light transmittance of the aperture region OA and the second display region DA2.

[0167] Reference FIG. 11 and FIG. 12C The second bridge wire BL2 electrically connects the second scan line GLW1 of the nth row to the third scan line GLI2 of the nth row.

[0168] The second scan line GLW1 and the third scan line GLI2 of the nth row are disposed on the second insulating layer 20 and covered by the third insulating layer 30 and the fourth insulating layer 40. In such an embodiment, a third contact hole CNT3 for exposing one end of the second scan line GLW1 of the nth row and a fourth contact hole CNT4 for exposing a portion of the third scan line GLI2 of the nth row can be defined or formed in the third insulating layer 30 and the fourth insulating layer 40. A second bridging wire BL2 is disposed on the fourth insulating layer 40 and is connected to the second scan line GLW1 and the third scan line GLI2 of the nth row through the third contact hole CNT3 and the fourth contact hole CNT4, respectively.

[0169] Therefore, the second scan line GLW1 in the nth row can have a structure that is cut in the opening region OA. However, as illustrated in the attached figure, the second scan line GLW1 in the nth row is connected to the third scan line GLI2 in the nth row via the second bridge wire BL2, and thus the second scan line GLW1 in the nth row can receive the scan signal through the third scan line GLI2 in the nth row. Therefore, the first pixel circuit section CC1 to the fourth pixel circuit section CC4 can receive the scan signal from the second scan line GLW1 in the nth row and operate normally.

[0170] In an embodiment where the second scan line GLW1 of the nth row is removed from the aperture region OA, the aperture ratio of the aperture region OA can be improved, thereby improving the light transmittance of the aperture region OA and the second display region DA2. In this embodiment, the improved light transmittance of the second display region DA2 improves the light transmittance of the electronic module 500 disposed below the second display region DA2. FIG. 1B The sensing sensitivity is shown in the figure.

[0171] FIG. 13 This is an enlarged plan view of a portion of a display panel according to an alternative embodiment of the present invention.

[0172] Reference FIG. 13 In this embodiment, the display panel 211 includes a first display area DA1 and a second display area DA2. The first display area DA1 includes a plurality of first pixel groups PG1, and the second display area DA2 includes a plurality of second pixel groups PG2. Each of the first pixel groups PG1 includes one or more pixels, and each of the plurality of second pixel groups PG2 includes one or more pixels.

[0173] In the first display area DA1, a plurality of first pixel groups PG1 can be arranged in a matrix form, which has, for example, rows and columns in a first direction DR1 and a second direction DR2 respectively in different directions, or rows and columns in two diagonal directions that intersect each other. Here, the two diagonal directions can be a fifth direction DR5 located between the first direction DR1 and the second direction DR2, and a fourth direction DR4 perpendicular to the fifth direction DR5.

[0174] The second display area DA2 includes multiple light-emitting areas EA in which multiple second pixel groups PG2 are respectively arranged, and multiple open areas OA in which the second pixel groups PG2 are not arranged. In an embodiment of the invention, three open areas OA can be arranged between two adjacent light-emitting areas EA in the first direction DR1. The multiple light-emitting areas EA can be alternated with the multiple open areas OA in the second direction DR2. One of the open areas OA is arranged between two adjacent light-emitting areas EA in the second direction DR2.

[0175] In such an embodiment, the number of multiple light-emitting regions EA in the second display area DA2 can be less than the number of multiple opening regions OA. In one embodiment, for example, the number of multiple light-emitting regions EA can be one-third the number of multiple opening regions OA. Therefore, in the same surface area of ​​the first display area DA1 and the second display area DA2, the number of second pixel groups PG2 can be one-quarter the number of first pixel groups PG1. As a result, the light transmittance of the second display area DA2 can be higher than that of the first display area DA1. In such an embodiment, the resolution of the second display area DA2 can be lower than that of the first display area DA1.

[0176] When with FIG. 5 When comparing the display panel 210 shown in the figure, FIG. 13 The display panel 211 shown in the figure has higher light transmittance.

[0177] FIG. 14 yes FIG. 13 An enlarged plan view of region VI, and FIG. 15 It is a diagram. FIG. 14 The diagram shows the connection relationship between the pixel circuit section and the wiring. FIG. 14 and FIG. 15 The same or similar elements shown have been adopted as described above. FIG. 9 and FIG. 10 The same reference numerals are used to denote the embodiments shown, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0178] Reference FIG. 14 The second display area DA2 includes multiple light-emitting areas EA in which multiple second pixel groups PG2 are respectively arranged, and multiple opening areas OA in which the second pixel groups PG2 are not arranged. FIG. 14 The diagram illustrates four light-emitting regions EA and twelve opening regions OA. In such an embodiment, the number of light-emitting regions EA can be one-third the number of opening regions OA. In an embodiment, as shown... FIG. 9 As shown, in the second display area DA2, the number of light-emitting areas EA can be the same as the number of opening areas OA. In alternative embodiments, such as FIG. 14 As shown, in the second display area DA2, the number of opening areas OA can be greater than the number of light-emitting areas EA. In such an embodiment, as... FIG. 14 As shown, the number of opening regions OA is increased to three times the number of light-emitting regions EA, and the connection structure of the first scan line to the fourth scan lines GLI1, GLW1, GLI2 and GLW2 is similar to FIG. 9 and FIG. 10The connection structure of the embodiment shown in the figure.

[0179] In an embodiment, such as FIG. 13 to FIG. 15 As illustrated, the display panel 211 includes first scan lines to fourth scan lines GLI1, GLW1, GLI2, and GLW2 connected to a plurality of second pixel groups PG2 disposed in the same row in a second display area DA2. The first scan line GLI1 and the second scan line GLW1 are connected to a first sub-pixel group SPG1, and the third scan line GLI2 and the fourth scan line GLW2 are connected to the second sub-pixel group SPG2. In such an embodiment, first pixel circuit portions to fourth pixel circuit portions CC1, CC2, CC3, and CC4 are connected to the first scan line GLI1 and the second scan line GLW1, and fifth pixel circuit portions to eighth pixel circuit portions CC5, CC6, CC7, and CC8 are connected to the third scan line GLI2 and the fourth scan line GLW2.

[0180] The third scan line GLI2 can be connected to the second scan line GLW1 outside the second display area DA2 (that is, in the peripheral area NAA). Therefore, the second scan line GLW1 is also electrically connected to the second sub-pixel group SPG2 via the third scan line GLI2. In an embodiment, as... FIG. 15 As illustrated, the second scan line GLW1 can be connected to the fifth to eighth pixel circuit sections CC5, CC6, CC7, and CC8 via the third scan line GLI2. In such an embodiment, the same signal can be applied to both the second scan line GLW1 and the third scan line GLI2.

[0181] In an embodiment, such as FIG. 14 and FIG. 15As illustrated, the first scan line GLI1 and the second scan line GLW1 extend in the first direction DR1 to overlap with the first pixel circuit portions CC1 to the fourth pixel circuit portions CC4. The first scan line GLI1, connected to the second pixel group PG2 in the nth row of a plurality of second pixel groups PG2, can be connected to the fourth scan line GLW2 in the second display area DA2. The fourth scan line GLW2 is connected to the second pixel group PG2 in the (n-1)th row. The fourth scan line GLW2, connected to the second pixel group PG2 in the nth row, is connected to the first scan line GLI3 in the second display area DA2. The first scan line GLI3 is connected to the second pixel group PG2 in the (n+1)th row. The first scan line GLI1 in the nth row can be connected to the fourth scan line GLW2 in the (n-1)th row in the second display area DA2 via a first bridging wire BL1. In such an embodiment, the fourth scan line GLW2, connected to the second pixel group PG2 in the nth row, can be connected to the first scan line GLI3 in the second display area DA2. The first scan line GLI3 is connected to the second pixel group PG2 in the (n+1)th row via a first bridging wire BL1. In such an embodiment, the first bridge cable BL1 can be arranged in the second display area DA2.

[0182] The third scan line GL12 and the fourth scan line GLW2 extend in the first direction DR1 to overlap with the fifth pixel circuit portion CC5 to the eighth pixel circuit portion CC8. One end of the second scan line GLW1, which connects to the second pixel group PG2 in the nth row of a plurality of second pixel groups PG2, is connected in the second display area DA2 to the third scan line GL12, which in turn connects to the second pixel group PG2 in the nth row. One end of the second scan line GLW1 in the nth row can be connected to the third scan line GL12 in the nth row via a second bridging wire BL2 in the second display area DA2. In such an embodiment, the second bridging wire BL2 can be arranged in the second display area DA2.

[0183] A third scan line GLI2 connected to the second pixel group PG2 in each row may extend in the first direction DR1 to overlap with an opening region OA located adjacent to the second pixel group PG2 in the same row. In an embodiment, the third scan line GLI2 may be bent and extend along the lower edge of the opening region OA. A second scan line GLW1 connected to the second pixel group PG2 in each row may have a structure that is cut within the opening region OA. In such an embodiment, the second scan line GLW1 may not overlap with the opening region OA.

[0184] The display panel 211 may further include first light-emitting control lines EL1 to fourth light-emitting control lines EL4, which are connected to a plurality of second pixel groups PG2 arranged in the same row. The first light-emitting control lines EL1 to fourth light-emitting control lines EL4 may extend in a first direction DR1. The first light-emitting control line EL1 and the third light-emitting control line EL3 may be connected to a first sub-pixel group SPG1, and the second light-emitting control line EL2 and the fourth light-emitting control line EL4 may be connected to the second sub-pixel group SPG2. The first light-emitting control line EL1 and the second light-emitting control line EL2 may extend in the first direction DR1 to overlap with an opening region OA located in the same row among a plurality of opening regions OA. In such an embodiment, the first light-emitting control line EL1 may be bent and extend along the upper edge of the opening region OA, and the second light-emitting control line EL2 may be bent and extend along the lower edge of the opening region OA.

[0185] Display panel 211 includes first to fourth data lines DL1, DL2, DL3, and DL4, which are connected to a plurality of second pixel groups PG2 disposed in the same column in a second display area DA2. The first to fourth data lines DL1, DL2, DL3, and DL4 extend in a second direction DR2 and are sequentially arranged in a first direction DR1. A first pixel circuit portion CC1 and a fifth pixel circuit portion CC5 are connected to the first data line DL1, and a second pixel circuit portion CC2 and a sixth pixel circuit portion CC6 are connected to the second data line DL2. A third pixel circuit portion CC3 and a seventh pixel circuit portion CC7 are connected to the third data line DL3, and a fourth pixel circuit portion CC4 and an eighth pixel circuit portion CC8 are connected to the fourth data line DL4.

[0186] The first data line DL1 to the fourth data line DL4 may extend in the second direction DR2 to overlap with one of the multiple open areas OA located in the same column. In one embodiment, for example, the first data line DL1 and the second data line DL2 may be bent and extend along the left edge of the open area OA, and the third data line DL3 and the fourth data line DL4 may be bent and extend along the right edge of the open area OA.

[0187] In an embodiment, such as FIG. 14 and FIG. 15As illustrated, the second scan line GLW1 and the fourth scan line GLW2 in the nth row can have a structure that is cut within the opening regions OA of a plurality of opening regions OA. In such an embodiment, the second scan line GLW1 and the fourth scan line GLW2 in the nth row are removed from the opening regions OA, which can improve the aperture ratio of the opening regions OA, thereby improving the light transmittance of the opening regions OA and the second display region DA2. In such an embodiment, the improved light transmittance of the second display region DA2 can improve the light transmittance of the electronic module 500 arranged below the second display region DA2. FIG. 1B The sensing sensitivity is shown in the figure.

[0188] FIG. 16 This is an equivalent circuit diagram of the first red pixel according to an embodiment of the present invention.

[0189] Reference FIG. 16 In an embodiment, the first pixel circuit portion CC1 of the first red pixel PXR1 may include a plurality of transistors T1 to T7, a capacitor CP, and a light-emitting element LD. Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a P-type transistor having a low-temperature polycrystalline silicon (LPTS) semiconductor layer, and each of the third transistor T3 and the fourth transistor T4 may be an N-type transistor having an oxide semiconductor layer. However, embodiments of the invention are not limited thereto, and alternatively, at least one of the first transistors T1 to the seventh transistor T7 may be an N-type transistor, and the remaining transistors among the first transistors T1 to the seventh transistor T7 may be P-type transistors.

[0190] The first data line DL1, the first P-type scan line GWP1, the first N-type scan line GWN1, the second N-type scan line GIN1, and the second P-type scan line GWPN1 can be connected to the first pixel circuit section CC1.

[0191] For ease of description, the first P-type scan line GWP1, the first N-type scan line GWN1, the second N-type scan line GIN1, and the second P-type scan line GWPN1 are respectively referred to as the first scan line GWP1, the second scan line GWN1, the third scan line GIN1, and the fourth scan line GWPN1.

[0192] The first scan line GWP1 and the fourth scan line GWPN1, which are the first to fourth scan lines GWP1, GWN1, GIN1, and GWPN1, can be connected to the second transistor T2 and the seventh transistor T7, which are P-type transistors, respectively. The second scan line GWN1 and the third scan line GIN1, which are the first to fourth scan lines GWP1, GWN1, GIN1, and GWPN1, can be connected to the third transistor T3 and the fourth transistor T4, which are N-type transistors, respectively.

[0193] FIG. 17 This is a plan view illustrating the connection relationship between the pixel circuit portion and the wiring according to an embodiment of the present invention.

[0194] Reference FIG. 16 and FIG. 17 In one embodiment, the first to eighth scan lines GWP1, GWN1, GIN1, GWPN1, GWP2, GWN2, GIN2, and GWPN2 can be connected to a plurality of second pixel groups PG2 disposed in the same row in the second display area DA2. The first to fourth scan lines GWP1, GWN1, GIN1, and GWPN1 are connected to the first sub-pixel group, and the fifth to eighth scan lines GWP2, GWN2, GIN2, and GWPN2 are connected to the second sub-pixel group. In such an embodiment, the first to fourth pixel circuit portions CC1, CC2, CC3, and CC4 are connected to the first to fourth scan lines GWP1, GWN1, GIN1, and GWPN1, and the fifth to eighth pixel circuit portions CC5, CC6, CC7, and CC8 are connected to the fifth to eighth scan lines GWP2, GWN2, GIN2, and GWPN2.

[0195] The first scan lines to the fourth scan lines GWP1, GWN1, GIN1, and GWPN1 extend in the first direction DR1 to overlap with the first pixel circuit portions CC1 to the fourth pixel circuit portions CC4. The first scan line GWP1, connected to the second pixel group PG2 in the nth row of the plurality of second pixel groups PG2, can be connected to the eighth scan line GWPN2, which is connected to the second pixel group PG2 in the (n-1)th row. The eighth scan line GWPN2, connected to the second pixel group PG2 in the nth row, is connected to the first scan line GWP1, which is connected to the second pixel group PG2 in the (n+1)th row.

[0196] The third scan line GIN1, which is connected to the second pixel group PG2 in the nth row among multiple second pixel groups PG2, can be connected to the sixth scan line GWN2, which is connected to the second pixel group PG2 in the (n-1)th row. The sixth scan line GWN2, which is connected to the second pixel group PG2 in the nth row, is connected to the third scan line GIN1, which is connected to the second pixel group PG2 in the (n+1)th row.

[0197] The second scan line GWN1, which is connected to the second pixel group PG2 in the nth row among multiple second pixel groups PG2, can be connected to the seventh scan line GIN2, which is also connected to the second pixel group PG2 in the nth row. The fourth scan line GWPN1, which is connected to the second pixel group PG2 in the nth row, is connected to the fifth scan line GWP2, which is also connected to the second pixel group PG2 in the nth row.

[0198] The third scan line GIN1, connected to the second pixel group PG2 in the nth row, is connected to the sixth scan line GWN2 via the first bridge wire BL1. The sixth scan line GWN2 is connected to the second pixel group PG2 in the (n-1)th row. The second scan line GWN1, connected to the second pixel group PG2 in the nth row, is connected to the seventh scan line GIN2 via the second bridge wire BL2. The seventh scan line GIN2 is connected to the second pixel group PG2 in the nth row.

[0199] The fourth scan line GWPN1, connected to the second pixel group PG2 in the nth row, is connected to the fifth scan line GWP2 via the third bridge wire BL3. The fifth scan line GWP2 is connected to the second pixel group PG2 in the nth row. The first scan line GWP1, connected to the second pixel group PG2 in the nth row, is connected to the eighth scan line GWPN2 via the fourth bridge wire BL4. The eighth scan line GWPN2 is connected to the second pixel group PG2 in the (n-1)th row.

[0200] The fifth scan line GWP2 and the seventh scan line GIN2, which are connected to the second pixel group PG2 in each row, can extend in the first direction DR1 to overlap with the opening regions OA in the same row among the multiple opening regions OA. In such an embodiment, the fifth scan line GWP2 and the seventh scan line GIN2 can be bent and extend along the lower edge of the opening region OA.

[0201] The second scan line GWN1 and the fourth scan line GWPN1, connected to the second pixel group PG2 in each row, can have a structure that is cut within the opening region OA. In such an embodiment, the second scan line GWN1 and the fourth scan line GWPN1 may not overlap with the opening region OA. The second scan line GWN1 and the fourth scan line GWPN1 are connected to the seventh scan line GIN2 and the fifth scan line GWP2, which are respectively connected to the second pixel group PG2 in the same row via the second bridging wire BL2 and the third bridging wire BL3.

[0202] In one embodiment, the sixth scan line GWN2 and the eighth scan line GWPN2 connected to the second pixel group PG2 in each row may have a structure that is cut within the opening region OA. In such an embodiment, the sixth scan line GWN2 and the eighth scan line GWPN2 may not overlap with the opening region OA. The sixth scan line GWN2 and the eighth scan line GWPN2 are connected to the first scan line GIN1 and the third scan line GWP1, which are respectively connected to the second pixel group PG2 in the next row via the first bridge wire BL1 and the fourth bridge wire BL4.

[0203] The display panel 211 may further include a first light-emitting control line EL1 and a second light-emitting control line EL2, which are connected to a plurality of second pixel groups PG2 arranged in the same row. The first light-emitting control line EL1 and the second light-emitting control line EL2 may extend in a first direction DR1. The first light-emitting control line EL1 may be connected to a first sub-pixel group, and the second light-emitting control line EL2 may be connected to a second sub-pixel group. The first light-emitting control line EL1 and the second light-emitting control line EL2 may extend in the first direction DR1 to overlap with an opening region OA located in the same row. In such an embodiment, the first light-emitting control line EL1 may be bent and extend along the upper edge of the opening region OA, and the second light-emitting control line EL2 may be bent and extend along the lower edge of the opening region OA.

[0204] In such an embodiment, the aperture ratio of the aperture region OA can be improved by removing the second scan line GWN1 and the fourth scan line GWPN1 from the aperture region OA, and by removing the sixth scan line GWN2 and the eighth scan line GWPN2 of the nth row from the aperture region OA, thereby improving the light transmittance of the aperture region OA and the second display region DA2. In this embodiment, the improved light transmittance of the second display region DA2 allows for improvements in the electronic module 500 disposed below the second display region DA2. FIG. 1B The sensing sensitivity is shown in the figure.

[0205] According to an embodiment of the present invention, the sensing sensitivity of an electronic module disposed below a second display area can be improved by reducing the number of scan lines passing through the opening area and by improving the light transmittance of the opening area and the second display area.

[0206] This invention should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be comprehensive and complete, and will fully convey the concept of the invention to those skilled in the art.

[0207] While the invention has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display panel, comprising: The display panel includes a first display area having a first transmittance value and a second display area having a second transmittance value that is higher than the first transmittance value. In the first display area, there are multiple first pixel groups, wherein each of the multiple first pixel groups includes a first pixel; In the second display area, a plurality of second pixel groups, wherein each of the plurality of second pixel groups includes a second pixel; and Multiple scan lines connected to the plurality of first pixel groups, and Multiple scan lines connected to the plurality of second pixel groups, The second display area includes multiple light-emitting areas and multiple opening areas. Multiple second pixel groups are respectively arranged in the multiple light-emitting areas. The multiple second pixel groups are not arranged in the multiple opening areas, and the second pixel groups are adjacent to the opening areas in the row direction. The scan line of the second pixel group in the nth row of the plurality of second pixel groups is cut and does not overlap with the opening region of the second pixel group in the nth row that is adjacent to it, and is connected to the scan line of the second pixel group in the (n-1)th row, the scan line of the second pixel group in the (n+1)th row, or other scan lines of the second pixel group in the nth row, where n is an integer greater than 1. The scan lines of the second pixel group in row (n-1) and the scan lines of the second pixel group in row (n+1) do not overlap with the opening region. The other scan lines of the second pixel group in the nth row are bent and extend along the lower edge of the opening region.

2. The display panel according to claim 1, wherein, Each of the plurality of second pixel groups includes a first sub-pixel group and a second sub-pixel group, and The multiple scan lines connected to the plurality of second pixel groups include: A first scan line and a second scan line, the first scan line and the second scan line being connected to the first sub-pixel group of the corresponding second pixel group among the plurality of second pixel groups; and The third scan line and the fourth scan line are connected to the second sub-pixel group of the corresponding second pixel group among the plurality of second pixel groups.

3. The display panel according to claim 2, wherein, The first scan line of the second pixel group in the nth row is cut off and does not overlap with the opening area of ​​the second pixel group in the nth row adjacent to it, and is connected to the fourth scan line of the second pixel group in the (n-1)th row adjacent to it in the nth row in the second display area. The fourth scan line of the second pixel group in the nth row is connected to the first scan line of the second pixel group in the (n+1)th row in the second display area.

4. The display panel according to claim 3, further comprising: A first bridging wire connects the fourth scan line of the second pixel group in the nth row to the first scan line of the second pixel group in the (n+1)th row. The first bridging wire is arranged in the second display area.

5. The display panel according to claim 4, wherein, The first bridging wire is arranged in a different layer than the layer in which the plurality of scan lines are arranged.

6. The display panel according to claim 2, wherein, The second scan line of the second pixel group in the nth row is connected to the third scan line of the second pixel group in the nth row in the second display area. The third scan line of the second pixel group in the nth row extends to overlap with the opening region of the second pixel group in the nth row that is adjacent to it. The second scan line of the second pixel group in the nth row is cut off and does not overlap with the opening region of the second pixel group in the nth row that is adjacent to it.

7. The display panel according to claim 6, further comprising: The second bridge wire connects the second scan line of the second pixel group in the nth row to the third scan line. The second bridging wire is arranged in the second display area.

8. The display panel according to claim 7, wherein, The second bridging wire is arranged in a different layer than the layer in which the plurality of scan lines are arranged.

9. The display panel according to claim 2, further comprising: A first light emission control line connected to the first sub-pixel group; as well as The second light emission control line is connected to the second sub-pixel group. Wherein, the first light-emitting control line extends in a first direction along the upper edge of the opening region adjacent to the first sub-pixel group, and The second light-emitting control line extends along the lower edge of the opening region.

10. The display panel according to claim 2, wherein, The first sub-pixel group includes a first red pixel, a first blue pixel, a first green pixel, and a second green pixel, and The second sub-pixel group includes a second red pixel, a second blue pixel, a third green pixel, and a fourth green pixel.

11. The display panel according to claim 10, wherein The first red pixel, the first green pixel, the first blue pixel, and the second green pixel are arranged sequentially in a first direction. The second blue pixel, the third green pixel, the second red pixel, and the fourth green pixel are arranged sequentially in the first direction, and The first sub-pixel group and the second sub-pixel group are arranged to be adjacent to each other in a second direction perpendicular to the first direction.

12. The display panel according to claim 11, wherein, The display panel includes multiple data lines connected to the plurality of second pixel groups. The multiple data lines include: A first data line connected to the first red pixel and the second blue pixel; A second data line connected to the first green pixel and the third green pixel; A third data line connected to the first blue pixel and the second red pixel; and A fourth data line connected to the second green pixel and the fourth green pixel.

13. The display panel according to claim 12, wherein, The first data line and the second data line extend in the second direction along the first side edge of the opening region adjacent to the second pixel group, and The third data line and the fourth data line extend along the second side edge of the opening region.

14. The display panel according to claim 2, wherein, The second pixel in the first sub-pixel group includes: The first transistor includes a first electrode connected to a first driving voltage, a second electrode electrically connected to the anode of a light-emitting element, and a control electrode. The second transistor includes a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to the first scan line. A third transistor, the third transistor comprising a first electrode connected to the second electrode of the first transistor, a second electrode connected to the control electrode of the first transistor, and a control electrode connected to the first scan line; and The fourth transistor includes a first electrode connected to the control electrode of the first transistor, a second electrode connected to the initialization voltage line, and a control electrode connected to the second scan line.

15. The display panel according to claim 2, wherein, The second pixel in the second sub-pixel group includes: The first transistor includes a first electrode connected to a first driving voltage, a second electrode electrically connected to the anode of a light-emitting element, and a control electrode. The second transistor includes a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to the third scan line; A third transistor, the third transistor comprising a first electrode connected to the second electrode of the first transistor, a second electrode connected to the control electrode of the first transistor, and a control electrode connected to the third scan line; and The fourth transistor includes a first electrode connected to the control electrode of the first transistor, a second electrode connected to the initialization voltage line, and a control electrode connected to the fourth scan line.

16. The display panel according to claim 1, wherein, One of the plurality of opening regions is arranged between two adjacent light-emitting regions in a first direction, and One of the plurality of opening regions is arranged between two adjacent light-emitting regions in the second direction.

17. The display panel according to claim 16, wherein, The number of the plurality of light-emitting areas in the second display area is the same as the number of the plurality of opening areas in the second display area.

18. The display panel according to claim 1, wherein, Three of the plurality of opening regions are arranged between two adjacent light-emitting regions in a first direction among the plurality of light-emitting regions.

19. The display panel according to claim 18, wherein, The number of the plurality of light-emitting areas in the second display area is one-third the number of the plurality of opening areas in the second display area.

20. A display device, comprising: A display panel, comprising: a first display area having a first resolution value; a second display area having a second resolution value lower than the first resolution value; a plurality of first pixel groups in the first display area; a plurality of second pixel groups in the second display area; a plurality of scan lines connected to the plurality of first pixel groups; and a plurality of scan lines connected to the plurality of second pixel groups, wherein each of the plurality of first pixel groups includes a first pixel, and each of the plurality of second pixel groups includes a second pixel; and The electronic module is located below the second display area. The second display area includes multiple light-emitting areas and multiple opening areas. The second pixel is arranged in the multiple light-emitting areas, but not in the multiple opening areas. Furthermore, the second pixel group is adjacent to the opening areas in the row direction. The scan line of the second pixel group in the nth row of the plurality of second pixel groups is cut and does not overlap with the opening area of ​​the second pixel group in the nth row that is adjacent to it, and is connected in the second display area to the scan line of the second pixel group in the (n-1)th row, the scan line of the second pixel group in the (n+1)th row, or other scan lines of the second pixel group in the nth row, where n is an integer greater than 1. The scan lines of the second pixel group in row (n-1) and the scan lines of the second pixel group in row (n+1) do not overlap with the opening region. The other scan lines of the second pixel group in the nth row are bent and extend along the lower edge of the opening region.

21. The display device according to claim 20, wherein, Each of the plurality of second pixel groups includes a first sub-pixel group and a second sub-pixel group, and The multiple scan lines connected to the plurality of second pixel groups include: A first scan line and a second scan line, the first scan line and the second scan line being connected to the first sub-pixel group of the corresponding second pixel group among the plurality of second pixel groups; and The third scan line and the fourth scan line are connected to the second sub-pixel group of the corresponding second pixel group among the plurality of second pixel groups.

22. The display device according to claim 21, wherein, The first scan line connected to the second pixel group in the nth row is cut and does not overlap with the opening area of ​​the second pixel group in the nth row adjacent to it, and in the second display area, the fourth scan line connected to the second pixel group in the (n-1)th row adjacent to it is connected to it. The fourth scan line of the second pixel group in the nth row is connected to the first scan line of the second pixel group in the (n+1)th row in the second display area.

23. The display device according to claim 21, wherein, The second scan line of the second pixel group in the nth row is connected to the third scan line of the second pixel group in the nth row in the second display area. The third scan line of the second pixel group in the nth row extends to overlap with the opening region of the second pixel group in the nth row that is adjacent to it. The second scan line of the second pixel group in the nth row is cut off and does not overlap with the opening region of the second pixel group in the nth row that is adjacent to it.

24. The display device according to claim 20, wherein, One of the plurality of opening regions is arranged between two adjacent light-emitting regions in a first direction, and One of the plurality of opening regions is arranged between two adjacent light-emitting regions in the second direction.

25. The display device according to claim 24, wherein, The number of the plurality of light-emitting areas in the second display area is the same as the number of the plurality of opening areas in the second display area.

26. The display device according to claim 20, wherein, Three of the plurality of opening regions are arranged between two adjacent light-emitting regions in a first direction among the plurality of light-emitting regions.

27. The display device according to claim 26, wherein, The number of the plurality of light-emitting areas in the second display area is one-third the number of the plurality of opening areas in the second display area.

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