Boron nitride layer, apparatus including the same, and method for manufacturing boron nitride layer.

Abstract

A boron nitride layer, an apparatus comprising the same, and a method for manufacturing the boron nitride layer are provided. The boron nitride layer comprises a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0135755, filed on October 29, 2019, and Korean Patent Application No. 10-2020-0054096, filed on May 6, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to boron nitride layers, apparatus (equipment) including boron nitride layers, and methods for manufacturing boron nitride layers. Background Technology

[0004] Electronic and semiconductor devices can be manufactured primarily by combining and connecting semiconductors, insulators, and conductors. For example, electronic and semiconductor devices can be arranged to form multiple unit devices on a semiconductor substrate, and then insulating layers (interlayer insulation layers) and electrode lines are repeatedly stacked on top of them to manufacture various integrated circuits.

[0005] However, during the fabrication or operation of such devices, the temperature of the constituent layers can rise and electrical stress can be generated due to the application of voltage / current. This can lead to the diffusion of material (atoms) between adjacent constituent layers, which can degrade device performance and reduce its reliability and durability. As the integration density of such devices increases, addressing the problems caused by material diffusion between constituent layers becomes more difficult. Furthermore, even without material diffusion, signal delay can occur due to mutual interference caused by the electric field between lines in highly integrated devices. Summary of the Invention

[0006] A boron nitride layer having a dielectric constant and a method for manufacturing the boron nitride layer are provided.

[0007] An apparatus is provided that includes a boron nitride layer having a dielectric constant.

[0008] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0009] According to one aspect of this disclosure, the boron nitride layer comprises a boron nitride compound, and the boron nitride layer has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

[0010] In some embodiments, the boron to nitrogen ratio of the boron nitride layer may be from about 0.9 to about 1.1.

[0011] In some embodiments, the boron nitride layer may be non-porous.

[0012] In some embodiments, the boron nitride layer may include at least one pore.

[0013] In some embodiments, the boron nitride layer may have a density of about 1 to about 3 g / cm³. 3 . mass density.

[0014] In some embodiments, the breakdown field of the boron nitride layer can be approximately 4 MΩcm. -1 Or larger.

[0015] In some embodiments, the breakdown field of the boron nitride layer can be approximately 10 MΩcm. -1 Or smaller.

[0016] In some embodiments, the root mean square (RMS) roughness of the boron nitride layer can be about 0.3 to about 0.6 nm.

[0017] In some embodiments, the boron nitride layer may have a band gap of about 6.00 eV or less.

[0018] In some embodiments, the nitrogen and boron in the boron nitride compound may include sp... 2 key.

[0019] In some embodiments, the boron nitride layer may have a hydrogen content ratio of about 10% or less.

[0020] In some implementations, the boron nitride layer may have a dielectric constant of about 2.3 or less at an operating frequency of 100 kHz.

[0021] In some embodiments, the boron nitride layer may be amorphous (non-crystalline).

[0022] In some embodiments, the boron nitride layer may have a dielectric constant of about 2.3 to about 2.5 at an operating frequency of 100 kHz.

[0023] In some embodiments, the boron nitride layer may include nanocrystals.

[0024] According to another embodiment, a method for manufacturing a boron nitride layer includes: preparing a substrate; and using plasma to grow a boron nitride layer on the substrate at a temperature of about 700°C or lower using a reaction gas including a boron nitride source.

[0025] In some implementations, preparing the substrate may include pre-treating the substrate.

[0026] In some embodiments, the plasma may include at least one of the following: inductively coupled plasma, capacitively coupled plasma, microwave plasma, plasma enhancement method, electron cyclotron resonance plasma, arc discharge plasma, and spiral wave (spiral) plasma.

[0027] In some implementations, the boron nitride layer may have a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

[0028] In some embodiments, the boron nitride layer may include at least one of an amorphous structure and nanocrystals. Attached Figure Description

[0029] The above and other aspects, features, and advantages of some embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0030] Figure 1 This is a diagram schematically showing a system for manufacturing a boron nitride layer according to an embodiment;

[0031] Figures 2A to 2C This is a reference diagram illustrating a method for manufacturing a boron nitride layer according to an embodiment;

[0032] Figures 3A to 3D This is a diagram showing the atomic structure of the boron nitride layer according to an embodiment;

[0033] Figure 4A This pertains to the Raman spectral results of the boron nitride layer according to the embodiment;

[0034] Figure 4B The Fourier transform infrared (FTIR) spectroscopic results for the boron nitride layer according to the embodiment are shown.

[0035] Figure 5 This is a graph showing the X-ray photoelectron spectroscopy (XPS) profile results of the amorphous boron nitride layer according to the embodiment;

[0036] Figure 6 The FTIR spectral results for the amorphous boron nitride layer according to the embodiment are shown;

[0037] Figure 7A The high-resolution Rutherford backscattering spectroscopy (HR-RBS) distribution results for the amorphous boron nitride layer according to the embodiment are shown;

[0038] Figure 7B The distribution results of high-resolution elastic recoil detection analysis (HR-ERDA) of the amorphous boron nitride layer according to the embodiment are shown;

[0039] Figure 7CThe composition ratio of the boron nitride layer is shown using HR-RBS and HR-ERDA spectra.

[0040] Figure 8A Raman spectral results are shown for the boron nitride layer transferred onto the substrate according to the embodiment;

[0041] Figure 8B This is an XPS image of the transferred boron nitride layer according to the embodiment.

[0042] Figure 9A The results of measuring the dielectric constant of the amorphous boron nitride layer according to the embodiment are shown;

[0043] Figure 9B The results regarding the dielectric constant of the boron nitride layer obtained by using elliptic polarization spectroscopy (SE) are shown.

[0044] Figure 10A These are simulation results regarding the mass density of the amorphous boron nitride layer according to the embodiments;

[0045] Figure 10B It is a graph showing the relationship between the dielectric constant and mass density of various materials;

[0046] Figure 11 It is a graph showing the relationship between the dielectric constant and the breakdown field of various materials;

[0047] Figure 12 This is a table summarizing the properties of the amorphous boron nitride layer and the hexagonal boron nitride layer according to the embodiments.

[0048] Figure 13 The energy dispersive spectroscopy (EDS) line distribution is obtained after thermal diffusion testing of the amorphous boron nitride layer according to the embodiment.

[0049] Figure 14(i) is a cross-sectional transmission electron microscope (TEM) image of the TiN layer after thermal diffusion testing, which serves as a comparative example, and Figure 14(ii) is the EDS line distribution of the TiN layer after thermal diffusion testing, which serves as a comparative example.

[0050] Figure 15 This shows the results of the breakdown bias of the amorphous boron nitride layer according to the embodiment, based on temperature.

[0051] Figure 16A This is an image of selective region electron diffraction of a boron nitride layer grown at approximately 700°C according to an embodiment.

[0052] Figure 16B This is a high-magnification TEM image of a boron nitride layer grown at approximately 700°C according to an embodiment.

[0053] Figure 16C The fast Fourier transform results of a boron nitride layer grown at approximately 700°C according to an embodiment are shown.

[0054] Figure 17 The results pertain to the Raman spectra of the boron nitride nanocrystal (nanocrystalline) layer according to the embodiment.

[0055] Figure 18 The FTIR spectral results for the nanocrystalline boron nitride layer according to the embodiment are shown;

[0056] Figure 19 This is a graph illustrating the XPS distribution results of the nanocrystalline boron nitride layer according to the embodiment;

[0057] Figure 20 This is a diagram illustrating an example of using a nanocrystalline boron nitride layer as a diffusion barrier layer according to an embodiment;

[0058] Figure 21 This is a graph showing the dielectric constant of the nanocrystalline boron nitride layer for each frequency according to an embodiment;

[0059] Figure 22A This is an atomic force microscope (AFM) image of a boron nitride layer grown at approximately 400°C.

[0060] Figure 22B This is an AFM image of a boron nitride layer grown at approximately 700°C.

[0061] Figure 23 This is a diagram illustrating a multilayer structure including a diffusion barrier layer according to one embodiment;

[0062] Figure 24 This is a cross-sectional view illustrating a multilayer structure including a diffusion barrier layer according to another embodiment;

[0063] Figure 25 This is a reference diagram illustrating a transistor including a boron nitride layer according to an embodiment;

[0064] Figure 26 This is a reference diagram illustrating a semiconductor device including an interconnect structure according to an embodiment;

[0065] Figure 27 This is a diagram illustrating a field-effect transistor including a boron nitride layer according to an embodiment;

[0066] Figure 28 This is a diagram illustrating a vertical field-effect transistor including a boron nitride layer according to an embodiment;

[0067] Figure 29 This is a diagram illustrating a finned transistor including a boron nitride layer according to an embodiment;

[0068] Figure 30A This is a diagram illustrating a portion of a display device including a boron nitride layer according to an embodiment;

[0069] Figure 30B It is along Figure 30A Cross-sectional views of lines AA′ and BB′; and

[0070] Figure 31 This is a diagram illustrating a NAND flash memory device including a boron nitride layer according to an embodiment. Detailed Implementation

[0071] The embodiments illustrated in the accompanying drawings will now be described in detail, with the same reference numerals always denoteing the same elements. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerated items. Expressions such as "at least one of" modify the entire list of elements when preceding or following it, without modifying any individual element of the list.

[0072] The embodiments illustrated in the accompanying drawings will now be described in detail. In the drawings, the same reference numerals consistently denote the same elements. Furthermore, for ease of explanation and clarity, the dimensions of the layers shown in the drawings may be enlarged. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein.

[0073] It will also be understood that when an element is referred to as being "on" or "above" another element, the element may be in direct contact with said other element, or there may be other intermediate elements present. Unless the meaning is clearly different in the context, singular expressions include plural expressions. It should be understood that when a component is described as "comprising" or "including" an element in the specification, other elements are not excluded from said component unless otherwise defined, and said component may further include other elements. In the context, the use of the term "the" and similar references is interpreted to cover both the singular and plural.

[0074] In the following embodiments, a boron nitride layer, a method for manufacturing the boron nitride layer using plasma, and an apparatus including the boron nitride layer will be described.

[0075] Figure 1 This is a schematic diagram illustrating a system 10 for manufacturing a boron nitride layer according to an embodiment. (See reference) Figure 1The system 10 for fabricating a boron nitride layer may include: a chamber 11 comprising a space in which a reactive gas for growing the boron nitride layer can move; a supply source 12 for supplying the reactive gas to the chamber 11; a flow controller 13 for controlling the mass flow rate of the reactive gas moving to the chamber 11; a plasma device 14 for generating plasma in the chamber 11; and a furnace 15 for regulating the temperature of the chamber 11 and for depositing boron nitride in the chamber 11. Additionally, the device for regulating the temperature may be a hot-wall type in which radiant heat is transferred to the substrate, or a cold-wall type in which the substrate is directly heated.

[0076] Figures 2A to 2C This is a reference diagram illustrating a method for manufacturing a boron nitride layer according to an embodiment.

[0077] First, a substrate S can be prepared in chamber 11 of system 10. The substrate S may include at least one of the following: a group IV semiconductor material, a semiconductor compound, an insulating material, and a metal. As a specific example, the substrate S may include a group IV semiconductor material, such as Si, Ge, or Sn. Alternatively, the substrate S may include at least one of the following: Si, Ge, C, Zn, Cd, Al, Ga, In, B, N, P, S, Se, As, Sb, Te, Ta, Ru, Rh, Ir, Co, Ti, W, Pt, Au, Ni, and Fe. Furthermore, the substrate S, as a SiCOH-based component, may further include, for example, N and F, and may also include pores to reduce permittivity (dielectric constant). Additionally, the substrate S may further include dopants. The materials of the substrate S described above are merely examples.

[0078] The substrate S can be pretreated before being placed in chamber 11. For example, the substrate S can be immersed in an organic solvent such as acetone, sonicated, and then cleaned with isopropanol (IPA) and nitrogen. The surface of the cleaned substrate S can be treated with plasma such as oxygen, hydrogen, NH3, etc., to remove residual carbon impurities on the surface. Alternatively, the substrate S can be immersed in an HF solution to remove natural oxides or residual HF solution can be removed using anhydrous ethanol and N2 gas.

[0079] The process temperature for growing the boron nitride layer can be approximately 700°C or lower, which is lower than the temperature used for chemical vapor deposition processes. For example, the process temperature inside chamber 11 can be approximately 400°C. Before increasing the process temperature, the process pressure for growing the boron nitride layer can be set to approximately 2 Torr or less. For example, the process pressure can be 10... -2 Or smaller.

[0080] Next, a reaction gas for growing the boron nitride layer can be injected into chamber 11. Here, the reaction gas can be a source of boron nitride for growing the boron nitride layer, and can be a source including both nitrogen and boron, such as borazine (B3N3H6) or ammonia-borane (NH3-BH3). Alternatively, the reaction gas can include a nitrogen source containing nitrogen and a boron source containing boron. The nitrogen source can include at least one of the following: ammonia (NH3) or nitrogen gas (N2), and the boron source can include at least one of the following: BH3, BF3, BCl3, B2H6, (CH3)3B, and (CH3CH2)3B.

[0081] The reactant gas may further include an inert gas. The inert gas may include at least one of the following: argon, neon, helium, krypton, and xenon. The reactant gas may further include hydrogen. Additionally, the mixing ratio of the reactant gases injected into chamber 11 may be varied depending on the growth conditions of the boron nitride layer.

[0082] The flow controller 13 controls the flow rate of the reactive gases flowing into the chamber 11. The flow rate of the boron nitride source can be lower than that of the other reactive gases. When the boron nitride layer is grown using plasma, the mixing ratio of the reactive gases injected into the chamber 11, i.e., the volume ratio of the boron nitride source to the inert gas, can be, for example, about 1:10 to 5000, and the volume ratio of the boron nitride source, the inert gas, and hydrogen can be, for example, about 1:10 to 5000:10 to 500.

[0083] Because the source of boron nitride is significantly smaller in proportion than other reactant gases, the crystallinity of boron nitride can be weak. Therefore, the boron nitride layer according to the embodiments can be formed with an amorphous structure or a nanoscale crystal structure.

[0084] When an excess of boron nitride source is supplied, the boron nitride layer can grow irregularly, and precursors can be adsorbed, thus the flow rate of the boron nitride source can be low.

[0085] For example, during the growth of a boron nitride layer, the flow controller 13 can control the flow rate of the boron nitride source to 0.05 sccm, the flow rate of the inert gas to 50 sccm, and the flow rate of hydrogen to 20 sccm. The flow controller 13 controls the flow rates of the boron nitride source and the inert gas, but is not limited to these. The flow controller 13 can also control only the flow rate of the boron nitride source.

[0086] Subsequently, when a boron nitride source is introduced into chamber 11, plasma device 14 can generate plasma within chamber 11. Here, the power used for plasma generation can be from about 10W to about 4000W. For example, the power used for plasma generation is about 30W, but it is not limited to this.

[0087] The plasma device 14 can be an apparatus that provides plasmas including, but is not limited to, inductively coupled plasma, capacitively coupled plasma, microwave plasma, plasma enhancement methods, electron cyclotron resonance plasma, arc discharge plasma, and spiral wave plasma. For example, an inductively coupled plasma device can provide a plasma in which energy is supplied by a current generated by electromagnetic induction (i.e., a time-varying magnetic field). When the power used to generate the plasma is applied from the plasma device 14 to the interior of the chamber 11, an electric field can be induced inside the chamber 11. As described above, when an electric field is induced in the presence of injected reactive gases, plasma for the growth of boron nitride (BN) layers can be formed.

[0088] refer to Figure 2B Activated nitrogen (N) and activated boron (B) can be generated by plasma of a reactant gas containing a mixture of boron nitride, an inert gas, and hydrogen, and can be adsorbed onto the surface of substrate S. Furthermore, the inert gas plasma can continuously induce the activation of substrate S, thus accelerating the adsorption of activated nitrogen (N) and activated boron (B) on the surface of substrate S. Activated nitrogen (N) and activated boron (B) can be adsorbed as amorphous substances. Even when activated nitrogen and boron are bound together, due to their small amounts, they can be adsorbed as nanoscale crystals.

[0089] refer to Figure 2C Furthermore, even at low temperatures, the adsorption of activated nitrogen (N) and activated boron (B) on the surface of the substrate S is accelerated, thus allowing the boron nitride layer (BN) to grow on the surface of the substrate S. According to this embodiment, since the boron nitride layer (BN) grows directly on the surface of the substrate S at low temperatures (e.g., at 700°C or lower) with a low proportion of activated nitrogen (N) and activated boron (B), the grown boron nitride layer (BN) can exhibit weak crystallinity.

[0090] The boron nitride (BN) layer according to the embodiments can be grown amorphously or as nanoscale crystals. Although crystals are present in the boron nitride layer BN formed amorphously, crystals of 3 nm or smaller may be present, and the boron nitride layer BN formed as nanocrystals may include crystals having a size of about 100 nm or smaller. More specifically, the boron nitride layer BN may include crystals having a size of about 0.5 nm to about 100 nm.

[0091] The thickness of the boron nitride (BN) layer according to the embodiments can be about 100 nm or less. For example, the thickness of the boron nitride (BN) layer can be 50 nm or less. Furthermore, because the boron nitride (BN) layer comprises amorphous or nanocrystalline materials, it can be formed as a thin layer. However, the boron nitride (BN) layer is not limited to this. Because the boron nitride (BN) layer comprises amorphous or nanocrystalline materials, it can be formed as a thick layer. The thickness of the boron nitride (BN) layer can be selected according to the application field.

[0092] After growth, the plasma can be shut off, and the furnace 15 can be gradually cooled at room temperature. For example, the furnace 15 can be cooled at room temperature by introducing 20 sccm of H2 gas into the chamber 11.

[0093] Devices can be fabricated by forming an additional layer on the boron nitride (BN) layer manufactured using the method described above. Alternatively, the manufactured boron nitride (BN) layer can be transferred to another layer. Hydrofluoric acid transfer technology can be applied during the transfer, but this disclosure is not limited thereto.

[0094] like Figures 2A to 2C The boron nitride (BN) layer fabricated as shown may be amorphous. Although the boron nitride (BN) layer according to the embodiments comprises crystalline material, it may comprise nanoscale crystals. Since the low-density activated nitrogen and boron are grown directly at low temperatures, the crystallinity may be weak. The lower at least one of the growth temperature and process pressure, the higher the amorphous content.

[0095] In the boron nitride layer BN according to the embodiments, the ratio of nitrogen to boron can be substantially the same. The ratio of boron to nitrogen can be from about 0.9 to about 1.1. Furthermore, the boron nitride layer BN may contain hydrogen, but the hydrogen content in the boron nitride layer BN can be low. For example, the hydrogen content can be about 10% or less. The boron nitride layer BN is chemically stable due to its low hydrogen content.

[0096] The boron nitride layer BN according to the embodiments may have a dielectric constant of 3 or less at an operating frequency of about 100 kHz (here, dielectric constant may refer to the relative dielectric constant with respect to vacuum or air). For example, the amorphous boron nitride layer a-BN may have a dielectric constant of 2.3 or less at an operating frequency of about 100 kHz, and the nanocrystalline boron nitride layer nc-BN may have a dielectric constant of 2.3 to 2.5 at an operating frequency of about 100 kHz.

[0097] Furthermore, the mass density of the boron nitride layer BN according to the embodiment can vary depending on the dielectric constant of the boron nitride layer BN. For example, the boron nitride layer BN according to the embodiment can have a mass density of 1 to 3 g / cm³. 3 . mass density.

[0098] Furthermore, the breakdown field of the boron nitride layer BN according to the embodiment can be 4 MVcm. -1 Or even greater. Specifically, the breakdown field of the boron nitride (BN) layer according to the embodiment can be about 5 to about 10 MVcm. -1 .

[0099] The boron nitride layer BN according to the embodiments may have a smooth surface. For example, the surface of the boron nitride layer BN may have a root mean square (RMS) roughness value of about 0.3 to about 0.6 nm. The surface roughness of the boron nitride layer BN may be determined by the flow rate of the boron nitride source.

[0100] To obtain the properties of the boron nitride (BN) layer, the BN layer was deposited using inductively coupled plasma-chemical vapor deposition (ICP-CVD) at approximately 10 °C. -4 The process pressure and process temperature of approximately 400°C are used to grow the material on a Si substrate.

[0101] Figures 3A to 3D This is a diagram showing the atomic structure of a boron nitride layer grown at a process temperature of approximately 400°C according to an embodiment. Figure 3A These are low-magnification transmission electron microscopy (TEM) images of the boron nitride layer, and Figure 3B This is an image of selective region electron diffraction of the boron nitride layer. Figure 3B The image shows a diffraction pattern without identifiable crystal rings. Figure 3C This is a high-magnification TEM image of a boron nitride layer in which the atoms are arranged in a disordered manner. Additionally, Figure 3D This is a graph showing the results of the Fast Fourier Transform of the boron nitride layer, and also showing a typical diffusion diffraction pattern of an amorphous film. Therefore, it can be confirmed that the boron nitride layer manufactured by the manufacturing method according to the embodiment is amorphous.

[0102] Figure 4A The results are Raman spectra of the boron nitride layers according to the embodiments. SiO2 / Si is the Raman spectrum measured relative to the substrate (e.g., a substrate including SiO2 / Si) itself, and in Example 1, the Raman spectrum was measured after forming the boron nitride layer a-BN according to the embodiments on a substrate including SiO2 / Si, and in Tri-hBN, the Raman spectrum was measured after epitaxially growing three hexagonal boron nitride layers on a substrate including SiO2 / Si.

[0103] like Figure 4A As shown, the Raman spectra of the substrate and the Raman spectra of the boron nitride layer according to the embodiment are similar to each other. When comparing the amorphous boron nitride layer a-BN and the tri-hexagonal boron nitride layer Tri-hBN according to the embodiment, it can be confirmed that at 1373 cm⁻¹... -1 The peaks present in the three hexagonal boron nitride layers Tri-hBN are not present in the amorphous boron nitride layer a-BN. This could mean that the boron nitride layer a-BN according to the embodiment does not have the crystallinity contained in the hexagonal boron nitride layer Tri-hBN.

[0104] Figure 4B The Fourier transform infrared (FTIR) spectra of the boron nitride layer according to the embodiment are shown. The FTIR spectra of the boron nitride layer were measured using s-polarized radiation at an incident angle of 60°. Figure 4BAs shown, it can be confirmed that in the boron nitride layer according to the embodiment, there exists a light at 1370 cm⁻¹ at an intensity at which the transverse optical mode (transverse light mode) is present. -1 The absorption peak is near 1570 cm⁻¹. -1 Another absorption peak exists nearby. At 1570 cm⁻¹ -1 The presence of nearby peaks indicates that the boron nitride layer according to the embodiment has amorphous properties.

[0105] Based on the experimental results, it can be confirmed that the boron nitride layer formed at a process temperature of approximately 400°C is amorphous. In the following text, the boron nitride layer formed at a process temperature of approximately 400°C using the manufacturing method according to the embodiment is referred to as the amorphous boron nitride layer a-BN.

[0106] Figure 5 This is a graph illustrating the X-ray photoelectron spectroscopy (XPS) distribution results of the amorphous boron nitride layer a-BN according to the embodiment. Figure 5 As shown, the 1s peaks for boron and nitrogen are confirmed to be 190.4 eV and 397.9 eV, respectively. This can be seen from... Figure 5 XPS distribution confirmed that, based on the peak sizes of boron and nitrogen, the atomic ratio of boron to nitrogen is approximately 1:1.08, and includes sp... 2 Combine.

[0107] Figure 6 The FTIR spectra of the amorphous boron nitride layer a-BN according to the embodiment are shown. Figure 6 As shown, no peaks were observed in the FTIR spectrum at the frequencies corresponding to BH and NH.

[0108] Figure 7A The high-resolution Rutherford backscattering spectroscopy (HR-RBS) distribution results for the amorphous boron nitride layer a-BN according to the embodiment are shown, and Figure 7B The distribution results of high-resolution elastic recoil detection analysis (HR-ERDA) for the amorphous boron nitride layer a-BN according to the embodiment are shown. Figure 7A The results are shown in the energy range of 240-400 keV, and Figure 7B The results measured in the energy range of 52-68 keV are shown, where it can be seen that Si and O atoms as substrate atoms were measured, and B and N atoms as boron nitride layer atoms were measured. Additionally, hydrogen was also measured.

[0109] Figure 7C The compositional ratios of the boron nitride layer calculated using HR-RBS and HR-ERDA spectra are shown. Figure 7C As shown, the ratio of boron to nitrogen can be confirmed to be approximately 1.04:1. Additionally, the hydrogen content in the boron nitride layer can be confirmed to be approximately 5.5%.

[0110] The properties of the boron nitride layer grown on the substrate have been demonstrated above. The boron nitride layer according to the embodiments can be grown on a substrate including a catalyst material and then transferred to another substrate.

[0111] Figure 8A and 8B This is a diagram illustrating the properties of the transferred boron nitride layer according to the embodiment. Figure 8A Raman spectral results of a boron nitride layer transferred to a SiO2 substrate according to an embodiment are shown. The boron nitride layer was grown on a copper foil at a plasma power of approximately 30 W and a growth temperature of approximately 300 °C. The grown boron nitride layer was then transferred to the SiO2 substrate, and Raman spectra were obtained. It was confirmed that the Raman spectrum of the SiO2 substrate on which no boron nitride layer was grown was similar to that of the transferred boron nitride layer. This confirms that the transferred boron nitride layer is also amorphous, like the SiO2 substrate.

[0112] Figure 8B This is based on XPS images of the transferred boron nitride layer in the embodiment. For example... Figure 8B As shown, it can be confirmed that, in the same manner as boron nitride layers grown at a process temperature of approximately 400°C, the 1s peaks for boron and nitrogen are 190.4 eV and 397.9 eV, respectively. This can be seen from... Figure 8B XPS distribution confirmed that, based on the peak sizes of boron and nitrogen, the atomic ratio of boron to nitrogen is approximately 1:1.08, and includes sp... 2 Therefore, it can be confirmed that even when the substrate on which the growth is carried out is a catalyst substrate, an amorphous boron nitride layer a-BN can be obtained by growing a boron nitride layer at low temperature.

[0113] The dielectric properties of amorphous boron nitride (a-BN) layers are described below. The dielectric constant is a physical measure of how easily an electric dipole is induced in a material by an applied electric field. The dielectric constant of air or vacuum is 1, but the polarization in solid-state materials is generated by the dipole, atomic, and electronic components (compositions, assemblies) most relevant to high-performance electronics. The contributions from these can be measured as a function of frequencies ranging from about 10 kHz to about 30 MHz. The dielectric constant can be measured using capacitance-frequency measurements on metal-insulator-metal (MIM) structures. For comparison, the relative dielectric constants for amorphous boron nitride (a-BN) layers and hexagonal boron nitride (h-BN) layers are measured at different frequencies.

[0114] Figure 9A The results of measuring the dielectric constant of an amorphous boron nitride layer a-BN grown at a growth temperature of about 300°C according to an embodiment are shown. Figure 9A The dielectric constant shown is the average of more than 50 measurements. Figure 9AAs shown, the dielectric constants of the amorphous boron nitride layer a-BN and the hexagonal boron nitride layer h-BN are inversely proportional to the operating frequency. It is confirmed that at an operating frequency of approximately 10 kHz, the dielectric constants of the amorphous boron nitride layer a-BN and the hexagonal boron nitride layer h-BN are approximately 2 and 3.5, respectively. It is confirmed that at an operating frequency of approximately 100 kHz, the dielectric constants of the amorphous boron nitride layer a-BN and the hexagonal boron nitride layer h-BN are approximately 1.78 and 3.28, respectively. It is confirmed that the dielectric constant of the amorphous boron nitride layer a-BN decreases to approximately 1.16 at a frequency of 1 MHz, which is close to the dielectric constant of air or vacuum. This is because the low dielectric constant of the amorphous boron nitride layer a-BN is attributed to the nonpolar bonds between BN layers and the lack of order (which prevents dipole alignment even at high frequencies).

[0115] The refractive index n of the boron nitride layer can be measured using elliptic polarization spectroscopy (SE), and its dielectric constant k can be determined using the relationship between the refractive index n and the dielectric constant k (i.e., n... 2 =k) ​​to obtain.

[0116] Figure 9B The results of the dielectric constant of the boron nitride layer measured using the SE method are shown. The refractive indices of the hexagonal boron nitride layer h-BN and the amorphous boron nitride layer a-BN at a wavelength of 633 nm, measured using the SE method, are 2.16 and 1.37, respectively. Therefore, it can be confirmed that the dielectric constants of the hexagonal boron nitride layer h-BN and the amorphous boron nitride layer a-BN are 4.67 and 1.88, respectively, and are close to the values ​​obtained using electrical measurements at 100 kHz.

[0117] Figure 10A This is a simulation of the mass density of an amorphous boron nitride layer a-BN according to an embodiment. An amorphous boron nitride layer a-BN with a thickness of 40 nm was grown on a Si substrate, and then the mass density was simulated along the z-direction, which is the thickness direction of the amorphous boron nitride layer a-BN on the Si substrate. Figure 10A As shown, it can be confirmed that the mass density of the amorphous boron nitride layer a-BN is approximately 2 g / cm³. 3 It can be seen that the amorphous boron nitride layer a-BN has a low dielectric constant and high density, which prevents the mechanical strength from deteriorating.

[0118] Figure 10B This is a graph showing the relationship between the dielectric constant and mass density of various materials. For example... Figure 10BAs shown, the dielectric constant and mass density of a material are generally proportional. Therefore, materials with low dielectric constants tend to have low mass density and low mechanical strength. However, amorphous boron nitride layer a-BN, with a dielectric density of approximately 2, has a mass density of approximately 2, which is relatively higher than other materials. Therefore, amorphous boron nitride layer a-BN can exhibit high mechanical strength.

[0119] Meanwhile, as another method for implementing low-dielectric materials, the material is made porous to utilize the low dielectric constant of air. However, this reduces the material's density, which in turn leads to poor mechanical strength. However, amorphous boron nitride (a-BN) layers exhibit good mechanical strength because a-BN layers are not porous, as described above. Figures 3A to 3D As shown in the diagram, at least one pore can be formed in the amorphous boron nitride layer a-BN. Multiple pores can be formed in the amorphous boron nitride layer a-BN, and thus the dielectric constant can be further reduced. In some cases, other materials can be filled into the pores of the amorphous boron nitride layer a-BN. Even if the pores of the amorphous boron nitride layer a-BN are filled with other materials, the utilization of the amorphous boron nitride layer a-BN can be increased without significantly increasing the dielectric constant.

[0120] Figure 11 This is a graph showing the relationship between the dielectric constant and breakdown field of various materials. For example... Figure 11 As shown, it can be confirmed that the dielectric constant and the breakdown field are proportional. Figure 11 As shown, it can be confirmed that the breakdown field of the amorphous boron nitride layer a-BN is higher than that of other materials with a dielectric constant close to 2.

[0121] Figure 12 This is a table summarizing the properties of the amorphous boron nitride layer a-BN and the hexagonal boron nitride layer according to the embodiments. For example... Figure 12 As shown, it can be confirmed that the amorphous boron nitride layer a-BN has a dielectric constant of 2 or lower at operating frequencies of 100 kHz or higher. Furthermore, the breakdown field of the amorphous boron nitride layer a-BN is 7.3 MV-cm. -1 This is much larger than the breakdown field of a hexagonal boron nitride layer, and its refractive index for electromagnetic waves at 633 nm is 2 or lower.

[0122] Due to the electrical and dielectric properties described above, amorphous boron nitride (a-BN) layers can be used as interlayer insulating layers. In particular, when amorphous boron nitride (a-BN) layers are used as interlayer insulating layers between conductive materials, parasitic capacitance can be reduced.

[0123] In addition, since amorphous boron nitride layer a-BN is chemically stable, it can be used as a diffusion barrier.

[0124] For example, a key step in the back-end of line (BEOL) CMOS fabrication of logic and memory devices is the deposition of a diffusion barrier between a low-dielectric material and metal interconnects to prevent metal atoms from migrating into the insulator. Ideally, if the low-dielectric material can also be used as a diffusion barrier, it is not necessary to deposit a separate diffusion barrier. According to embodiments, amorphous boron nitride (a-BN) layers can be used as diffusion barriers due to their low dielectric constant and large breakdown field.

[0125] Figure 13 This is the energy dispersive spectroscopy (EDS) line distribution after thermal diffusion testing of the amorphous boron nitride layer a-BN according to the embodiment. According to the embodiment, an amorphous boron nitride layer a-BN with a thickness of 3 nm is formed on a Si substrate, and an 80 nm cobalt layer is deposited on the amorphous boron nitride layer a-BN according to the embodiment. The diffusion barrier performance of the amorphous boron nitride layer a-BN is tested by annealing the Co / a-BN / Si device in vacuum at 600°C for 1 hour.

[0126] like Figure 13 As shown, it can be confirmed that the cobalt and silicon components are separated according to their thickness. This means that the cobalt component has not diffused into the silicon region. It can be seen that the amorphous boron nitride layer a-BN acts as a diffusion barrier.

[0127] Figure 14(i) is a cross-sectional TEM image of the TiN layer after thermal diffusion testing, serving as a comparative example, and Figure 14(ii) is the EDS line distribution of the TiN layer after thermal diffusion testing, also serving as a comparative example. A 3 nm thick TiN layer was formed on a silicon substrate, and an 80 nm thick cobalt layer was deposited on the TiN layer. The Co / TiN / Si device was then annealed in vacuum at 600 °C for approximately 1 hour. As shown in Figures 14(i) and 14(ii), it was confirmed that the cobalt separated from the cobalt layer and diffused into the silicon substrate.

[0128] from Figure 13 , 14(i) The results of 14(ii) show that the amorphous boron nitride layer a-BN has a greater effect in preventing metal diffusion than the TiN layer, which is usually used as a diffusion barrier.

[0129] Figure 15 This diagram shows the results of the breakdown bias voltage of the amorphous boron nitride layer a-BN according to an embodiment, based on temperature. It can be seen that the breakdown bias voltage of the amorphous boron nitride layer a-BN is inversely proportional to temperature. Although the breakdown voltage decreases with increasing temperature, it can be observed that the breakdown bias voltage of the amorphous boron nitride layer a-BN is greater than that of the TiN layer. This means that the amorphous boron nitride layer a-BN is stable at various temperatures, and as a result, the amorphous boron nitride layer a-BN can be an excellent low-k material for high-performance CMOS electronic devices.

[0130] Boron nitride layers formed at temperatures of 400°C or lower using inductively coupled plasma-chemical vapor deposition (ICP-CVD) are amorphous and act as diffusion barriers. Furthermore, compared to materials with similar dielectric constants, amorphous boron nitride layers (a-BN) exhibit a low dielectric constant and a large breakdown field. Amorphous boron nitride layers (a-BN) are fabricated at temperatures of 400°C or lower, and the process temperature can be adjusted depending on the substrate, pressure, etc. For example, when the substrate is used as a catalyst for forming the boron nitride layer, the layer can be formed at temperatures below 400°C, such as 300°C.

[0131] The following describes boron nitride layers formed at temperatures above 400°C. For example, these layers are formed using an ICP-CVD method at approximately 10 °C. -4 Boron nitride layers are grown on silicon substrates under process pressure and at a process temperature of approximately 700°C.

[0132] Figures 16A to 16C This is a diagram showing the atomic structure of a boron nitride layer grown at approximately 700°C according to an embodiment. Figure 16A This is an image of selective region electron diffraction of a boron nitride layer grown at approximately 700°C. Figure 16A The image shows a polycrystalline ring pattern. Figure 16B This is a high-magnification TEM image of a boron nitride layer grown at approximately 700°C, which confirms the arrangement of small, nanoscale crystallites. Additionally, Figure 16C This is a graph showing the Fast Fourier Transform (FFT) results of a boron nitride layer grown at approximately 700 °C, confirming that the boron nitride layer possesses a hexagonal superstructure. Therefore, it can be confirmed that boron nitride layers grown at temperatures above approximately 400 °C, such as 700 °C, comprise nanoscale crystallites.

[0133] Nanocrystalline boron nitride (nc-BN) layers possess good mechanical strength because they are not porous, as described above. Figures 3A to 3D As shown in the diagram. According to the apparatus for applying the nanocrystalline boron nitride layer nc-BN thereto, one or more pores can be formed in the nanocrystalline boron nitride layer nc-BN. Multiple pores can be formed in the nanocrystalline boron nitride layer nc-BN, and thus the dielectric constant can be further reduced. According to an embodiment, other materials can be filled into the pores of the nanocrystalline boron nitride layer nc-BN. Even if the pores of the nanocrystalline boron nitride layer nc-BN are filled with other materials, the utilization of the nanocrystalline boron nitride layer nc-BN can be increased without significantly increasing the dielectric constant.

[0134] Figure 17 These are the Raman spectra of the nanocrystalline boron nitride layer nc-BN according to the embodiment. Figure 17As shown, it can be confirmed that in the SiO2 / Si substrate and the amorphous boron nitride layer a-BN, at approximately 1370 cm⁻¹... -1 There is no peak at the wavelength, while in Example 2, which is a boron nitride layer formed at 700°C, and the hexagonal boron nitride layer Tri-hBN, there is a peak at approximately 1370 cm⁻¹. -1 A peak is observed at the specified wavelength. This indicates that the boron nitride layer formed at 700℃ is crystalline. In the following text, the boron nitride layer with nanoscale crystals will be referred to as nanocrystalline boron nitride layer nc-BN.

[0135] Figure 18 The FTIR spectra of the nanocrystalline boron nitride layer nc-BN according to an embodiment are shown. The FTIR spectra of the boron nitride layer were measured using s-polarized radiation at an incident angle of 60°. Figure 18 As shown, it can be confirmed that in the nanocrystalline boron nitride layer nc-BN, there exists a phenomenon at 1370 cm⁻¹ at which the transverse optical mode is attributed. -1 The absorption peak is near 1570 cm⁻¹. -1 There are no absorption peaks nearby. This means that the nanocrystalline boron nitride layer nc-BN according to the embodiment does not have amorphous properties.

[0136] Figure 19 This is a graph illustrating the XPS distribution results of the nanocrystalline boron nitride layer nc-BN according to the embodiment. (See figure) Figure 19 As shown, it can be confirmed that the 1s peaks for boron and nitrogen are 190.3 eV and 397.9 eV, respectively. It can be confirmed that the 1s peaks for boron and nitrogen in the nanocrystalline boron nitride layer nc-BN and the amorphous boron nitride layer a-BN are almost identical. This can be seen from... Figure 19 XPS distribution confirmed that the atomic ratio of boron to nitrogen was approximately 1:1.08.

[0137] Figure 20 This diagram illustrates an example of using a nanocrystalline boron nitride layer (nc-BN) as a diffusion barrier layer according to an embodiment. A boron nitride layer is grown on a silicon substrate at 700°C, and a cobalt layer with a thickness of 50 nm is deposited on the boron nitride layer. The boron nitride layer grown at 700°C can be a nanocrystalline boron nitride layer (nc-BN). The above structure is then vacuum annealed at 600°C for 1 hour. Figure 20 As shown, very low-density needle-like cobalt silicide was observed on the silicon substrate. This confirms that the nanocrystalline boron nitride layer (nc-BN) acts as a diffusion barrier even under annealing conditions.

[0138] Figure 21 This is a graph showing the dielectric constant of the nanocrystalline boron nitride layer nc-BN according to the embodiment for various frequencies. (See figure) Figure 21As shown, it can be confirmed that the nanocrystalline boron nitride layer nc-BN has a dielectric constant of 2.5 or lower in the operating frequency range of about 50 kHz to about 1 MHz. For example, it can be confirmed that the nanocrystalline boron nitride layer nc-BN has a dielectric constant of about 2.3 to about 2.5. It can be confirmed that crystalline hexagonal boron nitride typically has a dielectric constant of about 2.9 to about 3.8 in the operating frequency range of about 50 MHz to about 100 kHz, while the nanocrystalline boron nitride layer nc-BN has a low dielectric constant of 2.5 or lower. As mentioned above, the nanocrystalline boron nitride layer nc-BN can be used as an interlayer insulating layer due to its low dielectric constant. In particular, when the nanocrystalline boron nitride layer nc-BN is used as an interlayer insulating layer between conductive materials, parasitic capacitance can be reduced.

[0139] Even if the amorphous boron nitride layer a-BN itself is not porous, pores can be formed in the amorphous boron nitride layer a-BN depending on the device in which it is applied. Multiple pores can be formed in the amorphous boron nitride layer a-BN, and thus the dielectric constant can be further reduced.

[0140] Amorphous boron nitride (a-BN) layers can have band gaps of approximately 6.00 eV or less. Typically, it has been confirmed that trigonal boron nitride layers have band gaps of approximately 6.05 eV, while boron nitride layers grown at 400 °C have band gaps of approximately 5.96 eV, and those grown at 700 °C have band gaps of approximately 5.85 eV. That is, amorphous boron nitride (a-BN) layers and / or nanocrystalline boron nitride (nc-BN) layers have lower band gaps than hexagonal boron nitride layers. Therefore, amorphous boron nitride (a-BN) layers and / or nanocrystalline boron nitride (nc-BN) layers are chemically stable.

[0141] Figure 22A These are atomic force microscopy (AFM) images of boron nitride (BN) layers grown at approximately 400°C. Figure 22B This is an AFM image of a boron nitride layer grown at approximately 700°C. Figure 22A As shown, the surface roughness of the boron nitride (BN) layer grown at approximately 400°C was confirmed to be approximately 0.45 nm, and as shown... Figure 22B As shown, the surface roughness of the boron nitride layer grown at approximately 700°C is approximately 0.39 nm. Because the surface of the amorphous boron nitride layer a-BN is smooth, it is easy to form another layer on the boron nitride layer BN, thereby facilitating the fabrication of the device.

[0142] Figure 23 This is a diagram illustrating a multilayer structure 100 including a diffusion barrier layer according to one embodiment. (See diagram) Figure 23As shown, the multilayer structure 100 may include a first material layer 110, a second material layer 120 separate from the first material layer 110, and a diffusion barrier layer 130 between the first material layer 110 and the second material layer 120.

[0143] The first material layer 110 and the second material layer 220 may comprise different materials. The diffusion barrier layer 130 suppresses or prevents the movement (diffusion) of material (atoms) between the first material layer 110 and the second material layer 120. The diffusion barrier layer 130 may comprise at least one of the aforementioned amorphous boron nitride layer a-BN and nanocrystalline boron nitride layer nc-BN. Alternatively, the diffusion barrier layer 130 may further comprise materials other than amorphous boron nitride layer a-BN and nanocrystalline boron nitride layer nc-BN. For example, the diffusion barrier layer 130 may comprise a metal chalcogenide-based material with a two-dimensional crystal structure and graphene. Alternatively, the diffusion barrier layer 130 may comprise Ti, Ta, TiN, TaN, TiSiN, WC, Co, MnN, Mn, and metal silicides, etc. Figure 23 One of the first and second material layers 110 and 220 may be a conductive material, and the other may be a semiconductor material. Alternatively, one of the first and second material layers 110 and 120 may be a conductive material, and the other may be an insulating material.

[0144] For example, the first material layer 110 may be an insulating layer, and the second material layer 120 may be a conductive layer. The first material layer 110 may be an insulating layer comprising silicon oxide, silicon nitride, silicon nitride, etc., or comprising a high dielectric material having a dielectric constant higher than that of silicon nitride. Alternatively, the first material layer 110 may comprise an organic-inorganic hybrid insulating material based on SiCOH. Any insulating material used in conventional electronic devices or semiconductor devices may be applied to the first material layer 110. The second material layer 120 may be a metal layer or a metal compound layer. In this case, the diffusion barrier layer 130 may suppress / prevent the movement / diffusion of material from the second material layer 120, such as metal atoms, into the first material layer 110.

[0145] Figure 24 This is a cross-sectional view showing a multilayer structure 200 including a diffusion barrier layer 210 according to another embodiment.

[0146] refer to Figure 24A diffusion barrier layer 210 may be provided to cover at least one surface of the conductive layer 220. For example, the diffusion barrier layer 210 may be provided to cover the entire side surface of the conductive layer 220. The conductive layer 220 may be a layer comprising a metal or a metal compound. The diffusion barrier layer 210 may further comprise a material other than the amorphous boron nitride layer a-BN and the nanocrystalline boron nitride layer nc-BN. Although not shown, an additional material layer bonded to the conductive layer 220 may be further provided when the diffusion barrier layer 210 is present therebetween. The additional material layer may be a semiconductor layer or an insulating layer. Additionally, a desired and / or alternatively predetermined adhesive layer may be further provided between the diffusion barrier layer 210 and the conductive layer 220. Although not shown, the diffusion barrier layer 210 may be provided to surround the entire side surface of the conductive material layer.

[0147] Figure 25 This is a reference diagram showing a transistor 300 including a boron nitride layer according to an embodiment.

[0148] refer to Figure 25 The transistor 300 may include: a substrate 310, a channel 320 disposed on the substrate 310, a source 332 and a drain 334 disposed to apply a voltage to the channel 320 and spaced apart from each other, a gate 340 disposed to form an electric field on the channel 320, and a gate insulating layer 350 disposed between the channel 320 and the gate 340.

[0149] The substrate 310 may include materials such as silicon (Si), silicon-germanium, silicon carbide (SiC), glass, plastic, etc. Furthermore, the substrate 310 may include an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SEO) layer, etc.

[0150] The channel 320 can be formed as a suitable semiconductor according to the product design. For example, the channel 320 can be an oxide semiconductor, an organic semiconductor, amorphous silicon, polycrystalline silicon, etc. For example, oxide semiconductors may include zinc oxide (ZnO) or InZnO (IZO), InGaZnO (IGZO), HfInZnO (HIZO), etc., which are doped with zinc oxide (ZnO) and indium (In), gallium (Ga), hafnium (Hf), tin (Sn), etc.

[0151] The source 332 and drain 334 are electrically connected via a channel 320. The source 332 and drain 334 may comprise conductive materials. For example, the source 332 and drain 334 may comprise metals, metal alloys, conductive metal oxides, conductive metal nitrides, etc. The source 332 and drain 334 may be formed in a single-layer or multi-layer structure.

[0152] The gate 340 may include a conductive material, and may include metals, metal alloys, conductive metal oxides, conductive metal nitrides, etc. Furthermore, the gate 340 may include a semiconductor material doped with impurities.

[0153] A gate insulating layer 350 may be formed between the gate 340 and the channel 320. The gate insulating layer 350 may include an amorphous boron nitride layer a-BN or a nanocrystalline boron nitride layer nc-BN according to embodiments.

[0154] According to the embodiments, the amorphous boron nitride layer a-BN or the nanocrystalline boron nitride layer nc-BN can be used as a component of the interconnect structure. The fabrication and configuration of the interconnect structure can be applied to front-end process (FEOL) semiconductor fabrication and configuration, back-end process (BEOL) semiconductor fabrication and configuration, or both.

[0155] FEOL (Feature-on-Line) is a part of integrated circuit (IC) fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned on a semiconductor substrate or layer. FEOL typically covers all deposits up to (but not including) the metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any lines).

[0156] The BEOL (Break-in-Order) is the second part of IC manufacturing, where devices (e.g., transistors, capacitors, resistors, etc.) are interconnected on the wafer using lines (e.g., one or more metallization layers). The BEOL may include contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. During the manufacturing phase of the BEOL, contacts (pads), interconnects, vias, and dielectric structures can be formed. In recent IC processes, more than 10 metal layers can be added to the BEOL.

[0157] Figure 26 This is a reference diagram illustrating a semiconductor device 400 including an interconnect structure 420 according to an embodiment.

[0158] refer to Figure 26 The semiconductor device 400 may include a substrate 410 and an interconnect structure 420 disposed on the substrate 410. Here, the interconnect structure 420 may include a dielectric layer 422, a wire 424, and a diffusion barrier layer 426.

[0159] The substrate 410 may be a semiconductor substrate. For example, the substrate 410 may include a group IV semiconductor material, a group III / V semiconductor compound, or a group II / VI semiconductor compound. As specific examples, the substrate 410 may include Si, Ge, SiC, SiGe, SiGeC, Ge alloys, GaAs, InAs, InP, etc. However, this is only an example, and many other semiconductor materials may be used as the substrate 410.

[0160] The substrate 410 may comprise a single layer or a multilayer in which different materials are stacked. The substrate 410 may comprise, for example, a silicon-on-insulator (SOI) substrate or a silicon-germanium-on-insulator (SGOI) substrate. Additionally, the substrate 410 may comprise undoped or doped semiconductor materials.

[0161] The substrate 410 may include at least one semiconductor device (not shown). The semiconductor device may include at least one of the following: a transistor, a capacitor, a diode, and a resistor. However, the semiconductor device is not limited to these.

[0162] A dielectric layer 422 may be formed on a substrate 410. The dielectric layer 422 may have a monolayer structure or a multilayer structure in which different materials are stacked. The dielectric layer 422 may include dielectric materials used in conventional semiconductor manufacturing processes. For example, the dielectric layer 422 may include silicon oxide, nitride, silicon nitride, silicon carbide, silicates, etc. However, this is only an example, and many other dielectric materials may be used as the dielectric layer 422. Additionally, the dielectric layer 422 may include an organic / inorganic hybrid dielectric material based on SiCOH. Furthermore, the dielectric layer 422 may include at least one of an amorphous boron nitride layer a-BN and a nanocrystalline boron nitride layer nc-BN. When the dielectric layer 422 includes at least one of an amorphous boron nitride layer a-BN and a nanocrystalline boron nitride layer nc-BN, the diffusion barrier layer 426 may not be provided separately because the dielectric layer 422 may also function as a diffusion barrier layer 426, which will be described later.

[0163] At least one trench 422a may be formed in the dielectric layer 422 at a desired and / or alternatively predetermined depth. Here, the at least one trench 422a may be formed not to contact the substrate 110 or may be formed to contact the substrate 410. Figure 26 In the dielectric layer 422, two trenches 422a are formed, one of which does not contact the substrate 410, and the other trench 422a contacts the substrate 410.

[0164] A conductor 424 may be provided to fill the interior of the trench 422a. The conductor 424 may comprise a metal or metal alloy having excellent electrical conductivity. For example, the conductor 424 may comprise Cu, Ru, Al, Co, W, Mo, Ti, Ta, Ni, Pt, Cr, Rh, Ir, or alloys thereof. However, the conductor 424 is not limited to these, and a variety of other metals may be used as the conductor 424.

[0165] A diffusion barrier layer 426 may be disposed on the inner wall of the trench 422a. Here, the diffusion barrier layer 426 may be disposed to cover the conductor 424 between the dielectric layer 422 and the conductor 424. Specifically, the diffusion barrier layer 426 may be disposed on the inner wall of the trench 422a to cover the side and lower surfaces of the conductor 424. The upper surface of the conductor 424 may be exposed by the diffusion barrier layer 426. The diffusion barrier layer 426 prevents the diffusion of the material forming the conductor 424. Additionally, the diffusion barrier layer 426 may also serve as an adhesive layer between the dielectric layer 422 and the conductor 424. The diffusion barrier layer 426 may include at least one of an amorphous boron nitride layer a-BN and a nanocrystalline boron nitride layer nc-BN according to embodiments.

[0166] In addition, amorphous boron nitride (a-BN) layers and nanocrystalline boron nitride (nc-BN) layers can be used as diffusion barrier layers in various electronic devices. Boron nitride layers can be grown directly on the electronic device, or they can be grown on a base substrate and transferred to the electronic device.

[0167] Amorphous boron nitride (a-BN) layers and nanocrystalline boron nitride (nc-BN) layers can be directly grown on some components of electronic devices because they are grown at low temperatures. Furthermore, due to the low surface roughness of the boron nitride layers, other components of the electronic device can be directly stacked on the grown boron nitride (BN) layers.

[0168] Furthermore, the movement (diffusion) of material (or atoms) between the two material layers is suppressed, and thus the boron nitride layer can act as a diffusion barrier even at a thin thickness, such as 5 nm or less. Therefore, the integration density of the integrated circuit (or transistor) can be increased.

[0169] Simultaneously, with the integration of semiconductor devices, parasitic capacitances are generated between conductive material layers. These parasitic capacitances cause delays in signal transmission of semiconductor devices. According to the embodiments, the amorphous boron nitride layer or nanocrystalline boron nitride layer has a low dielectric constant, and therefore serves as an interlayer insulating layer between conductive material layers to reduce parasitic capacitance. The thickness of the amorphous boron nitride layer and nanocrystalline boron nitride layer used as the interlayer insulating layer can be about 5 nm or higher.

[0170] Furthermore, amorphous boron nitride layers or nanocrystalline boron nitride layers enable low-temperature processes and can therefore be formed on material layers of electronic devices without damaging other materials in the device. Additionally, because amorphous boron nitride layers or nanocrystalline boron nitride layers have low surface roughness, other material layers can be stacked sequentially. The aforementioned semiconductor devices may include transistors, resistors, capacitors, etc.

[0171] Figure 27 This is a diagram illustrating a field-effect transistor 500 including a boron nitride layer according to an embodiment. Figure 27 The field-effect transistor 500 disclosed herein may include: a plurality of channels 520 disposed on a substrate 510, a source 532 and a drain 534 in contact with the channels 520, and a plurality of gates 540 spaced apart from the channels 520.

[0172] The substrate 510 may be an insulating substrate or a semiconductor substrate having an insulating layer formed on its surface. The semiconductor substrate may include, for example, Si, Ge, SiGe, or III-V group semiconductor materials. The substrate 510 may be, for example, a silicon substrate having silicon oxide formed on its surface, but is not limited thereto.

[0173] On substrate 510, source 532 and drain 534 may be spaced apart from each other along a first direction, and a plurality of channels 520 between source 532 and drain 534 may be spaced apart from each other along a second direction. The first direction may be the x-direction, and the second direction may be the y-direction.

[0174] Multiple gates 540 may be spaced apart from the channel 520, and a gate insulating layer 550 may be disposed between the gates 540 and the channel 520. For example, the gate insulating layer 550 may be disposed to surround at least a portion of the gates 540. For example, the gates 540 and the channel 520 may be arranged alternately in a second direction, and the gate insulating layer 550 may be formed to surround the gates 540.

[0175] The gate insulating layer 550 can insulate between the channel 520 and the gate 540 and suppress leakage current.

[0176] The contact between each channel 520 and the source 532 and drain 534 can be in the form of an edge contact. For example, each end of the channel 520 is in contact with the source 532 and drain 534.

[0177] Meanwhile, each gate 540 may be spaced apart from the source 532 and the drain 534, and spacers 560 may be further provided between the gate 540 and the source 532 and between the gate 540 and the drain 534. Since the source 532, the gate 540 and the drain 534 are arranged in the first direction, parasitic capacitance may appear between the source 532 and the gate 540 and between the gate 540 and the drain 534.

[0178] To reduce parasitic capacitance, the spacer 560 according to the embodiment may include at least one of the amorphous boron nitride layer a-BN and the nanocrystalline boron nitride layer nc-BN. The aforementioned amorphous boron nitride layer a-BN and nanocrystalline boron nitride layer nc-BN have a dielectric constant of 2.5 or less at a frequency of 100 kHz, which effectively reduces parasitic capacitance. The spacer 560 may further include materials with low dielectric constants other than the boron nitride layer according to the embodiment.

[0179] Furthermore, the amorphous boron nitride layer a-BN and the nanocrystalline boron nitride layer nc-BN according to the embodiment do not have porosity and have mechanical strength, thereby supporting the channel 520 disposed on the upper layer of the spacer 560.

[0180] The field-effect transistor 500 according to the embodiment may have a multi-bridge shape, wherein multiple channels 520 are each stacked and spaced apart along a direction away from the substrate 510, with their ends contacting the source 532 and the drain 534. The multi-bridge channel shape can reduce short-channel effects and reduce the area occupied by the source / drain, and is therefore advantageous for high integration. In addition, since the channel can maintain a uniform source / drain junction capacitance regardless of the channel location, it has the advantage of being applicable to high-speed and high-reliability devices.

[0181] The gate insulating layer 550 may include a high-k dielectric material, which is a material with a high dielectric constant. The gate insulating layer 550 may include, for example, alumina, hafnium oxide, zirconium hafnium oxide, lanthanum oxide, etc. However, the gate insulating layer 550 is not limited to these.

[0182] The gate insulating layer 550 may include a ferroelectric material. When the gate insulating layer 550 includes a ferroelectric material, the field-effect transistor 500 can be applied to, for example, logic devices or memory devices. When the gate insulating layer 550 includes a ferroelectric material, performance can be improved while reducing the size of the field-effect transistor 500 because the subthreshold swing (SS) can be reduced through the negative capacitance effect.

[0183] Ferroelectric materials possess a non-centrosymmetric charge distribution within the unit cell of a crystalline material structure, and therefore exhibit spontaneously generated dipoles, i.e., spontaneous polarization. Thus, even in the absence of an external electric field, ferroelectric materials possess remanent polarization through dipoles. Furthermore, the polarization direction can be switched to the domain unit by an external electric field. Ferroelectric materials may include, for example, at least one oxide selected from the group consisting of Hf, Si, Al, Zr, Y, La, Gd, and Sr, but these are merely examples. Additionally, ferroelectric materials may further include dopants if necessary.

[0184] The gate insulating layer 550 may have a multilayer structure including high-k materials and ferroelectric materials. The gate insulating layer 550 may include a charge trapping layer, such as silicon nitride, so that the field-effect transistor 500 can operate as a memory transistor with storage characteristics.

[0185] Figure 28 This is a diagram illustrating a vertical field-effect transistor 600 including a boron nitride layer according to an embodiment. Figure 28 The field-effect transistor 600 shown can be called a vertical field-effect transistor because current flows in the vertical direction through a channel 620 extending vertically from the substrate 610. Figure 28 The field-effect transistor 600 may include a substrate 610, a channel 620, a source 632, a drain 634, a gate 640, a gate insulating layer 650, and a spacer 660.

[0186] The substrate 610 may include, for example, one or more semiconductor materials, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. In some embodiments, the substrate 610 may be a bulk silicon (silicon) substrate or a silicon-on-insulator (SOI) substrate.

[0187] The channels 620 may be spaced apart from each other in a first direction (e.g., the x-axis direction). The first direction may be parallel to the upper surface of the substrate 610. Each channel 620 may protrude from the upper surface of the substrate 610 in a second direction (e.g., the y-axis direction). The second direction may be perpendicular to the top surface of the substrate 610. Forming the channels 620 may include forming a mask layer (not shown) on the substrate 610 and using the mask layer as an etching mask to etch the substrate 610 to form the channels 620.

[0188] The source 632 may be disposed on the substrate 610. The source 632 may form a contact while surrounding a portion of the channel 620. The source 632 can be formed by using the substrate 610 as a seed layer in an epitaxial growth process, and impurities may be added during the epitaxial growth process. However, the source 632 is not limited to this. The source 632 can be formed by implanting impurities into the substrate 610. Additionally, the source 632 may be configured to contact the side surface of the channel 620, but is not limited to this, and may also be configured to contact the lower surface of the channel 620.

[0189] A first spacer 662 may be disposed on the source 632, and a gate 640 and a gate insulating layer 650 may be disposed on the first spacer 662. The first spacer 662 may be disposed as part of a side surface surrounding a channel 620, and the gate 640 may be disposed on the first spacer 662 while being spaced apart from the channel 620. The gate insulating layer 650 may be disposed on the first spacer 662 and between the gate 640 and the channel 620. The gate insulating layer 650 and the gate 640 may also extend vertically on the first spacer 662.

[0190] The second spacer 664 may be disposed on the gate 640 and the gate insulating layer 650, and the second spacer 664 may be disposed as part of the side surface surrounding the channel 620.

[0191] Additionally, a drain 634 can be formed on the channel 620. The drain 634 can be formed by an epitaxial growth process using the channel 620 as a seed layer. The drain 634 can be configured to cover at least a portion of the second spacer 664.

[0192] The first and second spacers 662 and 664 may comprise at least one of an amorphous boron nitride layer a-BN and a nanocrystalline boron nitride layer nc-BN according to embodiments. The aforementioned amorphous boron nitride layer a-BN and nanocrystalline boron nitride layer nc-BN have low dielectric constants, and therefore reduce parasitic capacitance. The first and second spacers 662 and 664 may further comprise materials with low dielectric constants other than the boron nitride layer according to embodiments.

[0193] Furthermore, the amorphous boron nitride layer a-BN and the nanocrystalline boron nitride layer nc-BN according to the embodiments do not have porosity and have mechanical strength, such that the first spacer 662 can support the gate 640 and the gate insulating layer 650, and the second spacer 664 can support the drain 634.

[0194] Additionally, a first spacer 662 may be formed after the source 632 is formed, and a second spacer 664 may be formed after the gate 640 and the gate insulating layer 650 are formed. The first and second spacers 662 and 664 may be formed by forming an amorphous boron nitride layer a-BN and a nanocrystalline boron nitride layer nc-BN at low temperatures, and therefore, the source 632 and the gate 640 may not be damaged.

[0195] exist Figure 28 In the channel 620, the source electrode 632 is formed on the lower side and the drain electrode 634 is formed on the upper side, but the source electrode 632 and the drain electrode 634 are not limited thereto. The drain electrode 634 may be formed on the lower side of the channel 620 and the source electrode 632 may be formed on the upper side of the channel 620.

[0196] Figure 29This is a diagram illustrating a fin transistor 700 including a boron nitride layer according to an embodiment. Figure 29 The fin transistor 700 is a three-dimensional transistor with protruding fin structures on a substrate 710. Since the fin transistor 700 can use the protruding fin structures 722 and 724 as the channel 720, the channel length is sufficiently ensured. Therefore, short-channel effects can be prevented or minimized, and leakage current and area problems can be improved.

[0197] Transistor 700 may include a substrate 710, active fins 722, dummy fins 724, a gate 740, a gate insulating layer 750, and spacers 760. Although not shown in the figures, each terminal of the active fin 722 is electrically connected to the source and drain. Although two active fins are illustrated as a channel 720, the number of active fins is not limited thereto.

[0198] The substrate 710 may be a semiconductor substrate. For example, the semiconductor substrate may include any one of silicon, silicon-on-insulator (SOI), silicon-on-sapphire, germanium, silicon-germanium, and gallium arsenide.

[0199] Active fin 722 and dummy fin 724 may be configured to connect to substrate 710. In one embodiment, active fin 722 may be an active (active) region partially doped with n+ or p+ protruding from substrate 710 into a vertical portion, and dummy fin 724 may be an undoped region partially protruding from substrate 710 into a vertical portion. In another embodiment, both active fin 722 and dummy fin 724 may be active regions doped with n+ or p+.

[0200] Each active fin 722 may have a width and a height, and the width and height of the active fin 722 can determine the width and height of the channel layer. The width and height of the channel 720 can be increased by the number of active fins 722.

[0201] The gate insulating layer 750 may be disposed on the active fin 722 and the dummy fin 724. The gate insulating layer 750 may include any one of an oxide layer, a nitride layer, or an oxynitride layer.

[0202] The spacer 760 may be configured to have a desired and / or alternatively predetermined height in the space between the active fin 722 and the dummy fin 724. The spacer 760 may be formed of a material having a low dielectric constant by including at least one amorphous boron nitride layer a-BN and a nanocrystalline boron nitride layer nc-BN according to embodiments. The spacer 760 may further include a dielectric material having a low dielectric constant in addition to the boron nitride layer according to embodiments. The spacer 760 may be disposed between the active fin 722 and the dummy fin 724 such that the spacer 760 can serve as a device isolation layer and reduce parasitic capacitance.

[0203] The gate 740 may be disposed on the upper portion of the gate insulating layer 750 and the spacer 760. Therefore, the gate 740 may have a structure surrounding the active fin 722, the dummy fin 724, and the spacer 760. In other words, the active fin 722 and the dummy fin 724 may have a structure disposed within the gate 740. The gate 740 may comprise a metallic material such as W, Ta, its nitride, its silicide, doped polysilicon, etc., and may be formed using a deposition process.

[0204] In addition to the low dielectric constant amorphous boron nitride layer a-BN and nanocrystalline boron nitride layer nc-BN according to the embodiments, it can be used in a variety of electronic devices.

[0205] Figure 30A and 30B This is a diagram illustrating a portion of a display device 800 including a boron nitride layer according to an embodiment. Figure 30A This is a diagram illustrating a portion of a display device 800 including a boron nitride layer according to an embodiment, and Figure 30B It is along Figure 30A The cross-sectional view taken by lines A-A' and B-B'.

[0206] refer to Figure 30A and 30B Gate lines 822 and 824 for transmitting gate signals are formed on an insulating substrate 810. Gate lines 822 and 824 include a gate line 822 extending in one direction (e.g., horizontal direction) and a gate 824 of a thin-film transistor formed by protruding from the gate line 822 in a protruding shape.

[0207] Additionally, storage lines 828 and 829 for transmitting storage voltage are formed on the insulating substrate 810. Storage lines 828 and 829 include a storage line 828 formed substantially parallel to the gate line 822 across a pixel region, and a storage electrode 829 branching from the storage line 828 and extending parallel to the data line 862.

[0208] The storage electrode 829 can be formed in the form of a square ring along the data line 862. That is, an opening region is formed in the center of the storage electrode 829 to accommodate the data line 862, and at least a portion of the ring portion of the storage electrode 829 overlaps with the pixel electrode 880.

[0209] The shape and arrangement of the storage electrode 829 and the storage line 828 can be modified in various ways, and the storage electrode 829 and the storage line 828 may not be formed when the storage capacitance caused by the overlap of the pixel electrode 880 and the gate line 822 is sufficient.

[0210] Gate lines 822 and 824, and storage lines 828 and 829, may comprise aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), and tantalum (Ta). Additionally, gate lines 822 and 824, and storage lines 828 and 829 may have a multilayer structure comprising two conductive layers (not shown) with different physical properties. One of these conductive layers comprises a metal with low resistivity, such as an aluminum-based metal, a silver-based metal, a copper-based metal, etc., to reduce signal delay or voltage drop in gate lines 822 and 824 and storage lines 828 and 829. In contrast, the other conductive layer comprises a material with excellent contact properties with other materials, particularly zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO), such as molybdenum-based metals, chromium (Cr), titanium (Ti), tantalum (Ta), etc. Good examples of such combinations include a chromium lower layer and an aluminum upper layer, an aluminum lower layer and a molybdenum upper layer, and a titanium lower layer and a copper upper layer. However, this disclosure is not limited thereto, and gate lines 822 and 824 and memory lines 828 and 829 may include a variety of metals and conductors.

[0211] A gate insulating layer 830 is formed on the insulating substrate 810, gate lines 822 and 824, and memory lines 828 and 829. The gate insulating layer 830 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc. Specifically, the gate insulating layer 830 may be formed as a single layer or multiple layers, and when formed as multiple layers, it may have a structure in which silicon nitride and silicon oxide are stacked. In this case, the gate insulating layer 830 may be formed as a silicon oxide layer in the region contacting the oxide semiconductor layer pattern 842, and a silicon nitride layer may be disposed on the lower portion of the silicon oxide layer. When the silicon oxide layer contacts the oxide semiconductor layer pattern 842, degradation of the oxide semiconductor layer pattern 842 can be prevented. When the gate insulating layer 830 is formed as a silicon oxynitride layer, an oxygen concentration distribution in the silicon oxynitride layer can be provided. Moreover, in this case, by increasing the oxygen concentration as it approaches the oxide semiconductor layer pattern 842, degradation of the oxide semiconductor layer pattern 842 can be prevented.

[0212] An oxide semiconductor layer pattern 842 for forming the channel of a thin-film transistor is formed on the gate insulating layer 830. The channel region is formed by the oxide semiconductor layer pattern 842 overlapping with the gate line 824. In this embodiment, except for the channel region, the oxide semiconductor layer pattern 842 is formed to have substantially the same shape as the data lines 862, 865, and 866, which will be described later. This is because, during the fabrication of the thin-film transistor substrate of this embodiment, which will be described later, an etch mask is used to pattern the oxide semiconductor layer pattern 842 and the data lines 862, 865, and 866. In other words, except for forming the oxide semiconductor layer pattern 842 in the channel region, the oxide semiconductor layer pattern 842 has the same shape as the data lines 862, 865, and 866.

[0213] The oxide semiconductor layer pattern 842 includes, for example, compounds having the formula AxBxOx or AxBxCxOx. A includes Zn or Cd, B includes Ga, Sn or In, and C includes Zn, Cd, Ga, In or Hf. x is not 0, and A, B, and C are different. According to another embodiment, the oxide semiconductor layer pattern 842 may include any material selected from: InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, GaZnSnO, GaInZnO, HfInZnO, and ZnO. Such oxide semiconductors have excellent semiconductor properties, wherein the effective mobility is about 2 to about 100 times that of hydrogenated amorphous silicon.

[0214] An etch resist pattern 852 is formed on an oxide semiconductor layer pattern 842. Here, the etch resist pattern 852 is formed on the following: a thin-film transistor region where the gate line 824 overlaps with the source / drain lines 865 and 866; a region where the gate line 822 overlaps with the data line 862 (hereinafter referred to as the first overlapping region); and a region where the memory lines 828 and 829 overlap with the data line 862 (hereinafter referred to as the second overlapping region).

[0215] The etch resist pattern 852 formed in the thin-film transistor region is used to prevent the oxide semiconductor layer pattern 842 from being damaged by plasma, etch solution, or etch gas during subsequent etching or deposition processes. This is because the performance of the thin-film transistor can be significantly degraded when the oxide semiconductor layer pattern 842 is damaged by plasma, etch solution, or etch gas. Therefore, the etch resist pattern 852 formed on the thin-film transistor region can cover the oxide semiconductor layer pattern 842, and in particular, is sufficient to cover the channel region. That is, in order to prevent the oxide semiconductor layer pattern 842 from being exposed in the channel region, the etch resist pattern 852 can be formed in the region overlapping with the channel region as being wider than the channel region in the longitudinal direction of the channel.

[0216] Simultaneously, the etch resist pattern 852 formed in the first overlap region is used to reduce the capacitance generated between the gate line 822 and the data line 862 in the first overlap region, and the etch resist pattern 852 formed in the second overlap region is used to reduce the capacitance generated between the storage lines 828 and 829 and the data line 862 in the second overlap region. This is because the capacitance generated between the gate line 822 and the data line 862, or between the storage lines 828 and 829 and the data line 862, causes RC delay. Therefore, the etch resist pattern 852 is formed on the oxide semiconductor layer pattern 842 in the first overlap region and the second overlap region.

[0217] The resist pattern 852 includes an insulating material and may include, for example, any material selected from SiOx and SiNx.

[0218] Data lines 862, 865, and 866 are formed on the gate insulating layer 830, the oxide semiconductor layer pattern 842, and the resist pattern 852. Data lines 862, 865, and 866 include: a data line 862 formed in a different direction from the gate line 822, for example, in a vertical direction, to intersect the gate line 822 and define a pixel; a source 865 branching from the data line 862 and extending to the upper portion of the oxide semiconductor layer pattern 842 and the resist pattern 852 in the thin-film transistor region; and a drain 866 spaced apart from the source 865 and formed on the upper portion of the oxide semiconductor layer pattern 842 and the resist pattern 852 in the thin-film transistor region, facing the source 865 with respect to the gate line 824.

[0219] The resist pattern 852 is at least partially exposed between the source 865 and the drain 866. An oxide semiconductor layer pattern 842 is disposed on the lower portion of the resist pattern 852, the source 865, and the drain 866. That is, the oxide semiconductor layer pattern 842 completely overlaps with the resist pattern 852, the source 865, and the drain 866. As described above, except for a separate region overlapping the channel region, the source 865 and the drain 866 have substantially the same shape as the oxide semiconductor layer pattern 842.

[0220] Data lines 862, 865, and 866 can be formed as single-layer or multi-layer structures, including: Ni, Co, Ti, Ag, Cu, Mo, Al, Be, Nb, Au, Fe, Se, W, Ru, or Ta. Furthermore, alloys of one or more elements selected from the following can be applied to the metals: Ti, Zr, W, Ta, Nb, Pt, Hf, O, C, and N. Examples of multi-layer structures include bilayers such as Ti / Cu, Ta / Al, Ni / Al, Co / Al, Mo (Mo alloy) / Cu, etc., or trilayers such as Mo / Al / Mo, Ti / Al / Ti, Ta / Al / Ta, Ti / Al / TiN, Ta / Al / TaN, Ni / Al / Ni, Co / Al / Co, etc. However, data lines 862, 865, and 866 are not limited to the materials mentioned above.

[0221] A low-k dielectric material pattern 858 may be further formed on the resist pattern 852. The low-k dielectric material pattern 858 may be formed to have substantially the same shape as the resist pattern 852.

[0222] The low-k dielectric material pattern 858 may include a material having a low dielectric constant compared to the silicon nitride layer, i.e., a low-k dielectric material having a relative dielectric constant of less than 3. The aforementioned low-k dielectric material pattern 858 may include at least one of an amorphous boron nitride layer a-BN and a nanocrystalline boron nitride layer nc-BN according to embodiments.

[0223] A low-k dielectric material pattern 858 is further formed on the resist pattern 852 to shorten the process time, while further reducing the capacitance generated between the gate line 822 and the data line 862 in the first overlap region and the capacitance generated between the storage lines 828 and 829 and the data line 862 in the second overlap region.

[0224] That is, as the sum of the thickness of the resist pattern 852 and the thickness of the low-k dielectric material pattern 858 increases, the capacitance generated between the gate line 822 and the data line 862 in the first overlapping region and the capacitance generated between the storage lines 828 and 829 and the data line 862 in the second overlapping region are further reduced.

[0225] In addition, preferably, the thickness of the low-k dielectric material pattern 858 is greater than the thickness of the resist pattern 852, and thus the process time can be shortened.

[0226] In this embodiment, a structure in which a low-k dielectric material pattern 858 is stacked on an etch-resistant pattern 852 is described; however, this disclosure is not limited thereto, and the stacking order may be reversed. That is, the etch-resistant pattern 852 may be stacked on top of the low-k dielectric material pattern 858.

[0227] A passivation layer 870 is formed on data lines 862, 865, and 866, and an etch resist pattern 852 is exposed on the data lines 862, 865, and 866. Like the gate insulating layer 830, the passivation layer 870 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc. According to an embodiment, the passivation layer 870 may include a bilayer comprising silicon nitride (SiNx) and silicon oxide (SiOx).

[0228] A contact hole 875 is formed in the passivation layer 870 to expose a portion of the drain 866.

[0229] A pixel electrode 880 electrically connected to a drain 866 via a contact hole 875 is formed on a passivation layer 870. The pixel electrode 880 may include a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a reflective conductor such as aluminum.

[0230] The pixel electrode 880 to which the data voltage is applied can control light emission in the pixel region (not shown) together with the common electrode of the upper substrate facing the thin-film transistor substrate.

[0231] Figure 31 This is a diagram illustrating a NAND flash memory device 900 including a boron nitride layer according to an embodiment. The memory cells of the NAND flash memory device 900 can be arranged three-dimensionally on a substrate 910.

[0232] The substrate 910 may be a semiconductor substrate 910, such as a Si single-crystal substrate, a compound semiconductor substrate, a silicon-on-insulator (SOI) substrate, and a strained substrate. In embodiments, a semiconductor layer may be formed in a peripheral circuit region defined on the lower portion of a 3D NAND flash memory cell, and the semiconductor layer itself may be the substrate 910. Embodiments of this disclosure are not limited thereto; for example, in another embodiment, the substrate 910 may be a ceramic substrate 910, a polymer substrate for realizing flexible devices, or even a fabric layer. The substrate 910 may be doped to provide wiring such as impurity regions (not shown) or conductive layers (not shown).

[0233] On a substrate 910, a plurality of semiconductor structures 920 spaced apart from the substrate 910 in a horizontal direction (e.g., a first direction x and a second direction y) may be arranged. The semiconductor structures 920 may include metal oxides. The metal oxides may include oxygen vacancies, and these oxygen vacancies may be locally formed in the depth direction of the semiconductor structures 920. The semiconductor structures 920 may have at least one type of covalent and ionic bond between the metal element constituting the metal oxide and oxygen atoms. The metal element may include zinc, nickel, niobium, titanium, zirconium, hafnium, vanadium, molybdenum, magnesium, cobalt, iron, copper, aluminum, manganese, or combinations thereof. For example, the metal oxide may be zinc oxide. Furthermore, the metal oxide may be doped with an impurity element such as indium or gallium. For example, the metal oxide may include indium gallium zinc oxide (IGZO). The metal oxide may have a polycrystalline structure, an amorphous structure, a structure in which nanocrystals are dispersed, or a mixture thereof. For example, the metal oxide may have an amorphous structure or a structure in which nanocrystals are dispersed in an amorphous structure.

[0234] Multiple semiconductor structures 920 may be arranged alternately in a direction perpendicular to the substrate 910, each consisting of semiconductor layers doped with different dopants. For example, a first doped layer 922 doped with an n-type dopant and a second doped layer 924 doped with a p-type dopant may be arranged alternately in a direction perpendicular to the substrate 910, but this is not a limitation.

[0235] A gate structure 930 may be disposed between adjacent semiconductor structures 920 in a first direction relative to the substrate 910. In the gate structure 930, an insulating layer 932 and a gate 934 may be alternately arranged in a direction perpendicular to the substrate 910, for example, in a third direction (z-direction). The insulating layer 932 and the gate 934 of the gate structure 930 may be arranged to correspond to a first doped layer 922 doped with a first dopant and a second doped layer 924 doped with a second dopant, respectively. For example, the insulating layer 932 may be arranged parallel to the first doped layer 922 doped with an n-type dopant, and the gate 934 may be arranged parallel to the second doped layer 924 doped with a p-type dopant.

[0236] The information storage layer 940 may be further disposed between the gate structure 930 and the semiconductor structure 920. The information storage layer 940 may surround the gate structure 930 and may be individualized by separating adjacent memory cells. The information storage layer 940 may include a charge blocking layer 942 on the semiconductor structure 920, a data storage layer 944 on the charge blocking layer 942, and a barrier insulating layer 946 on the data storage layer 944.

[0237] The charge blocking layer 942 may include any one of the following: SiO2, Si3N4, SiON, HfO2, HfSiO, Al2O3, and ZrO2, or combinations thereof. The data storage layer 944 may include a dielectric matrix and silicon nanocrystals (NC) dispersed in the dielectric matrix. The dielectric matrix may include at least one dielectric material selected from the following: SiO2, SiON, Si3N4, SRN (silicon-rich nitride), HfO2, HfSiO, HfSiON, HfON, HfAlO, Al2O3, and AlN. The barrier insulating layer 946 may include any one of the following: Al2O3, SiO2, HfO2, ZrO2, Ta2O5, LaO, LaAlO, LaHfO, and HfAlO, or combinations thereof.

[0238] The materials described above for the dielectric matrix of the data storage layer 944, charge blocking layer 942, and barrier insulating layer 946 are examples, and other known materials may be used. For example, the information storage layer 940 may have a stacked structure of various materials, such as SONOS (polysilicon-silicon dioxide-silicon nitride-silicon dioxide-silicon) structure, SANOS (polysilicon-alumina-silicon nitride-silicon dioxide-silicon) structure, TANOS (titanium nitride or tantalum-alumina-silicon nitride-silicon dioxide-silicon) structure, MANOS (metal-alumina-silicon nitride-silicon dioxide-silicon) structure, or Be-MANOS (metal-alumina-silicon nitride-bandengineered oxide-silicon) structure, in the stacking order of gate 934, gate insulating layer 932, barrier insulating layer 946, data storage layer 944, charge blocking layer 942, and substrate 910. However, it is obvious that the materials of the information storage layer 940 are examples, and other candidate materials may be applied.

[0239] NAND flash memory device 900 can be divided into select device 901 and string device 902, including the area at the lower end or the upper end of the gate structure 930 which can be the select device 901, and the area including the middle end of the gate structure 930 which can be the string device 902.

[0240] For example, the p-type doped second doped layer 924 disposed at the bottom of the semiconductor structure 920, the pair of n-type doped first doped layers 922 adjacent to the second doped layer 924, the gate 934 corresponding to the p-type doped second doped layer 924, and the information storage layer 940 between the second doped layer 924 and the gate 934 can be a selection device 901. The second doped layer 924 disposed at the bottom of the semiconductor structure 920 can be used as a channel region, and the pair of n-type doped first doped layers 922 adjacent to the second doped layer 924 can be the source and drain, respectively.

[0241] The p-type doped second doped layer 924 disposed in the central region of the semiconductor structure 920, the pair of n-type doped first doped layers 922 adjacent to the second doped layer 924, the gate 934 corresponding to the p-type doped second doped layer 924, and the information storage layer 940 between the second doped layer 924 and the gate 934 can be a serial device 902. The second doped layer 924 disposed in the central region of the semiconductor structure 920 can be used as a channel region, and the pair of n-type doped first doped layers 922 adjacent to the second doped layer 924 can be the source and drain, respectively.

[0242] Spacers 960 may be disposed between adjacent semiconductor structures 920 in a second direction relative to the substrate 910. Spacers 960 electrically separate adjacent memory strings. Spacers 960 may be an insulating material comprising at least one of an amorphous boron nitride layer a-BN and a nanocrystalline boron nitride layer nc-BN according to an embodiment. Since the amorphous boron nitride layer a-BN and the nanocrystalline boron nitride layer nc-BN are low-k materials, they not only electrically insulate adjacent memory strings but also reduce the generation of parasitic capacitances. Spacers 960 may further comprise a dielectric material with a low dielectric constant other than the boron nitride layer according to an embodiment.

[0243] Although embodiments of boron nitride layers with low dielectric constants have been described and illustrated above, this disclosure is not limited to the specific embodiments described above, and does not depart from the spirit of the disclosure as claimed in the claims.

[0244] It should be understood that the embodiments described herein should be considered in a descriptive sense only and are not intended to be limiting. The descriptions of features or aspects in each embodiment should typically be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A boron nitride layer, comprising: A boron nitride compound, wherein the boron nitride layer has a dielectric constant of 2.5 or less at an operating frequency of 100 kHz. wherein the boron nitride layer has a mass density of 2 to 3 g / cm 3 and comprises at least one of an amorphous structure and nanocrystals having a size of 100 nm or less, The root mean square (RMS) roughness of the boron nitride layer is 0.3 to 0.6 nm.

2. The boron nitride layer of claim 1, wherein the atomic ratio of boron to nitrogen in the boron nitride layer is from 0.9 to 1.

1.

3. The boron nitride layer of claim 1, wherein the boron nitride layer is non-porous.

4. The boron nitride layer of claim 1, wherein the boron nitride layer comprises one or more pores.

5. The boron nitride layer of claim 1, wherein the boron nitride layer has a breakdown field of 4 MV cm"1 or higher. -1 or more.

6. The boron nitride layer of claim 1, wherein the boron nitride layer has a breakdown field of 10 MV cm"2 or less. -1 or more.

7. The boron nitride layer of claim 1, wherein the boron nitride layer has a band gap of 6.00 eV or less.

8. The boron nitride layer of claim 1, wherein the nitrogen and boron of the boron nitride compound comprise sp 2 bonds.

9. The boron nitride layer of claim 1, wherein the boron nitride layer has a hydrogen content of 10% by weight or less, based on the total weight of the boron nitride layer.

10. The boron nitride layer of claim 1, wherein the boron nitride layer has a dielectric constant of 2.3 or less at an operating frequency of 100 kHz.

11. The boron nitride layer of claim 10, wherein the boron nitride layer is amorphous.

12. The boron nitride layer of claim 1, wherein the boron nitride layer has a dielectric constant of 2.3 to 2.5 at an operating frequency of 100 kHz.

13. The boron nitride layer of claim 12, wherein the boron nitride layer comprises nanocrystals.

14. A method for manufacturing a boron nitride layer as described in any one of claims 1-13, the method comprising: Prepare the base; and A boron nitride layer is grown on the substrate using plasma at a temperature of 700°C or lower using a reactive gas including a boron nitride source.

15. The method of claim 14, wherein preparing the substrate includes pretreating the substrate.

16. The method of claim 14, wherein the plasma comprises at least one of the following: inductively coupled plasma, capacitively coupled plasma, microwave plasma, plasma enhancement method, electron cyclotron resonance plasma, arc discharge plasma, and helical wave plasma.

17. An apparatus comprising a boron nitride layer as described in any one of claims 1-13.

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