Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods of manufacturing the same. One method includes forming an opening in a first dielectric layer. An area beneath the first dielectric layer is exposed to the opening. The method also includes depositing a dummy silicon layer that extends into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. A metal region fills the opening and is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded several generations of ICs, each with smaller and more complex circuitry than the previous one. In the evolution of ICs, functional density (e.g., the number of interconnect devices per unit chip area) typically increases, while geometry (e.g., the smallest component (or line) that can be produced using manufacturing processes) decreases. This miniaturization process generally provides benefits through increased production efficiency and reduced associated costs.

[0003] As devices shrink, manufacturers are using new and different materials and / or combinations of materials to facilitate this miniaturization. Miniaturization (alone and in combination with new and different materials) also presents challenges that previous generations of ICs may not have encountered at larger geometries. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming an opening in a first dielectric layer, wherein a lower region located below the first dielectric layer is exposed in the opening; depositing a dummy silicon layer extending into the opening; depositing an isolation layer, wherein the isolation layer and the dummy silicon layer respectively include a dummy silicon ring and an isolation ring in the opening; filling the opening with a metal region, wherein the metal region is surrounded by the isolation ring; etching the dummy silicon layer to form an air spacer; and forming a second dielectric layer to seal the air spacer.

[0005] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: etching a dielectric layer to form an opening, wherein a semiconductor region is located below the opening and exposed to the opening; forming a dummy silicon layer on a sidewall of the dielectric layer facing the opening, wherein the dummy silicon layer further includes a horizontal portion located at the bottom of the opening; forming an isolation layer to cover the dummy silicon layer; performing an anisotropic etching process on the dummy silicon layer and the isolation layer to expose the semiconductor region to the opening, wherein the silicon portion and the isolation portion remain in the opening, respectively; depositing a metal-containing layer extending into the opening; performing a silicide process to react the metal-containing layer with the semiconductor region, thereby forming a silicide region; filling the opening with the metal region; and etching the dummy silicon layer.

[0006] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: depositing a silicon layer extending into an opening in a first dielectric layer; depositing a second dielectric layer on the silicon layer; removing horizontal portions of the silicon layer and the second dielectric layer; forming a silicide region at the bottom of the opening; filling the opening with a metal region; etching the silicon layer to form an air spacer using an etching gas comprising hydrogen (H2) and nitrogen trifluoride (NF3) until the silicide region is exposed to the air spacer; and depositing a third dielectric layer to seal the air spacer. Attached Figure Description

[0007] When with attachment Figure 1 When reading this document, a better understanding of its various aspects can be achieved by referring to the following specific embodiments. It is worth noting that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figures 1-8 , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figures 11-13 , Figure 14A , Figure 14B , Figures 15-17 , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B and Figure 20 Perspective views, cross-sectional views, and top views are shown according to some embodiments of the intermediate stages in forming a fin field-effect transistor (FinFET), contact plug, and air spacer.

[0009] Figures 21 to 24 FinFETs and contact plugs, as well as air spacers, are shown according to some embodiments.

[0010] Figure 25 The process flow for forming a FinFET, corresponding contact plugs, and air spacers according to some embodiments is shown. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. To simplify this disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not, in itself, prescribe a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship of one element or feature to another element(s) or feature(s), as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein may be interpreted accordingly.

[0013] According to some embodiments, an air spacer surrounding a contact plug and a method of forming the same are provided. According to some embodiments, intermediate stages of forming the air spacer are shown. Some variations of some embodiments are discussed. The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of this disclosure, and modifications that can be made will be readily understood by those skilled in the art while remaining within the contemplated scope of the different embodiments. Similar reference numerals are used throughout the various views and illustrative embodiments to indicate similar elements. While method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] According to some embodiments of this disclosure, air spacers are formed to surround contact plugs. The air spacers serve to reduce parasitic capacitance between the contact plugs and adjacent conductive features. Forming the air spacers includes: depositing a sacrificial layer (e.g., a silicon layer) into the contact openings; depositing an isolation layer on the silicon layer; performing anisotropic etching on the silicon layer and the isolation layer; depositing a capping layer; performing an annealing process to form silicide regions; and filling the contact openings with a metallic material. A planarization process is then performed, followed by removal of the silicon layer to form the air spacers. During the etching of the silicon layer, the ratio of hydrogen (H2) flow rate to NF3 flow rate is adjusted to prevent the formation of undesirable byproducts that could prematurely block the path for removing the silicon layer. While FinFETs are used as an example, contact plugs and air spacers can also be formed for other types of transistors, such as planar transistors, gate-all-around (GAA) transistors, etc. Similarly, in addition to being formed around contact plugs, air spacers can also be used around other types of conductive features (e.g., conductive wires, conductive vias, etc.) to reduce parasitic capacitance.

[0015] Figures 1-8 , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figures 11-13 , Figure 14A , Figure 14B , Figures 15-17 , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B and Figure 20 Perspective, cross-sectional, and top views are shown according to some embodiments of the intermediate stages of forming a FinFET and an air spacer surrounding a contact plug. Figure 25 The process flow shown also schematically reflects the corresponding process.

[0016] exist Figure 1A substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., using p-type or n-type dopants) or undoped. The semiconductor substrate 20 can be part of a wafer 10 (e.g., a silicon wafer). Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer or gradient substrates. According to some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0017] Further reference Figure 1 A well region 22 is formed in the substrate 20. The corresponding process is shown as follows. Figure 25 Process 202 is shown in the process flow 200. According to some embodiments of this disclosure, the well region 22 is an n-type well region formed by implanting an n-type impurity (which may be phosphorus, arsenic, antimony, etc.) into the substrate 20. According to other embodiments of this disclosure, the well region 22 is a p-type well region formed by implanting a p-type impurity (which may be boron, indium, etc.) into the substrate 20. The resulting well region 22 can extend to the top surface of the substrate 20. The concentration of the n-type or p-type impurity can be equal to or less than 10. 18 cm -3 For example, in about 10 17 cm -3 Peace Treaty 10 18 cm -3 Within the range between.

[0018] refer to Figure 2 The isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 may optionally be referred to as a shallow trench isolation (STI) region. The corresponding process is shown as follows: Figure 25Process 204 is shown in the process flow 200. The portion of substrate 20 between adjacent STI regions 24 is referred to as semiconductor strip 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20, and then patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, wherein the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed from silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The patterned photoresist is then used as an etch mask to pattern the hard mask layer 30 to form, as shown in the image. Figure 2 The hard mask 30 shown.

[0019] Next, the patterned hard mask layer 30 is used as an etching mask to etch the pad oxide layer 28 and the substrate 20, and then the resulting trenches in the substrate 20 are filled with one or more dielectric materials. A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, is performed to remove excess portions of the dielectric material, and the remaining portions of the dielectric material are STI regions 24. STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, etc., formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). STI regions 24 may also include dielectric material located above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, etc. According to some embodiments, the dielectric material located above the pad dielectric may include silicon oxide.

[0020] The top surface of the hard mask 30 and the top surface of the STI region 24 can be substantially flush with each other. A semiconductor strip 26 is located between adjacent STI regions 24. According to some embodiments of this disclosure, the semiconductor strip 26 is a portion of the original substrate 20, and therefore the material of the semiconductor strip 26 is the same as the material of the substrate 20. In alternative embodiments of this disclosure, the semiconductor strip 26 is a replacement strip formed by etching a portion of the substrate 20 between the STI regions 24 to form a groove, and performing epitaxy to regrow another semiconductor material in the groove. Therefore, the semiconductor strip 26 is formed of a semiconductor material different from the semiconductor material of the substrate 20. According to some embodiments, the semiconductor strip 26 is formed of silicon-germanium, silicon-carbon, or a group III-V compound semiconductor material.

[0021] refer to Figure 3 The STI region 24 is recessed, causing the top of the semiconductor strip 26 to protrude above the top surface 24A of the remaining portion of the STI region 24, forming a protruding fin 36. The corresponding process is shown as follows. Figure 25 Process 206 in process flow 200 shown in the diagram. Etching can be performed using a dry etching process, where, for example, HF3 and NH3 are used as etching gases. Plasma can be generated during the etching process. Argon may also be included. According to an alternative embodiment of this disclosure, a wet etching process is used to perform the recessing of the STI region 24. Etching chemicals may include, for example, an HF solution.

[0022] In the above embodiments, the fins can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fins, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0023] refer to Figure 4 The dummy gate stack 38 is formed to extend on the top surface and sidewalls of the (protruding) fin 36. The corresponding process is shown as follows. Figure 25Process 208 in process flow 200 is shown in the diagram. Gate stack 38 may include a dummy gate dielectric 40 and a dummy gate electrode 42 located above the dummy gate dielectric 40. The dummy gate electrode 42 may be formed, for example, using polysilicon, and may also use other materials. Each dummy gate stack 38 may also include one (or more) hard mask layers 44 located above the dummy gate electrode 42. The hard mask layer 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 38 may intersect with one or more protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a length direction perpendicular to the length direction of the protruding fins 36.

[0024] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. The corresponding process is shown as follows. Figure 25 Process 208 in process flow 200 shown in the diagram. According to some embodiments of this disclosure, the gate spacer 46 is formed of one or more dielectric materials such as silicon oxycarbonate (SiOCN), silicon nitride, silicon carbonitride, etc., and may have a single-layer structure or a multi-layer structure (including multiple dielectric layers).

[0025] Then, an etching process is performed to etch the portion of the protruding fin 36 that is not covered by the dummy gate stack 38 and the gate spacer 46, thereby obtaining Figure 5 The structure is shown. The corresponding process is shown as follows. Figure 25 Process 210 in process flow 200 is shown in the diagram. The recess can be anisotropic, so the portion of fin 36 located directly below the dummy gate stack 38 and gate spacer 46 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 26 can be lower than the top surface 24A of the STI region 24. The space left by the etched protruding fin 36 is referred to as a recess 50. Recess 50 includes portions located between adjacent gate stacks 38. Some lower portions of recess 50 are located between adjacent STI regions 24.

[0026] Next, an epitaxial region (source / drain region) 54 is formed by selectively growing (by epitaxy) semiconductor material in the groove 50, thereby obtaining... Figure 6 The structure. The corresponding process is shown as... Figure 25Process 212 in process flow 200 shown in the diagram. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be doped in situ during epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc., can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphide (SiP), silicon carbon phosphide (SiCP), etc., can be grown. According to an alternative embodiment of this disclosure, the epitaxial region 54 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof. After filling the trench 50 with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to extend horizontally and can form a small facet. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to fuse together. Voids (air gaps) 56 may be generated.

[0027] Following the epitaxial process, the epitaxial region 54 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also designated by reference numeral 54. According to an alternative embodiment of this disclosure, when the epitaxial region 54 is in situ doped with p-type or n-type impurities during epitaxy, the implantation process is skipped.

[0028] Figure 7 A perspective view of the structure after the formation of the contact etch stop layer (CESL) 58 and the interlayer dielectric layer (ILD) 60 is shown. The corresponding process is illustrated as follows. Figure 25 Process 214 in process flow 200 is shown in the diagram. CESL 58 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 60 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. ILD 60 can be formed from a dielectric material, which can include silicon oxide, silicon phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped silicon phosphosilicate glass (BPSG), etc. Planarization processes such as CMP or mechanical polishing can be performed to make the top surfaces of ILD 60, dummy gate stack 38, and gate spacer 46 flush with each other.

[0029] In formation Figure 7 Following the structure shown, the dummy gate stack 38 is replaced with a replacement gate stack, as follows: Figure 8 , Figure 9A and Figure 9B The process is shown in the diagram. Figure 9B The top surface 24A of the STI region 24 is shown, and the semiconductor fin 36 protrudes above the top surface 24A.

[0030] To form a replacement gate, such as Figure 7 The hard mask layer 44, dummy gate electrode 42, and dummy gate dielectric 40 shown are removed to form a structure as shown below. Figure 8 The opening 62 is shown. The corresponding process is shown as follows. Figure 25 Process 216 in process flow 200 shown in the diagram. The top surface and sidewalls of the protruding fin 36 are exposed to the opening 62.

[0031] Figure 9A and Figure 9B The formation of the replacement gate stack 64 and the self-aligned hard mask 78 is shown. Figure 9B As shown Figure 9A The reference cross section 9B-9B is shown. (As shown) Figure 9A and Figure 9B As shown, a replacement gate stack 64 is formed. The corresponding process is shown as follows. Figure 25 Process 218 in process flow 200 is shown in the diagram. Gate stack 64 includes gate dielectric 70 and gate electrode 72. Gate dielectric 70 may include interface layer (IL) 66 and high-k dielectric layer 68. Figure 9B IL 66 is formed on the exposed surface of the protruding fin 36 and may include an oxide layer such as a silicon oxide layer, formed by thermal oxidation, chemical oxidation, or deposition processes of the protruding fin 36. The high-k dielectric layer 68 comprises a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9 and may be greater than about 7.0. According to some embodiments of this disclosure, the high-k dielectric layer 68 is formed using ALD, CVD, etc.

[0032] Further reference Figure 9A and Figure 9B A gate electrode 72 is formed on a gate dielectric 70. The gate electrode 72 may include a stacked layer 74. Figure 9BThe FinFET can include a diffusion barrier layer (cap layer) and one or more work function layers above the diffusion barrier layer. The diffusion barrier layer can be formed of titanium nitride, which may or may not be doped with silicon. Titanium nitride, when doped with silicon, is sometimes referred to as titanium silicon nitride (Ti-Si-N or TSN). The work function layer determines the work function of the gate electrode and includes at least one layer, or multiple layers formed of different materials. The specific material of the work function layer can be selected depending on whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer may include a TaN layer and a titanium aluminum (TiAl) layer above the TaN layer. When the FinFET is a p-type FinFET, the work function layer may include a TaN layer, a TiN layer above the TaN layer, and a TiAl layer above the TiN layer. After depositing the cap layer and the work function layer, a barrier layer, which may be another TiN layer, can be formed. The barrier layer can be formed using CVD.

[0033] Next, a metal-filled region 76 is deposited, the bottom surface of which is in solid contact with the top surface of the barrier layer. The metal-filled region 76 can be formed by CVD, ALD, physical vapor deposition (PVD), etc., and the metal-filled region 76 can be formed of cobalt, tungsten, their alloys, or other metals or metal alloys, or include cobalt, tungsten, their alloys, or other metals or metal alloys.

[0034] Next, planarization is performed, such as by chemical mechanical polishing (CMP) or mechanical grinding, so that the top surface of the gate stack 64 is coplanar with the top surface of the ILD 60. In a subsequent process, the gate stack 64 is etched back, creating grooves between the opposing gate spacers 46. A hard mask 78 is then formed over the replacement gate stack 64. The corresponding process is shown as follows. Figure 25 Process 220 is shown in process flow 200. According to some embodiments of this disclosure, the formation of the hard mask 78 includes a deposition process for forming a blanket dielectric material and a planarization process for removing excess dielectric material located over the gate spacer 46 and ILD60. The hard mask 78 may be formed of, for example, silicon nitride or other similar dielectric materials.

[0035] Figure 10A and Figure 10B The formation of the source / drain contact opening 80, formed by etching ILD 60 and CESL 58, is shown. The corresponding process is illustrated as follows. Figure 25 Process 222 in process flow 200 is shown in the diagram. Accordingly, the epitaxial region 54 is exposed. Figure 10B As shown Figure 10AThe reference cross section 10B-10B is shown. According to some embodiments, the depth D1 of the source / drain contact opening 80 is greater than about 80 nm, and according to some embodiments, it can be in the range of about 80 nm to about 200 nm.

[0036] Next, refer to Figure 11 A sacrificial layer of 82 was deposited. The corresponding process is shown as follows. Figure 25 Process 224 in process flow 200 shown in the diagram. The material of the sacrificial layer is selected such that it is relative to the material in... Figure 18A All exposed materials in the illustrated process have sufficiently high etch selectivity (e.g., above about 100). For example, exposed materials include ILD 60, CESL 58, gate spacer 46, hard mask 78, metal-filled region 90, and silicide region 88. According to some embodiments of this disclosure, depending on the material of the exposed region / layer, the sacrificial layer is selected to have high etch selectivity relative to silicon oxide, SiOCN, cobalt, SiN, tungsten, TiSi, etc., such that these materials are substantially undamaged when the sacrificial layer 82 is removed. According to some embodiments of this disclosure, the sacrificial layer 82 comprises silicon, and the sacrificial layer 82 may not contain other elements such as germanium, p-type impurities, n-type impurities, etc. The sacrificial layer 82 may be amorphous or may be polycrystalline silicon. In the following paragraphs, the sacrificial layer 82 is referred to as dummy silicon layer 82, but it may also be formed of other materials.

[0037] For example, a conformal deposition method is used to form the dummy silicon layer 82, wherein the difference between the horizontal thickness of the horizontal portion and the vertical thickness of the vertical portion is less than about 20% of one of the horizontal and vertical thicknesses. According to some embodiments, the deposition method includes atomic layer deposition (ALD) (e.g., radical-enhanced ALD), chemical vapor deposition (CVD), etc. The thickness T1 of the dummy silicon layer 82 is selected to obtain optimal results. When the thickness T1 is too small, the expected effect of reducing parasitic capacitance is too small. Furthermore, when the thickness T1 is too small, it is difficult to remove the dummy silicon layer 82 to form air spacers. On the other hand, if T1 is too large, the size of the resulting transistor increases excessively, and / or the allowable width of the subsequently filled metal region 90 is squeezed. According to some embodiments of this disclosure, the thickness T1 is in the range of about 1.5 nm to about 3.0 nm.

[0038] refer to Figure 12 For example, an isolation layer 84 can be deposited using ALD, CVD, etc. The corresponding process is shown as follows: Figure 25Process 226 in process flow 200 shown in the diagram. The isolation layer 84 can be formed of a dielectric material such as silicon nitride, silicon oxynitride, etc. The isolation layer 84 is also formed as a conformal layer. The isolation layer 84 serves to physically isolate the dummy silicon layer 82 from the subsequently deposited capping layer 86, which can react with the dummy silicon layer 82 to form a silicide.

[0039] In subsequent processes, such as Figure 13 As shown, an anisotropic etching process is performed to remove the horizontal portion of the isolation layer 84 and the dummy silicon layer 82. As a result, the epitaxial region 54 is exposed. The corresponding process is shown as follows. Figure 25 Process 228 in the process flow 200 shown in the figure.

[0040] Figure 14A and Figure 14B The formation of the cap layer 86 is shown. The corresponding process is illustrated as follows. Figure 25 Process 230 in the process flow 200 shown in the figure. Figure 14A A reference cross section obtained along the source-to-drain direction is shown, which can be compared with... Figure 10A The reference cross sections 10B-10B shown are identical. The capping layer 86 may be a titanium nitride layer, or may include a titanium nitride layer, which may be a titanium-rich layer having a high percentage of titanium atoms (e.g., above about 80%). According to an alternative embodiment, the capping layer 86 includes a metal layer (e.g., a titanium layer) and a metal nitride-containing layer above the metal layer. The metal nitride-containing layer may be formed of titanium nitride, tantalum nitride, etc., or may include titanium nitride, tantalum nitride, etc. The capping layer 86 may be formed by deposition, for example, using ALD, CVD, etc. According to an alternative embodiment, the capping layer 86 is formed by depositing a metal layer and then nitriding the surface layer of the metal layer while leaving the underlying layer of the metal layer unnitrided. According to some embodiments of this disclosure, the capping layer 86 may be a conformal layer.

[0041] Figure 14B A reference cross-section obtained along the gate length direction is shown, which can be compared with... Figure 10A The reference cross section shown is the same as 10C-10C. Figure 14B Fin spacer 55 is also schematically shown, which is formed using the same process as that used to form gate spacer 46. The formation of fin spacer 55 allows the epitaxial region 54 to begin growing at a higher location and allows the gap 56 to be larger, for example, as shown by dashed line 56'.

[0042] Then, an annealing process is performed to form the source / drain silicide region 88, such as Figure 15 As shown. The corresponding process is shown as follows. Figure 25Process 232 in process flow 200 is shown in the diagram. The annealing process can be performed by rapid thermal annealing (RTA), furnace annealing, etc. Therefore, the bottom of the cap layer 86 reacts with the dummy silicon layer 82 and the underlying source / drain region to form a metal silicide region 88 (e.g., TiSi or TiSiN), which may or may not include nitrogen. The opposite sidewalls of the source / drain silicide region 88 may be flush with the inner edge of the remaining isolation layer 84 above, or may extend laterally to be located directly below the remaining vertical portion of the isolation layer 84 and the dummy silicon layer 82.

[0043] In subsequent processes, capping layer 86 can first be pulled back to widen the top of opening 80, and then another capping layer can be formed, which can be formed from, for example, TiN. The additional capping layer will be conformal and will have a horizontal portion at the bottom of opening 80, as shown in dashed layer 87. According to other embodiments, pullback is not performed. If pullback is performed, the lower portion of capping layer 86 will be thicker than the corresponding upper portion. According to some embodiments, the pullback process includes: filling the opening 80 with a sacrificial material such as a photoresist, etching back the sacrificial material until its surface is below the top surface of ILD 60, using the sacrificial material as an etching mask to etch capping layer 86, and then removing the sacrificial material. The top of the remaining capping layer 86 can be at an intermediate level between the top and bottom surfaces of ILD 60. An additional capping layer is then formed. According to alternative embodiments, such as Figure 16 As shown, no additional capping layer is formed. According to some embodiments, the additional capping layer is formed of titanium nitride, tantalum nitride, etc. Figure 15 The remaining cap layer 86 left by the pull-back process is not shown separately.

[0044] Next, as Figure 16 As shown, metallic material 90 is deposited above and in contact with capping layer 86, and fills opening 80. The corresponding process is shown as follows. Figure 25 Process 234 in process flow 200 shown in the diagram. The metallic material 90 may be formed from cobalt, tungsten, or alloys thereof, or may include cobalt, tungsten, or alloys thereof. Next, as... Figure 17 As shown, a planarization process, such as CMP or mechanical polishing, is performed to remove the portion of the cap layer 86 and metal material 90 located above the top surface of the ILD 60. This exposes the dummy silicon layer 82.

[0045] Figure 18A and Figure 18B The process of removing the dummy silicon layer 82 via an etching process to form the air spacer 92 is shown. The corresponding process is illustrated as follows: Figure 25 Process 236 in the process flow 200 shown in the figure. Figure 18AA reference cross section obtained along the source-to-drain direction is shown, which can be compared with... Figure 10A The reference cross section 10B-10B shown is the same. Figure 18B A reference cross-section obtained along the gate length direction is shown, which can be compared with... Figure 10A The reference cross-section shown is the same for 10C-10C. The etching process is indicated by arrow 94.

[0046] According to some embodiments, the etching process 94 is performed using a mixture of hydrogen (H2) and nitrogen trifluoride (NF3). Other gases, such as N2, Ar, He, or combinations thereof, may also be added. According to some embodiments, the pressure in the etching chamber during etching can be in the range of about 200 mTorr to about 5000 mTorr. The temperature of wafer 10 can be in the range of about 10°C to about 120°C. The hydrogen flow rate can be in the range of about 100 sccm to about 5000 sccm, and the NF3 flow rate can be in the range of about 5 sccm to about 100 sccm. The N2 flow rate can be in the range of about 0 sccm to about 5000 sccm. The Ar flow rate can be in the range of about 0 sccm to about 1000 sccm. The He flow rate can be in the range of about 0 sccm to about 4000 sccm. Etching can be performed using remote plasma, and ions of the etching gas are removed by filtration while retaining the free radicals of the etching gas for etching the dummy silicon layer 82. This reduces damage to exposed areas.

[0047] Experimental results show that NF3 may form metal fluorides on the surface of the metal region 90%. Metal fluorides in... Figure 18A The region is schematically shown as region 96. For example, when metal region 90 is formed of or includes cobalt, metal fluoride region 96 includes cobalt fluoride (CoF). xIf a metal fluoride forms, the metal fluoride region 96 thickens and laterally expands as the dummy silicon layer 82 is etched. The laterally expanding metal fluoride region 96 is likely to seal the inlet of the air gap 92 before the dummy silicon layer 82 is completely removed (and the air gap 92 is fully formed). As a result, the bottom of the dummy silicon layer 82 cannot be removed. This adversely reduces the expected effect of reducing parasitic capacitance. Experimental results also show that by increasing the ratio FR(H2) / FR(NF3) (which is the flow rate ratio of hydrogen flow rate FR(H2) to NF3 flow rate FR(NF3)), the thickness of the metal fluoride region 96 decreases. An increase in the flow rate ratio FR(H2) / FR(NF3) means a decrease in the relative amount of NF3, the source gas for metal fluoride formation. As the thickness of the metal fluoride region 96 decreases, the likelihood of prematurely sealing the air gap 92 decreases. Experimental results show that when the flow rate ratio FR(H2) / FR(NF3) is equal to 0.44, 2.0, and 28, a distinct metal fluoride region 96 with a thickness between about 6 nm and about 9 nm is observed. This thickness is large enough to prematurely seal the air spacer 92 before it is fully formed. On the other hand, when the flow rate ratio FR(H2) / FR(NF3) is equal to or greater than 41, no distinguishable metal fluoride region 96 is found (e.g., by transmission electron microscopy (TEM)), and the air spacer 92 is fully formed as the dummy silicon layer 82 is completely removed. It is understood that the ratio FR(H2) / FR(NF3) cannot be too high either. Otherwise, the etching rate of the dummy silicon layer 82 is too low or even cannot be etched. According to some embodiments of this disclosure, the flow rate ratio FR(H2) / FR(NF3) is in the range of 41 to about 44.

[0048] Increasing the flow rate ratio FR(H2) / FR(NF3) can also increase the etch selectivity of the dummy silicon layer 82 relative to other exposed areas, resulting in less etching (damage) of the exposed areas. The ratio of the etch rate of the dummy silicon layer 82 to the etch rates of the gate spacer 46, CESL 58, ILD 60, metal region 90, cap layer 86, isolation layer 84, and silicide region 88 can, for example, be increased to above about 100. Accordingly, these areas are essentially undamaged when the dummy silicon layer 82 is completely removed.

[0049] When the dummy silicon layer 82 is completely removed, the underlying region is exposed, which may be a silicide region 88 or an epitaxial region 54. According to some embodiments, a thin oxide layer (not shown) may be formed on the surface of the epitaxial region 54 or the silicide region 88 to prevent etching of the epitaxial region 54. Although the thin oxide layer is observed to be located at the bottom of the dummy silicon layer 82, it is not observed in the final structure. If the silicide region 88 is exposed, further etching of the silicide region 88 also ceases. According to other embodiments, the epitaxial region 54 is slightly etched, so that the air spacer 92 extends downward into the epitaxial region 54, and the dashed line 93 schematically shows the location of the air spacer 92.

[0050] exist Figure 18A and Figure 18B In this structure, there exists a region directly beneath the isolation layer 84, labeled "92 / 82," meaning this region can be a portion of the air spacer 92 or may contain residual dummy silicon layer 82. According to some embodiments, the portion of the dummy silicon layer 82 directly beneath the isolation layer 84 is removed, and the air spacer 92 extends into these regions. According to alternative embodiments, at least some portions of the dummy silicon layer 82 directly beneath the isolation layer 84 are not etched, and the dummy silicon layer 82 remains in the final structure. According to some embodiments, the air spacer 92 has an irregular shape; for example, the upper portion of the air spacer 92 is wider than the corresponding lower portion. When residual dummy silicon layer 82 is present, the residual dummy silicon layer 82 can have an irregular shape; for example, the lower portion of the residual dummy silicon layer 82 is wider than the corresponding upper portion.

[0051] In such Figure 18A and Figure 18B In the resulting structure, a source / drain contact plug 98 is formed, which includes a cap layer 86 and a metal region 90. An isolation layer 84 surrounds the contact plug 98 and is further surrounded by an air spacer 92, which also forms a ring. Figure 18C A perspective view is shown, which illustrates the air spacer 92 and the source / drain contact plug 98. Figure 18D A top view is shown, illustrating that the air spacer 92 forms a complete ring surrounding the isolation layer 84 and the source / drain contact plug 98. The isolation layer 84 and the cap layer 86 are also formed as rings. Thus, a FinFET 100 is formed.

[0052] Figure 19A and Figure 19B The formation of an etch stop layer 102 is shown, which is formed from a dielectric material such as silicon carbide, silicon oxynitride, or silicon carbonitride. The corresponding process is shown as follows. Figure 25 Process 238 in the process flow 200 shown in the figure. Figure 19AA reference cross-section obtained along the source-to-drain direction is shown, and Figure 19B A reference cross-section obtained along the gate length direction is shown. The etch stop layer 102 can be formed using non-conformal and non-bottom-up methods (e.g., SiN, SiOCN, etc.) such that the etch stop layer 102 seals the air spacer 92 without filling it. The etch stop layer 102 may extend slightly into the previously formed air spacer 92.

[0053] refer to Figure 20 A dielectric layer 104 is formed. The dielectric layer 104 may comprise a material selected from PSG, BSG, BPSG, fluorine-doped silicon glass (FSG), silicon oxide, etc. The dielectric layer 104 may be formed using spin coating, FCVD, or deposition methods such as PECVD or low-pressure chemical vapor deposition (LPCVD). The dielectric layer 104 and the etch stop layer 102 are etched to form openings (occupied by plugs / vias 106 and 108). Etching may be performed using, for example, reactive ion etching (RIE). Contact plugs / vias 106 and 108 are formed in the openings. According to some embodiments of this disclosure, an air spacer 120 is formed to surround the contact plugs / vias 106 and 108. According to some embodiments of this disclosure, the plugs / vias 106 and 108 are formed using processes and materials selected from the same candidate processes and materials used for forming source / drain contact plugs 98. For example, the formation process may include: depositing a silicon layer (not shown), an isolation layer 122, and a capping layer 124; performing anisotropic etching 122 on the silicon layer and the isolation layer; and filling the metal regions 126. Because no silicide regions are formed, the annealing process is skipped. According to an alternative embodiment, the isolation layer 122 is skipped, and the capping layer 124 is exposed to the air spacers 120.

[0054] In subsequent processes, a planarization process is performed. Then, an additional etch stop layer and an additional dielectric layer are formed to seal the air spacer 120 therein. The cap layer 124 may be formed of Ti, TiN, Ta, TaN, etc., or may include Ti, TiN, Ta, TaN, etc. The metal region 126 may be formed of tungsten, cobalt, etc.

[0055] Figure 21 A FinFET 100 and a corresponding air spacer according to an alternative embodiment are shown. These embodiments are similar to... Figure 20In some embodiments of this disclosure, air spacers are not formed in the contact plugs / vias extending into the dielectric layer 104. According to some embodiments of this disclosure, plugs / vias 106' and 108' include a barrier layer 110 and a metallic material 112 above the barrier layer 110. According to some embodiments of this disclosure, the formation of plugs / vias 106' and 108' includes: etching layers 102 and 104 to form contact openings, forming a blanket barrier layer and a metallic material above the blanket barrier layer, and performing a planarization process to remove excess portions of the blanket barrier layer and the metallic material. The barrier layer 110 may be formed of Ti, TiN, Ta, TaN, etc., or may include Ti, TiN, Ta, TaN, etc. The metallic material 112 may be formed of copper, tungsten, cobalt, etc.

[0056] Figure 22 and Figure 23 The formation of a structure according to an alternative embodiment is illustrated. These embodiments are related to... Figure 16 The illustrated embodiment is similar, except that the ILD 60 has an additional portion extending above the gate spacer 46, the gate stack 64, and the hard mask 78. The air spacer 92 extends accordingly into the additional portion of the ILD 60. Figure 22 The process of forming air spacers 92 by etching the corresponding silicon layers is shown, and Figure 23 The formation of the additional features above is shown.

[0057] Figure 24 The structures shown are based on some embodiments of the present disclosure, which are similar to Figure 23 The embodiment shown, except that contact plugs 106' and 108' are not surrounded by air spacers.

[0058] The embodiments of this disclosure have several advantageous features. By forming air spacers, the parasitic capacitance between the conductive features surrounded by the air spacers and adjacent features is reduced. The increased flow rate ratio of hydrogen to nitrogen trifluoride reduces and eliminates the formation of metal fluorides during the removal of the dummy silicon layer, and thus avoids premature sealing of the air spacers.

[0059] According to some embodiments of this disclosure, a method includes: forming an opening in a first dielectric layer, wherein a lower region located beneath the first dielectric layer is exposed to the opening; depositing a dummy silicon layer extending into the opening; depositing an isolation layer, wherein the isolation layer and the dummy silicon layer respectively include a dummy silicon ring and an isolation ring in the opening; filling the opening with a metal region, wherein the metal region is surrounded by the isolation ring; etching the dummy silicon layer to form an air spacer; and forming a second dielectric layer to seal the air spacer. In embodiments, etching the dummy silicon layer is performed using a process gas comprising hydrogen (H2) and nitrogen trifluoride (NF3). In embodiments, the ratio of a first flow rate of H2 to a second flow rate of NF3 is greater than about 41. In embodiments, etching the dummy silicon layer is performed using a fluorine-based etching gas, and no metal fluoride remains on the exposed surface of the metal region during etching of the dummy silicon layer. In embodiments, the method further includes: forming a metal-containing capping layer extending into the opening; and performing an annealing process to react the metal-containing capping layer with the lower region, wherein the lower region comprises a silicon-containing semiconductor material. In one embodiment, the lower region includes a gate electrode. In another embodiment, depositing a dummy silicon layer includes depositing an amorphous silicon layer.

[0060] According to some embodiments of this disclosure, a method includes: etching a dielectric layer to form an opening, wherein a semiconductor region is located below the opening and exposed to the opening; forming a dummy silicon layer on a sidewall of the dielectric layer facing the opening, wherein the dummy silicon layer further includes a horizontal portion located at the bottom of the opening; forming an isolation layer to cover the dummy silicon layer; performing an anisotropic etching process on the dummy silicon layer and the isolation layer to expose the semiconductor region to the opening, wherein the silicon portion and the isolation portion remain in the opening; depositing a metal-containing layer extending into the opening; performing a silicide process to react the metal-containing layer with the semiconductor region, such that a silicide region is formed; filling the opening with the metal region; and etching the dummy silicon layer. In embodiments, the isolation layer is not etched during the etching of the dummy silicon layer. In embodiments, after the dummy silicon layer is etched, the silicide region is exposed, and the silicide region is not used for chemical etching of the dummy silicon layer. In embodiments, the etching of the dummy silicon layer is performed using an etching gas including a fluorine-containing gas, and no metal fluoride is formed on the metal region during etching. In an embodiment, the etching gas comprises hydrogen (H2) and nitrogen trifluoride (NF3), and the ratio of a first flow rate of hydrogen to a second flow rate of nitrogen trifluoride is greater than 41. In an embodiment, after etching the dummy silicon layer, air spacers are formed between the isolation layer and the dielectric layer, and the method further includes depositing an additional dielectric layer on the dielectric layer to seal the air spacers. In an embodiment, the dummy silicon layer is formed as a substantially conformal layer.

[0061] According to some embodiments of this disclosure, a method includes: depositing a silicon layer extending into an opening in a first dielectric layer; depositing a second dielectric layer on the silicon layer; removing horizontal portions of the silicon layer and the second dielectric layer; forming a silicide region at the bottom of the opening; filling the opening with a metal region; etching the silicon layer using an etching gas comprising hydrogen (H2) and nitrogen trifluoride (NF3) to form an air spacer until the silicide region is exposed to the air spacer; and depositing a third dielectric layer to seal the air spacer. In embodiments, forming the silicide region includes: depositing a metal-containing layer extending into the opening after the horizontal portions of the silicon layer and the second dielectric layer have been removed; and performing an annealing process. In embodiments, the method further includes: performing a planarization process to expose the silicon layer, the first dielectric layer, and the second dielectric layer before etching the silicon layer. In embodiments, no distinguishable metal fluoride residue remains on top of the metal region during etching of the silicon layer. In embodiments, the ratio of a first flow rate of hydrogen to a second flow rate of nitrogen trifluoride is greater than 41 during etching of the silicon layer. In embodiments, the silicon layer comprises amorphous silicon.

[0062] The foregoing summarizes features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for carrying out the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0063] Example 1. A method of manufacturing a semiconductor device, comprising: forming an opening in a first dielectric layer, wherein a lower region located below the first dielectric layer is exposed to the opening; depositing a dummy silicon layer extending into the opening; depositing an isolation layer, wherein the isolation layer and the dummy silicon layer respectively include a dummy silicon ring and an isolation ring in the opening; filling the opening with a metal region, wherein the metal region is surrounded by the isolation ring; etching the dummy silicon layer to form an air spacer; and forming a second dielectric layer to seal the air spacer.

[0064] Example 2. According to the method of Example 1, wherein the etching of the dummy silicon layer is performed using a process gas comprising hydrogen (H2) and nitrogen trifluoride (NF3).

[0065] Example 3. The method described in Example 2, wherein the ratio of the first flow rate of H2 to the second flow rate of NF3 is greater than 41.

[0066] Example 4. The method according to Example 1, wherein etching the dummy silicon layer is performed using a fluorine-based etching gas, and no metal fluoride remains on the exposed surface of the metal region during etching of the dummy silicon layer.

[0067] Example 5. The method according to Example 1 further includes: forming a metal-containing capping layer extending into the opening; and performing an annealing process to react the metal-containing capping layer with the underlying region, wherein the underlying region comprises a silicon-containing semiconductor material.

[0068] Example 6. The method according to Example 1, wherein the lower region includes an extensional region.

[0069] Example 7. The method according to Example 1, wherein depositing the dummy silicon layer includes depositing an amorphous silicon layer.

[0070] Example 8. A method of manufacturing a semiconductor device, comprising: etching a dielectric layer to form an opening, wherein a semiconductor region is located below and exposed to the opening; forming a dummy silicon layer on a sidewall of the dielectric layer facing the opening, wherein the dummy silicon layer further includes a horizontal portion located at the bottom of the opening; forming an isolation layer to cover the dummy silicon layer; performing an anisotropic etching process on the dummy silicon layer and the isolation layer to expose the semiconductor region to the opening, wherein the silicon portion and the isolation portion remain in the opening, respectively; depositing a metal-containing layer extending into the opening; performing a silicide process to react the metal-containing layer with the semiconductor region, such that a silicide region is formed; filling the opening with the metal region; and etching the dummy silicon layer.

[0071] Example 9. The method according to Example 8, wherein the isolation layer is not etched during the etching of the dummy silicon layer.

[0072] Example 10. The method according to Example 8, wherein after etching the dummy silicon layer, the silicide region is exposed, and the silicide region is not used for chemical etching of the dummy silicon layer.

[0073] Example 11. The method according to Example 8, wherein etching the dummy silicon layer is performed using an etching gas comprising a fluorine-containing gas, and no metal fluoride is formed on the metal region during etching.

[0074] Example 12. The method according to Example 11, wherein the etching gas comprises hydrogen (H2) and nitrogen trifluoride (NF3), and the ratio of a first flow rate of hydrogen to a second flow rate of nitrogen trifluoride is greater than 41.

[0075] Example 13. The method according to Example 8, wherein after etching the dummy silicon layer, an air spacer is formed between the isolation layer and the dielectric layer, and the method further comprises: depositing an additional dielectric layer over the dielectric layer to seal the air spacer.

[0076] Example 14. The method according to Example 8, wherein the dummy silicon layer is formed as a conformal layer.

[0077] Example 15. A method of manufacturing a semiconductor device, comprising: depositing a silicon layer extending into an opening in a first dielectric layer; depositing a second dielectric layer on the silicon layer; removing horizontal portions of the silicon layer and the second dielectric layer; forming a silicide region at the bottom of the opening; filling the opening with a metal region; etching the silicon layer to form an air spacer using an etching gas comprising hydrogen (H2) and nitrogen trifluoride (NF3) until the silicide region is exposed to the air spacer; and depositing a third dielectric layer to seal the air spacer.

[0078] Example 16. The method according to Example 15, wherein forming the silicide region comprises: depositing a metal-containing layer extending into the opening after the horizontal portions of the silicon layer and the second dielectric layer are removed; and performing an annealing process.

[0079] Example 17. The method according to Example 15 further includes: performing a planarization process to expose the silicon layer, the first dielectric layer, and the second dielectric layer before etching the silicon layer.

[0080] Example 18. The method according to Example 15, wherein during the etching of the silicon layer, no distinguishable metal fluoride remains on top of the metal region.

[0081] Example 19. The method according to Example 15, wherein, during etching of the silicon layer, the ratio of the first flow rate of hydrogen to the second flow rate of nitrogen trifluoride is greater than 41.

[0082] Example 20. The method according to Example 15, wherein the silicon layer comprises amorphous silicon.

Claims

1. A method of fabricating a semiconductor device, comprising: forming a gate spacer; forming a first dielectric layer over sidewalls of the gate spacer; forming an opening in the first dielectric layer, wherein an underlying region located below the first dielectric layer is exposed to the opening, and wherein a portion of the first dielectric layer separates the opening from the gate spacer after forming the opening; depositing a dummy silicon layer extending into the opening; depositing an isolation layer, wherein the isolation layer and the dummy silicon layer include a dummy silicon ring and an isolation ring, respectively, in the opening; performing an anisotropic etch process on the dummy silicon layer and the isolation layer to expose the underlying region to the opening; forming a metal-containing cap layer extending into the opening, wherein a portion of the metal-containing cap layer contacts a lower portion of the dummy silicon layer proximate to the underlying region; performing an anneal process to react the metal-containing cap layer with the underlying region, wherein the underlying region includes a silicon-containing semiconductor material; filling the opening with a metal region, wherein the metal region is encircled by the isolation ring; etching the dummy silicon layer to form an air spacer, wherein etching the dummy silicon layer also causes the underlying region to be etched, and the air spacer extends down into the underlying region; and forming a second dielectric layer to seal the air spacer, wherein etching the dummy silicon layer is performed using a process gas including hydrogen (H2) and nitrogen trifluoride (NF3), and wherein a ratio of a first flow rate of H2 to a second flow rate of NF3 is higher than 41.

2. The method of claim 1, wherein, etching the dummy silicon layer is performed using a fluorine-based etch gas, and no metal fluoride remains on an exposed surface of the metal region when etching the dummy silicon layer.

3. The method of claim 1, wherein, the underlying region includes an epitaxial region.

4. The method of claim 1, wherein, depositing the dummy silicon layer includes depositing an amorphous silicon layer.

5. A method of fabricating a semiconductor device, comprising: forming a gate spacer; forming a dielectric layer over sidewalls of the gate spacer; etching the dielectric layer to form an opening, wherein a semiconductor region is located below and exposed to the opening, and wherein a portion of the dielectric layer separates the opening from the gate spacer after forming the opening; forming a dummy silicon layer on a sidewall of the dielectric layer facing the opening, wherein the dummy silicon layer also includes a horizontal portion at a bottom of the opening; forming an isolation layer to cover the dummy silicon layer; performing an anisotropic etch process on the dummy silicon layer and the isolation layer to expose the semiconductor region to the opening, wherein a first remaining portion of the dummy silicon layer and a second remaining portion of the isolation layer remain in the opening, respectively; depositing a metal-containing layer extending into the opening, wherein a portion of the metal-containing layer contacts a lower portion of the dummy silicon layer proximate to the bottom of the opening; performing a silicidation process to react the metal-containing layer with the semiconductor region such that a silicide region is formed; filling the opening with a metal region; and etching the dummy silicon layer to form an air spacer, wherein etching the dummy silicon layer also causes the semiconductor region to be etched, and the air spacer extends down into the semiconductor region, wherein etching the dummy silicon layer is performed using an etching gas that includes a fluorine-containing gas, and wherein the etching gas includes hydrogen H2 and nitrogen trifluoride NF3, and a ratio of a first flow rate of the hydrogen to a second flow rate of the nitrogen trifluoride is greater than 41.

6. The method of claim 5, wherein, During etching the dummy silicon layer, the isolation layer is not etched.

7. The method of claim 5, wherein, After etching the dummy silicon layer, the silicide region is exposed, and the silicide region is not etched by a chemical used to etch the dummy silicon layer.

8. The method of claim 5, wherein, During etching, no metal fluoride is formed on the metal region.

9. The method of claim 5, wherein, After etching the dummy silicon layer, the air spacer is formed between the isolation layer and the dielectric layer, and the method further comprises depositing an additional dielectric layer over the dielectric layer to seal the air spacer.

10. The method of claim 5, wherein, The dummy silicon layer is formed as a conformal layer.

11. A method of manufacturing a semiconductor device, comprising: forming a gate spacer; forming a first dielectric layer over sidewalls of the gate spacer; forming an opening in the first dielectric layer, wherein an underlying region located below the first dielectric layer is exposed to the opening, and wherein after forming the opening, a portion of the first dielectric layer separates the opening from the gate spacer; depositing a silicon layer that extends into the opening in the first dielectric layer; depositing a second dielectric layer on the silicon layer; removing a horizontal portion of the silicon layer and the second dielectric layer; forming a silicide region at a bottom of the opening; filling the opening with a metal region; etching the silicon layer to form an air spacer using an etching gas that includes hydrogen H2 and nitrogen trifluoride NF3, wherein etching the silicon layer also causes the underlying region to be etched, and the air spacer extends down into the underlying region; and depositing a third dielectric layer to seal the air spacer, wherein forming the silicide region comprises: after the silicon layer and the horizontal portion of the second dielectric layer are removed, depositing a metal-containing layer that extends into the opening, wherein a portion of the metal-containing layer contacts a lower portion of the silicon layer proximate to the bottom of the opening; and performing an anneal process, wherein a ratio of a first flow rate of the hydrogen to a second flow rate of the nitrogen trifluoride is greater than 41 when etching the silicon layer.

12. The method of claim 11, further comprising: performing a planarization process to expose the silicon layer, the first dielectric layer, and the second dielectric layer prior to etching the silicon layer.

13. The method of claim 11, wherein, During etching the silicon layer, no resolvable metal fluoride remains on top of the metal region.

14. The method of claim 11, wherein, The silicon layer includes amorphous silicon.

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